Digital foreground calibration system and method for successive approximation analog-to-digital converter based on RRAM

Abstract

The invention discloses a digital foreground calibration system and method for a successive approximation type analog-to-digital converter based on an RRAM, and belongs to the related technical field of integrated circuits. The system comprises a step voltage generation module, a state monitoring module, an information storage module and a data processing module, the step voltage generation module is valid only in a calibration mode, and the data processing module is valid in a working mode; the state detection module receives the output of an ADC to be calibrated and detects the mode of the ADC, the information storage module adopts a storage array unit based on an RRAM, the calibration code generated by the step voltage generation module is stored in the calibration mode, and the data is continuously input into the data processing module in the working mode to be accumulated and cut off to generate a calibrated output code. According to the calibration method, the effective precision and the conversion linearity of the calibrated SAR ADC are improved, the requirements of the calibrated SAR ADC on the size and the area of a unit capacitor in the DAC are reduced, the power consumption of digital-to-analog conversion is reduced, the data stability is improved, and the calibration period is shortened.

Description

Technical Field

[0001] The present invention belongs to the technical field related to integrated circuits, and more specifically, relates to a digital front-end calibration system and method for a successive approximation analog-to-digital converter based on RRAM. Background Art

[0002] For a successive approximation analog-to-digital converter (SAR ADC), the switching energy consumption of its capacitor array is the main energy consumption. If the area of ​​its unit capacitor can be reduced, its energy consumption will be greatly reduced, but reducing the unit capacitor area will increase the mismatch rate between unit capacitors, making the linearity of the entire ADC unable to meet the requirements. Foreground calibration of the SAR ADC can compensate for the error caused by capacitor mismatch to a certain extent, improve the linearity of the system, and reduce the linearity requirements for capacitor mismatch.

[0003] However, the current digital front-end calibration schemes for SAR ADC are not non-volatile, which causes the stored data to be lost every time the power is turned off. Each time the SAR ADC is put into calibration mode before working, it greatly wastes time and energy.

[0004] Therefore, it is currently necessary to design a non-volatile and extremely low-power SAR ADC foreground calibration solution to calibrate the error caused by capacitor mismatch in the ADC, improve the linearity of the SAR ADC, relax the requirements on the capacitor mismatch rate, and improve the energy efficiency of the entire SAR ADC system. Summary of the invention

[0005] In view of the defects of the related art, the purpose of the present invention is to provide a digital front-end calibration system and method for a successive approximation analog-to-digital converter based on RRAM, aiming to solve the problem that the existing digital front-end calibration scheme is not non-volatile, resulting in the loss of stored data after each power failure, and the calibration mode must be entered before each work, which greatly wastes time and energy.

[0006] To achieve the above-mentioned object, in a first aspect, the present invention provides a digital front-end calibration system for a successive approximation analog-to-digital converter based on RRAM, comprising: a step voltage generation module, a state monitoring module, an information storage module and a data processing module; the step voltage generation module is only effective in a calibration mode and is turned off in an operating mode; the data processing module is turned off in the calibration mode and is effective in the operating mode; The step voltage generating module includes a counter with an N+M bit width and a digital-to-analog converter with an N+M bit resolution, wherein the input end of the counter is connected to an external clock, and the output end is connected to the input end of the digital-to-analog converter, and the output end of the digital-to-analog converter is connected to the input end of the successive approximation analog-to-digital converter to be calibrated; the counter is used to generate a continuously self-increasing digital code, and the digital-to-analog converter is used to convert the digital code into a continuously increasing analog step voltage Vt, and output it to the successive approximation analog-to-digital converter to be calibrated; wherein M and N are both positive integers; The state monitoring module includes a state detection logic unit and a selector; in the calibration mode, the input end of the state detection logic unit is connected to the output end of the successive approximation analog-to-digital converter to be calibrated, the output end is connected to the input end of the selector, and the output end of the selector is connected to the information storage module; the state detection logic unit is used to detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and the selector is used to respond to different control signals according to the mode of the digital output code; in the working mode, the input end of the state monitoring logic unit is connected to the output end of the successive approximation analog-to-digital converter to be calibrated, the state detection logic unit is used to detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and the selector is used to respond to different control signals according to the mode of the digital output code; The information storage module includes an address control unit and a storage array unit based on RRAM; in a calibration mode, the storage array unit is connected to the counter and is used to store the N (N+M)-bit digital calibration code generated by the step voltage generation module; the address control unit is used to select different columns in the storage array according to the control signal output by the state monitoring module, and write the digital calibration code into the storage array; in an operating mode, the storage array unit is connected to the data processing module, and the address control unit is used to select different columns in the storage array according to the control signal output by the state monitoring module, and read the digital calibration code from the storage array; The data processing module includes an N+M-bit data accumulator and an N-bit data chopper, the input end of the data accumulator is connected to the information storage module, and the output end is connected to the input end of the data chopper; the data accumulator is used to accumulate the N+M-bit digital calibration code selected in the information storage module, and the data chopper is used to chop the data and only retain the first N bits as the output of the calibrated successive approximation analog-to-digital converter.

[0007] Optionally, the counter receives an external clock signal and self-increments the output at each rising edge of the clock to generate a digital code with a bit width of N+M bits; The digital-to-analog converter periodically converts the digital output code of the counter into an analog voltage under the control of the system clock to obtain a step voltage Vt, which is output to a successive approximation analog-to-digital converter; the step voltage Vt includes all situations of the N-bit digital output.

[0008] Optionally, in the calibration mode, the state monitoring module is used to automatically detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and detect whether the mode is that only one bit is "1" and all other bits are "0". If the detection result is true, the position of "1" in the digital output code is detected, and the selector is used to output different control signals to the information storage module according to the detected position response; if the detection result is false, this calibration cycle is directly skipped; In the working mode, the status monitoring module is used to automatically monitor the mode of the digital output code of the calibrated successive approximation analog-to-digital converter, detect the number n of digital codes containing "1", and set the working cycle of this working mode to n, and detect the number of bits of each "1" in the digital output code. The selector is used to respond to different control signals for each different "1" in the next n working cycles.

[0009] Optionally, in the calibration mode, the address control unit in the information storage module is used to receive the control signal responded by the state detection module, select the columns at different positions in the storage array, and store the digital output code corresponding to the cycle in the corresponding position as the digital calibration code; In working mode, the address control unit in the information storage module is used to receive the control signal responded by the state detection module, select columns at different positions in the storage array, and read out the digital calibration code stored in the storage array periodically and transmit it to the data processing module.

[0010] Optionally, the number of the storage array units is N*(N+M); each of the storage array units includes 7 MOS tubes and 2 RRAMs, wherein 3 MOS tubes are used as signal selection switches, 4 MOS tubes constitute end-to-end inverters to enhance storage signals, and 2 RRAMs are used as media for storing information; In the calibration mode, the storage array unit is in a write mode, and the digital calibration codes are written one by one; In the working mode, the storage array unit is in the reading mode, and reads the digital calibration codes one by one to the data processing module.

[0011] Optionally, the data accumulator of the data processing module is used to accumulate the received N+M-bit digital calibration code and determine whether the accumulated result exceeds N+M bits. If so, N+M-bit "1" is output; if not, the data chopper performs a chopping operation on the accumulated data and only retains the high N bits of the data as output.

[0012] Optional, N=8, M=2.

[0013] In a second aspect, the present invention further provides a digital foreground calibration method for a successive approximation analog-to-digital converter based on RRAM, which is performed based on a digital foreground calibration system for a successive approximation analog-to-digital converter based on RRAM as described in any one of the first aspects, for a successive approximation analog-to-digital converter to be calibrated, a calibration mode is first performed, and the subsequent modes are all working modes; When in calibration mode, the method comprises: The step voltage generating module generates a step voltage Vt which is input into the successive approximation analog-to-digital converter to be calibrated, so that it generates different digital output codes; The state monitoring module detects the mode of the digital output code. If it meets the preset output mode, the selector responds to a control signal according to the position of "1" in the digital output code and injects it into the storage array unit to control it to write the corresponding digital calibration code; When in working mode, the method comprises: The state monitoring module detects the mode of the digital output code of the calibrated successive approximation analog-to-digital converter, records the number of "1"s in the digital output code and the position of each "1", and the selector responds to different control signals according to different digital output codes, and controls the storage array unit to read out corresponding digital calibration codes respectively; The data processing module acquires the digital calibration code periodically to perform data accumulation and chopping, and outputs a calibrated digital output code.

[0014] Compared with the prior art, the above technical solution conceived by the present invention can achieve the following beneficial effects: 1. The present invention provides a digital front-end calibration system for a successive approximation analog-to-digital converter based on RRAM. The storage part uses RRAM as a medium for storing digital signals. All digital signals are stored in RRAM, so that the stored data is non-volatile and will not be lost due to power-on or power-off. Therefore, stability is guaranteed. As long as the signal is written, there will be no signal leakage, so that the calibration accuracy is increased and the anti-interference ability is also enhanced. Therefore, the calibration system only needs to perform a calibration mode once for the SAR ADC. After obtaining enough calibration codes, the ADC does not need to be calibrated again and can directly enter the working mode. Therefore, the time consumed by calibration is greatly saved, the power consumption required for calibration is greatly reduced, and the speed is improved.

[0015] 2. The present invention provides a digital front-end calibration system for a successive approximation analog-to-digital converter based on RRAM. In the calibration mode, the stored N*M-bit digital calibration code is accumulated and replaces the digital output code of the SAR ADC to be calibrated, so that the dynamic performance of the ADC including the effective number of bits is significantly improved, the unit capacitance value of the ADC is reduced, and its energy consumption is greatly reduced, the energy efficiency of the calibrated ADC is improved, and its area is reduced.

[0016] 3. The digital front-end calibration system for a successive approximation analog-to-digital converter based on RRAM provided by the present invention mainly includes a multiplexer, an accumulator and a storage array composed of RRAM, which can use relatively simple hardware overhead to complete the calibration function, reduce the area of ​​the entire system, and improve the energy efficiency of the system. Among them, RRAM is used to replace the traditional SRAM for data storage. RRAM has the advantages of small area, low power consumption and high integration, so it can greatly save the area and power consumption required for storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a system structure block diagram of the calibration code detection, search and reading part in the digital front-end calibration system of the successive approximation analog-to-digital converter based on RRAM in the embodiment of the present application.

[0018] Figure 2 It is a system structure block diagram of the calibration code readout part in the digital foreground calibration system of the successive approximation analog-to-digital converter based on RRAM in the embodiment of the present application.

[0019] Figure 3 This is the calibration principle of the digital front-end calibration system for the successive approximation analog-to-digital converter based on RRAM in the embodiment of the present application.

[0020] Figure 4 It is a flow chart of a calibration algorithm of a digital front-end calibration system for a successive approximation analog-to-digital converter based on RRAM in an embodiment of the present application.

[0021] Figure 5 It is a schematic diagram of the RRAM storage array structure in an embodiment of the present application.

[0022] Figure 6 Schematic diagram of a specific circuit structure of an RRAM storage unit in an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0024] The contents involved in the above embodiment are described below in conjunction with a preferred embodiment.

[0025] Embodiment 1 The present invention provides a digital front-end calibration system for a successive approximation analog-to-digital converter based on RRAM, comprising: a step voltage generation module, a state monitoring module, an information storage module and a data processing module; the step voltage generation module is only effective in a calibration mode and is turned off in a working mode; the data processing module is turned off in the calibration mode and is effective in the working mode; The step voltage generating module includes a counter with an N+M bit width and a digital-to-analog converter with an N+M bit resolution, wherein the input end of the counter is connected to an external clock, and the output end is connected to the input end of the digital-to-analog converter, and the output end of the digital-to-analog converter is connected to the input end of the successive approximation analog-to-digital converter to be calibrated; the counter is used to generate a continuously self-increasing digital code, and the digital-to-analog converter is used to convert the digital code into a continuously increasing analog step voltage Vt, and output it to the successive approximation analog-to-digital converter to be calibrated; wherein M and N are both positive integers; The state monitoring module includes a state detection logic unit and a selector; in the calibration mode, the input end of the state detection logic unit is connected to the output end of the successive approximation analog-to-digital converter to be calibrated, the output end is connected to the input end of the selector, and the output end of the selector is connected to the information storage module; the state detection logic unit is used to detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and the selector is used to respond to different control signals according to the mode of the digital output code; in the working mode, the input end of the state monitoring logic unit is connected to the output end of the successive approximation analog-to-digital converter to be calibrated, the state detection logic unit is used to detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and the selector is used to respond to different control signals according to the mode of the digital output code; The information storage module includes an address control unit and a storage array unit based on RRAM; in a calibration mode, the storage array unit is connected to the counter and is used to store the N (N+M)-bit digital calibration code generated by the step voltage generation module; the address control unit is used to select different columns in the storage array according to the control signal output by the state monitoring module, and write the digital calibration code into the storage array; in an operating mode, the storage array unit is connected to the data processing module, and the address control unit is used to select different columns in the storage array according to the control signal output by the state monitoring module, and read the digital calibration code from the storage array; The data processing module includes an N+M-bit data accumulator and an N-bit data chopper, the input end of the data accumulator is connected to the information storage module, and the output end is connected to the input end of the data chopper; the data accumulator is used to accumulate the N+M-bit digital calibration code selected in the information storage module, and the data chopper is used to chop the data and only retain the first N bits as the output of the calibrated successive approximation analog-to-digital converter.

[0026] The RRAM-based digital foreground calibration method provided by the present invention is divided into two parts when it is actually working. First, it enters the calibration mode. After the calibration is completed, it enters the working mode when the ADC to be calibrated is working, that is, the calibration code calculated and stored in the calibration mode is read out to calibrate the output code of the ADC. The hardware system structure block diagram of the calibration mode of the RRAM-based digital foreground calibration method is as follows: Figure 1 The hardware system corresponding to the calibration mode is mainly composed of four modules, namely, the step voltage generation module, the ADC module to be calibrated, the state monitoring module and the information storage module.

[0027] After the calibration mode is completed, the SAR ADC being calibrated completes the calibration and enters the working mode. The hardware system corresponding to the working mode is mainly composed of four modules, namely the ADC module to be calibrated, the status monitoring module, the information storage module and the data processing module. The system block diagram of the data readout and processing part of the digital foreground calibration solution based on RRAM in the SAR ADC working mode is as follows Figure 2 shown.

[0028] In the calibration mode, the analog step voltage Vt generated by the step voltage generation module is stored and input into the successive approximation analog-to-digital converter to be calibrated. After the analog step voltage Vt passes through the analog-to-digital converter, a digital output code is generated. The state detection module receives the digital output code of the ADC to be calibrated and detects its mode, and selectively stores the digital output code in the corresponding position of the storage array as a digital calibration code. The RRAM storage array is composed of storage cells composed of a 7T2R structure. In the working mode, the information storage module continuously inputs data into the data processing module for accumulation and chopping to generate a calibrated output code.

[0029] Through the above structure, the effective accuracy and conversion linearity of the calibrated SAR ADC can be improved, and the requirements of the calibrated SAR ADC on the size and area of ​​the unit capacitor in the DAC can be reduced. The power consumption of the digital-to-analog conversion can be reduced by foreground calibration, and a non-volatile memristor is introduced for storage, which improves the stability of the data and reduces the calibration cycle.

[0030] Optionally, the counter receives an external clock signal and self-increments the output at each rising edge of the clock to generate a digital code with a bit width of N+M bits; The digital-to-analog converter periodically converts the digital output code of the counter into an analog voltage under the control of the system clock to obtain a step voltage Vt, which is output to a successive approximation analog-to-digital converter; the step voltage Vt includes all situations of the N-bit digital output.

[0031] Optionally, in the calibration mode, the state monitoring module is used to automatically detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and detect whether the mode is that only one bit is "1" and all other bits are "0". If the detection result is true, the position of "1" in the digital output code is detected, and the selector is used to output different control signals to the information storage module according to the detected position response; if the detection result is false, this calibration cycle is directly skipped; In the working mode, the status monitoring module is used to automatically monitor the mode of the digital output code of the calibrated successive approximation analog-to-digital converter, detect the number n of digital codes containing "1", and set the working cycle of this working mode to n, and detect the number of bits of each "1" in the digital output code. The selector is used to respond to different control signals for each different "1" in the next n working cycles.

[0032] The scheme of the present invention is described in detail with reference to the accompanying drawings. Figure 3 As shown in FIG. 1 , a calibration principle diagram of the digital front-end calibration scheme of the RRAM-based SAR ADC is shown in FIG. A counter generates a continuously self-increasing digital input signal Din, and the number of bits of the digital signal is N+N. extra bits, where N refers to the resolution N of the SAR ADC being calibrated, N extra It refers to the difference between the number of bits of the digital signal output by the counter and the number of bits of the ADC. The continuously self-added digital input signal Din drives an ideal DAC, making the DAC generate a very ideal rising step signal Vt. The step signal Vt is input to the calibrated SAR ADC and sampled by the ADC. After N conversion cycles, the calibrated SAR ADC outputs an N-bit digital signal Dout.

[0033] When the output result Dout is 00...001, that is, only the LSB is '1' and the rest are all '0', then the corresponding Din in this case will be stored in the register implemented by RRAM. After the subsequent calibration mode is completed, the SAR ADC enters the working mode. When the LSB code is '1' in the SAR ADC working mode, then the Din will be called to replace the Dout output at this time. Then the step signal Vt continues to rise and is continuously input into the calibrated ADC. When the output result Dout of the ADC is 00...010, the above process is repeated and its corresponding Din is stored in the corresponding RRAM register. Then the Vt signal continues to rise until the corresponding registers of all bits of Dout store the corresponding calibration code Din, and the calibration mode ends.

[0034] like Figure 4As shown in FIG. 1 , the flow chart of the calibration algorithm of the digital foreground calibration scheme of the RRAM-based SAR ADC is shown. The ideal step signal Vt(i) generated by the counter and the ideal DAC is sampled and input by the SAR ADC. After N conversion cycles, the ADC outputs an N-bit digital signal Dout. Then the output mode detection module detects whether Dout contains only one '1' and the rest of the bits are '0'. If the detection result is yes, the detection module will continue to detect whether the register corresponding to the corresponding bit with the code value of '1' is empty. If the corresponding register is empty, then the corresponding Din, that is, the calibration code corresponding to the bit, will be written into the RRAM-based register; if the corresponding register is not empty, then the cycle ends, the output value i of the counter is incremented by 1, and then the step signal Vt rises and continues to be input into the SAR ADC to start the next cycle; if the detection result is that Dout does not contain only one '1', then the current cycle ends early and directly enters the next cycle as described above.

[0035] There are two judgment conditions for the end of the calibration mode. If any one of the conditions is met, the calibration is considered to be completed. The two judgment conditions are: every time a write operation to the RRAM register is completed, the status of all registers is checked. If all RRAM registers are filled, the calibration is considered to be completed; or every time the output i of the counter is incremented once, it is judged whether the value of i is less than 2. N+Nextra If the judgment result is no, the calibration is also considered completed.

[0036] Optionally, in the calibration mode, the address control unit in the information storage module is used to receive the control signal responded by the state detection module, select the columns at different positions in the storage array, and store the digital output code corresponding to the cycle in the corresponding position as the digital calibration code; In working mode, the address control unit in the information storage module is used to receive the control signal responded by the state detection module, select columns at different positions in the storage array, and read out the digital calibration code stored in the storage array periodically and transmit it to the data processing module.

[0037] like Figure 5 The schematic diagram of the RRAM storage array structure is shown in Figure 1. The information storage module mainly consists of two parts, namely the 8*10 storage array based on RRAM and the address control logic module. The address control logic mainly includes a counter, an address pointer and some small control logic.

[0038] In this embodiment, N=8 and M=2 are set. In this embodiment, the capacity of the RRAM storage array is 8*10, where 8 is the resolution N of the SAR ADC being calibrated in this embodiment, and 10 is the bit width N+N of the output of the counter in this embodiment. extra. The RRAM storage array contains 8 RRAM registers, each of which is 10 bits wide. Among them, each bit of data is stored by a storage unit composed of a 7T2R structure based on RRAM. In addition, the RRAM storage array has a pointer controlled by the mode detection logic. After the mode detection module detects that the output Dout of the SAR ADC at a certain moment meets the mode detection condition, it confirms the location of the '1' in Dout, and passes the address of the bit to the pointer in the RRAM storage array, so that the pointer points to the corresponding 10-bit register in the RRAM storage array, so that the corresponding 10-bit calibration code Din is stored in the corresponding register in the RRAM storage array. When the input signal Vt scans from 0 to the MSB bit of the calibrated SAR ADC, that is, the pointer finally points to the register corresponding to the MSB in the RRAM storage array, after the write action is executed, it can be directly regarded as the completion of the calibration, saving the subsequent unnecessary calibration cycle and shortening the time required for the calibration mode. Compared with the full range of Vt scanning, this solution can save 50% of the calibration cycle.

[0039] In the above content, each storage unit of the 8*10 RRAM storage array is not composed of traditional SRAM or DRAM, but is composed of a 7T2R structure based on RRAM. The schematic diagram of the structure is shown in the attached figure. Figure 6 shown.

[0040] Optionally, the number of the storage array units is N*(N+M); each of the storage array units includes 7 MOS tubes and 2 RRAMs, wherein 3 MOS tubes are used as signal selection switches, 4 MOS tubes constitute end-to-end inverters to enhance storage signals, and 2 RRAMs are used as media for storing information; In the calibration mode, the storage array unit is in a write mode, and the digital calibration codes are written one by one; In the working mode, the storage array unit is in the reading mode, and reads the digital calibration codes one by one to the data processing module.

[0041] Specifically, the storage array unit is composed of three transistors for controlling switches, two RRAM units for information storage, and two inverters connected end to end, which are composed of four transistors. The input end of the storage unit is the drain of the switch tube, named Din, and the output end is the source of the switch tube, named Dout. The gate of the switch tube is controlled by the WR signal, and the gates of the other two switch tubes are controlled by the E signal and the R signal, respectively. Here, WR represents read and write operations, E represents enable, and R represents read operations. The source of the switch transistor controlled by the E signal is connected to the memristor R1, and the other end of the memristor R1 is connected to the voltage Vc for storing the written 1 bit of information; the source of the switch transistor controlled by the R signal is connected to the memristor R2, and the other end of the memristor R2 is connected to the ground for reading out the 1 bit of information stored by the memristor R1.

[0042] Furthermore, the working principle of the 7T2R cell based on RRAM is: In the reset phase, all control signals, namely the WR signal, the E signal and the R signal, are at low level, the three controlled switch transistors are turned off, and the initial states of the memristors R1 and R2 are both high impedance. When a 1-bit signal Din requests to be written, the WR signal changes from low level to high level, indicating that the signal is valid, and the controlled switch transistor is turned on at the same time, and Din is directly connected to the next node. At this time, the E signal also changes from low level to high level, indicating that the signal is valid. At the same time, the controlled switch transistor is turned on, but the R signal is still at a low level at this time, that is, the switch transistor controlled by the R signal is still in the off state. At this time, Din will only be transmitted to the lower plate of the memristor R1, and the memristor R1 writes and stores the information by reducing the resistance state or keeping the resistance state unchanged; when Din is 1, the memristor R1 changes from a high resistance state to a low resistance state, indicating that "1" is stored; when Din is 0, the memristor R1 maintains the initial high resistance state unchanged, indicating that "0" is stored, waiting for the next clock cycle to come, the WR signal and the E signal are reset to a low level, the switch tube is turned off, and the writing of the information is completed. The information is stored in the form of different resistance states of the memristor R1.

[0043] When the stored 1-bit signal request is read out, at this time, the WR signal remains at a low level and remains unchanged, the controlled switch tube is turned off, isolating the input and output, and then the E signal and the R signal are both changed from low level to high level at the same time, indicating that the signal is valid, and the two controlled switch transistors are turned on at the same time. At this time, a short pulse signal is input to the Vc terminal. At this time, since both the E signal and the R signal are valid, the memristors R1 and R2 can be regarded as straight-through, and the stored information can be read out through the resistance voltage division of the two memristors. If the stored information is "1", then the memristor R1 is in a low resistance state and the memristor R2 is in a high resistance state. After the resistance voltage division of the memristor, the output end outputs Vc, so only To control the value of Vc to be greater than half of VDD, the output can be pulled to "1" through the subsequent inverter; if the stored information is "0", then the memristor R1 is in a high impedance state, and the memristor R2 is also in a high impedance state. After the resistance voltage division of the memristor, the output end output is approximately Vc / 2. Therefore, as long as the value of Vc / 2 is controlled to be less than half of VDD, the output can be pulled to "0" through the subsequent inverter. Therefore, as long as the high level Vc of the short pulse is controlled to be less than VDD but greater than VDD / 2, such as 3 / 4VDD, the signal can be read correctly, and sufficient noise margin is left at both the upper and lower ends, which increases the accuracy and stability of the signal reading. The two inverters connected end to end are responsible for maintaining the signal during both read and write operations, especially during read operations, enhancing the signal driving capability.

[0044] Optionally, the data accumulator of the data processing module is used to accumulate the received N+M-bit digital calibration code and determine whether the accumulated result exceeds N+M bits. If so, N+M-bit "1" is output; if not, the data chopper performs a chopping operation on the accumulated data and only retains the high N bits of the data as output.

[0045] In the embodiment of the present invention, the storage part uses RRAM as a medium for storing digital signals, and all digital signals are stored in RRAM, so that the data stored in it is non-volatile and will not be lost due to power-on and power-off; the calibration system only needs to perform a calibration mode once for the SAR ADC, and after obtaining enough calibration codes, the ADC can be used again without calibration, and can directly enter the working mode. By reducing the unit capacitance area of ​​the SAR ADC to reduce its power consumption, and using RRAM to store it, it is non-volatile and suitable for the application scenario of in-memory computing. It solves the technical problem that the existing digital front-end calibration scheme is not non-volatile, resulting in the loss of stored data after each power failure, and the calibration mode must be entered before work each time, which greatly wastes time and energy. It achieves improved calibration stability and anti-interference, and has a smaller area and lower power consumption; saves the time consumed by calibration and the required power consumption, and improves the speed.

[0046] Embodiment 2 The present invention also provides a digital foreground calibration method for a successive approximation analog-to-digital converter based on RRAM, which is performed based on the digital foreground calibration system for a successive approximation analog-to-digital converter based on RRAM as described in any one of the first embodiments, for a successive approximation analog-to-digital converter to be calibrated, a calibration mode is first performed, and the subsequent modes are all working modes; When in calibration mode, the method comprises: The step voltage generating module generates a step voltage Vt which is input into the successive approximation analog-to-digital converter to be calibrated, so that it generates different digital output codes; The state monitoring module detects the mode of the digital output code. If it meets the preset output mode, the selector responds to a control signal according to the position of "1" in the digital output code and injects it into the storage array unit to control it to write the corresponding digital calibration code; When in working mode, the method comprises: The state monitoring module detects the mode of the digital output code of the calibrated successive approximation analog-to-digital converter, records the number of "1"s in the digital output code and the position of each "1", and the selector responds to different control signals according to different digital output codes, and controls the storage array unit to read out corresponding digital calibration codes respectively; The data processing module acquires the digital calibration code periodically to perform data accumulation and chopping, and outputs a calibrated digital output code.

[0047] In a specific embodiment, when the calibration mode starts, a rising edge of a starting clock is waited for, and the counter starts working and outputs a 10-bit self-increasing digital code. Compared with the 8-bit SAR ADC to be calibrated in this embodiment, the digital code is 2 bits redundant. Since these calibration codes are accumulated to replace the output code of the SAR ADC for calibration in the working mode, the 2-bit precision redundancy is moderate. While increasing the calibration accuracy, too many RRAM storage units are not introduced, which also reduces the complexity of the logic circuit involved, saving power consumption and hardware overhead.

[0048] The 10-bit self-added digital code is input into a 10-bit DAC. At this time, the self-added digital code is converted into an ideal step voltage Vt in the analog domain. The accuracy of Vt, that is, the step size of the step voltage, is 1 LSB value of the 10-bit DAC. Since the resolution or accuracy of the front-stage DAC is higher than the 8-bit SAR ADC to be calibrated in the subsequent stage, the step size of the step voltage is small enough to cover all equivalent input signals of the subsequent stage SAR ADC. That is, after the 10-bit precision step signal Vt is input into the 8-bit SAR ADC to be calibrated, the output code value of the ADC must increase gradually from the minimum value 0...00 to the maximum value 1...11, which can cover the possibility of all output code values ​​of the 8-bit SAR ADC. Then, among the output codes of these ADCs, there must be all output codes that meet the state detection conditions, and no missing codes will appear.

[0049] The output code of the 8-bit SAR ADC with the above characteristics is input into the state monitoring module, and the state monitoring module will automatically detect the output code of the ADC that meets the conditions and perform subsequent operations at the same time. This module consists of two parts, namely the state detection logic and an 8-to-1 data selector. According to the aforementioned calibration algorithm, the state detection logic will detect the ADC output code with the characteristics of only 1 bit "1" and the rest of the bits are "0". If the detection logic finds that a certain ADC output code meets the characteristics required or specified by all algorithms, such as 0...010, then the detection logic will regard the output code as a valid signal, and generate different 3-bit selection signals according to the code position of "1" in the output code to control the subsequent 8-to-1 selector. Assuming that the code position of "1" is the nth bit of the output code, the detection logic will generate a 3-bit selection signal representing n-1. For example, if the code value "1" in this example is in the second bit of the ADC output code, then after the detection logic, a 3-bit selection signal sel representing "1" will be generated, that is, 001 to control the subsequent logic circuit. If the detected ADC output code is 010...0, then the detection logic will generate a selection signal sel<2:0> representing "6", that is, 110. Then the selection signal sel<2:0> passes through the 8-to-1 selector to select a unique valid address channel corresponding to the "1" in different code positions in the ADC output code.

[0050] In the information storage module, the address pointer initially points to the first column of 10-bit RRAM-based storage units, which corresponds to the LSB of the 8-bit SAR ADC to be calibrated. When receiving the channel selection signal from the 8-to-1 selector, the address pointer selects a column of RRAM registers, and then stores the 10-bit calibration code corresponding to the cycle into the corresponding RRAM column storage unit, that is, the RRAM column pointed to by the address pointer at this time. When the 8*10 RRAM array is full of 8 columns of 10-bit calibration codes, that is, when the address pointer points to the address of the highest column of RRAM registers and the column register is not empty, a finish signal is generated to indicate that the calibration mode is over and the calibration is completed. 8 columns of 10-bit calibration codes have been stored in the RRAM storage array, and these calibration codes correspond to the calibration codes when the output mode of the ADC to be calibrated is 0...01 to 10...0 from low to high.

[0051] After the calibration mode is completed, the calibrated SAR ADC completes the calibration and starts to enter the working mode. The system block diagram of the data readout and processing part of the RRAM-based digital foreground calibration solution in the SAR ADC working mode is as follows: Figure 2As shown. When the calibrated 8-bit SAR ADC completes a data conversion, it generates an 8-bit digital output code, which is called the pre-calibration output code here. The readout control logic in the readout control module is responsible for reading the pre-calibration output code of the SAR ADC. First, the number of bits in the pre-calibration output code is detected, and the number of "1" in the pre-calibration output code is calculated through a detection accumulation logic. If there are n "1", the working cycle of the entire digital front-end calibration module is set to n; then each cycle detects which bit each "1" is located at, and controls the subsequent MUX 8-to-1 selector according to the readout control logic to generate different outputs and select different stored calibration codes. For example, the 8-bit pre-calibration output code generated by the calibrated 8-bit SAR ADC in a certain conversion cycle is 1001_0010, then the readout control logic will accumulate the number of "1" in the pre-calibration output code in turn, which is 3 in this example, and then the timing control module sets the working cycle of the digital front-end calibration module to 3. In the first working cycle, the position of the lowest bit "1" in "1" is first detected, which is the second bit in this example, so the read control logic will pass the information "2" to the subsequent information storage module through the subsequent 8-to-1 selector, and select the 10-bit calibration code stored in the second column of the RRAM-based register corresponding to the information "2" through the address control module. Similarly, in the second working cycle, the position of the second lowest bit "1" in "1" is detected, which is the fifth bit in this example, so the read control logic will pass the information "5" to the subsequent information storage module through the subsequent 8-to-1 selector, and select the 10-bit calibration code stored in the fifth column of the RRAM-based register corresponding to the information "5" through the address control module. Finally, in the third working cycle, the position of the highest bit of "1" in the detection "1" is the eighth bit in this example, so the read control logic will pass the information "8" to the subsequent information storage module through the subsequent 8-to-1 selector, and select the 10-bit calibration code stored in the 8th column of the RRAM-based register corresponding to the information "8" through the address control module.

[0052] After the readout control module completes the detection of the number of "1"s in the output code before calibration and the extraction of the information of the bit where each "1" is located, the 8*10 RRAM storage array in the information storage module outputs the corresponding 10-bit digital calibration code to the data accumulator in the subsequent data processing module in a periodic manner under the control of the address control module, and extracts one column of 10-bit calibration code corresponding to a certain "1" in the output code before calibration in each working cycle. When it reaches the last working cycle specified by the timing control module, an EN valid signal is sent to the data processing module, and the module starts to process all the received data. First, the data accumulator continuously accumulates n 10-bit calibration codes from the 8*10 RRAM storage array. Here n depends on the number of "1"s in the pre-calibration output code of the calibrated SAR ADC detected by the readout control module. When the accumulation is completed, since the accumulation result is a 10-bit digital code, and what we need is an 8-bit calibrated output code, the 10-bit accumulated digital code is input into the data chopper for data chopping, taking only the upper eight bits of the data, and the final output is the 8-bit calibration output. At this point, the digital foreground calibration under the SAR ADC working mode is completed.

[0053] The execution of a digital foreground calibration method for a successive approximation analog-to-digital converter based on RRAM provided in an embodiment of the present invention depends on a digital foreground calibration system for a successive approximation analog-to-digital converter based on RRAM provided in any embodiment of the present invention, and has corresponding beneficial effects.

[0054] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A digital front-end calibration system for a successive approximation analog-to-digital converter based on RRAM, characterized in that: include: A step voltage generation module, a state monitoring module, an information storage module and a data processing module; the step voltage generation module is only effective in the calibration mode and is turned off in the working mode; the data processing module is turned off in the calibration mode and is effective in the working mode; The step voltage generation module includes a counter with an N+M bit width and a digital-to-analog converter with an N+M bit resolution, wherein the input end of the counter is connected to an external clock, the output end is connected to the input end of the digital-to-analog converter, and the output end of the digital-to-analog converter is connected to the input end of the successive approximation analog-to-digital converter to be calibrated; The counter is used to generate a continuously self-increasing digital code, and the digital-to-analog converter is used to convert the digital code into a continuously increasing analog step voltage Vt, and output it to the successive approximation analog-to-digital converter to be calibrated; wherein M and N are both positive integers; The state monitoring module includes a state detection logic unit and a selector; in the calibration mode, the input end of the state detection logic unit is connected to the output end of the successive approximation analog-to-digital converter to be calibrated, the output end is connected to the input end of the selector, and the output end of the selector is connected to the information storage module; the state detection logic unit is used to detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and the selector is used to respond to different control signals according to the mode of the digital output code; in the working mode, the input end of the state monitoring logic unit is connected to the output end of the successive approximation analog-to-digital converter to be calibrated, the state detection logic unit is used to detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and the selector is used to respond to different control signals according to the mode of the digital output code; The information storage module includes an address control unit and a storage array unit based on RRAM; in a calibration mode, the storage array unit is connected to the counter and is used to store the N (N+M)-bit digital calibration code generated by the step voltage generation module; the address control unit is used to select different columns in the storage array according to the control signal output by the state monitoring module, and write the digital calibration code into the storage array; in an operating mode, the storage array unit is connected to the data processing module, and the address control unit is used to select different columns in the storage array according to the control signal output by the state monitoring module, and read the digital calibration code from the storage array; The data processing module includes an N+M-bit data accumulator and an N-bit data chopper, the input end of the data accumulator is connected to the information storage module, and the output end is connected to the input end of the data chopper; the data accumulator is used to accumulate the N+M-bit digital calibration code selected in the information storage module, and the data chopper is used to chop the data and only retain the first N bits as the output of the calibrated successive approximation analog-to-digital converter.

2. The system according to claim 1, characterized in that The counter receives an external clock signal and self-increments the output at each rising edge of the clock to generate a digital code with a bit width of N+M bits; The digital-to-analog converter periodically converts the digital output code of the counter into an analog voltage under the control of the system clock to obtain a step voltage Vt, which is output to a successive approximation analog-to-digital converter; the step voltage Vt includes all situations of the N-bit digital output.

3. The system according to claim 2, characterized in that In the calibration mode, the state monitoring module is used to automatically detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and detect whether the mode is that only one bit is "1" and all other bits are "0". If the detection result is true, the position of the "1" in the digital output code is detected, and the selector is used to respond to different control signals according to the detected position and output them to the information storage module; If the test result is false, this calibration cycle is skipped directly; In the working mode, the state monitoring module is used to automatically monitor the mode of the digital output code of the calibrated successive approximation analog-to-digital converter, detect the number n of digital codes containing "1", and set the working cycle of this working mode to n, and detect the number of bits of each "1" in the digital output code. The selector is used to respond to different control signals for each different "1" in the next n working cycles.

4. The system according to claim 1, characterized in that In the calibration mode, the address control unit in the information storage module is used to receive the control signal responded by the state detection module, select the columns at different positions in the storage array, and store the digital output code corresponding to the cycle in the corresponding position as the digital calibration code; In working mode, the address control unit in the information storage module is used to receive the control signal responded by the state detection module, select columns at different positions in the storage array, and read out the digital calibration code stored in the storage array periodically and transmit it to the data processing module.

5. The system according to claim 4, characterized in that The number of the storage array units is N*(N+M); each of the storage array units includes 7 MOS tubes and 2 RRAMs, wherein 3 MOS tubes are used as signal selection switches, 4 MOS tubes form inverters connected end to end to enhance storage signals, and 2 RRAMs are used as media for storing information; In the calibration mode, the storage array unit is in a write mode, and the digital calibration codes are written one by one; In the working mode, the storage array unit is in the reading mode, and reads the digital calibration codes one by one to the data processing module.

6. The system according to claim 1, characterized in that The data accumulator of the data processing module is used to accumulate the received N+M-bit digital calibration code and determine whether the accumulated result exceeds N+M bits. If so, N+M-bit "1" is output; if not, the data chopper chops the accumulated data and only retains the high N bits of the data as output.

7. The system according to claim 1, characterized in that N=8,M=2.

8. A digital foreground calibration method for a successive approximation analog-to-digital converter based on RRAM, performed based on a digital foreground calibration system for a successive approximation analog-to-digital converter based on RRAM as claimed in any one of claims 1 to 7, characterized in that: For a successive approximation analog-to-digital converter to be calibrated, a calibration mode is first performed, and the subsequent modes are all working modes; When in calibration mode, the method comprises: The step voltage generating module generates a step voltage Vt which is input into the successive approximation analog-to-digital converter to be calibrated, so that it generates different digital output codes; The state monitoring module detects the mode of the digital output code. If it meets the preset output mode, the selector responds to a control signal according to the position of "1" in the digital output code and injects it into the storage array unit to control it to write the corresponding digital calibration code; When in working mode, the method comprises: The state monitoring module detects the mode of the digital output code of the calibrated successive approximation analog-to-digital converter, records the number of "1"s in the digital output code and the position of each "1", and the selector responds to different control signals according to different digital output codes, and controls the storage array unit to read out corresponding digital calibration codes respectively; The data processing module acquires the digital calibration code periodically to perform data accumulation and chopping, and outputs a calibrated digital output code.

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