Metastable state detector applied to successive approximation analog-to-digital converter and control method

Abstract

The invention discloses a metastable state detector applied to a successive approximation type analog-to-digital converter and a control method. The metastable state detector is in signal connection with an asynchronous logic control circuit; the input of the asynchronous logic control circuit is an output signal of the voltage comparator and a metastable state marking signal META output by the metastable state detector, and the output of the asynchronous logic control circuit is a clock control signal CLK and the output ADCout of the whole analog-to-digital converter; cLK is respectively input into a voltage comparator and a metastable state detector; the asynchronous logic control circuit executes a successive approximation algorithm according to the output of the voltage comparator and the META, generates ADCout and feeds back the ADCout to the digital-to-analog converter; the metastable state detector monitors the voltage comparator through the CLK and the META, and when the metastable state is detected, the META outputs a high level indication to drive the processing of the asynchronous logic control circuit; the metastable state detector controls the detection time sequence through CLK and CLKD, and meanwhile, a reset MOS tube is added to carry out multiple times of metastable state detection. According to the invention, the load of the analog-to-digital converter system is reduced, and metastable state detection can be realized for many times.

Description

Technical Field

[0001] The present invention relates to the field of analog / mixed signal integrated circuit design, and in particular to a metastable detector and a control method applied to a successive approximation analog-to-digital converter. Background Art

[0002] In the field of high-speed and high-precision analog-to-digital conversion, successive approximation analog-to-digital converters (SAR ADCs) are widely used in key systems such as 5G communications and medical imaging due to their excellent energy efficiency ratio. However, as the conversion rate moves towards the giga-sampling level, the metastable problem generated by the voltage comparator in the critical judgment state has become increasingly prominent, becoming the core bottleneck restricting system reliability. When the input signal amplitude is close to the quantization threshold, the positive feedback loop inside the comparator will enter the nonlinear working area due to insufficient signal establishment, resulting in unpredictable delay fluctuations in the logic judgment. This timing instability phenomenon will not only cause single conversion errors, but also cause error transmission in the multi-level successive approximation process. Traditional metastable detection methods are usually complicated. Traditional voltage domain detection schemes require the introduction of redundant comparison cycles or auxiliary reference voltages, resulting in an extension of the conversion cycle, or require additional channels, resulting in an increase in area and difficulty in multiple detections. The traditional time window monitoring method uses a delay circuit to monitor the comparator working cycle, but it often introduces additional loads at the output of the comparator and it takes too long to wait for the output result of the comparator. Moreover, existing metastable state detection methods are often limited to single-shot detection and are not suitable for application scenarios involving multiple metastable states. Summary of the invention

[0003] Aiming at the problem of bit errors caused by the voltage comparator entering a metastable state due to too small input signals in the existing SAR ADC, the present invention proposes a metastable detector and control method applied to a successive approximation analog-to-digital converter. The method is based on the dynamic detection mechanism and collaborative processing architecture of the time comparator, and realizes real-time identification of metastable states and system fault-tolerant control by quantizing the working state characteristics of the comparator. The metastable detector of the present invention supports multiple detections, which improves the anti-interference ability and accuracy of the system.

[0004] The purpose of the present invention is achieved through the following technical solutions: A metastable detector applied to a successive approximation analog-to-digital converter, the successive approximation analog-to-digital converter comprising a connected sampling and holding circuit, a digital-to-analog converter, a voltage comparator and an asynchronous logic control circuit; the metastable detector is signal-connected to the asynchronous logic control circuit; The input of the asynchronous logic control circuit is the output signal OUT of the voltage comparator and the metastable flag signal META output by the metastable detector, and the output is the clock control signal CLK and the output ADCout of the entire analog-to-digital converter; wherein the clock control signal CLK is input to the voltage comparator and the metastable detector respectively; the asynchronous logic control circuit performs a successive approximation algorithm according to the output of the voltage comparator and the metastable flag signal META, generates a final digital output ADCout, and feeds it back to the digital-to-analog converter for the next round of comparison; The input of the metastable detector is the clock control signal CLK, and the output is the metastable flag signal META; the metastable detector monitors the metastable state of the voltage comparator output through the clock control signal CLK and the metastable flag signal META, and when the metastable state is detected, the metastable flag signal META will output a high level indication to drive the processing of the asynchronous logic control circuit; the metastable detector controls the detection timing through the clock control signal CLK and the delay signal CLKD of the clock control signal CLK, and adds a reset MOS tube to perform multiple metastable detections.

[0005] Further, the metastable detector includes a time comparison unit, a threshold adjustment unit and a reset execution unit, wherein: The time comparison unit is composed of a cascaded delay circuit and a trigger, and is used to quantify the pulse width of the clock control signal CLK; the first input end of the time comparison unit is connected to the output end of the threshold adjustment unit, the second input end is connected to the clock control signal CLK, and the output end of the time comparison unit is connected to the drain of the reset execution unit to generate a metastable flag signal META; The threshold adjustment unit includes a programmable delay element for dynamically setting the pulse width detection threshold; the input of the threshold adjustment unit is the clock control signal CLK, the output is a delayed signal CLKD of the clock control signal, and the output is connected to the first input terminal of the time comparison unit; The reset execution unit includes a MOS tube switch circuit, which is used to reset the metastable flag signal META; the gate of the MOS tube switch circuit is connected to the inverted signal CLKB of the clock control signal; the source of the MOS tube switch circuit is grounded, and the drain is connected to the output end of the time comparison unit and connected to the metastable flag signal META.

[0006] Furthermore, the input end of the sampling and holding circuit is connected to the analog signal input port, and the output end is connected to the first input end of the voltage comparator; the sampling and holding circuit is used to receive the analog input signal, sample and hold the signal, and ensure that the signal is stably transmitted to the digital-to-analog converter.

[0007] Furthermore, the output end of the digital-to-analog converter is connected to the second input end of the voltage comparator, and the input end of the digital-to-analog converter is connected to the asynchronous logic control circuit; the digital-to-analog converter is used to receive the digital output signal ADCAout from the asynchronous logic control circuit and convert it into a corresponding analog signal for comparison with the analog input signal.

[0008] Furthermore, the voltage comparator is used to receive signals from the sampling and holding circuit and the digital-to-analog converter, as well as the clock control signal CLK output by the asynchronous logic control circuit, and generate a comparison result OUT, which is output to the asynchronous logic control circuit; during the comparison process, the voltage comparator may generate a metastable state and trigger the metastable detector.

[0009] Furthermore, the programmable delay element is implemented by a digitally controlled variable capacitor array.

[0010] Furthermore, the digital-to-analog converter is a capacitive digital-to-analog converter.

[0011] A control method for a metastable detector applied to a successive approximation analog-to-digital converter, comprising: Normal working stage: the voltage comparator works normally under the asynchronous logic control circuit, and the pulse width of the clock control signal CLK changes according to the size of the input signal; the metastable detector monitors the pulse width of the clock control signal CLK output by the asynchronous logic control circuit in real time; Comparison time judgment stage: compare the pulse width of the clock control signal with the pulse width preset threshold to determine whether the voltage comparator is in a normal working state: if the pulse width of the clock control signal is less than the pulse width preset threshold, the inverted signal CLKD of the clock control signal CLK triggers the trigger, and the metastable flag signal META is not triggered, and the voltage comparator is still in a normal working stage; otherwise, if the pulse width of the clock control signal is not less than the pulse width preset threshold, the metastable flag signal META is activated after CLKD triggers the trigger; Metastable processing stage: when the metastable detector detects that the pulse width of the clock control signal is not less than the preset pulse width threshold, a metastable flag signal META is generated and sent to the asynchronous logic control circuit; Reset working stage: after the metastable flag signal META is generated, the clock control signal CLK of the voltage comparator is reset, triggering the voltage comparator to reset and output a preset digital value; after the voltage comparator is reset, the clock control signal CLK generated by the asynchronous logic control circuit controls the metastable detector to reset; the analog-to-digital converter continues to work normally and waits for the next metastable processing.

[0012] The beneficial effects of the present invention are as follows: The metastable detector and control method applied to a successive approximation analog-to-digital converter of the present invention only use a clock control signal as the input of the metastable detector, thereby reducing the load on the analog-to-digital converter system. The metastable detector adopts a comparison processing reset process, and can realize metastable detection multiple times. The metastable detector of the present invention does not need to wait for the output result of the comparator, and can speed up the working speed of the analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The diagram is a circuit diagram of a metastable detector applied to a successive approximation register analog-to-digital converter according to one embodiment of the present invention.

[0014] Figure 2 FIG. 4 is a circuit diagram of a metastable detector according to one embodiment of the present invention.

[0015] Figure 3 The invention is a control timing diagram of a control method for a metastable detector applied to a successive approximation analog-to-digital converter. DETAILED DESCRIPTION

[0016] The present invention will be described in detail below based on the accompanying drawings and preferred embodiments, and the purpose and effects of the present invention will become more clear. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0017] Technical term explanation: S / H: sample and hold sampling and holding circuit DAC: digital analog converter Comp: comparator editor VIN: input voltage CLK: clock signal clock control signal META:Metastability signal OUT: output signal CLKD: Delayed clock signal Delayed signal of clock control signal CLKB: Inverted signal of the clock control signal like Figure 1As shown, the metastable detector of the present embodiment is applied to a successive approximation analog-to-digital converter, wherein the successive approximation analog-to-digital converter includes a sampling and holding circuit, a digital-to-analog converter, a voltage comparator and an asynchronous logic control circuit, and the metastable detector is signal-connected to the asynchronous logic control circuit. The digital-to-analog converter in the present embodiment is a capacitive digital-to-analog converter.

[0018] in: The input end of the sampling and holding circuit S / H is connected to the analog signal input port, and the output end is connected to the first input end of the voltage comparator; the sampling and holding circuit is used to receive the analog input signal, sample and hold the signal, and ensure that the signal is stably transmitted to the digital-to-analog converter DAC; The output end of the digital-to-analog converter DAC is connected to the second input end of the voltage comparator, and the input end is connected to the asynchronous logic control circuit; the digital-to-analog converter is used to receive the digital output signal from the asynchronous logic control circuit and convert it into a corresponding analog signal for comparison with the analog input signal.

[0019] The voltage comparator is used to receive the signal from the sampling and holding circuit and the digital-to-analog converter, as well as the clock control signal CLK output by the asynchronous logic control circuit, and generate a comparison result OUT, which is output to the asynchronous logic control circuit. During the comparison process, the voltage comparator may generate a metastable state, which will trigger the metastable detector.

[0020] The first input of the asynchronous logic control circuit is the output signal OUT of the voltage comparator, the second input is the metastable flag signal META output by the metastable detector, the first output is the clock control signal CLK, which is output to the voltage comparator and the metastable detector; the second output is the output ADCout of the entire analog-to-digital converter. The asynchronous logic control circuit performs a successive approximation algorithm based on the output of the voltage comparator and the metastable flag signal META, generates the final digital output ADCout, and feeds it back to the digital-to-analog converter DAC for the next round of comparison.

[0021] The input of the metastable detector is the clock control signal CLK, and the output is the metastable flag signal META. The metastable detector is implemented by a simple clock comparator. The clock control signal CLK and the metastable flag signal META monitor the metastable state output by the voltage comparator. When the metastable state is detected, the metastable flag signal META will output a high level indication to drive the processing of the asynchronous logic control circuit. The metastable detector controls the detection timing through the CLK and CLKD signals, and a reset MOS tube is added to perform multiple metastable detections.

[0022] like Figure 2 As shown, the metastable detector includes a time comparison unit FF, a threshold adjustment unit and a reset execution unit, wherein: The time comparison unit FF is composed of a trigger and is used to quantify the pulse width of the clock control signal; the first input end of the time comparison unit is connected to the output end of the threshold adjustment unit, the second input end is connected to the clock control signal CLK, and the output end of the time comparison unit is connected to the drain of the reset execution unit to generate a metastable flag signal META; The threshold adjustment unit includes a programmable delay element for dynamically setting the pulse width detection threshold; the input of the threshold adjustment unit is connected to the clock control signal CLK, generates a delay signal CLKD of the clock control signal, and outputs it to the first input end of the time comparison unit. In this embodiment, the programmable delay element is implemented by a digitally controlled variable capacitor array, and the detection sensitivity is changed by adjusting the RC time constant to ensure the accuracy and reliability of signal conversion.

[0023] The reset execution unit includes a MOS tube switch circuit for resetting the metastable flag signal META; the gate of the MOS tube switch circuit is connected to the inverted signal CLKB of the clock control signal; the source is grounded, the drain is connected to the output end of the time comparison unit, and is connected to the metastable flag signal META.

[0024] The timing control method of the present invention includes four main signals: CLK, CLKD, META and output signal ADCout. CLK is a global clock that drives the operation of the voltage comparator; the META signal is used to indicate the metastable state and is fed back to the asynchronous logic control circuit; the inverted signal CLKB of the clock control signal CLK controls the operation and reset of the metastable detector for multiple detections. The metastable flag signal META of the metastable detector is controlled by the clock signal CLK and its delayed signal CLKD.

[0025] like Figure 3 As shown, the circuit control method includes the following steps: (a) Normal working stage: The voltage comparator works normally under the asynchronous logic control circuit, and the pulse width of the clock control signal CLK changes according to the size of the input signal; the metastable detector monitors the pulse width of the clock control signal CLK output by the asynchronous logic control circuit in real time; (b) Comparison time judgment stage: compare the pulse width of the clock control signal with the pulse width preset threshold to determine whether the voltage comparator is in normal working state; specifically: if the pulse width of the clock control signal is less than the pulse width preset threshold, the inverted signal CLKD of the clock control signal CLK triggers the trigger, the metastable flag signal META is not triggered, and the voltage comparator is still in normal working stage; otherwise, if the pulse width of the clock control signal is not less than the pulse width preset threshold, the metastable flag signal META is activated after CLKD triggers the trigger. Since the metastable detector uses the clock control signal CLK of the voltage comparator as input, the impact on the normal operation of the analog-to-digital converter is reduced.

[0026] (c) Metastable processing stage: When the metastable detector detects that the pulse width of the clock control signal is not less than the preset pulse width threshold, a metastable flag signal META is generated and sent to the asynchronous logic control circuit.

[0027] (d) Reset working stage: After the metastable flag signal META is generated, the clock control signal CLK of the reset voltage comparator triggers the voltage comparator to reset and output a preset digital value. After the voltage comparator is reset, the clock control signal CLK generated by the asynchronous logic control circuit controls the metastable detector to reset, and the analog-to-digital converter continues to work normally and waits for the next metastable processing.

[0028] Those skilled in the art can understand that the above are only preferred examples of the invention and are not intended to limit the invention. Although the invention is described in detail with reference to the above examples, those skilled in the art can still modify the technical solutions recorded in the above examples or replace some of the technical features therein with equivalents. Any modification, equivalent replacement, etc. made within the spirit and principle of the invention shall be included in the protection scope of the invention.

Claims

1. A metastable detector for a successive approximation analog-to-digital converter, characterized in that: The successive approximation analog-to-digital converter comprises a connected sampling and holding circuit, a digital-to-analog converter, a voltage comparator and an asynchronous logic control circuit; the metastable detector is signal-connected to the asynchronous logic control circuit; The input of the asynchronous logic control circuit is the output signal OUT of the voltage comparator and the metastable flag signal META output by the metastable detector, and the output is the clock control signal CLK and the output ADCout of the entire analog-to-digital converter; wherein the clock control signal CLK is input to the voltage comparator and the metastable detector respectively; the asynchronous logic control circuit performs a successive approximation algorithm according to the output of the voltage comparator and the metastable flag signal META, generates a final digital output ADCout, and feeds it back to the digital-to-analog converter for the next round of comparison; The input of the metastable detector is the clock control signal CLK, and the output is the metastable flag signal META; the metastable detector monitors the metastable state of the voltage comparator output through the clock control signal CLK and the metastable flag signal META, and when the metastable state is detected, the metastable flag signal META will output a high level indication to drive the processing of the asynchronous logic control circuit; the metastable detector controls the detection timing through the clock control signal CLK and the delay signal CLKD of the clock control signal CLK, and adds a reset MOS tube to perform multiple metastable detections.

2. The metastable detector for a successive approximation analog-to-digital converter according to claim 1, characterized in that: The metastable detector comprises a time comparison unit, a threshold adjustment unit and a reset execution unit, wherein: The time comparison unit is composed of a trigger, and is used to quantify the pulse width of the clock control signal CLK; the first input end of the time comparison unit is connected to the output end of the threshold adjustment unit, the second input end is connected to the clock control signal CLK, and the output end of the time comparison unit is connected to the drain of the reset execution unit to generate a metastable flag signal META; The threshold adjustment unit includes a programmable delay element for dynamically setting the pulse width detection threshold; the input of the threshold adjustment unit is the clock control signal CLK, the output is a delayed signal CLKD of the clock control signal, and the output is connected to the first input terminal of the time comparison unit; The reset execution unit includes a MOS tube switch circuit, which is used to reset the metastable flag signal META; the gate of the MOS tube switch circuit is connected to the inverted signal CLKB of the clock control signal; the source of the MOS tube switch circuit is grounded, and the drain is connected to the output end of the time comparison unit and connected to the metastable flag signal META.

3. The metastable detector for a successive approximation analog-to-digital converter according to claim 2, characterized in that: The input end of the sampling and holding circuit is connected to the analog signal input port, and the output end is connected to the first input end of the voltage comparator; the sampling and holding circuit is used to receive the analog input signal, sample and hold the signal, and ensure that the signal is stably transmitted to the digital-to-analog converter.

4. The metastable detector for a successive approximation analog-to-digital converter according to claim 3, characterized in that: The output end of the digital-to-analog converter is connected to the second input end of the voltage comparator, and the input end of the digital-to-analog converter is connected to the asynchronous logic control circuit; the digital-to-analog converter is used to receive the digital output signal ADCAout from the asynchronous logic control circuit and convert it into a corresponding analog signal for comparison with the analog input signal.

5. The metastable detector for a successive approximation analog-to-digital converter according to claim 4, characterized in that: The voltage comparator is used to receive signals from the sampling and holding circuit and the digital-to-analog converter, as well as the clock control signal CLK output by the asynchronous logic control circuit, and generate a comparison result OUT, which is output to the asynchronous logic control circuit; during the comparison process, the voltage comparator may generate a metastable state and trigger the metastable detector.

6. The metastable detector for a successive approximation analog-to-digital converter according to claim 2, characterized in that: The programmable delay element is implemented by a digitally controlled variable capacitor array.

7. The metastable detector for a successive approximation analog-to-digital converter according to claim 1, characterized in that: The digital-to-analog converter is a capacitive digital-to-analog converter.

8. A control method for a metastable detector applied to a successive approximation analog-to-digital converter according to any one of claims 1 to 7, characterized in that: include: Normal working stage: the voltage comparator works normally under the asynchronous logic control circuit, and the pulse width of the clock control signal CLK changes according to the size of the input signal; The metastable detector monitors the pulse width of the clock control signal CLK output by the asynchronous logic control circuit in real time; Comparison time judgment stage: compare the pulse width of the clock control signal with the pulse width preset threshold to determine whether the voltage comparator is in a normal working state: if the pulse width of the clock control signal is less than the pulse width preset threshold, the inverted signal CLKD of the clock control signal CLK triggers the trigger, and the metastable flag signal META is not triggered, and the voltage comparator is still in a normal working stage; Otherwise, if the pulse width of the clock control signal is not less than the pulse width preset threshold, the metastable flag signal META is activated after CLKD triggers the flip-flop; Metastable processing stage: when the metastable detector detects that the pulse width of the clock control signal is not less than the preset pulse width threshold, a metastable flag signal META is generated and sent to the asynchronous logic control circuit; Reset working stage: after the metastable flag signal META is generated, the clock control signal CLK of the voltage comparator is reset, triggering the voltage comparator to reset and output a preset digital value; after the voltage comparator is reset, the clock control signal CLK generated by the asynchronous logic control circuit controls the metastable detector to reset; the analog-to-digital converter continues to work normally and waits for the next metastable processing.

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