High-speed analog comparator circuit with imbalance correction

Abstract

The invention relates to a high-speed analog comparator circuit with imbalance correction, which comprises a three-stage signal amplification stage circuit and a voltage imbalance correction circuit, and is characterized in that the three-stage signal amplification stage circuit comprises a first-stage circuit part, a second-stage circuit part and a third-stage circuit part which are cascaded; the first-stage circuit part is used for providing a gain to attenuate noise, imbalance and kickback of the second-stage circuit part and the third-stage circuit part; the second-stage circuit part is used for increasing the differential output of the signal in an exponential mode; the third-pole circuit part adopts a bidirectional latch structure to minimize regeneration time; the first-stage circuit part is also connected with an auxiliary input branch; and the voltage offset correction circuit is used for charging and discharging the capacitor of the auxiliary input branch by detecting the output of the three-stage signal amplification stage circuit in a correction mode so as to control the common-mode level of the auxiliary branch to reduce the voltage offset. According to the invention, the requirement of high-speed and high-precision ADC design can be met.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-speed analog comparator circuit with offset correction. Background Art

[0002] Among the currently popular analog-to-digital converter (ADC) technologies, the successive approximation register (SAR) ADC is widely used in analog-to-digital mixed signal processing systems due to its low power consumption, high precision, small area and relatively simple structure. As the core module of SAR ADC, the speed, precision and power consumption of the comparator have gradually become the bottleneck of the development of SAR ADC. Due to the limitations of process and circuit architecture, when the operating speed of the ADC is above GHz, the speed of the comparator completely determines the total sampling rate of the ADC, and its delay becomes a key indicator. In addition, in high-precision ADCs, the offset of the comparator causes the comparator to be unable to compare two similar voltage values, which reduces the sensitivity and affects the accuracy of the ADC.

[0003] ADC plays a role as a bridge from analog to digital domain in current mixed signal processing systems, affecting signal processing quality and signal-to-noise ratio. The design of high-speed, low-offset comparators is crucial to achieving high-performance ADCs. It not only needs to respond quickly to changes in input signals to meet the needs of high-speed sampling, but also needs to reduce offset while maintaining high speed to improve signal processing capabilities.

[0004] Currently, commonly used comparators can be divided into two types: static comparators and dynamic comparators. Static comparators are usually open-loop applications of operational amplifiers, with relatively few devices, simple structure, and no need for frequency compensation, but the response speed is not fast enough, the output common mode is not easy to determine, and the power consumption is large during operation. In current ADC applications, they are gradually replaced by dynamic comparators. Compared with static comparators, dynamic comparators have almost no power consumption and faster comparison speed, but there is a large voltage offset. At present, traditional high-speed dynamic comparators include StrongArm latch comparators, double-tail current latch comparators, two-stage latch comparators, and three-stage latch comparators. They use a structure in which one or more pre-amplifier stages and latches are connected in series, and small signals are amplified through the high bandwidth and gain of the pre-amplifier stage, and then the latch is used to amplify and latch the large signal through positive feedback. However, due to the limited small signal gain, the comparator delay is difficult to reduce to less than 50Ps, and the acceleration method through the stacked latch structure reduces the voltage margin of the comparator, which is difficult to design under low-voltage nanometers. Although the three-stage latch comparator improves the gain of small signals, the increase in the number of cascade stages increases the delay and offset, making it difficult to meet the requirements of high-speed and high-precision ADC design. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a high-speed analog comparator circuit with offset correction, which can meet the requirements of high-speed and high-precision ADC design.

[0006] The technical solution adopted by the present invention to solve its technical problems is: providing a high-speed analog comparator circuit with offset correction, including a three-stage signal amplification stage circuit and a voltage offset correction circuit, the three-stage signal amplification stage circuit including a cascaded first-stage circuit part, a second-stage circuit part and a third-stage circuit part; the first-stage circuit part is used to provide a gain to attenuate the noise, offset and kickback of the second-stage circuit part and the third-stage circuit part; the second-stage circuit part is used to increase the differential output of the signal in an exponential manner; the third-stage circuit part adopts a bidirectional latch structure to minimize the regeneration time; the first-stage circuit part is also connected to an auxiliary input branch; the voltage offset correction circuit is used to charge and discharge the capacitance of the auxiliary input branch by detecting the output of the three-stage signal amplification stage circuit in a correction mode, so as to control the common mode level of the auxiliary branch to reduce the voltage offset.

[0007] The first-stage circuit part includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube and a first control tube; the gate of the first NMOS tube serves as the first input end of the first-stage circuit part, the source is connected to the drain of the first control tube, and the drain is connected to the source of the third NMOS tube; the gate of the second NMOS tube serves as the second input end of the first-stage circuit part, the source is connected to the drain of the first control tube, and the drain is connected to the source of the fourth NMOS tube; the gate of the third NMOS tube is connected to the first output end of the first-stage circuit part, the drain is connected to the drain of the first PMOS tube, and serves as the second output end of the first-stage circuit part; the gate of the fourth NMOS tube is connected to the second output end of the first-stage circuit part, the drain is connected to the drain of the second PMOS tube, and serves as the first output end of the first-stage circuit part; the gate of the first PMOS tube is connected to the clock signal, and the source is connected to the power supply end; the gate of the second PMOS tube is connected to the clock signal, and the source is connected to the power supply end; the gate of the first control tube is connected to the clock signal, and the source is grounded.

[0008] The auxiliary input branch includes a first auxiliary NMOS tube and a second auxiliary NMOS tube, the drain of the first auxiliary NMOS tube is connected to the drain of the first NMOS tube, and the source is connected to the drain of the first control tube; the gate of the second auxiliary NMOS tube is connected to one end of the capacitor, the drain is connected to the drain of the second NMOS tube, and the source is connected to the drain of the first control tube; the other end of the capacitor is grounded.

[0009] The second-stage circuit part includes a fifth NMOS tube, a sixth NMOS tube, a third PMOS tube, a fourth PMOS tube and a second control tube. The gate of the fifth NMOS tube is connected to the second output end of the first-stage circuit part, the drain is connected to the drain of the third PMOS tube, and serves as the first output end of the second-stage circuit part, and the source is grounded; the gate of the sixth NMOS tube is connected to the first output end of the first-stage circuit part, the drain is connected to the drain of the fourth PMOS tube, and serves as the second output end of the second-stage circuit part, and the source is grounded; the gate of the third PMOS tube is connected to the second output end of the second-stage circuit part, and the source is connected to the drain of the second control tube; the gate of the fourth PMOS tube is connected to the first output end of the second-stage circuit part, and the source is connected to the drain of the second control tube; the gate of the second control tube is connected to the inverted signal of the clock signal, and the source is connected to the power supply end.

[0010] The third-stage circuit portion includes a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube and a third control tube. The gate of the seventh NMOS tube is connected to the first output end of the first-stage circuit portion, the drain is connected to the drain of the ninth NMOS tube and serves as the second output end of the third-stage circuit portion, and the source is connected to the drain of the third control tube; the gate of the eighth NMOS tube is connected to the second output end of the first-stage circuit portion, the drain is connected to the drain of the tenth NMOS tube and serves as the first output end of the third-stage circuit portion, and the source is connected to the drain of the third control tube; the gate of the ninth NMOS tube is connected to the first output end of the third-stage circuit portion, the drain is connected to the drain of the tenth NMOS tube and serves as the first output end of the third-stage circuit portion, and the source is connected to the drain of the third control tube; The gate of the tenth NMOS tube is connected to the second output end of the third circuit part, the drain is connected to the drain of the sixth PMOS tube, and the source is connected to the drain of the third control tube; the gate of the fifth PMOS tube is connected to the first output end of the second-stage circuit part, the drain is connected to the drain of the seventh PMOS tube, and the source is connected to the power supply end; the gate of the sixth PMOS tube is connected to the second output end of the second-stage circuit part, the drain is connected to the drain of the eighth PMOS tube, and the source is connected to the power supply end; the gate of the seventh PMOS tube is connected to the clock signal, and the source is connected to the power supply end; the gate of the eighth PMOS tube is connected to the clock signal, and the source is connected to the power supply end.

[0011] The voltage offset correction circuit comprises a first NAND gate, a second NAND gate, a first AND gate, a second AND gate, an offset correction PMOS tube, an offset correction NMOS tube, a first current source and a second current source; the first input end of the first NAND gate is connected to the first output end of the third pole circuit part, the second input end is connected to the second output end of the third pole circuit part, and the output end is connected to the first input end of the first AND gate; the second input end of the first AND gate is connected to the Cal signal, and the output end is respectively connected to the second input end of the second NAND gate and the second input end of the second AND gate; the first input end of the second NAND gate is connected to the third pole circuit part The first output terminal of the AND gate is connected to the first output terminal of the third pole circuit part, and the output terminal is connected to the gate of the offset correction PMOS tube; the first input terminal of the second AND gate is connected to the second output terminal of the third pole circuit part, and the output terminal is connected to the gate of the offset correction NMOS tube; the source of the offset correction PMOS tube is connected to the positive electrode of the first current source, and the drain is connected to the drain of the offset correction NMOS tube; the source of the offset correction NMOS tube is connected to the negative electrode of the second current source; the drain of the offset correction NMOS tube is also connected to the capacitor of the auxiliary input branch; the negative electrode of the first current source is connected to the power supply terminal, and the positive electrode of the second current source is grounded.

[0012] Beneficial Effects

[0013] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art: the present invention reduces the offset of the comparator by designing the offset voltage of the comparator through the auxiliary branch, and the offset is controlled within 1mV, so that it can be used in the design of high-speed and high-precision ADC. In addition, the present invention also reduces the conversion time of small signals by increasing the feedforward path of the signal, and combines the high gain of the feedforward path and the direct path, so that the comparator has the advantage of two-stage low delay on the basis of the original three-stage amplification, and controls the delay of the comparator to about 30Ps, which can be used for high-speed comparison above 10GHz. The present invention increases the voltage margin of the comparator by horizontally cascading with the latch instead of vertically stacking, so that the circuit architecture of the present invention can be applied in more advanced processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a circuit diagram of a high-speed analog comparator circuit with offset correction according to an embodiment of the present invention;

[0015] Figure 2 is a signal transmission path diagram of the second-level circuit part and the third-level circuit part in an embodiment of the present invention;

[0016] Figure 3 is a transient simulation circuit diagram of a comparator in an embodiment of the present invention;

[0017] Figure 4 is a diagram of transient simulation results of a comparator in an embodiment of the present invention;

[0018] Figure 5 is a circuit diagram of a voltage offset correction circuit in an embodiment of the present invention;

[0019] Figure 6 4 is a diagram of a comparator offset calibration process in an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0021] The embodiments of the present invention relate to a high-speed analog comparator circuit with offset correction, such as Figure 1 As shown, it includes a three-stage signal amplification stage circuit and a voltage offset correction circuit, wherein the three-stage signal amplification stage circuit includes a cascaded first-stage circuit part, a second-stage circuit part and a third-stage circuit part; the first-stage circuit part is used to provide a gain to attenuate the noise, offset and kickback of the second-stage circuit part and the third-stage circuit part; the second-stage circuit part is used to increase the differential output of the signal in an exponential manner; the third-stage circuit part adopts a bidirectional latch structure to minimize the regeneration time; the first-stage circuit part is also connected to an auxiliary input branch; the voltage offset correction circuit is used to charge and discharge the capacitance of the auxiliary input branch by detecting the output of the three-stage signal amplification stage circuit in a correction mode, so as to control the common mode level of the auxiliary branch to reduce the voltage offset.

[0022] The first-stage circuit portion in this embodiment includes a first NMOS transistor MN11, a second NMOS transistor MN12, a third NMOS transistor MN13, a fourth NMOS transistor MN14, a first PMOS transistor MP11, a second PMOS transistor MP12 and a first control transistor T1; the gate of the first NMOS transistor MN11 serves as a first input terminal INP of the first-stage circuit portion, the source is connected to the drain of the first control transistor T1, and the drain is connected to the source of the third NMOS transistor MN13; the gate of the second NMOS transistor MN12 serves as a second input terminal INN of the first-stage circuit portion, the source is connected to the drain of the first control transistor T1, and the drain is connected to the source of the fourth NMOS transistor MN14; the third NMOS transistor MN12 serves as a second input terminal INN of the first-stage circuit portion, the source is connected to the drain of the first control transistor T1, and the drain is connected to the source of the fourth NMOS transistor MN14; The gate of the MOS transistor MN13 is connected to the first output terminal VX+ of the first-stage circuit part, and the drain is connected to the drain of the first PMOS transistor MP11, and serves as the second output terminal VX- of the first-stage circuit part; the gate of the fourth NMOS transistor MN14 is connected to the second output terminal VX- of the first-stage circuit part, and the drain is connected to the drain of the second PMOS transistor MP12, and serves as the first output terminal VX+ of the first-stage circuit part; the gate of the first PMOS transistor MP11 is connected to the clock signal CLK, and the source is connected to the power supply terminal; the gate of the second PMOS transistor MP12 is connected to the clock signal CLK, and the source is connected to the power supply terminal; the gate of the first control transistor T1 is connected to the clock signal CLK, and the source is grounded.

[0023] The auxiliary input branch in this embodiment includes a first auxiliary NMOS transistor MNC1 and a second auxiliary NMOS transistor MNC2, wherein the drain of the first auxiliary NMOS transistor MNC1 is connected to the drain of the first NMOS transistor MN11, and the source is connected to the drain of the first control transistor T1; the gate of the second auxiliary NMOS transistor MNC2 is connected to one end of the capacitor C, the drain is connected to the drain of the second NMOS transistor MN12, and the source is connected to the drain of the first control transistor T1; the other end of the capacitor C is grounded.

[0024] The second stage circuit part in this embodiment includes a fifth NMOS transistor MN21, a sixth NMOS transistor MN22, a third PMOS transistor MP21, a fourth PMOS transistor MP22 and a second control transistor T2. The gate of the fifth NMOS transistor MN21 is connected to the second output terminal VX- of the first stage circuit part, the drain is connected to the drain of the third PMOS transistor MP21 and serves as the first output terminal VY+ of the second stage circuit part, and the source is grounded. The gate of the sixth NMOS transistor MN22 is connected to the first output terminal VX+ of the first stage circuit part. The drain is connected to the drain of the fourth PMOS tube MP22 and serves as the second output terminal VY- of the second-stage circuit part, and the source is grounded; the gate of the third PMOS tube MP21 is connected to the second output terminal VY- of the second-stage circuit part, and the source is connected to the drain of the second control tube T2; the gate of the fourth PMOS tube MP22 is connected to the first output terminal VY+ of the second-stage circuit part, and the source is connected to the drain of the second control tube T2; the gate of the second control tube T2 is connected to the inverted signal CLKN of the clock signal, and the source is connected to the power supply terminal.

[0025] The third-stage circuit part in this embodiment includes a seventh NMOS transistor MN31, an eighth NMOS transistor MN32, a ninth NMOS transistor MN33, a tenth NMOS transistor MN34, a fifth PMOS transistor MP31, a sixth PMOS transistor MP32, a seventh PMOS transistor MP33, an eighth PMOS transistor MP34 and a third control transistor T3. The gate of the seventh NMOS transistor MN31 is connected to the first output terminal VX+ of the first-stage circuit part, the drain is connected to the drain of the ninth NMOS transistor MN33 and serves as the second output terminal VON of the third-stage circuit part, and the source is connected to the drain of the third control transistor T3; the gate of the eighth NMOS transistor MN32 is connected to the second output terminal VX- of the first-stage circuit part, the drain is connected to the drain of the tenth NMOS transistor MN34 and serves as the first output terminal VOP of the third-stage circuit part, and the source is connected to the drain of the third control transistor T3; the gate of the ninth NMOS transistor MN33 is connected to the first output terminal VX+ of the first-stage circuit part, the drain is connected to the drain of the tenth NMOS transistor MN34 and serves as the first output terminal VOP of the third-stage circuit part, and the source is connected to the drain of the third control transistor T3; The first output terminal VOP of the triode circuit part is connected, the drain is connected to the drain of the fifth PMOS tube MP31, and the source is connected to the drain of the third control tube T3; the gate of the tenth NMOS tube MN34 is connected to the second output terminal VON of the third circuit part, the drain is connected to the drain of the sixth PMOS tube MP32, and the source is connected to the drain of the third control tube T3; the gate of the fifth PMOS tube MP31 is connected to the first output terminal VY+ of the second-stage circuit part, the drain is connected to the drain of the seventh PMOS tube MP33, and the source is connected to the power supply terminal; the gate of the sixth PMOS tube MP32 is connected to the second output terminal VY- of the second-stage circuit part, the drain is connected to the drain of the eighth PMOS tube MP34, and the source is connected to the power supply terminal; the gate of the seventh PMOS tube MP33 is connected to the clock signal CLK, and the source is connected to the power supply terminal; the gate of the eighth PMOS tube MP34 is connected to the clock signal CLK, and the source is connected to the power supply terminal.

[0026] The voltage offset correction circuit in this embodiment includes a first NAND gate, a second NAND gate, a first AND gate, a second AND gate, an offset correction PMOS transistor MPSC, an offset correction NMOS transistor MNSC, a first current source, and a second current source; the first input end of the first NAND gate is connected to the first output end VOP of the third pole circuit part, the second input end is connected to the second output end VON of the third pole circuit part, and the output end is connected to the first input end of the first AND gate; the second input end of the first AND gate is connected to the Cal signal, and the output end is respectively connected to the second input end of the second NAND gate and the second input end of the second AND gate; the first input end of the second NAND gate is connected to the first output end VOP of the third pole circuit part The first input terminal of the second AND gate is connected to the second output terminal VON of the third pole circuit part, and the output terminal is connected to the gate of the offset correction NMOS tube MNSC; the source of the offset correction PMOS tube MPSC is connected to the positive electrode of the first current source, and the drain is connected to the drain of the offset correction NMOS tube MNSC; the source of the offset correction NMOS tube MNSC is connected to the negative electrode of the second current source; the drain of the offset correction NMOS tube MNSC is also connected to the capacitor C of the auxiliary input branch; the negative electrode of the first current source is connected to the power supply terminal, and the positive electrode of the second current source is grounded.

[0027] The working principle of the high-speed analog comparator circuit with offset correction in this embodiment is as follows:

[0028] When the clock signal CLK is at a low level, the first-stage circuit part, the second-stage circuit part and the third-stage circuit part are all in the off state, the first output terminal VX+ of the first-stage circuit part and the second output terminal VX- of the first-stage circuit part are raised to VDD through the first PMOS tube MP11 and the second PMOS tube MP12, the second output terminal VON of the third-stage circuit part and the first output terminal VOP of the third-stage circuit part are raised to VDD through the seventh PMOS tube MP33 and the eighth PMOS tube MP34, the first output terminal VY+ of the second-stage circuit part and the second output terminal VY- of the second-stage circuit part are pulled down to GND through the fifth NMOS tube MN21 and the sixth NMOS tube MN22, and the comparator completes the reset.

[0029] When the clock signal CLK is at a high level, the first stage circuit part, the second stage circuit part and the third stage circuit part are all in the on state. Under the action of the input signal ΔVIN, one end of the first output terminal VX+ of the first stage circuit part and the second output terminal VX- of the first stage circuit part is raised and the other end is pulled down, so that the input signal is amplified and used as the input of the second stage circuit part and the third stage circuit part; the first output terminal VY+ of the second stage circuit part and the second output terminal VY- of the second stage circuit part are raised and the other end is pulled down under the action of the first output terminal VX+ of the first stage circuit part and the second output terminal VX- of the first stage circuit part, and the difference signal is further amplified and transmitted to the third stage circuit part. Figure 2 As shown, the second output terminal VON of the third-stage circuit part and the first output terminal VOP of the third-stage circuit part perform VY difference lifting differentiation through a direct signal path on the one hand, and perform VX difference pulling-down differentiation through a feedforward signal path on the other hand, so that the output differentiation is accelerated, the speed of the comparator is significantly improved, and the comparator completes the comparison.

[0030] When the Cal signal is at a low level, the output SP of the second NAND gate is at a high level, and the output SN of the second AND gate is at a low level. At this time, the offset correction PMOS tube MPSC and the offset correction NMOS tube MNSC are both in the off state, and the calibration capacitor has no current path. At this time, the comparator is in normal working mode.

[0031] When the Cal signal is high, assuming that the comparator has a positive equivalent offset voltage, the output result of the comparator is high VOP and low VON; at this time, the offset correction PMOS tube MPSC is turned on, the offset correction NMOS tube MNSC is turned off, and the current flows into the calibration capacitor C, causing its voltage to rise, and the transconductance of the right branch increases to balance the offset voltage. Assuming that the comparator has a negative equivalent offset voltage, the output result of the comparator is low VOP and high VON; at this time, the offset correction PMOS tube MPSC is controlled to be turned off, the offset correction NMOS tube MNSC is turned on, and the current flows out of the calibration capacitor C, causing its voltage to drop, and the transconductance of the right branch is reduced to balance the offset voltage.

[0032] When the calibration is completed, the offset of the comparator is 0, the output is alternately high and low, and the calibration capacitor C reaches a balance in charge and discharge.

[0033] Figure 3 The transient simulation circuit of the three-stage signal amplifier circuit in this embodiment is given. Set the input positive terminal voltage to 600mV, the input negative terminal voltage to 595mV, the difference to 5mV, the clock cycle to 200Ps, the frequency to 5GHz, and use Cadence to perform transient simulation of the circuit with a simulation time of 1ns. The simulation results are shown in Figure 4As shown, the input difference signal is amplified to the output end through the direct path and the feedforward path. When the output is VDD / 2, it takes 29Ps, which meets the comparison speed requirement of more than 10GHz.

[0034] Figure 5 The circuit diagram of the voltage offset correction circuit in this embodiment is given. The offset correction of the comparator must be performed before the comparator works. For example, the input VIP, VIN, and VIPC are set to 600mV. The capacitor upper board VINC is the correction adjustment terminal, which is the gate voltage of the auxiliary branch of the negative input terminal. There is no need to pay attention to its initial value. It will reach stability after the correction is completed. In addition, since the capacitor is charged and discharged according to the output result, a slower comparison clock is set during the correction so that the correction can be completed in a short time. The circuit calibration process is as follows Figure 6 As shown in the figure, it takes 153ns from the Cal signal being high to the completion of calibration. When the calibration starts, VOP always outputs a high level, and current flows into the capacitor to cause the VINC voltage to rise. When VOP and VON output high levels alternately, the calibration is completed. At this time, the capacitor charging and discharging reaches a balance, and the voltage VINC fluctuates within 1mV, indicating that the voltage offset after correction is less than 1mV, which meets the design requirements of high-speed and high-precision ADC.

[0035] It is not difficult to find that the present invention reduces the offset of the comparator by designing an auxiliary branch to correct the offset voltage of the comparator, and the offset is controlled within 1mV, so that it can be used in the design of high-speed and high-precision ADC. In addition, the present invention also reduces the conversion time of small signals by increasing the feedforward path of the signal, and combines the high gain of the feedforward path and the direct path, so that the comparator has the advantage of two-stage low delay on the basis of the original three-stage amplification, and controls the delay of the comparator to about 30Ps, which can be used for high-speed comparisons above 10GHz. The present invention increases the voltage margin of the comparator by horizontally cascading with the latch instead of vertically stacking, so that the circuit architecture of the present invention can be applied in more advanced processes.

Claims

1. A high-speed analog comparator circuit with offset correction, characterized in that: The invention comprises a three-stage signal amplification stage circuit and a voltage offset correction circuit, wherein the three-stage signal amplification stage circuit comprises a cascaded first-stage circuit part, a second-stage circuit part and a third-stage circuit part; the first-stage circuit part is used to provide a gain to attenuate noise, offset and kickback of the second-stage circuit part and the third-stage circuit part; The second-stage circuit portion is used to increase the differential output of the signal exponentially; the third-stage circuit portion adopts a bidirectional latch structure to minimize the regeneration time; the first-stage circuit portion is also connected to an auxiliary input branch; the voltage offset correction circuit is used to charge and discharge the capacitance of the auxiliary input branch by detecting the output of the three-stage signal amplification stage circuit in a correction mode, so as to control the common mode level of the auxiliary branch to reduce the voltage offset.

2. The high-speed analog comparator circuit with offset correction according to claim 1, characterized in that: The first-stage circuit part includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube and a first control tube; the gate of the first NMOS tube serves as the first input end of the first-stage circuit part, the source is connected to the drain of the first control tube, and the drain is connected to the source of the third NMOS tube; the gate of the second NMOS tube serves as the second input end of the first-stage circuit part, the source is connected to the drain of the first control tube, and the drain is connected to the source of the fourth NMOS tube; the gate of the third NMOS tube is connected to the first output end of the first-stage circuit part, the drain is connected to the drain of the first PMOS tube, and serves as the second output end of the first-stage circuit part; the gate of the fourth NMOS tube is connected to the second output end of the first-stage circuit part, the drain is connected to the drain of the second PMOS tube, and serves as the first output end of the first-stage circuit part; the gate of the first PMOS tube is connected to the clock signal, and the source is connected to the power supply end; the gate of the second PMOS tube is connected to the clock signal, and the source is connected to the power supply end; the gate of the first control tube is connected to the clock signal, and the source is grounded.

3. The high-speed analog comparator circuit with offset correction according to claim 2, characterized in that: The auxiliary input branch includes a first auxiliary NMOS tube and a second auxiliary NMOS tube, the drain of the first auxiliary NMOS tube is connected to the drain of the first NMOS tube, and the source is connected to the drain of the first control tube; the gate of the second auxiliary NMOS tube is connected to one end of the capacitor, the drain is connected to the drain of the second NMOS tube, and the source is connected to the drain of the first control tube; the other end of the capacitor is grounded.

4. The high-speed analog comparator circuit with offset correction according to claim 1, characterized in that: The second-stage circuit part includes a fifth NMOS tube, a sixth NMOS tube, a third PMOS tube, a fourth PMOS tube and a second control tube. The gate of the fifth NMOS tube is connected to the second output end of the first-stage circuit part, the drain is connected to the drain of the third PMOS tube, and serves as the first output end of the second-stage circuit part, and the source is grounded; the gate of the sixth NMOS tube is connected to the first output end of the first-stage circuit part, the drain is connected to the drain of the fourth PMOS tube, and serves as the second output end of the second-stage circuit part, and the source is grounded; the gate of the third PMOS tube is connected to the second output end of the second-stage circuit part, and the source is connected to the drain of the second control tube; the gate of the fourth PMOS tube is connected to the first output end of the second-stage circuit part, and the source is connected to the drain of the second control tube; the gate of the second control tube is connected to the inverted signal of the clock signal, and the source is connected to the power supply end.

5. The high-speed analog comparator circuit with offset correction according to claim 1, characterized in that: The third-stage circuit portion includes a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube and a third control tube. The gate of the seventh NMOS tube is connected to the first output end of the first-stage circuit portion, the drain is connected to the drain of the ninth NMOS tube and serves as the second output end of the third-stage circuit portion, and the source is connected to the drain of the third control tube; the gate of the eighth NMOS tube is connected to the second output end of the first-stage circuit portion, the drain is connected to the drain of the tenth NMOS tube and serves as the first output end of the third-stage circuit portion, and the source is connected to the drain of the third control tube; the gate of the ninth NMOS tube is connected to the first output end of the third-stage circuit portion, the drain is connected to the drain of the tenth NMOS tube and serves as the first output end of the third-stage circuit portion, and the source is connected to the drain of the third control tube; The gate of the tenth NMOS tube is connected to the second output end of the third circuit part, the drain is connected to the drain of the sixth PMOS tube, and the source is connected to the drain of the third control tube; the gate of the fifth PMOS tube is connected to the first output end of the second-stage circuit part, the drain is connected to the drain of the seventh PMOS tube, and the source is connected to the power supply end; the gate of the sixth PMOS tube is connected to the second output end of the second-stage circuit part, the drain is connected to the drain of the eighth PMOS tube, and the source is connected to the power supply end; the gate of the seventh PMOS tube is connected to the clock signal, and the source is connected to the power supply end; the gate of the eighth PMOS tube is connected to the clock signal, and the source is connected to the power supply end.

6. The high-speed analog comparator circuit with offset correction according to claim 1, characterized in that: The voltage offset correction circuit comprises a first NAND gate, a second NAND gate, a first AND gate, a second AND gate, an offset correction PMOS tube, an offset correction NMOS tube, a first current source and a second current source; the first input end of the first NAND gate is connected to the first output end of the third pole circuit part, the second input end is connected to the second output end of the third pole circuit part, and the output end is connected to the first input end of the first AND gate; the second input end of the first AND gate is connected to the Cal signal, and the output end is respectively connected to the second input end of the second NAND gate and the second input end of the second AND gate; the first input end of the second NAND gate is connected to the third pole circuit part The first output terminal of the AND gate is connected to the first output terminal of the third pole circuit part, and the output terminal is connected to the gate of the offset correction PMOS tube; the first input terminal of the second AND gate is connected to the second output terminal of the third pole circuit part, and the output terminal is connected to the gate of the offset correction NMOS tube; the source of the offset correction PMOS tube is connected to the positive electrode of the first current source, and the drain is connected to the drain of the offset correction NMOS tube; the source of the offset correction NMOS tube is connected to the negative electrode of the second current source; the drain of the offset correction NMOS tube is also connected to the capacitor of the auxiliary input branch; the negative electrode of the first current source is connected to the power supply terminal, and the positive electrode of the second current source is grounded.

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