Comparator circuit for SAR ADC and calibration circuit thereof

Abstract

The invention discloses a comparator circuit for SAR ADC, which comprises a pre-amplifier and a comparator, the pre-amplifier comprises a first amplification unit and a second amplification unit, the comparator comprises a first comparison unit and a second comparison unit, the first amplification unit comprises a first MOS tube and a second MOS tube, the source electrode of the first MOS tube is grounded, and the drain electrode of the first MOS tube is connected with the source electrode of the second MOS tube; the first comparison unit comprises a third MOS tube, a fourth MOS tube and a fifth MOS tube, the grid electrode of the third MOS tube is connected with the grid electrode of the fifth MOS tube, the source electrodes of the fourth MOS tube and the fifth MOS tube are connected with the power supply, and the drain electrodes of the fourth MOS tube, the fifth MOS tube and the third MOS tube are connected together. According to the scheme, the positive feedback process can be quickly started, and the comparison time is shortened; and the offset voltage can be calibrated, so that the precision of the output result of the comparator is improved. Meanwhile, the invention also discloses a calibration circuit for the comparator circuit of the SAR ADC.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more particularly to a comparator circuit for SAR ADC. Background Art

[0002] The traditional comparator circuit for SAR ADC generally includes a preamplifier and a post comparator, such as Figure 1 The figure shows the structure diagram of the conventional preamplifier circuit for SAR ADC. Figure 2 , which is a schematic diagram of the structure of a traditional comparator.

[0003] exist Figure 1 The two output terminals Von and Vop correspond to Figure 2 The input terminals Vin and Vip in are connected to form a complete comparator circuit for SAR ADC.

[0004] exist Figure 1 and Figure 2 When the external clock CLK is low, Figure 1 In the middle: MOS tubes M11 and M22 are turned on, MOS tubes M13, M14, and M15 are turned off, and the voltages of the output terminals Von and Vop are the power supply voltage AVD, which is the reset state at this time; in Figure 2 In the embodiment, the MOS tubes M113, M114, M115 and M116 of the comparator are turned on, and the other MOS tubes are turned off. The output voltages of the output terminals Voutn and Voutp of the comparator are the power supply voltage AVD, which is a reset state.

[0005] When the external clock CLK is high, Figure 1 In the state of comparison, MOS tubes M11 and M12 are turned off, and MOS tubes M13, M14, and M15 are turned on. Since the input signals of input terminals Vip and Vin are different, the voltages of output terminals Voutp and Voutn drop from power supply voltage AVD to ground voltage GND at different speeds. Figure 2 In the embodiment, MOS tubes M18, M19 and M110 are turned on. At this time, due to the different signals inputted by input terminals Vip and Vin, the voltages of output terminals Voutp and Voutn start to drop from power supply voltage AVD at different speeds. When the voltage drops to AVD-VTH (VTH is the threshold voltage of Pmos tubes M115 and M116), one of MOS tubes M111 and M112 is turned on first, and the positive feedback formed by MOS tubes M115, M116, M111 and M112 starts to work, so that the voltages of output terminals Voutp and Voutn increase to power supply voltage AVD and drop to ground voltage GND, which is a comparison state.

[0006] In the above-mentioned comparator circuit for SAR ADC, the comparator has no calibration function, and there will be an offset voltage error of tens to hundreds of millivolts at the input of the preamplifier, which will cause an error in the output result at the output end; in addition, after entering the comparison state, the voltage of the output terminals Voutp and Voutn needs to drop to AVD-VTH before the positive feedback starts, so that the entire delay time is composed of two parts, the voltage drop time of the output terminals Voutp and Voutn and the positive feedback time, resulting in a reduction in the speed of the entire comparator circuit.

[0007] Therefore, it is necessary to provide an improved comparator circuit for SAR ADC to overcome the above defects. Summary of the invention

[0008] The purpose of the present invention is to provide a comparator circuit and a calibration circuit thereof for SAR ADC, which can quickly start a positive feedback process, reduce the comparison time, and speed up the comparison; and can also calibrate the offset voltage, thereby improving the accuracy of the comparator output result.

[0009] To achieve the above-mentioned object, the present invention provides a comparator circuit for SAR ADC, comprising a preamplifier and a comparator, wherein the preamplifier amplifies a pair of input differential signals, and the comparator compares the amplified pair of differential signals to obtain a comparison result; wherein the preamplifier comprises a first amplifying unit and a second amplifying unit having the same structural features, and the comparator comprises a first comparing unit and a second comparing unit having the same structural features, an external pair of differential signals are respectively input to the input ends of the first amplifying unit and the second amplifying unit, an output end of the first amplifying unit is connected to the output end of the first comparing unit, and an output end of the second amplifying unit is connected to the output end of the second comparing unit; the first amplifying unit comprises a first MOS tube and a second MOS tube, the source of the first MOS tube is grounded, and the drain is connected to the drain of the second MOS tube. The first comparison unit comprises a third MOS tube, a fourth MOS tube and a fifth MOS tube, the source of the third MOS tube is grounded, the drain forms the output end of the first comparison unit, the gate of the third MOS tube is connected with the gate of the fifth MOS tube and connected with the output end of the second comparison unit, the source of the fourth MOS tube and the fifth MOS tube are connected with the power supply voltage, the drain of the fourth MOS tube and the fifth MOS tube is connected with the drain of the third MOS tube, and the external first clock signal is input to the gate of the fourth MOS tube; the external first clock signal has the same frequency as the second clock signal and has an opposite phase.

[0010] Preferably, the comparator further comprises a sixth MOS tube, the drain of the sixth MOS tube is connected to the source of the third MOS tube of the first comparison unit and the second comparison unit, the first clock signal is input into the gate of the sixth MOS tube, and the source of the sixth MOS tube is grounded.

[0011] Preferably, the first amplifying unit further comprises a seventh MOS tube, the source of the seventh MOS tube is connected to the drain of the first MOS tube, the drain of the seventh MOS tube is connected to the output end of the second comparing unit, an external positive calibration voltage is input to the gate of the seventh MOS tube; and an external negative calibration voltage is input to the second amplifying unit.

[0012] Preferably, the fourth MOS tube and the fifth MOS tube are both P-type MOS tubes.

[0013] Preferably, the size of the fourth MOS tube is adjusted and changed, the voltage at the output end of the first comparison unit is adjusted to the difference between the power supply voltage and the threshold voltage of the fifth MOS tube, and the fifth MOS tube is in a sub-threshold state.

[0014] Preferably, the relationship between the offset voltage Vo of the comparator equivalent to the preamplifier end and the output voltage Vout of the preamplifier is as follows:

[0015] Vout=Va-Vb=A·(Vinp-Vinn-Vo-W(VREF+-VREF-))

[0016] Among them, A is the gain of the preamplifier, Va is the voltage value of the output end of the first comparison unit, Vb is the voltage value of the output end of the second comparison unit, Vinp and Vinn are the voltage values ​​of the differential input signals input to the preamplifier, VREF+ and VREF- are the external calibration voltages input to the first amplification unit and the second amplification unit respectively, and W is the ratio of the width of the second MOS tube to the seventh MOS tube.

[0017] At the same time, the present invention also discloses a calibration circuit for a comparator circuit of a SAR ADC, which includes a comparator, a DAC unit and a digital logic unit. The same external reference voltage is input as a differential signal into the positive input terminal and the negative input terminal of the comparator respectively. The output terminal of the comparator is connected to the digital logic unit. Under the control of a first clock signal, the digital logic controls the DAC unit to output a positive calibration voltage and a negative calibration voltage to the comparator.

[0018] Preferably, each time the comparator outputs an output value, the digital logic unit controls the DAC unit to output a pair of calibration voltage values ​​to the comparator until the DAC unit completes the output of the last bit.

[0019] Compared with the prior art, the comparator circuit for SAR ADC and the calibration circuit thereof of the present invention have a fourth MOS tube disposed between the output terminals of the first amplifying unit and the first comparing unit and the power supply voltage, and between the output terminals of the second amplifying unit and the second comparing unit and the power supply voltage. Therefore, when the fourth MOS tube is turned on, the voltages of the two output terminals are adjusted to the difference between the power supply voltage and the threshold voltage of the P-type MOS tube, and the P-type MOS tube is turned on quickly, and the positive feedback process is started quickly, thereby reducing the comparison time and accelerating the comparison speed. In addition, by arranging the calibration circuit, a positive calibration voltage and a negative calibration voltage are input from the outside, so that the offset voltage existing at the input terminal of the preamplifier can be calibrated, thereby improving the accuracy of the output result of the comparator circuit.

[0020] The present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, which are used to illustrate embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The present invention is a schematic diagram of the structure of a preamplifier circuit for a SAR ADC in the prior art.

[0022] Figure 2 The present invention is a schematic diagram of the structure of a preamplifier circuit for a SAR ADC in the prior art.

[0023] Figure 3 It is a schematic structural diagram of a comparator circuit for SAR ADC of the present invention.

[0024] Figure 4 It is a schematic structural diagram of a calibration circuit for a comparator circuit of a SAR ADC according to the present invention. DETAILED DESCRIPTION

[0025] Embodiments of the present invention are now described with reference to the accompanying drawings, in which like element numbers represent like elements. As described above, the present invention provides a comparator circuit for SAR ADC and a calibration circuit thereof, which can quickly start the positive feedback process, reduce the comparison time, and speed up the comparison; and can also calibrate the offset voltage, thereby improving the accuracy of the output result of the comparator circuit.

[0026] Please refer to Figure 3 , Figure 3 FIG. 1 is a schematic diagram of the structure of a comparator circuit for SAR ADC of the present invention. Figure 3 As shown, the comparator circuit for SAR ADC of the present invention includes a preamplifier and a comparator. The preamplifier amplifies a pair of input differential signals Vinp and Vinn, and the comparator compares the amplified pair of differential signals to obtain a comparison result, so as to realize the function of the entire comparator circuit.

[0027] The preamplifier includes a first amplifying unit and a second amplifying unit with the same structural features. An external pair of differential signals Vinp and Vinn are respectively input into the input ends of the first amplifying unit and the second amplifying unit. Specifically, the differential signal Vinp is input into the input end of the first amplifying unit, and the differential signal Vinn is input into the input end of the second amplifying unit. Since the first amplifying unit and the second amplifying unit of the preamplifier of the present invention have the same structural features, the first amplifying unit is used for description herein; the first amplifying unit includes a first MOS tube M21 and a second MOS tube M22, the source of the first MOS tube M21 is grounded, the drain is connected to the source of the second MOS tube M22, an external second clock signal Clkb is input to the gate of the second MOS tube M22, a differential signal Vinp is input to the gate of the second MOS tube M22, and the drain of the second MOS tube M22 is connected to the output end of the first amplifying unit; when the external second clock signal Clkb is at a high level (power supply voltage VCC), the first MOS tube M21 and the second MOS tube M22 are turned on, the first amplifying unit starts to work, and amplifies the input differential signal Vinp, and the amplified signal is input from the drain of the second MOS tube M22 to the comparator to complete the function of the first amplifying unit. Correspondingly, the second amplifying unit includes a first MOS tube M21' and a second MOS tube M22', another differential signal Vinn is input to the gate of the second MOS tube M22', and after amplification, is input to the comparator through the drain of the second MOS tube M22'; the specific structure and function of the second amplifying unit are the same as those of the first amplifying unit, which will not be described in detail here.

[0028] The comparator includes a first comparison unit and a second comparison unit having the same structural features, and the output end of the first amplification unit is connected to the output end of the first comparison unit to form an output end (node ​​a) of the entire comparator circuit, and the output end of the second amplification unit is connected to the output end of the second comparison unit to form another output end (node ​​b) of the entire comparator circuit. In the present invention, since the first comparison unit and the second comparison unit have the same structural features, only the first comparison unit is specifically described herein. The first comparison unit includes a third MOS tube M23, a fourth MOS tube M24 and a fifth MOS tube M25, the source of the third MOS tube M23 is grounded, the drain is connected to the drain of the second MOS tube M22 and forms the output end (node ​​a) of the first comparison unit, the gate of the third MOS tube M23 is connected to the gate of the fifth MOS tube M25 and is connected to the output end of the second comparison unit, the source of the fourth MOS tube M24 and the fifth MOS tube M25 is connected to the power supply voltage VCC, the drain of the fourth MOS tube M24 and the fifth MOS tube M25 is connected to the drain of the third MOS tube M23, and the external first clock signal Clk is input to the gate of the fourth MOS tube M24. In addition, the second comparison unit has the same structural features as the first comparison unit, and also includes a third MOS tube M23', a fourth MOS tube M24' and a fifth MOS tube M25', and the drain of the third MOS tube M23' is connected to the drain of the second MOS tube M22' to form the output end (node ​​b) of the second comparison unit. In the present invention, the external first clock signal Clk and the second clock signal Clkb have the same frequency and opposite phases, which can be easily obtained by adding an inverter to the existing clock signal, and will not be described in detail here.

[0029] In addition, in the amplifier of the present invention, the fourth MOS tubes M24, M24' and the fifth MOS tubes M25, M25' are all P-type MOS tubes. When the preamplifier is working, the first amplification unit and the second amplification unit amplify the input differential signals Vinp, Vinn and transmit them to nodes a, b, so that the fourth MOS tubes M24, M24' are turned on. By adjusting the size of the fourth MOS tubes M24, M24', the voltage of nodes a, b can be adjusted to near VCC-VTH (VTH is the threshold voltage of the fifth MOS tubes M25, M25', that is, the threshold voltage of the P-type MOS tube, which is a constant value) so that the fifth MOS tubes M25, M25' are in a subthreshold state at this time, and the third MOS tubes M23, M23' are turned on, so at this time, two of the four MOS tubes (fifth MOS tubes M25, M25', third MOS tubes M23, M23') of positive feedback are in a turned-on state and two are in a subthreshold state. When the external first clock signal Clk is high, the external second clock signal Clkb is low, so that the preamplifier is in an inoperative state; at this time, since the voltages of nodes a and b are near the value of VCC-VTH, the fifth MOS tubes M25 and M25' can quickly turn on one of them based on the voltage difference between nodes a and b, so that positive feedback is quickly performed, thereby reducing the comparison time and speeding up the comparison. Finally, one of the voltages of nodes a and b will be pulled up to the power supply voltage VCC, and the other will be pulled down to the ground voltage GND. At this time, the voltages of nodes a and b are also output as the output voltages of the entire comparator circuit.

[0030] As a preferred embodiment of the present invention, the comparator further includes a sixth MOS tube M26, a drain of the sixth MOS tube M26 is connected to the source of the third MOS tubes M23 and M23' of the first comparison unit and the second comparison unit, a first clock signal CLK is input to the gate of the sixth MOS tube M26, and the source of the sixth MOS tube M26 is grounded; that is, the source of the third MOS tubes M23 and M23' is grounded through the sixth MOS tube M26, so as to provide the third MOS tubes M23 and M23' with a suitable tail current, thereby controlling the current size of the entire comparator circuit.

[0031] In addition, as described in the background technology, there is an offset voltage Vo at the input end of the preamplifier. This erroneous offset voltage Vo may cause an error in the output result of the output end. In order to reduce or even prevent the influence of the offset voltage Vo on the entire circuit, in the preamplifier of the present invention, the first amplification unit further includes a seventh MOS tube M27, the source of the seventh MOS tube M27 is connected to the drain of the first MOS tube M21, and the drain is connected to the output end of the second comparison unit, and the external positive calibration voltage V REF+ Input the gate of the seventh MOS tube M27; correspondingly, the external negative calibration voltage VREF- The gate of the seventh MOS tube M27' of the second amplifying unit is input; thereby the forward calibration voltage V REF+ With negative calibration voltage V REF- The influence of the offset voltage Vo on the entire circuit can be reduced or eliminated, thereby improving the accuracy of the comparator output result. REF+ With negative calibration voltage V REF- The voltage value of is related to the offset voltage Vo, and the relationship between the offset voltage Vo and the output voltage Vout of the preamplifier is as follows:

[0032] Vout=Va-Vb=A·(Vinp-Vinn-Vo-W(V REF+ -V REF- )) (1)

[0033] Wherein, in formula (1), Vout is the output voltage of the preamplifier, A is the gain of the preamplifier, Va is the voltage value of the output end of the first comparison unit, Vb is the voltage value of the output end of the second comparison unit, Vinp and Vinn are the voltage values ​​of the differential input signals input to the preamplifier, and V REF+ and V REF- are external calibration voltages input to the first amplifying unit and the second amplifying unit, that is, the calibration voltage V REF+ Input the gate of the seventh MOS tube M27, calibrate the voltage V REF- Input the gate of the seventh MOS tube M27', W is the ratio of the width of the second MOS tube M22 to the width of the seventh MOS tube M27. In the above formula, when Vinp = Vinn, and there is no influence of the offset voltage Vo in the whole circuit, the output voltage Vout of the preamplifier is 0, that is, Va = Vb, and the formula (1) can be obtained by transformation:

[0034] Vinp-Vinn=Vo-W(V REF+ -V REF- ) (2)

[0035] That is,

[0036] Vo = W(V REF+ -V REF- ) (3)

[0037] As mentioned above, in equation (3), the parameter W is a known constant, and the offset voltage Vo is also a fixed constant, so that the offset voltage V can be adjusted by inputting a suitable calibration voltage V REF+ 、V REF- So that equation (3) holds true, thereby eliminating the influence of the offset voltage Vo on the entire circuit.

[0038] Please refer to Figure 4 , Figure 4 FIG. 1 is a schematic diagram of a calibration circuit for a comparator circuit of a SAR ADC according to the present invention. Figure 4 As shown, the calibration circuit includes a comparator COPM, a DAC unit and a digital logic unit; wherein the comparator COPM is Figure 3 The comparator circuit shown in the figure; the same external reference voltage VCM is input as a differential signal to the positive input terminal (Vinp) and the negative input terminal (Vinn) of the comparator COPM respectively, and the output terminal (node ​​a or node b) of the comparator COPM is connected to the digital logic unit. Under the control of the first clock signal Clk, the digital logic controls the DAC unit to output the positive calibration voltage V REF+ With negative calibration voltage V REF- to the comparator COPM to achieve calibration of the offset voltage Vo of the comparator COPM. Figure 4 In the circuit shown, since the comparator COPM has an offset voltage VO, the output (Va or Vb) of the comparator COPM must be VCC or 0, and is output to the digital logic unit. The digital logic unit controls the DAC unit to output the positive calibration voltage V by inputting 0 or the power supply voltage VCC. REF+ With negative calibration voltage V REF- ; For example, if the output of comparator COPM is 0, it means that the positive calibration voltage V REF+ If the value of is too small and needs to be increased, the digital logic unit outputs a digital control character with a larger digit to the DAC unit, so that the DAC unit outputs a positive calibration voltage V with a larger value. REF+ , while the negative calibration voltage V REF- The adjustment process is the opposite. Repeat the above process until the DAC unit completes the output of the last bit. Keep the positive calibration voltage V REF+ With negative calibration voltage V REF- The value of the comparator circuit ( Figure 3 ) During normal operation, this value is input into the gate of the seventh MOS tube M27, M27' of the comparator circuit to complete the calibration of the offset voltage Vo. In the calibration process of the offset voltage Vo of the present invention, the positive calibration voltage V REF+ With negative calibration voltage V REF- The accuracy is specifically determined by the number of output bits of the DAC unit. The more output bits there are, the higher the corresponding accuracy is. Of course, the more repeated calibrations are required, and the more time is required. In the specific application process, the DAC unit with the required accuracy can be flexibly selected according to the actual situation, and the present invention is not limited to this.

[0039] The comparator circuit and calibration circuit for SAR ADC of the present invention are provided with fourth MOS tubes M24 and M24' between the output terminals of the first amplifying unit and the first comparing unit and the power supply voltage, and between the output terminals of the second amplifying unit and the second comparing unit and the power supply voltage. Therefore, when the fourth MOS tubes M24 and M24' are turned on, the voltages of the two output terminals are adjusted to the difference between the power supply voltage VCC and the threshold voltage VTH of the P-type MOS tube (fifth MOS tube M25 and M25'), and the P-type MOS tube (fifth MOS tube M25 and M25') is turned on quickly, and the positive feedback process is started quickly, thereby reducing the comparison time and accelerating the comparison speed. In addition, by providing the calibration circuit, the positive calibration voltage V REF+ With negative calibration voltage V REF- , the offset voltage Vo existing at the input end of the preamplifier can be calibrated, thereby improving the accuracy of the output result of the comparator circuit.

[0040] The present invention has been described above in conjunction with the best embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations based on the essence of the present invention.

Claims

1. A comparator circuit for a SAR ADC, comprising a preamplifier and a comparator, wherein the preamplifier amplifies a pair of input differential signals, and the comparator compares the amplified pair of differential signals to obtain a comparison result; characterized in that: The preamplifier includes a first amplifying unit and a second amplifying unit with the same structural features, the comparator includes a first comparing unit and a second comparing unit with the same structural features, an external pair of differential signals are respectively input into the input ends of the first amplifying unit and the second amplifying unit, the output end of the first amplifying unit is connected to the output end of the first comparing unit, and the output end of the second amplifying unit is connected to the output end of the second comparing unit; the first amplifying unit includes a first MOS tube and a second MOS tube, the source of the first MOS tube is grounded, the drain is connected to the source of the second MOS tube, an external second clock signal is input into the gate of the second MOS tube, and a differential signal is input into the second MOS The gate of the MOS tube is connected to the gate of the second MOS tube, and the drain of the second MOS tube is connected to the output end of the first amplifying unit; the first comparing unit includes a third MOS tube, a fourth MOS tube and a fifth MOS tube, the source of the third MOS tube is grounded, the drain forms the output end of the first comparing unit, the gate of the third MOS tube is commonly connected with the gate of the fifth MOS tube and connected to the output end of the second comparing unit, the source of the fourth MOS tube and the fifth MOS tube are connected to the power supply voltage, the drain of the fourth MOS tube and the fifth MOS tube is connected to the drain of the third MOS tube, and the external first clock signal is input to the gate of the fourth MOS tube; the external first clock signal has the same frequency as the second clock signal but has an opposite phase.

2. The comparator circuit for SAR ADC according to claim 1, wherein: The comparator further includes a sixth MOS tube, the drain of which is connected to the sources of the third MOS tubes of the first comparison unit and the second comparison unit, the first clock signal is input to the gate of the sixth MOS tube, and the source of the sixth MOS tube is grounded.

3. The comparator circuit for SAR ADC according to claim 2, wherein: The first amplifying unit also includes a seventh MOS tube, the source of the seventh MOS tube is connected to the drain of the first MOS tube, and the drain is connected to the output end of the second comparing unit. An external positive calibration voltage is input to the gate of the seventh MOS tube; and an external negative calibration voltage is input to the second amplifying unit.

4. The comparator circuit for SAR ADC according to claim 3, characterized in that: The fourth MOS tube and the fifth MOS tube are both P-type MOS tubes.

5. The comparator circuit for SAR ADC according to claim 4, characterized in that: The size of the fourth MOS tube is adjusted and changed, and the voltage at the output end of the first comparison unit is adjusted to the difference between the power supply voltage and the threshold voltage of the fifth MOS tube, so that the fifth MOS tube is in a sub-threshold state.

6. The comparator circuit for SAR ADC according to claim 5, characterized in that: The relationship between the offset voltage Vo of the comparator equivalent to the preamplifier end and the output voltage Vout of the preamplifier is as follows: Vout=Va-Vb=A·(Vinp-Vinn-Vo-W(V REF +-V REF- )) Wherein, A is the gain of the preamplifier, Va is the voltage value of the output end of the first comparison unit, Vb is the voltage value of the output end of the second comparison unit, Vinp and Vinn are the voltage values ​​of the differential input signal input to the preamplifier, V REF + and V REF- are external calibration voltages input to the first amplifying unit and the second amplifying unit respectively, and W is the ratio of the width of the second MOS tube to that of the seventh MOS tube.

7. The calibration circuit for the comparator circuit of the SAR ADC according to claim 6, characterized in that: It includes a comparator, a DAC unit and a digital logic unit. The same external reference voltage is input as a differential signal into the positive input terminal and the negative input terminal of the comparator respectively. The output terminal of the comparator is connected to the digital logic unit. Under the control of a first clock signal, the digital logic controls the DAC unit to output a positive calibration voltage and a negative calibration voltage to the comparator.

8. The calibration circuit for the comparator circuit of the SAR ADC according to claim 7, characterized in that: Each time the comparator outputs an output value, the digital logic unit controls the DAC unit to output a pair of calibration voltage values ​​to the comparator until the DAC unit completes the output of the last bit.

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