Three-stage pipelined successive approximation analog-to-digital converter

Abstract

The invention relates to a three-stage pipelined successive approximation analog-to-digital converter, an SAR ADC circuit comprises a first-stage sub SAR ADC module, a second-stage sub SAR ADC module and a third-stage sub SAR ADC module which are connected in sequence, and a shared residual operational amplifier comprises a first differential input stage and a second differential input stage which are mutually independent; the first-stage sub-SAR ADC module is used for sampling and quantizing the input signal and outputting a first residual signal; the first differential input stage is used for amplifying the first residual signal; the second-stage sub SAR ADC module is used for sampling and quantifying the first residual signal amplified by the first differential input stage and outputting a second residual signal; the second differential input stage is used for amplifying a second residual signal; and the third-stage sub SAR ADC module is used for sampling and quantizing the second residual signal amplified by the second differential input stage and outputting the second residual signal. The two stages of sub SAR ADC modules share one shared residual operational amplifier for amplification, so that the area of the whole circuit of the analog-to-digital converter is effectively saved, and the power consumption is reduced.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit design, and in particular relates to a three-stage pipelined successive approximation analog-to-digital converter. Background Art

[0002] An analog-to-digital converter (ADC) is an electronic device that converts analog signals into digital signals. It plays a vital role in many applications, such as audio processing, measurement and control, digital image processing, and audio encoding and decoding. The core principles behind these applications are the diversity and continuity of analog signals, while digital signals offer the advantages of easier storage, processing, and transmission. Therefore, ADCs are widely used in modern electronics, communications, and data processing.

[0003] Ultrasonic imaging systems require extremely high precision to capture subtle echo signals in order to generate high-resolution images. The resolution and accuracy of the ADC determine the signal details that can be captured. A high-resolution ADC (such as 12 bits) can provide higher signal accuracy, thereby helping to form finer and more accurate images. With the development of imaging technology, in order to obtain higher longitudinal and radial resolution, the number of transducer elements and the resonant frequency are increasing, and the accuracy and bandwidth required for ultrasonic signal processing circuits are also increasing. Among them, the Pipeline SAR ADC combines the advantages of the Pipeline ADC and the SAR C (Successive approximation Register) ADC architecture, achieving a good balance between power consumption, speed and resolution, and is particularly suitable for medium-speed and high-precision applications.

[0004] Some ultrasound imaging technologies utilize SAR ADCs (Successive Approximation Register ADCs). SAR ADCs typically offer high resolution (12 to 16 bits), making them suitable for ultrasound systems requiring high-resolution imaging. They also typically consume low power, making them suitable for portability and long-duration applications. Pipeline ADCs are also commonly used in ultrasound imaging systems. Their ability to provide very high sampling rates, typically reaching hundreds of MHz or even higher, gives them significant advantages in real-time applications requiring high-speed imaging. They offer a wide dynamic range, making them crucial for accurately capturing ultrasound signals, especially when dealing with weak echo signals from deep tissues, effectively reducing distortion and ensuring image quality. However, the sampling rate of existing SAR ADCs is limited by their successive approximation principle. While they offer high sampling accuracy, their sampling speed is typically slow, making them unsuitable for ultrasound systems requiring high sampling rates. Furthermore, each conversion requires several clock cycles, resulting in long conversion times. Existing pipelined analog-to-digital converters use a multi-stage structure, which may cause delays during the conversion process. Especially in ultrasound imaging applications that require extremely high speed and extremely low latency, the delay of the pipelined analog-to-digital converter may become a bottleneck limiting its application. In addition, the multi-stage structure also requires multiple corresponding residual amplifiers for residual methods, which easily leads to excessive power consumption, resulting in limited application in ultrasound imaging systems in portable or battery-powered devices.

[0005] Therefore, it is necessary to reduce the power consumption and area of ​​the entire analog-to-digital converter circuit, and propose a low-power and compact analog-to-digital converter structure. Summary of the Invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a three-stage pipelined successive approximation analog-to-digital converter. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] The present invention provides a three-stage pipelined successive approximation analog-to-digital converter, comprising: a SAR ADC circuit and a shared residual operational amplifier; the SAR ADC circuit comprises a first-stage sub-SAR ADC module, a second-stage sub-SAR ADC module, and a third-stage sub-SAR ADC module connected in sequence; the shared residual operational amplifier comprises two mutually independent first differential input stages and second differential input stages; wherein the first-stage sub-SAR ADC module is configured to sample and quantize an input signal and output a first residual signal; the first differential input stage is configured to amplify the first residual signal; the second-stage sub-SAR ADC module is configured to sample and quantize the first residual signal amplified by the first differential input stage and output a second residual signal; the second differential input stage is configured to amplify the second residual signal; and the third-stage sub-SAR ADC module is configured to sample and quantize the second residual signal amplified by the second differential input stage and output the second residual signal.

[0008] In one embodiment of the present invention, the resolutions of the three-stage sub-SAR ADC modules connected sequentially are 5-bit, 5-bit, and 6-bit, respectively.

[0009] In one embodiment of the present invention, the three-stage pipelined successive approximation analog-to-digital converter further includes a digital correction module for respectively correcting the output signals of the first-stage sub-SAR ADC module, the second-stage sub-SAR ADC module, and the third-stage sub-SAR ADC module to obtain a 14-bit output signal.

[0010] In one embodiment of the present invention, the SAR ADC circuit, the shared residual operational amplifier, and the digital correction module are all controlled by a clock control signal.

[0011] In one embodiment of the present invention, the shared residual operational amplifier includes: a PMOS transistor M0, a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, a PMOS transistor M4, a PMOS transistor M5, a PMOS transistor M6, a PMOS transistor M7, a PMOS transistor M8, an NMOS transistor M9, an NMOS transistor M10, an NMOS transistor M11, an NMOS transistor M12, an NMOS transistor M13, an NMOS transistor M14, an NMOS transistor M15, an NMOS transistor M16, a PMOS transistor M17, a PMOS transistor M18, a second auxiliary operational amplifier module, and a first auxiliary operational amplifier module; wherein the gate of the PMOS transistor M0 is connected to the first bias voltage terminal, and the source is connected to the high level terminal of the driving power supply. , the drains are respectively connected to the sources of the PMOS tubes M1, M2, M3, M4, M17 and M18; the gate of the PMOS tube M1 inputs the first negative-phase residual signal, the gate of the PMOS tube M2 inputs the first positive-phase residual signal; the gate of the PMOS tube M3 inputs the second negative-phase residual signal, the gate of the PMOS tube M4 inputs the second positive-phase residual signal; the gate of the PMOS tube M17 is connected to the gate of the PMOS tube M18 and is connected to the common-mode signal terminal; the drain of the PMOS tube M17 is connected to the drain of the NMOS tube M10; the drain of the PMOS tube M18 is connected to the drain of the NMOS tube M9; the gate of the PMOS tube M5 inputs the first clock control The gate of the PMOS tube M6 receives the first clock control signal, the source is connected to the drain of the PMOS tube M2, and the drain is connected to the drains of the PMOS tube M8 and the NMOS tube M9 respectively; the gate of the PMOS tube M7 receives the second clock control signal, and the source is connected to the drain of the PMOS tube M3; the gate of the PMOS tube M8 receives the second clock control signal, and the source is connected to the drain of the PMOS tube M4; the gate of the NMOS tube M9 is connected to the gate of the NMOS tube M10 and is also connected to the common-mode feedback signal terminal; the sources of the NMOS tubes M9 and M10 are both connected to the low-level terminal of the driving power supply. The drain of the NMOS tube M9 is respectively connected to the source of the NMOS tube M11 and the non-inverting input terminal of the first auxiliary operational amplifier module; the drain of the NMOS tube M10 is respectively connected to the source of the NMOS tube M12 and the inverting input terminal of the first auxiliary operational amplifier module; the gate of the NMOS tube M11 is connected to the non-inverting output terminal of the first auxiliary operational amplifier module, and the drain is connected to the drain of the NMOS tube M13; the gate of the NMOS tube M12 is connected to the inverting output terminal of the first auxiliary operational amplifier module, and the drain is connected to the drain of the NMOS tube M14; the gate of the NMOS tube M13 is connected to the inverting output terminal of the second auxiliary operational amplifier module, and the source is respectively connected to the drain of the NMOS tube M15 and the non-inverting input terminal of the second auxiliary operational amplifier module;The gate of NMOS transistor M14 is connected to the non-inverting output terminal of the second auxiliary operational amplifier module, and the source is respectively connected to the drain of NMOS transistor M16 and the inverting input terminal of the second auxiliary operational amplifier module; the gate of NMOS transistor M15 is connected to the gate of NMOS transistor M16 and to the first bias voltage terminal; the sources of NMOS transistors M15 and M16 are both connected to the high-level terminal of the driving power supply.

[0012] In one embodiment of the present invention, the drain of the NMOS transistor M11 serves as the inverting differential output terminal of the shared residual operational amplifier; the drain of the NMOS transistor M12 serves as the non-inverting differential output terminal of the shared residual operational amplifier.

[0013] In one embodiment of the present invention, the first auxiliary operational amplifier module includes: PMOS tube M01, PMOS tube M02, PMOS tube M03, PMOS tube M04, PMOS tube M05, PMOS tube M06, PMOS tube M07, PMOS tube M08, PMOS tube M09, NMOS tube M010, NMOS tube M011, NMOS tube M012 and NMOS tube M013; wherein the gate of the PMOS tube M01 inputs the inverted differential input signal, and the source is connected to the PMOS tubes M01 and M02 respectively. The source of M02, the source of PMOS tube M03 and the drain of PMOS tube M05 are connected to the source of NMOS tube M011 and the drain of NMOS tube M013 respectively; the gate of PMOS tube M02 inputs the positive phase differential input signal, and the drain is connected to the source of NMOS tube M010 and the drain of NMOS tube M012 respectively; the gate of PMOS tube M03 inputs the positive phase common mode voltage signal, and the drain is connected to the low level end of the driving power supply; the gate of PMOS tube M04 inputs the first positive phase bias voltage, and the source is connected to the driving power supply The high-level end of the PMOS transistor M06 is connected to the source of the PMOS transistor M08, and the drain of the PMOS transistor M07 is connected to the source of the PMOS transistor M09; the gate of the PMOS transistor M05 inputs the second positive phase bias voltage; the gate of the PMOS transistor M06 is connected to the gate of the PMOS transistor M07 and inputs the first positive phase bias voltage; the sources of the PMOS transistors M06 and M07 are both connected to the high-level end of the driving power supply; the drain of the PMOS transistor M06 is connected to the source of the PMOS transistor M08, and the drain of the PMOS transistor M07 is connected to the source of the PMOS transistor M09; the gate of the PMOS transistor M08 is connected to the gate of the PMOS transistor M09. The gate of the PMOS tube M09 is connected to the drain of the NMOS tube M010, and the second positive phase bias voltage is input; the drain of the PMOS tube M08 is connected to the drain of the NMOS tube M010; the drain of the PMOS tube M09 is connected to the drain of the NMOS tube M011; the gate of the NMOS tube M010 is connected to the gate of the NMOS tube M011, and the second negative phase bias voltage is input; the gate of the NMOS tube M012 is connected to the gate of the NMOS tube M013, and the first negative phase bias voltage is input; the source electrodes of the NMOS tubes M012 and M013 are both connected to the low level end of the driving power supply.

[0014] In one embodiment of the present invention, the second auxiliary operational amplifier module includes: NMOS transistor M21, NMOS transistor M22, NMOS transistor M23, NMOS transistor M24, NMOS transistor M25, PMOS transistor M26, PMOS transistor M27, PMOS transistor M28, PMOS transistor M29, NMOS transistor M210, NMOS transistor M211, NMOS transistor M212 and NMOS transistor M213; wherein the gate of NMOS transistor M21 inputs the inverted differential input signal, and the source is connected to the NMOS transistors M21 and M213 respectively. The source of M22, the source of NMOS tube M23 and the drain of NMOS tube M24 are connected to the drain of PMOS tube M27 and the source of PMOS tube M29 respectively; the gate of NMOS tube M22 inputs the positive phase differential input signal, and the drain is connected to the drain of PMOS tube M26 and the source of PMOS tube M28 respectively; the gate of NMOS tube M23 inputs the negative phase common mode voltage signal, and the drain is connected to the high level end of the driving power supply; the gate of NMOS tube M24 inputs the second negative phase bias voltage, and the source is connected to NMOS tube M25 The drain of the NMOS tube M25 is connected to the gate of the NMOS tube M25 and inputs the first negative phase bias voltage, and the source is connected to the low level end of the driving power supply; the gate of the PMOS tube M26 is connected to the gate of the PMOS tube M27 and inputs the first positive phase bias voltage; the sources of the PMOS tubes M26 and M27 are both connected to the high level end of the driving power supply; the gate of the PMOS tube M28 is connected to the gate of the PMOS tube M29 and inputs the second positive phase bias voltage; the drain of the PMOS tube M28 is connected to the drain of the NMOS tube M210; the drain of the PMOS tube M29 is connected to the drain of the NMOS tube M210. The gate of the NMOS transistor M210 is connected to the drain of the NMOS transistor M211; the gate of the NMOS transistor M210 is connected to the gate of the NMOS transistor M211 and inputs the second inverting bias voltage; the source of the NMOS transistor M210 is connected to the drain of the NMOS transistor M212; the source of the NMOS transistor M211 is connected to the source of the NMOS transistor M213; the gate of the NMOS transistor M212 is connected to the gate of the NMOS transistor M213 and inputs the first inverting bias voltage; the sources of the NMOS transistors M212 and M213 are both connected to the low-level end of the driving power supply.

[0015] In one embodiment of the present invention, the three-stage pipelined successive approximation analog-to-digital converter further includes: a common-mode feedback module, which is respectively connected to the positive-phase differential output terminal and the negative-phase differential output terminal of the shared residual operational amplifier, and is used to maintain the balance between the positive-phase differential output terminal and the negative-phase differential output terminal of the shared residual operational amplifier.

[0016] In one embodiment of the present invention, a common-mode feedback module includes: a clock switch Φ1, a clock switch Φ2, a clock switch Φ3, a clock switch Φ4, a clock switch Φ5, a clock switch Φ6, a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4; wherein the first end of the clock switch Φ1 is respectively connected to the inverting differential output end and the first plate of the capacitor C2; the second end of the clock switch Φ1 is respectively connected to the first end of the clock switch Φ2 and the first plate of the capacitor C1; the second end of the clock switch Φ2 is connected to the common-mode signal end; the second plate of the capacitor C2 is respectively connected to the common-mode feedback signal end, the first end of the clock switch Φ3, and the first plate of the capacitor C4; The second plate of capacitor C1 is respectively connected to the second end of clock switch Φ3, the first end of clock switch Φ4, and the first plate of capacitor C3; the second end of clock switch Φ4 inputs the first inverted bias voltage; the second plate of capacitor C4 is respectively connected to the inverted differential output end and the first end of clock switch Φ5; the second plate of capacitor C3 is respectively connected to the second end of clock switch Φ5 and the first end of clock switch Φ6; the second end of clock switch Φ6 is connected to the common-mode signal end; clock switch Φ1, clock switch Φ3, and clock switch Φ5 are all controlled by the first clock control signal; clock switch Φ2, clock switch Φ4, and clock switch Φ6 are all controlled by the second clock control signal.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The three-stage pipelined successive approximation analog-to-digital converter (ADC) of the present invention features a shared residual operational amplifier (HA) equipped with two independent first and second differential input stages, each for inputting the residual signals output by the two-stage sub-SAR ADC modules. Simultaneously, both residual signals are amplified within the shared HA, reducing the number of interstage amplifiers required from two to one. This effectively reduces the overall ADC circuit area and power consumption, meeting the high-resolution, high-sampling-rate, and low-power requirements of ultrasonic imaging systems.

[0019] The three-stage sub-SAR ADC module of the present invention follows the area power consumption distribution and is distributed into 5-bit, 5-bit and 6-bit resolution structures according to the optimal speed, area and power consumption distribution law, meeting the low-power and compact design requirements.

[0020] The shared residual operational amplifier of the present invention is controlled by two pairs of switching tubes, and the switching tubes are controlled by clock signals. The compact design of the switching tubes is conducive to saving the area of ​​the overall circuit of the analog-to-digital converter and reducing power consumption. By switching the switching tubes, the function of amplification between two stages can be realized.

[0021] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 1 is a schematic diagram of a framework of a three-stage pipelined successive approximation analog-to-digital converter provided by an embodiment of the present invention;

[0023] Figure 2 This is a working timing diagram of a three-stage pipelined successive approximation analog-to-digital converter provided by an embodiment of the present invention;

[0024] Figure 3 1 is a schematic structural diagram of a shared residual operational amplifier provided by an embodiment of the present invention;

[0025] Figure 4 A schematic structural diagram of a first auxiliary operational amplifier module provided in an embodiment of the present invention.

[0026] Figure 5 A schematic structural diagram of a second auxiliary operational amplifier module provided by an embodiment of the present invention.

[0027] Figure 6 A schematic structural diagram of a common-mode feedback module provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, a three-stage pipelined successive approximation analog-to-digital converter proposed in accordance with the present invention is described in detail below with reference to the accompanying drawings and specific implementation methods.

[0029] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0030] Example 1

[0031] In order to meet the performance requirements of ADC in ultrasound imaging system and maximize the efficiency of area and power consumption, the present invention provides a three-stage pipelined successive approximation analog-to-digital converter, such as Figure 1 As shown,

[0032] In this embodiment, a three-stage pipelined successive approximation analog-to-digital converter includes: a SAR ADC circuit and a shared residual operational amplifier; the SAR ADC circuit includes a first-stage sub-SAR ADC module, a second-stage sub-SAR ADC module, and a third-stage sub-SAR ADC module connected in sequence; the shared residual operational amplifier includes two independent first and second differential input stages; wherein the first-stage sub-SAR ADC module is configured to sample and quantize an input signal VIN and output a first residual signal; the first differential input stage is configured to amplify the first residual signal; the second-stage sub-SAR ADC module is configured to sample and quantize the first residual signal amplified by the first differential input stage and output a second residual signal; the second differential input stage is configured to amplify the second residual signal; and the third-stage sub-SAR ADC module is configured to sample and quantize the second residual signal amplified by the second differential input stage and output it.

[0033] The principle is that the input signal VIN is input to the first-stage sub-SAR ADC module. After sampling and quantization, the first residual signal is output to the first differential input stage of the shared residual operational amplifier. The amplified signal is input to the second-stage sub-SAR ADC module. The second residual signal output after the second-stage sampling and quantization process is input to the second differential input stage of the shared residual amplifier. After further amplification, it is input to the third-stage sub-SAR ADC module. The third-stage sub-SAR ADC module only requires sampling and quantization, without amplification, and therefore has the longest conversion time.

[0034] It is worth noting that due to the architecture of the three-stage sub-SAR ADC module of the SAR ADC circuit, the two amplification stages of the shared residual operational amplifier will not work simultaneously. Therefore, the two residual amplifiers originally required can be combined into one, and the residual signals are input separately by the two differential input stages of the shared residual operational amplifier, reducing the power consumption and area of ​​the overall circuit.

[0035] Furthermore, in order to maximize the efficiency of area power consumption, the SAR ADC circuit is distributed according to the optimal speed, area and power consumption distribution law, and the resolutions of the three-stage sub-SAR ADC modules connected in sequence are set to 5-bit, 5-bit and 6-bit respectively.

[0036] Furthermore, the three-stage sub-SAR ADC modules all follow the area and power consumption allocation formula, and the resulting three-stage structure meets the requirements of low-power and compact design. Since there is 1-bit redundancy between each stage, a digital correction module is also provided to correct the output signals of the first-stage sub-SAR ADC module, the second-stage sub-SAR ADC module, and the third-stage sub-SAR ADC module respectively to obtain a 14-bit output signal.

[0037] Specifically, the working principle of the digital correction circuit is that the digital correction circuit is mainly composed of an error detection module and a calibration control logic, which is used to process the residual signal output by the three-stage sub-SAR ADC module through the digital correction circuit. Specifically, by digitally correcting the output of each stage and comparing the error with the preset target, when the output result deviates from the expected value, the digital correction circuit will feed back these errors to the corresponding stage and correct them through means including but not limited to gain, bias, nonlinear compensation, etc., which can effectively improve accuracy, linearity and stability. Finally, the digital codes generated by the three-stage sub-SAR ADC module are staggered and added. Since there is 1 bit of redundancy between each stage, a 14-bit output signal is finally obtained through dynamic range optimization.

[0038] It is understandable that the structures of the sub-SAR ADC modules and the digital correction circuit in the three-stage sub-SAR ADC module can be configured with reference to relevant prior art, and are not limited in this embodiment.

[0039] In this embodiment, the SAR ADC circuit, the shared residual operational amplifier, and the digital correction module are all controlled by a clock control signal.

[0040] It should be noted that the clock control signal can be generated by an external clock generation module. This clock control signal controls the sampling and quantization processes of the three-stage sub-SAR ADC module, as well as the two differential input stages and corresponding amplification stages of the shared residual amplifier. Similarly, each bias voltage signal can also be generated by an external bias signal generation circuit.

[0041] It is worth noting that the working timing diagram of the three-stage pipelined successive approximation analog-to-digital converter of this embodiment is as follows: Figure 2 As shown in the figure, it can be seen that the two residual amplification stages do not overlap during operation. Since there is no conflict between the two residual amplification processes of the sub-module in the SAR ADC circuit, if two amplifiers are used, the power consumption will be too high and the layout area will be too large. Therefore, the two inter-stage amplifiers originally required can be reduced to one, and a shared residual operational amplifier can be used for amplification.

[0042] like Figure 3As shown, in this embodiment, the shared residual operational amplifier includes: a PMOS transistor M0, a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, a PMOS transistor M4, a PMOS transistor M5, a PMOS transistor M6, a PMOS transistor M7, a PMOS transistor M8, an NMOS transistor M9, an NMOS transistor M10, an NMOS transistor M11, an NMOS transistor M12, an NMOS transistor M13, an NMOS transistor M14, an NMOS transistor M15, an NMOS transistor M16, a PMOS transistor M17, a PMOS transistor M18, a second auxiliary operational amplifier module AN, and a first auxiliary operational amplifier module AP;

[0043] Among them, the gate of the PMOS transistor M0 is connected to the first bias voltage terminal Vbp1, the source is connected to the high-level terminal VDD of the driving power supply, and the drain is respectively connected to the sources of the PMOS transistors M1, M2, M3, M4, M17 and M18; the gate of the PMOS transistor M1 is input with the first negative-phase residual signal Vin1, the gate of the PMOS transistor M2 is input with the first positive-phase residual signal Vip1; the gate of the PMOS transistor M3 is input with the second negative-phase residual signal Vin2, and the gate of the PMOS transistor M4 is input with the second positive-phase residual signal Vip2; the gate of the PMOS transistor M17 is connected to the gate of the PMOS transistor M18 and is also connected to the common-mode signal terminal VCM; The drain of the OS transistor M17 is connected to the drain of the NMOS transistor M10; the drain of the PMOS transistor M18 is connected to the drain of the NMOS transistor M9; the gate of the PMOS transistor M5 inputs the first clock control signal CLK1, the source is connected to the drain of the PMOS transistor M1, and the drain is respectively connected to the drains of the PMOS transistor M7 and the NMOS transistor M10; the gate of the PMOS transistor M6 inputs the first clock control signal CLK1, the source is connected to the drain of the PMOS transistor M2, and the drain is respectively connected to the drains of the PMOS transistor M8 and the NMOS transistor M9; the gate of the PMOS transistor M7 inputs the second clock control signal CLK2, and the source is connected to the drain of the PMOS transistor M3; the gate of the PMOS transistor M8 inputs the second clock control signal, and the source is connected to The drain of the PMOS transistor M4; the gate of the NMOS transistor M9 is connected to the gate of the NMOS transistor M10 and is connected to the common-mode feedback signal terminal Vcmc; the sources of the NMOS transistors M9 and M10 are both connected to the low-level terminal GND of the driving power supply; the drain of the NMOS transistor M9 is respectively connected to the source of the NMOS transistor M11 and the positive-inverting input terminal of the first auxiliary operational amplifier module AP; the drain of the NMOS transistor M10 is respectively connected to the source of the NMOS transistor M12 and the negative-inverting input terminal of the first auxiliary operational amplifier module AP; the gate of the NMOS transistor M11 is connected to the positive-inverting output terminal of the first auxiliary operational amplifier module AP, and the drain is connected to the drain of the NMOS transistor M13; the gate of the NMOS transistor M12 is connected to the positive-inverting output terminal of the first auxiliary operational amplifier module AP The inverting output terminal of the amplifier module AP and the drain are connected to the drain of the NMOS tube M14; the gate of the NMOS tube M13 is connected to the inverting output terminal of the second auxiliary operational amplifier module AN, and the source is respectively connected to the drain of the NMOS tube M15 and the non-inverting input terminal of the second auxiliary operational amplifier module AN; the gate of the NMOS tube M14 is connected to the non-inverting output terminal of the second auxiliary operational amplifier module AN, and the source is respectively connected to the drain of the NMOS tube M16 and the inverting input terminal of the second auxiliary operational amplifier module AN; the gate of the NMOS tube M15 is connected to the gate of the NMOS tube M16 and is connected to the first bias voltage terminal Vbp1; the sources of the NMOS tubes M15 and M16 are both connected to the high-level terminal VDD of the driving power supply.

[0044] Specifically, the drain of the NMOS transistor M11 serves as the inverting differential output terminal VON of the shared residual operational amplifier; the drain of the NMOS transistor M12 serves as the positive differential output terminal VOP of the shared residual operational amplifier.

[0045] like Figure 4 As shown, in an optional embodiment, the first auxiliary operational amplifier module AP includes: a PMOS transistor M01, a PMOS transistor M02, a PMOS transistor M03, a PMOS transistor M04, a PMOS transistor M05, a PMOS transistor M06, a PMOS transistor M07, a PMOS transistor M08, a PMOS transistor M09, an NMOS transistor M010, an NMOS transistor M011, an NMOS transistor M012, and an NMOS transistor M013;

[0046] Among them, the gate of the PMOS transistor M01 inputs the inverting differential input signal Vin, the source is respectively connected to the source of the PMOS transistor M02, the source of the PMOS transistor M03 and the drain of the PMOS transistor M05, and the drain is respectively connected to the source of the NMOS transistor M011 and the drain of the NMOS transistor M013; the gate of the PMOS transistor M02 inputs the positive differential input signal Vip, and the drain is respectively connected to the source of the NMOS transistor M010 and the drain of the NMOS transistor M012; the gate of the PMOS transistor M03 inputs the positive common mode voltage signal Vmp, and the drain is connected to the low level terminal GND of the driving power supply; the gate of the PMOS transistor M04 inputs the first positive phase bias voltage Vbp1, the source is connected to the high level terminal VDD of the driving power supply, and the drain is connected to the source of the PMOS transistor M05; the gate of the PMOS transistor M05 inputs the second positive phase bias voltage Vbp2; the gate of the PMOS transistor M06 is connected to the gate of the PMOS transistor M07 and inputs The first positive phase bias voltage Vbp1 is input; the sources of the PMOS transistors M06 and M07 are both connected to the high level terminal VDD of the driving power supply; the drain of the PMOS transistor M06 is connected to the source of the PMOS transistor M08, and the drain of the PMOS transistor M07 is connected to the source of the PMOS transistor M09; the gate of the PMOS transistor M08 is connected to the gate of the PMOS transistor M09, and the second positive phase bias voltage Vbp2 is input; the drain of the PMOS transistor M08 is connected to the drain of the NMOS transistor M010; the drain of the PMOS transistor M09 is connected to the drain of the NMOS transistor M011; the gate of the NMOS transistor M010 is connected to the gate of the NMOS transistor M011, and the second negative phase bias voltage Vbn2 is input; the gate of the NMOS transistor M012 is connected to the gate of the NMOS transistor M013, and the first negative phase bias voltage Vbn1 is input; the sources of the NMOS transistors M012 and M013 are both connected to the low level terminal of the driving power supply.

[0047] like Figure 5As shown, in an optional embodiment, the second auxiliary operational amplifier module AN includes: an NMOS transistor M21, an NMOS transistor M22, an NMOS transistor M23, an NMOS transistor M24, an NMOS transistor M25, a PMOS transistor M26, a PMOS transistor M27, a PMOS transistor M28, a PMOS transistor M29, an NMOS transistor M210, an NMOS transistor M211, an NMOS transistor M212, and an NMOS transistor M213;

[0048] Among them, the gate of the NMOS transistor M21 inputs the inverted differential input signal Vin, the source is respectively connected to the source of the NMOS transistor M22, the source of the NMOS transistor M23 and the drain of the NMOS transistor M24, and the drain is respectively connected to the drain of the PMOS transistor M27 and the source of the PMOS transistor M29; the gate of the NMOS transistor M22 inputs the positive differential input signal Vip, and the drain is respectively connected to the drain of the PMOS transistor M26 and the source of the PMOS transistor M28; the gate of the NMOS transistor M23 inputs the inverted common mode voltage signal Vmn, and the drain is connected to the high level terminal VDD of the driving power supply; the gate of the NMOS transistor M24 inputs the second inverted bias voltage Vbn2, and the source is connected to the drain of the NMOS transistor M25; the gate of the NMOS transistor M25 inputs the first inverted bias voltage Vbn1, and the source is connected to the low level terminal GND of the driving power supply; the gate of the PMOS transistor M26 is connected to the gate of the PMOS transistor M27, and inputs the first positive voltage Vmn. The first positive phase bias voltage Vbp1 is input to the PMOS transistor M26; the sources of the PMOS transistor M26 and the PMOS transistor M27 are both connected to the high-level end of the driving power supply; the gate of the PMOS transistor M28 is connected to the gate of the PMOS transistor M29 and inputs the second positive phase bias voltage Vbp2; the drain of the PMOS transistor M28 is connected to the drain of the NMOS transistor M210; the drain of the PMOS transistor M29 is connected to the drain of the NMOS transistor M211; the gate of the NMOS transistor M210 is connected to the gate of the NMOS transistor M211 and inputs the second negative phase bias voltage Vbn2; the source of the NMOS transistor M210 is connected to the drain of the NMOS transistor M212; the source of the NMOS transistor M211 is connected to the source of the NMOS transistor M213; the gate of the NMOS transistor M212 is connected to the gate of the NMOS transistor M213 and inputs the first negative phase bias voltage Vbn1; the sources of the NMOS transistors M212 and M213 are both connected to the low-level end GND of the driving power supply.

[0049] It should be noted that by setting the positive common-mode voltage signal Vmp and the negative common-mode voltage signal Vmn, both the PMOS transistor M03 and the NMOS transistor M23 operate at an appropriate common-mode point. By introducing two auxiliary operational amplifier modules into the main structure of the shared residual operational amplifier, with the first auxiliary operational amplifier module AP and the second auxiliary operational amplifier module AN both connected to the differential output terminals of the main structure of the shared residual operational amplifier for gain compensation, a high-gain feedback path is provided to ensure high gain over a wide frequency range, thereby increasing gain without significantly affecting the system bandwidth.

[0050] In order to further improve the output stability of the shared residual operational amplifier in this embodiment, a common-mode feedback module is further provided. The common-mode feedback module is respectively connected to the positive-phase differential output terminal VOP and the negative-phase differential output terminal VON of the shared residual operational amplifier, and is used to maintain the balance between the positive-phase differential output terminal VOP and the negative-phase differential output terminal VON of the shared residual operational amplifier.

[0051] Specifically, the main function of the common-mode feedback module is to maintain the balance of the output signal by adjusting the common-mode signal between the two differential output terminals, thereby effectively reducing common-mode interference and improving the stability and accuracy of the system.

[0052] Furthermore, since the three-stage pipelined successive approximation analog-to-digital converter of this embodiment adopts a two-phase non-alternating clock control signal, this feature can also be utilized in the design to establish a common-mode feedback module CMFB based on the two-phase non-alternating clock control signal and the clock switch.

[0053] like Figure 6 As shown, specifically, the common-mode feedback module CMFB includes: a clock switch Φ1, a clock switch Φ2, a clock switch Φ3, a clock switch Φ4, a clock switch Φ5, a clock switch Φ6, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4; wherein the first end of the clock switch Φ1 is respectively connected to the inverting differential output terminal VON and the first plate of the capacitor C2; the second end of the clock switch Φ1 is respectively connected to the first end of the clock switch Φ2 and the first plate of the capacitor C1; the second end of the clock switch Φ2 is connected to the common-mode signal terminal VCM; the second plate of the capacitor C2 is respectively connected to the common-mode The feedback signal terminal Vcmc, the first terminal of the clock switch Φ3 and the first plate of the capacitor C4; the second plate of the capacitor C1 are respectively connected to the second terminal of the clock switch Φ3, the first terminal of the clock switch Φ4 and the first plate of the capacitor C3; the second terminal of the clock switch Φ4 inputs the first inverting bias voltage Vbn1; the second plate of the capacitor C4 is respectively connected to the inverting differential output terminal VON and the first terminal of the clock switch Φ5; the second plate of the capacitor C3 is respectively connected to the second terminal of the clock switch Φ5 and the first terminal of the clock switch Φ6; the second terminal of the clock switch Φ6 is connected to the common-mode signal terminal VCM.

[0054] In the common-mode feedback module, clock switches Φ1 , Φ3 and Φ5 are all controlled by the first clock control signal CLK1 ; clock switches Φ2 , Φ4 and Φ6 are all controlled by the second clock control signal CLK2 .

[0055] It is noteworthy that the common-mode feedback module (CMFB) can operate normally without being restricted by the output voltage range of the shared residual operational amplifier, thereby improving the flexibility and stability of the system. In addition, the design of the common-mode feedback module (CMFB) avoids the introduction of new parasitic zeros and poles, thereby reducing complexity and further improving system performance.

[0056] The operating principle of the three-stage pipelined successive approximation analog-to-digital converter of this embodiment is that the first differential input stage and the second differential input stage of the shared residual operational amplifier serve as two independent input paths. The first differential input stage and the second differential input stage respectively receive the residual signals output by the first-stage sub-SAR ADC module and the second-stage sub-SAR ADC module, and are amplified in the first-stage amplifier and the second-stage amplifier. The switching transistors PMOS transistors M5 and PMOS transistors M6 of the first-stage amplifier are controlled by a first clock control signal CLK1, while the switching transistors PMOS transistors M3 and PMOS transistors M4 of the second differential input stage are controlled by a second clock control signal CLK2.

[0057] When amplifying the residual signal output by the first-stage sub-SAR ADC module, the first clock control signal CLK1 is at a low level, and the switching transistors PMOS transistors M5 and PMOS transistors M6 of the first-stage amplifier are both turned on to achieve residual amplification. When amplifying the residual signal output by the second-stage sub-SAR ADC module, the second clock control signal CLK2 is at a low level, and the switching transistors PMOS transistors M7 and PMOS transistors M8 of the second-stage amplifier are both turned on to achieve residual amplification.

[0058] During the remaining phases, both the first and second clock control signals CLK1 and CLK2 are high. The first-stage amplifier's switching transistors, PMOS transistors M5 and M6, as well as the second differential input transistors, PMOS transistors M3 and M4, are all turned off. Both input paths are fully reset outside their respective amplification phases. PMOS transistors M17 and M18 receive a common-mode signal, creating a short circuit that eliminates residual charge at the input terminals and reduces the memory effect caused by parasitic capacitance at the input nodes. Furthermore, sharing a single operational amplifier streamlines the circuit structure, saving nearly 20% of area.

[0059] It is noteworthy that the three-stage pipelined successive approximation analog-to-digital converter of this embodiment uses a shared residual amplifier for residual amplification in a three-stage pipelined SAR ADC circuit with a distribution law that achieves optimal area and power consumption. Controlled by a clock control signal, it implements a two-stage amplification function using only two pairs of switching transistors (PMOS transistor M5, PMOS transistor M6, PMOS transistor M7, and PMOS transistor M8), effectively reducing area and power consumption compared to traditional circuits.

[0060] The three-stage pipelined successive approximation analog-to-digital converter (ADC) of the present invention features a shared residual operational amplifier (HA) equipped with two independent first and second differential input stages, each for inputting the residual signals output by the two-stage sub-SAR ADC modules. Simultaneously, both residual signals are amplified within the shared HA, reducing the number of interstage amplifiers required from two to one. This effectively reduces the overall ADC circuit area and power consumption, meeting the high-resolution, high-sampling-rate, and low-power requirements of ultrasonic imaging systems.

[0061] The three-stage sub-SAR ADC module of the present invention follows the area power consumption distribution and is distributed into 5-bit, 5-bit and 6-bit resolution structures according to the optimal speed, area and power consumption distribution law, meeting the low-power and compact design requirements.

[0062] The shared residual operational amplifier of the present invention is controlled by two pairs of switching tubes, and the switching tubes are controlled by clock signals. The compact design of the switching tubes is conducive to saving the area of ​​the overall circuit of the analog-to-digital converter and reducing power consumption. By switching the switching tubes, the function of amplification between two stages can be realized.

[0063] It should be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed. Without further limitation, elements defined by the phrase "comprising a..." do not preclude the presence of additional identical elements in the article or device comprising the elements. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. References to directions or positional relationships, such as "upper," "lower," "left," and "right," are based on those shown in the accompanying drawings and are intended solely for ease of description and simplification of the present invention. They do not indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limitations on the present invention.

[0064] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A three-stage pipelined successive approximation analog-to-digital converter, characterized in that: include: SAR ADC circuit and shared residual operational amplifier; The SAR ADC circuit includes a first-stage sub-SAR ADC module, a second-stage sub-SAR ADC module and a third-stage sub-SAR ADC module connected in sequence, and the shared residual operational amplifier includes a first differential input stage and a second differential input stage which are independent of each other; Among them, the first-stage sub-SAR ADC module is used to sample and quantize the input signal and output a first residual signal; the first differential input stage is used to amplify the first residual signal; the second-stage sub-SAR ADC module is used to sample and quantize the first residual signal amplified by the first differential input stage and output a second residual signal; the second differential input stage is used to amplify the second residual signal; the third-stage sub-SAR ADC module is used to sample and quantize the second residual signal amplified by the second differential input stage and output it.

2. The three-stage pipelined successive approximation analog-to-digital converter according to claim 1, characterized in that: The resolutions of the three-stage sub-SAR ADC modules connected sequentially are 5-bit, 5-bit and 6-bit respectively.

3. The three-stage pipelined successive approximation analog-to-digital converter according to claim 1, characterized in that: Also includes: The digital correction module is used to correct the output signals of the first-stage sub-SAR ADC module, the second-stage sub-SAR ADC module and the third-stage sub-SAR ADC module respectively to obtain a 14-bit output signal.

4. The three-stage pipelined successive approximation analog-to-digital converter according to claim 3, characterized in that: The SARADC circuit, the shared residual operational amplifier and the digital correction module are all controlled by a clock control signal.

5. The three-stage pipelined successive approximation analog-to-digital converter according to claim 1, characterized in that: The shared residual operational amplifier includes: PMOS tube M0, PMOS tube M1, PMOS tube M2, PMOS tube M3, PMOS tube M4, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, NMOS tube M9, NMOS tube M10, NMOS tube M11, NMOS tube M12, NMOS tube M13, NMOS tube M14, NMOS tube M15, NMOS tube M16, PMOS tube M17, PMOS tube M18, a second auxiliary operational amplifier module and a first auxiliary operational amplifier module; The gate of the PMOS tube M0 is connected to the first bias voltage terminal, the source is connected to the high level terminal of the driving power supply, and the drain is respectively connected to the source of the PMOS tube M1, the PMOS tube M2, the PMOS tube M3, the PMOS tube M4, the PMOS tube M17 and the PMOS tube M18; The gate of the PMOS tube M1 inputs a first negative phase residual signal, and the gate of the PMOS tube M2 inputs a first positive phase residual signal; the gate of the PMOS tube M3 inputs a second negative phase residual signal, and the gate of the PMOS tube M4 inputs a second positive phase residual signal; The gate of the PMOS tube M17 is connected to the gate of the PMOS tube M18 and is connected to the common mode signal terminal; the drain of the PMOS tube M17 is connected to the drain of the NMOS tube M10; the drain of the PMOS tube M18 is connected to the drain of the NMOS tube M9; The gate of the PMOS tube M5 inputs the first clock control signal, the source is connected to the drain of the PMOS tube M1, and the drain is respectively connected to the drains of the PMOS tube M7 and the NMOS tube M10; the gate of the PMOS tube M6 inputs the first clock control signal, the source is connected to the drain of the PMOS tube M2, and the drain is respectively connected to the drains of the PMOS tube M8 and the NMOS tube M9; The gate of the PMOS tube M7 inputs the second clock control signal, and the source is connected to the drain of the PMOS tube M3; the gate of the PMOS tube M8 inputs the second clock control signal, and the source is connected to the drain of the PMOS tube M4; The gate of the NMOS tube M9 is connected to the gate of the NMOS tube M10 and is connected to the common-mode feedback signal terminal; the source of the NMOS tube M9 and the NMOS tube M10 are both connected to the low-level terminal of the driving power supply; the drain of the NMOS tube M9 is respectively connected to the source of the NMOS tube M11 and the positive-phase input terminal of the first auxiliary operational amplifier module; the drain of the NMOS tube M10 is respectively connected to the source of the NMOS tube M12 and the negative-phase input terminal of the first auxiliary operational amplifier module; The gate of the NMOS tube M11 is connected to the positive phase output terminal of the first auxiliary operational amplifier module, and the drain is connected to the drain of the NMOS tube M13; the gate of the NMOS tube M12 is connected to the negative phase output terminal of the first auxiliary operational amplifier module, and the drain is connected to the drain of the NMOS tube M14; The gate of the NMOS tube M13 is connected to the inverting output terminal of the second auxiliary operational amplifier module, and the source is respectively connected to the drain of the NMOS tube M15 and the non-inverting input terminal of the second auxiliary operational amplifier module; the gate of the NMOS tube M14 is connected to the non-inverting output terminal of the second auxiliary operational amplifier module, and the source is respectively connected to the drain of the NMOS tube M16 and the inverting input terminal of the second auxiliary operational amplifier module; The gate of the NMOS tube M15 is connected to the gate of the NMOS tube M16 and to the first bias voltage terminal; the source electrodes of the NMOS tube M15 and the NMOS tube M16 are both connected to the high level terminal of the driving power supply.

6. The three-stage pipelined successive approximation analog-to-digital converter according to claim 5, characterized in that: The drain of the NMOS tube M11 serves as the inverting differential output terminal of the shared residual operational amplifier; the drain of the NMOS tube M12 serves as the positive differential output terminal of the shared residual operational amplifier.

7. The three-stage pipelined successive approximation analog-to-digital converter according to claim 5, characterized in that: The first auxiliary operational amplifier module includes: PMOS tube M01, PMOS tube M02, PMOS tube M03, PMOS tube M04, PMOS tube M05, PMOS tube M06, PMOS tube M07, PMOS tube M08, PMOS tube M09, NMOS tube M010, NMOS tube M011, NMOS tube M012 and NMOS tube M013; The gate of the PMOS tube M01 inputs an inverted differential input signal, the source is respectively connected to the source of the PMOS tube M02, the source of the PMOS tube M03 and the drain of the PMOS tube M05, and the drain is respectively connected to the source of the NMOS tube M011 and the drain of the NMOS tube M013; The gate of the PMOS tube M02 inputs a positive phase differential input signal, and the drain is respectively connected to the source of the NMOS tube M010 and the drain of the NMOS tube M012; The gate of the PMOS tube M03 inputs a positive common mode voltage signal, and the drain is connected to the low level end of the driving power supply; The gate of the PMOS tube M04 is input with a first positive phase bias voltage, the source is connected to the high level end of the driving power supply, and the drain is connected to the source of the PMOS tube M05; the gate of the PMOS tube M05 is input with a second positive phase bias voltage; The gate of the PMOS tube M06 is connected to the gate of the PMOS tube M07, and the first positive phase bias voltage is input; the source of the PMOS tube M06 and the PMOS tube M07 are both connected to the high level end of the driving power supply; the drain of the PMOS tube M06 is connected to the source of the PMOS tube M08, and the drain of the PMOS tube M07 is connected to the source of the PMOS tube M09; The gate of the PMOS tube M08 is connected to the gate of the PMOS tube M09 and inputs the second positive phase bias voltage; the drain of the PMOS tube M08 is connected to the drain of the NMOS tube M010; the drain of the PMOS tube M09 is connected to the drain of the NMOS tube M011; The gate of the NMOS tube M010 is connected to the gate of the NMOS tube M011, and inputs the second inverting bias voltage; the gate of the NMOS tube M012 is connected to the gate of the NMOS tube M013, and inputs the first inverting bias voltage; the source electrodes of the NMOS tube M012 and the NMOS tube M013 are both connected to the low level end of the driving power supply.

8. The three-stage pipelined successive approximation analog-to-digital converter according to claim 5, characterized in that: The second auxiliary operational amplifier module includes: NMOS tube M21, NMOS tube M22, NMOS tube M23, NMOS tube M24, NMOS tube M25, PMOS tube M26, PMOS tube M27, PMOS tube M28, PMOS tube M29, NMOS tube M210, NMOS tube M211, NMOS tube M212 and NMOS tube M213; The gate of the NMOS tube M21 inputs an inverted differential input signal, the source is respectively connected to the source of the NMOS tube M22, the source of the NMOS tube M23 and the drain of the NMOS tube M24, and the drain is respectively connected to the drain of the PMOS tube M27 and the source of the PMOS tube M29; The gate of the NMOS tube M22 inputs a positive phase differential input signal, and the drain is respectively connected to the drain of the PMOS tube M26 and the source of the PMOS tube M28; the gate of the NMOS tube M23 inputs a negative phase common mode voltage signal, and the drain is connected to the high level end of the driving power supply; The gate of the NMOS tube M24 inputs the second reverse bias voltage, and the source is connected to the drain of the NMOS tube M25; the gate of the NMOS tube M25 inputs the first reverse bias voltage, and the source is connected to the low level end of the driving power supply; The gate of the PMOS tube M26 is connected to the gate of the PMOS tube M27 and inputs a first positive phase bias voltage; the source electrodes of the PMOS tube M26 and the PMOS tube M27 are both connected to the high level end of the driving power supply; The gate of the PMOS tube M28 is connected to the gate of the PMOS tube M29 and inputs a second positive phase bias voltage; the drain of the PMOS tube M28 is connected to the drain of the NMOS tube M210; the drain of the PMOS tube M29 is connected to the drain of the NMOS tube M211; The gate of the NMOS tube M210 is connected to the gate of the NMOS tube M211 and inputs a second reverse bias voltage; the source of the NMOS tube M210 is connected to the drain of the NMOS tube M212; the source of the NMOS tube M211 is connected to the source of the NMOS tube M213; The gate of the NMOS tube M212 is connected to the gate of the NMOS tube M213 and inputs a first reverse bias voltage; the source electrodes of the NMOS tube M212 and the NMOS tube M213 are both connected to the low level end of the driving power supply.

9. The three-stage pipelined successive approximation analog-to-digital converter according to claim 6, characterized in that: Also includes: A common-mode feedback module is connected to the positive-phase differential output terminal and the negative-phase differential output terminal of the shared residual operational amplifier, respectively, and is used to maintain a balance between the positive-phase differential output terminal and the negative-phase differential output terminal of the shared residual operational amplifier.

10. The three-stage pipelined successive approximation analog-to-digital converter according to claim 9, characterized in that: The common mode feedback module includes: a clock switch Φ1, a clock switch Φ2, a clock switch Φ3, a clock switch Φ4, a clock switch Φ5, a clock switch Φ6, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4; Wherein, the first end of the clock switch Φ1 is respectively connected to the inverted differential output end and the first plate of the capacitor C2; the second end of the clock switch Φ1 is respectively connected to the first end of the clock switch Φ2 and the first plate of the capacitor C1; the second end of the clock switch Φ2 is connected to the common mode signal end; The second electrode plate of the capacitor C2 is respectively connected to the common-mode feedback signal terminal, the first terminal of the clock switch Φ3 and the first electrode plate of the capacitor C4; the second electrode plate of the capacitor C1 is respectively connected to the second terminal of the clock switch Φ3, the first terminal of the clock switch Φ4 and the first electrode plate of the capacitor C3; the second terminal of the clock switch Φ4 inputs the first reverse bias voltage; The second electrode plate of the capacitor C4 is respectively connected to the inverted differential output terminal and the first end of the clock switch Φ5; the second electrode plate of the capacitor C3 is respectively connected to the second end of the clock switch Φ5 and the first end of the clock switch Φ6; the second end of the clock switch Φ6 is connected to the common mode signal terminal; The clock switch Φ1, the clock switch Φ3 and the clock switch Φ5 are all controlled by the first clock control signal; The clock switch Φ2, the clock switch Φ4 and the clock switch Φ6 are all controlled by the second clock control signal.

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