A perturbation injection circuit and a perturbation injection method

Abstract

The present invention discloses a perturbation injection circuit and a perturbation injection method, which are applied to an analog-to-digital converter with a 1-bit quantizer. The perturbation injection circuit includes a capacitor array of a first-stage integrator in a loop filter, a 1-bit quantizer, and a perturbation unit. The output of the loop filter is connected to the 1-bit quantizer; the 1-bit quantizer includes a second sampling capacitor, a comparison capacitor, a first injection capacitor, a second injection capacitor, a comparator, and a register. The present invention injects two perturbation signals through the comparison capacitor, the first injection capacitor, and the second injection capacitor to obtain a corresponding second digital output quantity, and finally perturbs the capacitor array by combining the first digital output quantity output by the perturbation unit, so that the quantizer can ensure that the residual voltage is less than one least significant bit within the full input range, thereby solving the problem that the suppression effect of the prior art on the additional noise caused by the perturbation signal significantly decreases when the resolution is 1-bit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to a perturbation injection circuit and a perturbation injection method. Background Art

[0002] Sigma-delta ADC (Analog-to-Digital Converter) is a commonly used medium and high-precision ADC structure. However, when the input signal is DC or slowly changing with a small amplitude (such as in sensor applications and other fields), the output of the modulator will exhibit an idle tone phenomenon, thereby deteriorating the signal-to-noise and distortion ratio (SNDR) in the band. By injecting a discrete random perturbation signal (dither) at the input of the quantizer, the problem of idle tone can be eliminated. However, this method not only reduces the signal-to-quantization noise ratio (SQNR) of the modulator, but also causes an increase in the output swing of the first-stage integrator, thereby imposing higher linearity requirements on the transconductance operational amplifier (OTA) in the first-stage integrator. In addition, for a modulator structure using a low-resolution quantizer, the injection of dither may also reduce the maximum stable input amplitude (MSA).

[0003] In the prior art, subtractive dithering can be adopted to meet the above requirements, such as Figure 1 As shown, by injecting a dither signal equal in amplitude to the input of the quantizer into both the DA capacitor array of the first-stage integrator and the digital output of the quantizer simultaneously, the additional noise power caused by dither can be effectively reduced. However, when the quantizer resolution is 1-bit, the suppression effect of subtractive dithering on the additional noise caused by dither will decrease significantly.

[0004] Based on this, a new technical solution is needed. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a perturbation injection circuit and a perturbation injection method to at least solve the problem that the suppression effect of the existing subtractive dithering technology on the additional noise caused by the perturbation signal decreases significantly when the resolution is 1-bit.

[0006] Embodiments of the present invention provide the following technical solutions:

[0007] Embodiments of the present invention provide a perturbation injection circuit applied to an analog-to-digital converter with a 1-bit quantizer. The perturbation injection circuit includes a capacitor array of the first-stage integrator in a loop filter, a 1-bit quantizer, and a perturbation unit. The output of the loop filter is connected to the 1-bit quantizer, and the perturbation unit is used to output a first digital output quantity;

[0008] The 1-bit quantizer includes a second sampling capacitor, a comparison capacitor, a first injection capacitor, a second injection capacitor, a comparator, and a register;

[0009] The bottom plate of the second sampling capacitor can be respectively connected to the output terminal of the loop filter and the common-mode voltage through a sampling switch. The bottom plates of the comparison capacitor, the first injection capacitor, and the second injection capacitor can all be connected to the positive reference voltage, the negative reference voltage, or the common-mode voltage through corresponding switches, and can all obtain the perturbation signal injected by the perturbation unit through the corresponding switches;

[0010] The top plates of the second sampling capacitor, the comparison capacitor, the first injection capacitor, and the second injection capacitor are all connected to the positive input terminal of the comparator. The negative input terminal of the comparator is grounded, and the positive input terminal of the comparator is connected to the negative input terminal of the comparator through a comparator input switch. The output terminal of the comparator is connected to the register. The register outputs a corresponding second digital output according to the output result of the comparator. After the second digital output and the first digital output are superimposed, they control the array capacitors in the capacitor array to be connected to the positive reference voltage or the negative reference voltage.

[0011] Further, the comparison capacitor is connected to the positive reference voltage, the negative reference voltage, or the common-mode voltage through a comparison switch;

[0012] The first injection capacitor is connected to the positive reference voltage, the negative reference voltage, or the common-mode voltage through a first injection switch;

[0013] The second injection capacitor is connected to the positive reference voltage, the negative reference voltage, or the common-mode voltage through a second injection switch;

[0014] The perturbation unit injects a first perturbation signal into the second injection capacitor through the second injection switch, and injects a second perturbation signal into the comparison capacitor and the first injection capacitor through the comparison switch and the first injection switch respectively;

[0015] The comparator outputs a first comparison result according to the input signal, the second perturbation signal injected into the first injection capacitor, and the first perturbation signal injected into the second injection capacitor, and outputs a second comparison result according to the input signal and the second perturbation signal injected into the comparison capacitor;

[0016] The register stores the first comparison result and the second comparison result, and outputs the two second digital outputs according to the first comparison result and the second comparison result.

[0017] Further, when the second perturbation signal is equal to 0, the first injection capacitor is connected to the negative reference voltage through the first injection switch; when the second perturbation signal is equal to 1, the first injection capacitor is connected to the positive reference voltage through the first injection switch.

[0018] When the first perturbation signal is equal to 0, the second injection capacitor is connected to the negative reference voltage through the second injection switch; when the first perturbation signal is equal to 1, the second injection capacitor is connected to the positive reference voltage through the second injection switch.

[0019] Further, when the second perturbation signal is equal to 0, the comparison capacitor is connected to the positive reference voltage through the comparison switch; when the second perturbation signal is equal to 1, the comparison capacitor is connected to the negative reference voltage through the comparison switch.

[0020] Further, when the output result of the comparator is 1, the register outputs 0; when the output of the comparator is 0, the register outputs -1.

[0021] Further, the capacitor array includes a plurality of array capacitors connected in parallel, and each array capacitor can be connected to the positive reference voltage, the negative reference voltage or the common mode voltage through a corresponding array switch.

[0022] Further, the loop filter further includes:

[0023] An operational amplifier, the positive input terminal of the operational amplifier is grounded, the negative input terminal is respectively connected to the first sampling capacitor and the capacitor array, and the positive input terminal of the operational amplifier is connected to the negative input terminal of the operational amplifier through a corresponding operational amplifier input switch;

[0024] An integrating capacitor, the integrating capacitor is connected between the negative input terminal and the output terminal of the operational amplifier;

[0025] A backend integration unit, the input terminal of the backend integration unit is connected to the output terminal of the operational amplifier, and the output terminal of the backend integration unit is connected to the second sampling capacitor.

[0026] The present invention also provides a perturbation injection method, which is applied to the perturbation injection circuit as described above, and includes:

[0027] Connect the bottom plates of the capacitor array, the comparison capacitor, the first injection capacitor, and the second injection capacitor to the common mode voltage, sample the input signal through the first sampling capacitor, and sample the output of the loop filter through the second sampling capacitor;

[0028] Connect the bottom plate of the first sampling capacitor to the common-mode voltage, and connect the bottom plates of the first injection capacitor and the second injection capacitor to the positive reference voltage or the negative reference voltage according to the perturbation signals injected into the first injection capacitor and the second injection capacitor, so as to sum the input signal, the perturbation signal injected into the first injection capacitor, and the perturbation signal injected into the second injection capacitor in the signal domain and obtain a first input voltage;

[0029] The comparator obtains the first input voltage, compares it with the first comparator threshold, obtains a first comparison result, and sends the first comparison result to the register for temporary storage;

[0030] The bottom plate of the comparison capacitor is connected to the positive reference voltage or the negative reference voltage according to the value of the corresponding perturbation signal, so as to sum the input signal and the perturbation signal injected into the comparison capacitor in the signal domain to obtain a second input voltage;

[0031] The comparator obtains the second input voltage, compares it with the second comparator threshold, obtains a second comparison result, and sends the second comparison result to the register for temporary storage;

[0032] The register correspondingly outputs two second digital output quantities according to the first comparison result and the second comparison result;

[0033] Superimpose the two second digital output quantities on the first digital output quantity output by the perturbation unit to obtain a third digital output quantity, and adjust the connection of the bottom plates of the array capacitors in the capacitor array to the positive reference voltage or the negative reference voltage according to the third digital output quantity.

[0034] Further, the connecting the bottom plates of the first injection capacitor and the second injection capacitor to the positive reference voltage or the negative reference voltage according to the perturbation signals injected into the first injection capacitor and the second injection capacitor includes:

[0035] When the values of the perturbation signals injected into the first injection capacitor and the second injection capacitor are 0, the bottom plates of the first injection capacitor and the second injection capacitor are connected to the negative reference voltage;

[0036] When the values of the perturbation signals injected into the first injection capacitor and the second injection capacitor are 1, the bottom plates of the first injection capacitor and the second injection capacitor are connected to the positive reference voltage.

[0037] Further, the connecting the bottom plate of the comparison capacitor to the positive reference voltage or the negative reference voltage according to the value of the corresponding perturbation signal includes:

[0038] When the value of the perturbation signal injected into the comparison capacitor is 1, the bottom plate of the comparison capacitor is connected to the negative reference voltage;

[0039] When the value of the perturbation signal injected into the comparison capacitor is 0, the bottom plate of the comparison capacitor is connected to the positive reference voltage.

[0040] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the embodiments of the present invention at least include:

[0041] A perturbation injection circuit of the present invention injects perturbation signals into a first injection capacitor and a second injection capacitor, so that a comparator makes a first comparison according to the injected perturbation signal and an input signal, and after the first comparison of the comparator ends, adjusts the comparator threshold according to the injected perturbation signal, and continues to inject a perturbation signal into the comparison capacitor, so that the comparator makes a second comparison according to the perturbation signal injected into the comparison capacitor and the input signal, thereby obtaining a quantizer digital output by summing the two comparison results. According to the quantizer digital output result, an injection is performed once on the capacitor array of the first-stage integrator, so that the capacitor array controls the connection of the capacitor array to the corresponding voltage according to the quantizer output result and the injection signal injected into the capacitor array, thereby ensuring that the residual voltage is less than one least significant bit within the full input range of the quantizer. The perturbation injection circuit of the present invention obtains two corresponding second digital output quantities by injecting two perturbation signals into a 1-bit quantizer twice. Under the joint action of the first digital output quantity and the two second digital output quantities, the array capacitors of the perturbation control capacitor array are connected to the corresponding voltages, thereby solving the problem that the suppression effect of the existing subtractive perturbation injection technology on the additional noise caused by the perturbation signal is significantly reduced when the resolution is 1-bit, and the quantization residual randomization effect is good. Description of the Drawings

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0043] Figure 1 Is the existing sigma-delta ADC subtractive perturbation injection method;

[0044] Figure 2 Is Figure 1 The residual curve of the subtractive perturbation injection method shown;

[0045] Figure 3 Is the existing signal-related dither injection method;

[0046] Figure 4 For Figure 3 the residual curve of the method shown;

[0047] Figure 5 is a schematic circuit diagram of a perturbation injection circuit according to an embodiment of the present invention;

[0048] Figure 6 is the residual curve of a perturbation injection circuit according to an embodiment of the present invention. Specific Embodiments

[0049] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0050] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts belong to the scope of protection of the present application.

[0051] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on the present application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects described herein can be used to implement the device and / or practice the method. In addition, this device and / or this method can be implemented using other structures and / or functions in addition to one or more of the aspects described herein.

[0052] It should also be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. The drawings only show the components related to the present application and are not drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0053] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the examples can be practiced without these specific details.

[0054] The suppression effect of the existing subtractive perturbation injection technique on the additional noise caused by dither will be greatly reduced when the quantizer resolution is 1-bit. To illustrate this problem, Figure 2 The schematic diagram of the residual curve after adopting the 2-bit (4 levels) subtractive perturbation injection technique for a 1-bit quantizer is given. The injection amplitudes are {-3 / 8Vr, -1 / 8Vr, 1 / 8Vr, 3 / 8Vr}, and Vr is half of the range of the quantizer. The black solid line in the figure represents the residual curve of the ideal 1-bit quantizer without using dither, while the four dotted lines with different shapes correspond to the output residual curves of the quantizer under different levels of dither injection. It can be seen that when the absolute value of the input amplitude exceeds 5 / 8Vr, the residual voltage after using dither will exceed the voltage range of half of the least significant bit (LSB), resulting in an increase in quantization noise.

[0055] As Figure 2 shown, the black solid line corresponds to the residual curve without any injection. Therefore, the 1-bit quantizer (i.e., the comparator) flips at the input vi = 0, and the residual curve jumps at vi = 0. When the dither signal is 00, a dither signal of -3 / 8Vr is added to the input signal. At this time, the true input signal of the 1-bit quantizer is vi - 3 / 8Vr. Then, the jump point originally at vi = 0 is shifted to 3 / 8Vr. Therefore, the residual curve at this time becomes a dash line. Similarly, dither = 01, 10, 11 respectively correspond to adding dither signals with amplitudes of -1 / 8Vr, 1 / 8Vr, 3 / 8Vr, and shift the jump point at vi = 0 to 1 / 8Vr, -1 / 8Vr, -3 / 8Vr respectively. The residual curves respectively correspond to Figure 2 the dotted line, the single dot and dash line, and the double dot and dash line in

[0056] For a 1-bit quantizer, its output is 1 or 0, and the digital output values correspond to 1 or -1 respectively. When dither is added, there will be decimals in the digital output. Taking four different injection amounts of -3 / 8Vr, -1 / 8Vr, 1 / 8Vr, 3 / 8Vr as examples, 0.75, 0.25, -0.25, -0.75 are added to the original 1, 0 outputs. The examples are as follows:

[0057] For the input Vi = 0.3Vr, when no dither is introduced, since the input Vi > 0, the 1-bit quantizer outputs 1 and the digital output is 1; the residual voltage is Vi - 0.5Vr * 1 = -0.2Vr.

[0058] When the injection amount is -3 / 8Vr, vi - 3 / 8Vr = -0.125Vr, which is less than 0. So the quantizer output is 0, and the digital output is +0.75 added to -1. Therefore, the digital output is -0.25; the residual voltage is Vi - 0.5Vr*(-1) - 3 / 8Vr = 0.425Vr.

[0059] When the injection amount is -1 / 8Vr, vi - 1 / 8Vr = 0.175Vr, which is greater than 0. So the quantizer output is 1, and the digital output is +0.25 added to 1. Therefore, the digital output is 1.25; the residual voltage is Vi - 0.5Vr*1 - 1 / 8Vr = -0.325Vr.

[0060] When the injection amount is 1 / 8Vr, vi + 1 / 8Vr = 0.425Vr, which is greater than 0. So the quantizer output is 1, and the digital output is -0.25 added to 1. Therefore, the digital output is 0.75; the residual voltage is Vi - 0.5Vr*1 + 1 / 8Vr = -0.075Vr.

[0061] When the injection amount is 3 / 8Vr, vi + 3 / 8Vr = 0.675Vr, which is greater than 0. So the quantizer output is 1, and the digital output is -0.75 added to 1. Therefore, the digital output is 0.25; the residual voltage is Vi - 0.5Vr*1 + 3 / 8Vr = -0.175Vr.

[0062] In summary, for a fixed input vi = 0.3Vr, when no dither is introduced, the output of the 1-bit quantizer is fixed at 1. While under the injection of 4 levels of dither, there are four possibilities for the output of the 1-bit quantizer: -0.25, 1.25, 0.75, 0.25. When no dither is introduced, the residual voltage is fixed at 0.2Vr, while under the injection of 4 levels of dither, there are four possibilities: 0.425Vr, -0.325Vr, -0.075Vr, -0.175Vr. The values of these four residual voltages respectively correspond to Figure 2 the y-coordinate values of the four dashed lines at vi = 0.3Vr in Figure 2 It should be noted that when the magnitude of Vi is close to -Vr or Vr, it can be seen from

[0063] Figure 3 A conventional dither injection technique applicable to sigma-delta ADCs employing 1-bit quantizers is given. Compared with the traditional subtractive perturbation injection scheme, Figure 3In the shown solution, a comparator CMP2, a digital domain comparator DCMP1 and two switches are additionally added. Comparator CMP1 and comparator CMP2 respectively compare the cases of introducing and not introducing dither at the input point of the quantizer. The comparison results of the two are sent to the digital domain comparator DCMP1. When the output results of comparator CMP1 and comparator CMP2 are the same, the dither function is turned off, and when the output results of comparator CMP1 and comparator CMP2 are different, the dither function is turned on.

[0064] The residual voltage curve corresponding to this solution is as Figure 4 shown. Taking the example of dither injection with 4 levels to explain this solution, it can be seen that when the dither value is less than zero, only the dither function of two levels is turned on for the input signal less than 0, and when the dither value is greater than zero, only the dither function of the other two levels is turned on for the input signal greater than 0. In this way, although the problem of increased quantization noise caused by the residual voltage exceeding one quantization LSB voltage can be avoided, however, the dither method is related to the input signal and for a given input voltage, the number of dither levels is halved, which results in a weakened randomization effect introduced by dither.

[0065] Based on this, the embodiments of this specification propose a processing solution: as Figure 5 shown, a perturbation injection circuit of the present invention, a perturbation unit injects a perturbation signal into a first injection capacitor C5 and a second injection capacitor C6. The perturbation signal and the input signal Vin are summed in the signal domain to obtain the first input voltage of the comparator. The comparator makes a first comparison between the first input voltage and a first comparator threshold and outputs a first comparison result Q1, and then stores the first comparison result Q1 in a register; then the perturbation unit injects a perturbation signal into a comparison capacitor C4 and sums the perturbation signal injected into the comparison capacitor C4 and the input signal Vin in the signal domain to obtain the second input voltage of the comparator. The comparator makes a second comparison between the second input voltage and a second comparator threshold and outputs a second comparison result Q2, and then stores the second comparison result Q2 in the register. Finally, the register outputs two second digital output quantities according to the first comparison result Q1 and the second comparison result Q2, so that the second digital output quantities cooperate with the first digital output Ddi quantity output by the perturbation unit to adjust the connection of the array capacitors in the capacitor array DWA in the loop filter, so that the quantizer can ensure that the residual voltage is less than one least significant bit within the full input range. The present invention has the advantages of small quantization noise and good quantization residual randomization effect at the cost of introducing extremely little additional hardware.

[0066] The following will combine the accompanying drawings to explain this application in detail.

[0067] Embodiment 1

[0068] This embodiment takes the injection of a 2-bit 4-level perturbation signal as an example to illustrate the present application in detail. The 4-level perturbation signals are {-3 / 8Vr, -1 / 8Vr, 1 / 8Vr, 3 / 8Vr} respectively.

[0069] Among them, 2-bit is the number of bits of the injection signal. In the example, a total of 4 levels of injection amounts are used, so it can be written as 2-bit. The values of the 4-level perturbation signals corresponding to the 2-bit perturbation signal are {-3 / 8Vr, -1 / 8Vr, 1 / 8Vr, 3 / 8Vr} respectively.

[0070] As Figures 5 - 6 shown, a perturbation injection circuit of the present invention is applied to an analog-to-digital converter with a 1-bit quantizer, especially a sigma-delta analog-to-digital converter with a 1-bit quantizer. The perturbation injection circuit includes a loop filter 10 with a first-stage integrator, a 1-bit quantizer 20, and a perturbation unit 30. The loop filter 10 is connected to the 1-bit quantizer 20. The first-stage integrator includes a first sampling capacitor C1 and a capacitor array DWA. The first sampling capacitor C1 is used to acquire the input signal Vin, and the perturbation unit 30 is used to output a first digital output quantity.

[0071] Among them, the first sampling capacitor C1 can be connected to the input signal Vin or the common-mode voltage Vcm through corresponding switches.

[0072] Among them, the range of the 1-bit quantizer 20 is {-Vr, Vr}.

[0073] Among them, the loop filter 10 is used to acquire the input signal Vin and amplify and filter the input signal Vin.

[0074] Among them, the perturbation unit 30 is used to add a perturbation signal to the input signal Vin. As described above, the injection amounts of the perturbation signals in this embodiment include four levels {-3 / 8Vr, -1 / 8Vr, 1 / 8Vr, 3 / 8Vr}.

[0075] Specifically, the 1-bit quantizer 20 includes a second sampling capacitor C3, a comparison capacitor C4, a first injection capacitor C5, a second injection capacitor C6, a comparator 21, and a register 22. The bottom plate of the second sampling capacitor C3 can be connected to the output terminal of the loop filter 10 and the common-mode voltage Vcm respectively through a sampling switch K4. The bottom plates of the comparison capacitor C4, the first injection capacitor C5, and the second injection capacitor C6 can all be connected to the positive reference voltage Vrefp, the negative reference voltage Vrefn, or the common-mode voltage Vcm through corresponding switches, and can all obtain the disturbance signals injected by the disturbance unit 30 through the corresponding switches. The top plates of the second sampling capacitor C3, the comparison capacitor C4, the first injection capacitor C5, and the second injection capacitor C6 are all connected to the positive input terminal of the comparator 21. The negative input terminal of the comparator 21 is grounded, and the positive input terminal of the comparator 21 is connected to the negative input terminal of the comparator 21 through a comparator input switch K3. The output terminal of the comparator 21 is connected to the register 22. The register 22 outputs a corresponding second digital output according to the output result of the comparator 21. After the second digital output and the first digital output Ddi are superimposed, they control the array capacitors in the capacitor array DWA to be connected to the positive reference voltage Vrefp or the negative reference voltage Vrefn.

[0076] Among them, the second sampling capacitor C3 is used to sample the output of the loop filter 10, and the output of the loop filter 10 is mainly the input signal Vin that has passed through the operational amplifier and filtering.

[0077] Among them, the bottom plate of the second sampling capacitor C3 can be connected to the output terminal of the loop filter 10 or the common-mode voltage Vcm according to requirements under the action of the sampling switch K4.

[0078] Specifically, the comparison capacitor C4 is connected to the positive reference voltage Vrefp, the negative reference voltage Vrefn, or the common-mode voltage Vcm through a comparison switch K5. The first injection capacitor C5 is connected to the positive reference voltage Vrefp, the negative reference voltage Vrefn, or the common-mode voltage Vcm through a first injection switch K6. The second injection capacitor C6 is connected to the positive reference voltage Vrefp, the negative reference voltage Vrefn, or the common-mode voltage Vcm through a second injection switch K7. The disturbance unit 30 injects a first disturbance signal di<0> into the second injection capacitor C6 through the second injection switch K7. The disturbance unit 30 injects a second disturbance signal di<1> into the comparison capacitor C4 and the first injection capacitor C5 through the comparison switch K5 and the first injection switch K6 respectively.

[0079] Among them, the switches described in this application can all switch the corresponding capacitors to different voltages according to requirements.

[0080] For example, the comparison switch K5 can control the connection of the comparison capacitor C4 to any one of the positive reference voltage Vrefp, the negative reference voltage Vrefn, and the common-mode voltage Vcm.

[0081] Further, the comparator 21 outputs a first comparison result Q1 according to the input signal Vin, the second perturbation signal di<1> injected into the first injection capacitor C5, and the first perturbation signal di<0> injected into the second injection capacitor C6; outputs a second comparison result Q2 according to the input signal Vin and the second perturbation signal di<1> injected into the comparison capacitor C4; the register 22 can store the first comparison result Q1 and the second comparison result Q2, and outputs two second digital output quantities according to the first comparison result Q1 and the second comparison result Q2.

[0082] Among them, when the second perturbation signal di<1> is equal to 0, the first injection capacitor C5 is connected to the negative reference voltage Vrefn through the first injection switch K6, and when the second perturbation signal di<1> is equal to 1, the first injection capacitor C5 is connected to the positive reference voltage Vrefp through the first injection switch K6; when the first perturbation signal di<0> is equal to 0, the second injection capacitor C6 is connected to the negative reference voltage Vrefn through the second injection switch K7, and when the first perturbation signal di<0> is equal to 1, the second injection capacitor C6 is connected to the positive reference voltage Vrefp through the second injection switch K7.

[0083] Among them, when the second perturbation signal di<1> is equal to 0, the comparison capacitor C4 is connected to the positive reference voltage Vrefp through the comparison switch K5, and when the second perturbation signal di<1> is equal to 1, the comparison capacitor C4 is connected to the negative reference voltage Vrefn through the comparison switch K5.

[0084] Specifically, after the first injection capacitor C5 is injected with the second perturbation signal di<1> by the perturbation unit 30 and the second injection capacitor C6 is injected with the first perturbation signal di<0> by the perturbation unit 30, the first injection capacitor C5 adds the second perturbation signal di<1> to the input signal Vin, and the second injection capacitor C6 adds the first perturbation signal di<0> to the input signal Vin, so that the first perturbation signal di<0>, the second perturbation signal di<1> and the input signal Vin are summed in the signal domain to obtain the first input voltage of the comparator 21. At this time, the comparator 21 compares the first input voltage with the threshold of the first comparator 21 and outputs the first comparison result Q1.

[0085] After comparing capacitor C4, the disturbed unit 30 injects the second disturbance signal di<1>. The input signal Vin and the second disturbance signal di<1> injected onto capacitor C4 are summed in the signal domain, enabling comparator 21 to obtain a second input voltage. After comparator 21 compares the second input voltage with the second comparator 21 threshold, it outputs a second comparison result Q2.

[0086] Among them, the second comparator 21 threshold is adjusted according to the second disturbance signal di<1> injected onto capacitor C4.

[0087] Therefore, comparator 21 mainly compares the obtained input voltage with the corresponding comparator 21 threshold to obtain a comparison result, and then inputs the comparison result into register 22 for temporary storage.

[0088] Among them, register 22 is used to output two second digital output quantities corresponding to the two output results of comparator 21.

[0089] Among them, since the output value of comparator 21 is usually 1 or 0, register 22 can output the corresponding second digital output quantity according to the comparison result of comparator 21.

[0090] Specifically, when the output result of comparator 21 is 1, the output of register 22 is 0; when the output of comparator 21 is 0, the output of register 22 is -1.

[0091] Furthermore, the capacitor array DWA includes multiple array capacitors C21~C27 connected in parallel. Each array capacitor can be connected to the positive reference voltage Vrefp, the negative reference voltage Vrefn, or the common-mode voltage Vcm through the corresponding switch.

[0092] Among them, the array capacitor can adjust the number of array capacitors connected to the positive reference voltage Vrefp or the negative reference voltage Vrefn according to the value obtained by superimposing the two second digital output quantities and the first digital output Ddi quantity.

[0093] Furthermore, loop filter 10 also includes an operational amplifier OTA, an integration capacitor CINT, and a backend integration unit. The positive input terminal of operational amplifier OTA is grounded, the negative input terminal is respectively connected to the first sampling capacitor C1 and the capacitor array DWA, and the positive input terminal of operational amplifier OTA is connected to the negative input terminal of operational amplifier OTA through the corresponding switch; the integration capacitor CINT is connected between the negative input terminal and the output terminal of operational amplifier OTA; the input terminal of the backend integration unit is connected to the output terminal of operational amplifier OTA, and the output terminal of the backend integration unit is connected to the second sampling capacitor C3.

[0094] The perturbation signal injection circuit for the 1-bit quantizer 20 proposed in this embodiment injects the perturbation signal twice at the 1-bit quantizer, and injects the perturbation signal once through the D / A capacitor array at the first-stage integrator of the loop filter. At the cost of introducing very little additional hardware circuit, it solves the problem that the quantization residual exceeds the voltage of one quantization LSB caused by the traditional subtractive perturbation injection, and at the same time has the advantage of good randomization effect.

[0095] Embodiment 2

[0096] This embodiment provides a perturbation injection method, which is applied to the perturbation injection circuit described in any one of Embodiment 1, and includes:

[0097] Step S102: Connect the bottom plates of the capacitor array DWA, the bottom plate of the comparison capacitor C4, the bottom plate of the first injection capacitor C5, and the bottom plate of the second injection capacitor C6 to the common-mode voltage Vcm, sample the input signal Vin through the first sampling capacitor C1, and sample the output of the loop filter 10 through the second sampling capacitor C3.

[0098] Specifically, in the first-stage integrator part, the switches between the positive input terminal and the negative input terminal of the operational amplifier OTA and the first switch are both closed. The bottom plate of the first sampling capacitor C1 tracks the input signal Vin, and the bottom plates of the array capacitors in the capacitor array DWA are all connected to the common-mode voltage Vcm; in the 1-bit quantizer 20 part, the comparator input switch K3 and the sampling switch K4 are closed. The bottom plate of the second sampling capacitor C3 tracks the output of the loop filter 10, and at the same time, the bottom plates of the comparison capacitor C4, the first injection capacitor C5, and the second injection capacitor C6 are connected to the common-mode voltage Vcm.

[0099] Then, the switch between the positive input terminal and the negative input terminal of the operational amplifier OTA and the comparator input switch K3 are simultaneously disconnected to complete the sampling of the input signal Vin by the first sampling capacitor C1 and the sampling of the output of the loop filter 10 by the second sampling capacitor C3.

[0100] Among them, the perturbation unit 30 outputs a 2-bit perturbation signal di<1:0> and the corresponding first digital output Ddi quantity. The correspondence between the value of the perturbation signal di<1:0>, the voltage injection quantity of the perturbation signal di<1:0>, and the first digital output Ddi quantity is shown in the following table:

[0101]

[0102] Among them, Vr is the difference between the positive reference voltage Vrefp and the negative reference voltage Vrefn.

[0103] Step S104: Connect the bottom plate of the first sampling capacitor C1 to the common-mode voltage Vcm, and according to the perturbation signals injected into the first injection capacitor C5 and the second injection capacitor C6, connect the bottom plates of the first injection capacitor C5 and the second injection capacitor C6 to the positive reference voltage Vrefp or the negative reference voltage Vrefn, so as to sum the input signal Vin, the perturbation signal injected into the first injection capacitor C5, and the perturbation signal injected into the second injection capacitor C6 in the signal domain and obtain the first input voltage.

[0104] As shown in the figure, in the first-stage integrator, the bottom plate of the first sampling capacitor C1 is connected to the common-mode voltage Vcm. At the same time, in the 1-bit quantizer 20 part, the bottom plates of the first injection capacitor C5 and the second injection capacitor C6 are respectively connected to the positive reference voltage Vrefp or the negative reference voltage Vrefn according to the values of di<1> and di<0>.

[0105] The connection rules for the bottom plates of the first injection capacitor C5 and the second injection capacitor C6 are as follows: when the value of the second perturbation signal di<1> injected into the first injection capacitor C5 is 0, the bottom plates of the first injection capacitor C5 and the second injection capacitor C6 are connected to the negative reference voltage Vrefn; when the value of the first perturbation signal di<0> injected into the second injection capacitor C6 is 1, the bottom plates of the first injection capacitor C5 and the second injection capacitor C6 are connected to the positive reference voltage Vrefp.

[0106] Through the operations on the first injection capacitor C5 and the second injection capacitor C6 in step S104, the summation of the input signal Vin and the perturbation signals {-3 / 8Vr, -1 / 8Vr, 1 / 8Vr, 3 / 8Vr} in the signal domain can be achieved. At this time, the first input voltages of the comparator 21 are Vi - 3 / 8Vr, Vi - 1 / 8Vr, Vi + 1 / 8Vr, and Vi + 3 / 8Vr.

[0107] Step S106: The comparator 21 obtains the first input voltage, compares it with the threshold of the first comparator 21, obtains the first comparison result Q1, and sends the first comparison result Q1 to the register 22 for temporary storage.

[0108] Among them, after the comparator 21 makes the first comparison and outputs the first comparison result Q1, when the input of the comparator 21 is greater than zero, the first comparison result Q1 outputs 1, otherwise the first comparison result Q1 outputs 0, and then the first comparison result Q1 is sent to the register 22 for temporary storage.

[0109] Step S108: The bottom plate of the comparison capacitor C4 is connected to the positive reference voltage Vrefp or the negative reference voltage Vrefn according to the value of the corresponding perturbation signal, so as to sum the input signal Vin and the perturbation signal injected into the comparison capacitor C4 in the signal domain and obtain the second input voltage.

[0110] Among them, the bottom plate of the comparison capacitor C4 is connected to the positive reference voltage Vrefp or the negative reference voltage Vrefn according to the value of the injected second disturbance signal di<1>, and the rules are as follows:

[0111] When the value of the second disturbance signal di<1> injected into the comparison capacitor C4 is 1, the bottom plate of the comparison capacitor C4 is connected to the negative reference voltage Vrefn;

[0112] When the value of the second disturbance signal di<1> injected into the comparison capacitor C4 is 0, the bottom plate of the comparison capacitor C4 is connected to the positive reference voltage Vrefp.

[0113] When the second disturbance signal di<1> = 1, it indicates that the injection amount is 1 / 8Vr or 3 / 8Vr, and the residual curve is Figure 2 The single dot single short line and double dot single short line in. In step S108, by connecting the bottom plate of the comparison capacitor C4 to the negative reference voltage Vrefn, it is equivalent to introducing an injection amount of -Vr at the comparator input again, forming Figure 6 The two jumps of the above two dotted lines at 7 / 8Vr and 5 / 8Vr in.

[0114] When the second disturbance signal di<1> = 0, it indicates that the injection amount is -1 / 8Vr or -3 / 8Vr, and the residual curve is Figure 2 The dotted line and short line in. In this step, the bottom plate of c4 is connected to the positive reference voltage Vrefp, which is equivalent to introducing an injection amount of +Vr at the comparator input again, forming Figure 6 The two jumps of the above two dotted lines at -7 / 8Vr and -5 / 8Vr in.

[0115] After the operation on the comparison capacitor C4 in step S108, corresponding to the injection amounts of {-3 / 8Vr, -1 / 8Vr, 1 / 8Vr, 3 / 8Vr}, the input voltages of the comparator are Vi - 3 / 8Vr + Vr = Vi + 5 / 8Vr, Vi - 1 / 8Vr + Vr = Vi + 7 / 8Vr, Vi + 1 / 8Vr - Vr = Vi - 7 / 8Vr, and Vi + 3 / 8Vr - Vr = Vi - 5 / 8Vr respectively.

[0116] Step S110: The comparator 21 obtains the second input voltage, compares it with the threshold of the second comparator 21, obtains the second comparison result Q2, and sends the second comparison result Q2 to the register 22 for temporary storage.

[0117] In this step, the comparator 21 performs a second comparison and outputs the second comparison result Q2. When the input of the comparator 21 is greater than zero, the second comparison result Q2 is equal to 1; otherwise, the second comparison result Q2 is equal to 0, and the second comparison result Q2 is temporarily stored by the register 22.

[0118] Step S112: Register 22 outputs two second digital output quantities according to the first comparison result Q1 and the second comparison result Q2.

[0119] Register 22 converts the stored first comparison result Q1 and second comparison result Q2 into two second digital output quantities (Do1, Do2) respectively, and ensures that the two second digital output quantities are output synchronously in time.

[0120] Specifically, when the comparison result is equal to 1, the second digital output quantity is equal to 1, and when the comparison result is equal to 0, the second digital output quantity is equal to -1.

[0121] Wherein, Do1 is the value corresponding to the first comparison result Q1, and Do2 is the value corresponding to the second comparison result Q2.

[0122] Step S114: Superimpose the two second digital output quantities on the first digital output Ddi quantity output by the dither unit 30 to obtain a third digital output quantity, and adjust the connection of the bottom plate of the array capacitor in the capacitor array DWA to the positive reference voltage Vrefp or the negative reference voltage Vrefn according to the third digital output quantity.

[0123] Wherein, the sum of the two second digital output quantities and the first digital output quantity Ddi forms the third digital output Dout together, and the bottom plate of the array capacitor is connected to the positive reference voltage Vrefp or the negative reference voltage Vrefn according to the value of the third digital output Dout.

[0124] When the output of the loop filter 10 is within the range of the 1-bit quantizer, the dither injection technique proposed by the present invention can ensure that the value of the third digital output quantity Dout is only one of the 8 values {-1.75, -1.25, -0.75, -0.25, 0.25, 0.75, 1.25, 1.75}. The relationship between the connection modes of the bottom plates of the array capacitors C21~C27 in the capacitor array DWA to Vrefp and Vrefn and Dout is shown in the following table:

[0125]

[0126] When the first comparison result Q1 = 1 or 0, the second digital output D1 corresponding to the first comparison result Q1 = 1 or -1; when the second comparison result Q2 = 1 or 0, the second digital output corresponding to the second comparison result Q2 is D2 = 1 or -1; and according to the convention of the first step, when dither = 00, 01, 10, 11, the digital outputs Ddi corresponding to dither are 0.75, 0.25, -0.25, -0.75 respectively. The final digital output is D1 + D2 + Ddi, and this value will be sent as the output of the modulator to the subsequent digital decimation filter.

[0127] For example:

[0128] When Vi = 0.3Vr and dither = 01, the result of the first comparison of the quantizer is Q1 = 1, so D1 = 1. The result of the second comparison of the quantizer is Q2 = 0, so D2 = -1. The first digital output Ddi corresponding to dither is 0.25. Therefore, the third digital output is 1 - 1 + 0.25 = 0.25. Among C21 to C27, 3 bottom plates are connected to the negative reference voltage Vrefn, and 4 bottom plates are connected to the positive reference voltage Vrefp.

[0129] When Vi = 0.9Vr and dither = 11, the result of the first comparison of the quantizer is Q1 = 1, so D1 = 1. The result of the second comparison of the quantizer is Q2 = 1, so D2 = 1. The first digital output Ddi corresponding to dither is -0.75. Therefore, the third digital output is 1 + 1 - 0.75 = 1.25. Among C21 to C27, 1 bottom plate is connected to Vrefn, and 6 bottom plates are connected to Vrefp.

[0130] When Vi = 0.9Vr and dither = 10, the result of the first comparison of the quantizer is Q1 = 1, so D1 = 1. The result of the second comparison of the quantizer is Q2 = 1, so D2 = 1. The first digital output Ddi corresponding to dither is -0.25. Therefore, the third digital output is 1 + 1 - 0.25 = 1.75. All the bottom plates of C21 to C27 are connected to Vrefp.

[0131] Figure 6 The residual voltage curve of the 1-bit quantizer 20 after adopting the dither injection technique proposed by the present invention is given. It can be seen that within the full-scale input range of (-Vr, Vr), the residual voltage is less than one quantization LSB. And for any input within the range, the 4-level dither works and is independent of the magnitude of the input signal Vin, and the randomization effect introduced by the dither is excellent.

[0132] The dither injection method for the 1-bit quantizer 20 proposed by the present invention solves the problem that the quantization residual exceeds one quantization LSB voltage caused by the traditional subtractive dither injection at the cost of introducing very few additional hardware circuits, and at the same time has the advantage of good randomization effect.

[0133] In this specification, for the same or similar parts among the various embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and for the relevant parts, reference can be made to the partial descriptions of the system embodiments.

[0134] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A disturbance injection circuit, characterized in that: The disturbance injection circuit comprises a capacitor array of a first-stage integrator in a loop filter, a 1-bit quantizer and a disturbance unit, the output of the loop filter is connected to the 1-bit quantizer, and the disturbance unit is used to output a first digital output quantity; The 1-bit quantizer includes a second sampling capacitor, a comparison capacitor, a first injection capacitor, a second injection capacitor, a comparator and a register; The bottom plate of the second sampling capacitor can be connected to the output terminal and the common mode voltage of the loop filter respectively through a sampling switch, and the bottom plate of the comparison capacitor, the bottom plate of the first injection capacitor, and the bottom plate of the second injection capacitor can all be connected to a positive reference voltage, a negative reference voltage, or a common mode voltage through corresponding switches, and can all obtain the disturbance signal injected by the disturbance unit through the corresponding switches; The top plate of the second sampling capacitor, the top plate of the comparison capacitor, the top plate of the first injection capacitor, and the top plate of the second injection capacitor are all connected to the positive input terminal of the comparator, the negative input terminal of the comparator is grounded, and the positive input terminal of the comparator is connected to the negative input terminal of the comparator through a comparator input switch, the output terminal of the comparator is connected to the register, and the register outputs a corresponding second digital output according to the output result of the comparator, and the second digital output and the first digital output are superimposed to control the array capacitor in the capacitor array to be connected to a positive reference voltage or a negative reference voltage; The comparison capacitor is connected to the positive reference voltage, the negative reference voltage or the common mode voltage through a comparison switch; The first injection capacitor is connected to the positive reference voltage, the negative reference voltage or the common mode voltage through a first injection switch; The second injection capacitor is connected to the positive reference voltage, the negative reference voltage or the common mode voltage through a second injection switch; The disturbance unit injects a first disturbance signal into the second injection capacitor through the second injection switch, and injects a second disturbance signal into the comparison capacitor and the first injection capacitor through the comparison switch and the first injection switch, respectively.

2. The disturbance injection circuit according to claim 1, characterized in that: The comparator outputs a first comparison result according to an input signal, a second disturbance signal injected into the first injection capacitor, and the first disturbance signal injected into the second injection capacitor, and outputs a second comparison result according to the input signal and the second disturbance signal injected into the comparison capacitor; The register stores the first comparison result and the second comparison result, and outputs two second digital output quantities according to the first comparison result and the second comparison result.

3. The disturbance injection circuit according to claim 2, characterized in that: When the second disturbance signal is equal to 0, the first injection capacitor is connected to the negative reference voltage through the first injection switch; when the second disturbance signal is equal to 1, the first injection capacitor is connected to the positive reference voltage through the first injection switch; When the first disturbance signal is equal to 0, the second injection capacitor is connected to the negative reference voltage through the second injection switch; when the first disturbance signal is equal to 1, the second injection capacitor is connected to the positive reference voltage through the second injection switch.

4. The disturbance injection circuit according to claim 2, characterized in that: When the second disturbance signal is equal to 0, the comparison capacitor is connected to the positive reference voltage through the comparison switch, and when the second disturbance signal is equal to 1, the comparison capacitor is connected to the negative reference voltage through the comparison switch.

5. The disturbance injection circuit according to claim 2, characterized in that: When the comparator outputs a result of 1, the register outputs 0; when the comparator outputs a result of 0, the register outputs -1.

6. The disturbance injection circuit according to any one of claims 1 to 5, characterized in that: The capacitor array includes a plurality of array capacitors connected in parallel, and each of the array capacitors can be connected to the positive reference voltage, the negative reference voltage or the common mode voltage through a corresponding array switch.

7. The disturbance injection circuit according to claim 6, characterized in that: The loop filter further comprises: An operational amplifier, wherein the positive input terminal of the operational amplifier is grounded, the negative input terminal is connected to the first sampling capacitor and the capacitor array respectively, and the positive input terminal of the operational amplifier is connected to the negative input terminal of the operational amplifier through a corresponding operational amplifier input switch; an integrating capacitor connected between the negative input terminal of the operational amplifier and the output terminal of the operational amplifier; A back-end integrated unit, wherein the input end of the back-end integrated unit is connected to the output end of the operational amplifier, and the output end of the back-end integrated unit is connected to the second sampling capacitor.

8. A disturbance injection method, characterized in that: The disturbance injection circuit as claimed in any one of claims 1 to 7 comprises: Connecting the bottom plate of the capacitor array, the bottom plate of the comparison capacitor, the bottom plate of the first injection capacitor, and the bottom plate of the second injection capacitor to a common mode voltage, sampling the input signal through the first sampling capacitor, and sampling the output of the loop filter through the second sampling capacitor; Connecting the bottom plate of the first sampling capacitor to the common mode voltage, and connecting the bottom plate of the first injection capacitor and the bottom plate of the second injection capacitor to a positive reference voltage or a negative reference voltage according to the disturbance signal injected into the first injection capacitor and the second injection capacitor, so as to sum the input signal, the disturbance signal injected into the first injection capacitor, and the disturbance signal injected into the second injection capacitor in the signal domain and obtain a first input voltage; The comparator obtains the first input voltage, compares it with the first comparator threshold, obtains a first comparison result, and sends the first comparison result to a register for temporary storage; The bottom plate of the comparison capacitor is connected to a positive reference voltage or a negative reference voltage according to the value of the corresponding disturbance signal, so as to achieve the summation of the input signal and the disturbance signal injected into the comparison capacitor in the signal domain to obtain a second input voltage; The comparator obtains the second input voltage, compares it with the second comparator threshold, obtains a second comparison result, and sends the second comparison result to the register for temporary storage; The register outputs two second digital output quantities correspondingly according to the first comparison result and the second comparison result; The two second digital outputs are superimposed on the first digital output outputted by the disturbance unit to obtain a third digital output, and the bottom plate of the array capacitor in the capacitor array is adjusted to be connected to the positive reference voltage or the negative reference voltage according to the third digital output.

9. The disturbance injection method according to claim 8, characterized in that: The step of connecting the bottom plate of the first injection capacitor and the bottom plate of the second injection capacitor to the positive reference voltage or the negative reference voltage according to the disturbance signal injected into the first injection capacitor and the second injection capacitor comprises: When the value of the disturbance signal injected into the first injection capacitor and the second injection capacitor is 0, the bottom plate of the first injection capacitor and the bottom plate of the second injection capacitor are connected to the negative reference voltage; When the value of the disturbance signal injected into the first injection capacitor and the second injection capacitor is 1, the bottom plate of the first injection capacitor and the bottom plate of the second injection capacitor are connected to the positive reference voltage.

10. The disturbance injection method according to claim 8, characterized in that: The bottom plate of the comparison capacitor is connected to a positive reference voltage or a negative reference voltage according to the value of the corresponding disturbance signal, including: When the value of the disturbance signal injected into the comparison capacitor is 1, the bottom plate of the comparison capacitor is connected to the negative reference voltage; When the value of the disturbance signal injected into the comparison capacitor is 0, the bottom plate of the comparison capacitor is connected to the positive reference voltage.

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