Data compression method and device, equipment and medium

Abstract

The invention relates to a data compression method and device, equipment and a medium, and the method comprises the steps: carrying out the sign bit rotation of input data of a current period, and obtaining first data; performing comparative incremental operation on the first data and the second data to obtain third data; wherein the second data is data after sign bit rotation in the previous period; performing bit-plane transformation and bitwise exclusive-or operation on the third data of the plurality of cycles stored according to the column to obtain deformed data; and performing bit-plane data coding on the deformed data to obtain output data. The data compression capacity can be improved, the carried data volume is reduced, the bandwidth pressure of data transmission is greatly relieved, and therefore the operation performance is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing technology, and in particular to a data compression method, device, equipment and medium. Background Art

[0002] With the development of technology, processor performance has been improved at a high speed, but memory performance has been improved at a relatively slow speed. The uneven development speed has caused the current memory read and write speed to lag seriously behind the processor's computing speed. Compared with increasing physical bandwidth, researching data compression algorithms can more effectively cope with the growing challenges.

[0003] However, to use data compression algorithms to connect computing units and storage units and alleviate the data reading speed gap, we must not only consider the data compression rate of the algorithm, but also the complexity of the algorithm itself and the time spent on compression and decompression. Most of the existing data compression algorithms rely on the CPU for calculations, and the execution process of the algorithm is relatively complex, making it difficult to design an independent acceleration circuit for the algorithm. Therefore, how to improve the data transmission bandwidth wall caused by the explosive growth of data has become a technical problem. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a data compression method, device, equipment and medium.

[0005] According to one aspect of the present disclosure, there is provided a data compression method, comprising:

[0006] Rotate the sign bit of the input data of the current cycle to obtain first data;

[0007] Performing an incremental operation by comparing the first data with the second data to obtain third data; wherein the second data is data after the sign bit is rotated in the previous cycle;

[0008] Performing bit plane transformation and bitwise XOR operation on the third data of a plurality of cycles stored in columns to obtain deformed data;

[0009] The deformed data is encoded in bit plane data to obtain output data.

[0010] According to another aspect of the present disclosure, there is also provided a data compression device, comprising:

[0011] A sign bit rotation module, used for performing sign bit rotation on input data of a current cycle to obtain first data;

[0012] A comparison increment operation module, used for performing a comparison increment operation on the first data and the second data to obtain third data; wherein the second data is data after the sign bit is rotated in the previous cycle;

[0013] A transformation module, used for performing bit plane transformation and bitwise XOR operation on the third data of a plurality of cycles stored in columns to obtain deformed data;

[0014] The encoding module is used to perform bit plane data encoding on the deformation data to obtain output data.

[0015] According to another aspect of the present disclosure, an electronic device is provided, the electronic device comprising:

[0016] processor;

[0017] a memory for storing instructions executable by the processor;

[0018] The processor is used to read the executable instructions from the memory and execute the instructions to implement the above data compression method.

[0019] According to another aspect of the present disclosure, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is used to execute the above data compression method.

[0020] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0021] The technical solution provided by the embodiment of the present disclosure includes: rotating the sign bit of the input data of the current cycle to obtain the first data; performing a comparison increment operation on the first data and the second data to obtain the third data; wherein the second data is the data after the sign bit is rotated in the previous cycle; performing a bit plane transformation and a bitwise XOR operation on the third data of multiple cycles stored in columns to obtain the deformed data; performing bit plane data encoding on the deformed data to obtain the output data. The technical solution firstly reduces the sign bit weight by rotating the sign bit of the input data to be compressed, making it more convenient to compress; then replaces the traditional incremental operation by the comparison increment operation, which can improve the data compression rate; secondly, the bit plane transformation and the bitwise XOR operation can further extract the characteristics of the data for compression, thereby improving the data compression capability; finally, the bit plane data encoding can facilitate data storage and output. Therefore, the present disclosure can improve the data compression capability, reduce the amount of data to be transported, greatly alleviate the bandwidth pressure of data transmission, thereby improving the computing performance, and can be applied to the compression of different types of data, while still ensuring the structure of the algorithm is simple, which is convenient for its hardware implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0024] Figure 1 This is a flow chart of the data compression method described in an embodiment of the present disclosure;

[0025] Figure 2 A schematic diagram of the sign bit rotation according to an embodiment of the present disclosure;

[0026] Figure 3 A schematic diagram of the comparison increment operation described in an embodiment of the present disclosure;

[0027] Figure 4 A schematic diagram of the bit plane transformation described in an embodiment of the present disclosure;

[0028] Figure 5 A schematic diagram of a bitwise XOR operation according to an embodiment of the present disclosure;

[0029] Figure 6 A schematic diagram comparing two transformation results described in an embodiment of the present disclosure;

[0030] Figure 7 A schematic diagram of the structural rearrangement described in an embodiment of the present disclosure;

[0031] Figure 8 It is a structural schematic diagram of the data compression device according to an embodiment of the present disclosure;

[0032] Fig. 9 It is a schematic diagram of the structure of the electronic device described in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0034] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0035] In response to the technical problem of the data transmission bandwidth wall caused by the explosive growth of data, the present disclosure provides a data compression method, device, equipment and medium. The scheme is a data lossless compression algorithm for data transmission, which can ensure the data compression capability, reduce the transmission bandwidth requirements of neural network model data, and improve data transmission efficiency. For ease of understanding, the following is a detailed description of the embodiments of the present disclosure.

[0036] Figure 1 This is a flow chart of a data compression method provided by an embodiment of the present disclosure. This method improves the bit-plane compression algorithm (BPC) based on the characteristics of the neural network model and makes full use of the distribution law of the neural network model parameters, thereby improving the data compression capability. It can be applied to the compression of different types of data such as 8-bit, 16-bit and 32-bit, while still ensuring that the algorithm structure is simple and convenient for its hardware implementation. This method can be executed by a data compression device, which can be implemented in software and / or hardware. Figure 1 As shown, the data compression method provided in this embodiment may include the following steps.

[0037] S102, performing sign bit rotation on input data of the current cycle to obtain first data.

[0038] In this embodiment, the input data includes but is not limited to data in FP32, FP16, INT32, and INT8 formats. The input data is, for example, 32-bit floating point data, which consists of 1 sign bit, 8 exponent bits, and 23 mantissa bits, where the sign bit is located at the most significant bit. Alternatively, the input data is, for example, signed integer data, and the sign bit of the signed integer data is also located at the most significant bit. In order to reduce the influence of the sign bit, this embodiment can rotate the sign bit of the input data, as shown below:

[0039] The sign bit at the most significant bit in the input data of the current cycle is moved to the least significant bit, and the other bit data in the input data except the sign bit are moved forward in sequence to obtain the first data.

[0040] Specifically, in order to reduce the influence of the sign bit, this embodiment moves the sign bit in the input data from the most significant bit to the least significant bit, and moves the other data bits forward by one bit in sequence, which is the sign bit rotation.

[0041] Reference Figure 2, taking 8-bit input data as an example to show the process of sign bit rotation. For example, the input data of the first row is 0xE0 1110 0000, and the sign bit is rotated, that is, the sign bit "1" of the most significant bit is moved to the least significant bit, and the other bits of data "110 0000" are shifted one bit to the left in sequence, forming "1100 0001". On this basis, the new input data corresponding to the first row of input data is 0xC1 1100 0001.

[0042] Considering that the existing bit plane compression algorithm can only compress 32-bit data (such as FP32 and INT type data). Based on this, for data smaller than 32-bit such as 16-bit data and 8-bit data, an embodiment of rotating the sign bit of the input data to obtain the first data can also be provided, including:

[0043] When the input data of the current cycle is data with a bit width less than 32 bits, the input data is subjected to sign bit rotation; the specific implementation process of the sign bit rotation can refer to the above embodiment. Then, the data after the sign bit rotation is placed in the low bit of 32 bits, and the high bit of 32 bits is filled with 0 to obtain the first data.

[0044] For data smaller than 32 bits, this embodiment fills high bits with zeros to form 32-bit data, so that the difficulty of data compression can be reduced through subsequent data compression processes such as comparison and increment operations.

[0045] S104, performing an incremental operation on the first data and the second data to obtain third data; wherein the second data is data after the sign bit is rotated in the previous cycle.

[0046] In some bit plane compression algorithms, an incremental operation is usually adopted, that is, both data are regarded as unsigned integers and subtracted. Specifically, the latter data is subtracted from the previous data in binary, and the absolute value of the difference is recorded. This incremental operation does not consider the value of floating-point numbers. In essence, it treats two adjacent data as unsigned integers and subtracts them. If the difference is a negative number, the result is likely to have more "1" values.

[0047] In order to avoid the above problems, this embodiment adopts a comparison increment operation, that is, the data of the two cycles before and after are compared and incremented to obtain the third data. Figure 3 The implementation process of this step can be referred to as follows.

[0048] Compare the numerical values ​​of the first data and the second data. Exemplarily, the first data can be used as the minuend, the second data can be used as the subtrahend, and the minuend and the subtrahend can be compared. The above-mentioned second data is the data after the sign bit is rotated in the previous cycle. It can be understood that the current cycle mentioned in the above embodiment is a relative concept, which is used to characterize a time period for receiving input data and performing sign bit rotation; similarly, the first data and the second data are also relative, and are the data after the sign bit is rotated corresponding to the upper and lower adjacent cycles, that is, the first data of the previous cycle becomes the second data that needs to be used as the subtrahend in the current cycle, and so on. The first data that is the minuend in the current cycle becomes the second data that needs to be used as the subtrahend in the next cycle.

[0049] According to the comparison result, the data with a larger value is subtracted from the data with a smaller value to obtain a difference. If the minuend is smaller after comparing the size of the minuend and the subtrahend, the difference is a negative value. In order to avoid a large number of "1" values ​​in the negative difference, the present embodiment can use the data with a larger value as the minuend and the data with a smaller value as the subtrahend according to the comparison result, so that the data with a smaller value is subtracted from the data with a larger value to obtain a non-negative difference. The present embodiment refers to the above algorithm, in which the minuend and the subtrahend are exchanged and then subtracted if the minuend is smaller, as a comparison increment operation.

[0050] Then, based on the difference, a high-order extension bit is added to obtain the third data; wherein, when the value of the first data is greater than or equal to the value of the second data, the high-order extension bit is the first value; when the value of the first data is less than the value of the second data, the high-order extension bit is the second value.

[0051] Specifically, in this embodiment, the output of the comparison increment operation is increased by one high-order extension bit compared to the input, and the high-order extension bit is used to indicate the numerical value between the data of two adjacent periods; for example, the high-order extension bit is the first numerical value "0", indicating that the numerical value of the first data of the current period is greater than or equal to the numerical value of the second data of the previous period; the high-order extension bit is the second numerical value "1", indicating that the numerical value of the first data of the current period is less than the numerical value of the second data of the previous period, which means that the minuend and the subtrahend are exchanged, and the high-order extension bit is the second numerical value "1" to remind the decompressor to perform a corresponding exchange when restoring the data.

[0052] Reference Figure 3The first and second rows of input data of the upper and lower cycles in the first row represent the first data of the current cycle as 1100 1101, and the second row represents the second data of the previous cycle as 0000 0100. After comparison, the first data 1100 1101 is greater than the second data 00000100. Subtract the second data 0000 0100 with a smaller value from the first data 1100 1101 with a larger value, and get the difference 1101 1001. Based on the difference again, add the high-order extension bit to the first value "0". Based on this, the third data is 0 1101 1001.

[0053] In addition, it should be noted that for the bottom row of data ( Figure 3 1100 0001), which has no data of the next cycle adjacent to it, so it remains unchanged.

[0054] S106, performing bit plane transformation and bitwise XOR operation on the third data of multiple cycles stored in columns to obtain deformed data.

[0055] Through the above embodiment, the third data of multiple cycles can be obtained, that is, Figure 3 The right figure shows a plurality of rows of first data stored in the form of blocks. In this case, the third data can be written into the data transformation array in this embodiment, and Figure 4 As shown, in the data transformation array, the third data of multiple cycles are stored in the column direction.

[0056] In this embodiment, the third data of multiple cycles stored in columns are first subjected to bit plane transformation, and then subjected to bitwise XOR operation. The bit plane transformation process may include:

[0057] The basic number in the third data of multiple cycles stored in columns remains unchanged; for other column data except the basic number in the multiple third data, the same weight bits in each column data are reorganized row by row to obtain multiple rows of bit plane transformation data.

[0058] Reference Figure 4 In one implementation, the third data in the first column is called a base number, and the base number 1100 0001 remains unchanged. The third data in other columns are read by row instead of by column, that is, the data in the same column are arranged by row. Specifically, the data in the first column (i.e., the highest bit) of each third data are respectively: 0, 1, 0, 1, 0, 1, and 0. The above data in the first column are composed of the first new data 0101010, which is the bit-plane transformed data; similarly, the data in the second column (i.e., the second highest bit) of each data are composed of the second bit-plane transformed data 0000011; and so on, until the data in the last column (i.e., the lowest bit) are composed of the last bit-plane transformed data.

[0059] Reference Figure 5 This embodiment performs a bitwise XOR operation on the base number and multiple lines of bit plane transformation data, including: keeping the base number and the first bit plane transformation data unchanged; starting from the second line of bit plane transformation data, performing a bitwise XOR operation on each line of bit plane transformation data and the previous line of bit plane transformation data to obtain deformed data.

[0060] Specifically, the characteristic of XOR operation is that when the input is two identical values, the output is "0". For an input that has undergone a sudden change in the data, multiple consecutive "1" bits may be generated after incremental calculation (of course, the use of comparative incremental operation in this embodiment will reduce the generation of "1" values), and after the bit plane transformation, the same weight bit of multiple data becomes "1", which will be converted into "0" through XOR operation. Therefore, this embodiment can further extract the characteristics of the data for compression by performing bitwise XOR operation on the base number and multiple rows of bit plane transformation data, thereby improving the data compression capability.

[0061] Reference Figure 6 , showing the original transformation result of transforming 8-bit data using the original bit plane compression algorithm, and the improved transformation result of transforming 8-bit data using the improved bit plane compression algorithm in the embodiment of the present disclosure. It can be clearly seen that the improved transformation result obtained by using the embodiment of the present disclosure produces more values ​​that can reduce the amount of data through data encoding, including Figure 6 Bold font is used to indicate multiple lines of data.

[0062] For 8-bit data, after bit plane transformation and bitwise XOR operation, the original third data is transformed into a column of 8-bit base numbers and 9 rows of 8-bit deformation numbers; for 32-bit data, after bit plane transformation and bitwise XOR operation, the original third data is transformed into a column of 32-bit base numbers and 33 rows of 31-bit deformation numbers. One column of base numbers and multiple rows of deformation numbers constitute deformation data in the form of data blocks.

[0063] S108, performing bit plane data encoding on the deformed data to obtain output data.

[0064] After the deformed data is obtained, bit plane data encoding is performed on the deformed data to fully compress the "0" symbol. This embodiment may include the following steps (1) and (2).

[0065] (1) bit-plane data encoding is performed on the deformed data to obtain encoded data; wherein the bit-plane data encoding at least includes: zero-value run-length encoding and frequent pattern encoding, and the priority of zero-value run-length encoding is higher than the priority of frequent pattern encoding.

[0066] Bit plane data encoding can include two priority encoding methods: zero run-length encoding and frequent pattern encoding. Since there is a high probability of generating all "0" values ​​during data transformation, zero run-length encoding is matched first during the encoding process. The following is an exemplary description of the encoding method for compressing 32-bit data.

[0067] Zero-value run-length coding replaces continuous repeated values ​​with values ​​and runs. In this embodiment, the bit plane data coding uses zero-value run-length coding, which is only compressed and recorded when there are all "0" values. If the run is only 1, the full "0" value of the row is replaced by the code "001", that is, the output result is changed from the original 31-bit data to a 3-bit "001" code; if the run is greater than 1, it is encoded as "01+the number of consecutive '0's", with a total code length of 7 bits, and a maximum run length of 32 can be recorded. If all 33 data are all "0" values, the last data is separately encoded with a zero-value run of 1, generating the code "001".

[0068] Frequent pattern coding is used to encode several other common data forms other than "0", and the encoding method table is shown in Table 1. The first type is a row with all "1" values, which is encoded as "00000". The second type is a row that is not "0" after the bitwise XOR operation, but is all "0" values ​​before the bitwise XOR operation, which is encoded as "00001". The third type is a row with only two consecutive "1" values, which is encoded as "00010+the position of the first '1' value". The fourth type is a row with only one "1" value, which is encoded as "00011+the position of the '1' value". For values ​​that do not conform to the above types, they are not compressed, and the prefix "1" is added and the value is output as it is.

[0069] Table 1

[0070] Data Style Code length Encoding method Continuous 0 values 7-bit {2b'01+5b' the number of consecutive "0" values} Single 0 value 3-bit {3b’001} All 1 values 5-bit {5b’00000} DBX!=0 and DBP=0 5-bit {5b’00001} There are only two consecutive "1"s in the data 10-bit {5b'00010+5b'"1" value position} There is only one "1" in the data 10-bit {5b'00011+5b'"1" value position} other 32-bit {1b'1+31b' original data}

[0071] In one embodiment, in addition to the bit plane data, the base number may also be compressed. The base number encoding method can be referred to as shown in Table 2. The compression of the base number depends only on its own characteristics. If it is all "0", or only the lower 4 bits, lower 8 bits, and lower 16 bits have data, 3 bits will be encoded and the corresponding non-0 bits will be recorded. Otherwise, it will be stored in the form of "1+original 32-bit number". All data are encoded and compressed through the above embodiments.

[0072] Data Style Code length Encoding method 0x0000_0000 3-bit {3’b000} 0x0000_000x 7-bit {3'b001,4-bit data} 0x0000_00xx 11-bit {3'b010,8-bit data} 0x0000_xxxx 19-bit {3'b011,16-bit data} other 33-bit {1'b1,32-bit data}

[0073] In addition, the existing bit plane compression algorithm only compresses 32-bit data. For data smaller than 32-bit, such as 16-bit data and 8-bit data, since the aforementioned embodiment can form 32-bit data by padding high bits with zeros, and performing comparative increment operations, bit plane transformations, and XOR operations on this basis, each 0 bit filled with data is converted into a continuous all-0 value, and converted into a 7-bit code using zero-value run-length coding during the data encoding process.

[0074] (2) Rearrange the structure of the encoded data to obtain output data.

[0075] like Figure 7 As shown, according to the above embodiment, fixed-length input data is converted into codes of different lengths. If the codes are not closely arranged, the "0" value generated by the bit plane compression algorithm is not actually utilized, and the total amount of data is not reduced. Therefore, this embodiment needs to design a structure rearrangement unit to rearrange the code structure before outputting it to obtain compressed output data. Figure 7 Comparing the left and right sides, it can be seen that the output data after structural rearrangement has significantly reduced the amount of data.

[0076] In summary, the data compression method provided by the embodiment of the present disclosure firstly rotates the sign bit of the input data of the current cycle, reduces the sign bit weight, and makes the first data more convenient to compress; then compares the first data with the second data by incremental operation, which can improve the data compression rate and obtain the third data with a smaller data volume; secondly, the third data of multiple cycles stored in columns are subjected to bit plane transformation and bitwise XOR operation to obtain deformed data, which step can further extract the features of the data for compression and improve the data compression capability; finally, the deformed data is subjected to bit plane data encoding, which can facilitate data storage and output. Therefore, the technical solution can effectively compress a variety of data format parameters in the neural network model through sign bit rotation, comparison incremental operation, bit plane transformation and bitwise XOR operation and bit plane data encoding, improve data compression capability, reduce the amount of data to be transported, greatly alleviate the bandwidth pressure of data transmission, thereby improving the computing performance, and can be applied to the compression of different types of data, while still ensuring the simplicity of the algorithm structure and facilitating its hardware implementation.

[0077] Figure 8 The structure diagram of a data compression device provided by an embodiment of the present disclosure is shown in FIG. 1 . The device can be used to implement a data compression method, and the device can be implemented using software and / or hardware. Figure 8 As shown, the data compression device provided in this embodiment may include the following modules.

[0078] A sign bit rotation module 210, configured to perform sign bit rotation on input data of a current cycle to obtain first data;

[0079] A comparison increment operation module 220 is used to perform a comparison increment operation on the first data and the second data to obtain third data; wherein the second data is the data after the sign bit is rotated in the previous cycle;

[0080] A transformation module 230, configured to perform bit plane transformation and bitwise XOR operation on the third data of the plurality of cycles stored in columns to obtain deformed data;

[0081] The encoding module 240 is used to perform bit plane data encoding on the deformation data to obtain output data.

[0082] The implementation principle and technical effects of the device provided in this embodiment are the same as those of the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the device embodiment, reference may be made to the corresponding contents in the aforementioned method embodiment.

[0083] Fig. 9 The structure diagram of an electronic device provided by the embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the electronic device 300 includes one or more processors 301 and a memory 302 .

[0084] The processor 301 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 300 to perform desired functions.

[0085] The memory 302 may include one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 301 may run the program instructions to implement the data compression method of the embodiment of the present disclosure described above and / or other desired functions. Various contents such as input signals, signal components, noise components, etc. may also be stored in the computer-readable storage medium.

[0086] In one example, the electronic device 300 may further include: an input device 303 and an output device 304 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0087] In addition, the input device 303 may also include, for example, a keyboard, a mouse, and the like.

[0088] The output device 304 can output various information to the outside, including the determined distance information, direction information, etc. The output device 304 can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0089] Of course, to simplify, Fig. 9 Only some of the components related to the present disclosure in the electronic device 300 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 300 may also include any other appropriate components.

[0090] Furthermore, this embodiment also provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program is used to execute the above data compression method.

[0091] A computer program product of a data compression method, device, electronic device and medium provided in the embodiments of the present disclosure includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the previous method embodiments. The specific implementation can be found in the method embodiments and will not be repeated here.

[0092] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0093] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data compression method, characterized in that: include: Rotate the sign bit of the input data of the current cycle to obtain first data; Performing an incremental operation by comparing the first data with the second data to obtain third data; wherein the second data is data after the sign bit is rotated in the previous cycle; Performing bit plane transformation and bitwise XOR operation on the third data of a plurality of cycles stored in columns to obtain deformed data; The deformed data is encoded in bit plane data to obtain output data.

2. The method according to claim 1, characterized in that The step of performing sign bit rotation on the input data of the current cycle to obtain the first data includes: The sign bit at the most significant bit in the input data of the current cycle is moved to the least significant bit, and the other bit data in the input data except the sign bit are moved forward in sequence to obtain the first data.

3. The method according to claim 1, characterized in that The step of performing sign bit rotation on the input data of the current cycle to obtain the first data includes: When the input data of the current cycle is data with a bit width less than 32 bits, the input data is subjected to sign bit rotation; The data after the sign bit is rotated is placed in the 32-bit low order, and the 32-bit high order is filled with 0 to obtain the first data.

4. The method according to claim 1, characterized in that: The step of performing an incremental operation on the first data and the second data to obtain the third data comprises: Compare the first data with the second data in terms of numerical value; According to the comparison result, the data with a larger value is subtracted from the data with a smaller value to obtain the difference; A high-order extension bit is added on the basis of the difference to obtain third data; wherein, when the value of the first data is greater than or equal to the value of the second data, the high-order extension bit is the first value; when the value of the first data is less than the value of the second data, the high-order extension bit is the second value.

5. The method according to claim 1, characterized in that The step of performing bit plane transformation on the third data of the plurality of cycles stored in columns comprises: keeping the base numbers in the third data of the plurality of cycles stored in columns unchanged; For other column data except the base number in the plurality of third data, the same weighted bits in each column data are reorganized row by row to obtain a plurality of rows of bit plane transformation data.

6. The method according to claim 5, characterized in that The bitwise XOR operation includes: maintaining the base number and the first bit plane transformation data unchanged; Starting from the second row of the bit plane transformation data, each row of the bit plane transformation data is subjected to a bitwise XOR operation with the previous row of the bit plane transformation data to obtain deformed data.

7. The method according to claim 1, characterized in that The step of performing bit plane data encoding on the deformed data to obtain output data comprises: Performing bit plane data encoding on the deformed data to obtain encoded data; wherein the bit plane data encoding includes: zero-value run-length encoding and frequent mode encoding, and the priority of the zero-value run-length encoding is higher than the priority of the frequent mode encoding; The encoded data is restructured to obtain output data.

8. A data compression device, characterized in that: include: A sign bit rotation module, used for performing sign bit rotation on input data of a current cycle to obtain first data; A comparison increment operation module, used for performing a comparison increment operation on the first data and the second data to obtain third data; wherein the second data is data after the sign bit is rotated in the previous cycle; A transformation module, used for performing bit plane transformation and bitwise XOR operation on the third data of a plurality of cycles stored in columns to obtain deformed data; The encoding module is used to perform bit plane data encoding on the deformation data to obtain output data.

9. An electronic device, characterized in that: The electronic device comprises: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the instructions to implement the method described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed on a terminal device, the terminal device implements the method according to any one of claims 1 to 7.

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