Timing error detection method and device matched with shaping filter, electronic equipment and storage medium

Abstract

The invention discloses a timing error detection method and device matched with a shaping filter, electronic equipment and a storage medium. The method comprises the following steps: acquiring a demodulation signal to be subjected to timing synchronization, and inputting the demodulation signal to be subjected to timing synchronization into an interpolation filter of a receiving end to output interpolation data of a current round; obtaining ideal median data and actual median data between two adjacent target symbol data in the current round of interpolation data, and determining a median error according to the ideal median data and the actual median data; according to the median error, calculating a current wheel phase deviation control coefficient for a numerical control oscillator of a receiving end; and generating a current wheel interpolation coefficient for an interpolation filter according to the current wheel phase offset control coefficient by using a numerical control oscillator so as to adjust an interpolation data phase, and generating a current wheel sampling clock so as to detect a timing phase error of an interpolation data sampling point. The technical scheme of the invention is adaptive to a high-order phase modulation system, and the synchronization error is reduced while the synchronization speed is improved.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a timing error detection method, device, electronic equipment and storage medium matched to a shaping filter. Background Art

[0002] In wireless communication systems based on digital baseband signal processing, since the transmitter and receiver of the signal are usually two independent devices, there is often a certain phase deviation between the symbol clock of the transmitter and the sampling clock of the receiver. The timing synchronization unit in the receiver is often used to adjust the phase of the sampling clock to ensure that the symbols of the receiver are synchronized with the symbols of the transmitter, so that the symbol information of the transmitter can be correctly restored at the receiver.

[0003] In the existing timing synchronization technology based on MPSK (multi-level digital phase modulation), the Gardner timing synchronization algorithm is usually used. The Gardner timing synchronization unit is mainly composed of three modules: an interpolation filter, a timing error detection module and an NCO (numerically controlled oscillator).

[0004] However, in the traditional Gardner timing synchronization algorithm, because the timing error detection module only extracts the timing phase error data when the sampling data symbol changes, and simply uses the sampling data between two symbol sampling points as the timing phase error, the influence of the transmitter shaping filter on the baseband waveform is ignored. While the synchronization speed is slow, the synchronization error is also large, and it is not suitable for high-order phase modulation systems. Summary of the invention

[0005] The present invention provides a timing error detection method, device, electronic device and storage medium matched to a shaping filter, so as to adapt to a high-order phase modulation system, improve the synchronization speed and reduce the synchronization error at the same time.

[0006] According to one aspect of the present invention, a timing error detection method matched to a shaping filter is provided, the method being applied to a receiving end of a phase modulation and demodulation system, the method comprising:

[0007] Acquire a demodulated signal to be synchronized at a certain time, and input the demodulated signal to be synchronized at a certain time into an interpolation filter at the receiving end to output current round interpolation data;

[0008] Acquire ideal median data and actual median data between two adjacent target symbol data in the current round of interpolation data, and determine a median error according to the ideal median data and the actual median data;

[0009] Calculating a current round phase deviation control coefficient for a digitally controlled oscillator at the receiving end according to the median error;

[0010] The digital controlled oscillator is used to generate a current round of interpolation coefficients for the interpolation filter according to the current round of phase deviation control coefficients to adjust the interpolation data phase, and to generate a current round of sampling clocks to detect the timing phase error of the interpolation data sampling points.

[0011] According to another aspect of the present invention, there is provided a timing error detection device matched to a shaping filter, the device being configured at a receiving end of a phase modulation and demodulation system, the device comprising:

[0012] An interpolation data acquisition module, used for acquiring a demodulated signal to be synchronized at a certain time, and inputting the demodulated signal to be synchronized at a certain time into the interpolation filter of the receiving end to output the current round of interpolation data;

[0013] A median error determination module, used to obtain ideal median data and actual median data between two adjacent target symbol data in the current round of interpolation data, and determine the median error according to the ideal median data and the actual median data;

[0014] A phase deviation control coefficient calculation module, used for calculating the current round phase deviation control coefficient for the digital controlled oscillator of the receiving end according to the median error;

[0015] The timing error detection module is used to use the digital controlled oscillator to generate the current round interpolation coefficient for the interpolation filter according to the current round phase deviation control coefficient to adjust the interpolation data phase, and generate the current round sampling clock to detect the timing phase error of the interpolation data sampling point.

[0016] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0017] at least one processor; and

[0018] a memory communicatively connected to the at least one processor; wherein,

[0019] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the timing error detection method matched to the shaping filter described in any embodiment of the present invention.

[0020] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the timing error detection method matched to a shaping filter described in any embodiment of the present invention when executed.

[0021] The technical solution of the embodiment of the present invention obtains the demodulated signal to be synchronized at the timing, and inputs the demodulated signal to be synchronized at the timing into the interpolation filter of the receiving end to output the current round of interpolation data; obtains the ideal median data and the actual median data between two adjacent target symbol data in the current round of interpolation data, and determines the median error according to the ideal median data and the actual median data; calculates the current round of phase deviation control coefficient for the numerically controlled oscillator of the receiving end according to the median error; uses the numerically controlled oscillator to generate the current round of interpolation coefficient for the interpolation filter according to the current round of phase deviation control coefficient to adjust the phase of the interpolation data, and generates the current round of sampling clock to detect the timing phase error of the sampling point of the interpolation data, and adopts the technical means of calculating the ideal median data for the interpolation data to calculate the median error according to the ideal median data and the actual median data, so as to realize the timing phase error detection based on the median error, solves the problem that the prior art ignores the influence of the transmitter shaping filter on the baseband waveform, resulting in a slow synchronization speed of the receiving end and a large synchronization error, and cannot be applied to a high-order phase modulation system, adapts to the high-order phase modulation system, improves the synchronization speed and reduces the synchronization error.

[0022] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1a A brief schematic block diagram of part of the data flow in a standard MPSK system provided by an embodiment of the present invention;

[0025] Figure 1b A schematic diagram of the time domain waveform of a constellation mapping signal of a transmitting end taking 8PSK as an example provided in an embodiment of the present invention before and after passing through a shaping filter;

[0026] Figure 1c It is a schematic diagram of a timing error detection method in a traditional Gardner timing synchronization algorithm;

[0027] Figure 1d A schematic diagram of a time domain waveform of a shaping filter provided by an embodiment of the present invention;

[0028] Figure 1eA flowchart of a timing error detection method matched to a shaping filter provided in Embodiment 1 of the present invention;

[0029] Figure 1f A schematic diagram of the working principle of a digitally controlled oscillator provided in an embodiment of the present invention;

[0030] Figure 2 A schematic block diagram of a receiving end module provided by an embodiment of the present invention;

[0031] Figure 3 A schematic structural diagram of a timing error detection device matched to a shaping filter provided in Embodiment 2 of the present invention;

[0032] Figure 4 It is a structural schematic diagram of an electronic device for implementing a timing error detection method matched to a shaping filter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] Embodiment 1

[0036] Figure 1eA flowchart of a timing error detection method matched to a shaping filter is provided in Embodiment 1 of the present invention. This embodiment can be applicable to the situation where a receiving end of a phase modulation and demodulation system that matches a shaping filter at a transmitting end performs timing error detection. The method can be executed by a timing error detection device matched to the shaping filter. The timing error detection device matched to the shaping filter can be implemented in the form of hardware and / or software. The timing error detection device matched to the shaping filter can be configured in the signal receiving end of the phase modulation and demodulation system.

[0037] Before introducing the timing error detection method matched to the shaping filter of this embodiment, a brief schematic diagram of part of the data flow in the standard MPSK (multiple phase shift keying, multi-level digital phase modulation) system is first introduced. Figure 1a As shown, it includes a constellation mapping signal, a shaping filter, a shaping signal, a carrier modulation, and filtering at the signal transmitting end, as well as filtering, orthogonal demodulation, a demodulation signal, a timing synchronization unit, and a synchronization signal at the signal receiving end. The present invention only relates to Figure 1a The timing synchronization unit in the figure is described, and the reason why the present invention can accurately detect the timing error is explained by explaining the constellation diagram mapping signal, shaping filter, shaping signal, demodulation signal and timing synchronization unit in the figure.

[0038] In a high-order (>4) phase modulation and demodulation system, taking 8PSK as an example, the time domain waveform of the constellation mapping signal at the transmitter before and after passing through the shaping filter can be as follows: Figure 1b As shown. It can be seen that the shaping filter can avoid the interference between the symbols of the constellation diagram while also smoothing the burst constellation diagram mapping signal. The shaping signal output by the shaping filter is converted into a demodulated signal after carrier modulation, filtering, transmission, wireless transmission, reception, filtering, and orthogonal carrier demodulation. Ideally, it is assumed that these intermediate processes are error-free, and the demodulated signal can be consistent with the shaping signal in the time domain waveform.

[0039] Figure 1c The figure shows the timing error detection method in the traditional Gardner timing synchronization algorithm. When the positive and negative symbol values ​​of two adjacent symbols reverse, the value of the sampling point between the two symbols is taken as the phase offset error of the sampling clock, and the sampling clock phase is adjusted according to the error. When the positive and negative symbol values ​​of two adjacent symbols do not change, the sampling clock phase offset error is considered to be 0, that is, the sampling clock phase does not need to be adjusted at this time.

[0040] from Figure 1bIt can be understood from the time domain waveform of the formed signal shown that the positive and negative signs of two adjacent symbols of the demodulated signal (formed signal) are not always changing, such as s1 and s2, s5 and s6. As a result, the sampling clock phase of the traditional Gardner timing synchronization algorithm is not always adjusted during the timing synchronization stage. It is necessary to wait for the positive and negative signs of two adjacent symbols to reverse before the phase error can be detected and the phase adjustment can be made. Therefore, the synchronization speed is slow. At the same time, the traditional Gardner timing synchronization algorithm believes that after the timing synchronization is stable, when the positive and negative signs of two adjacent symbols change, the sampling data of the middle sampling point should be stable at around 0. But also from Figure 1b It can be seen from the time domain waveform of the shaping signal shown that when the positive and negative signs of two adjacent symbols change, the sampling data of the middle sampling point is affected by the shaping filter and is not necessarily stable around 0, such as m0, m1, m2, and m3. Therefore, after the synchronization is stable, the traditional Gardner timing synchronization algorithm may judge the correct non-zero middle sampling point data as a phase error and make unnecessary phase adjustments, resulting in sampling errors.

[0041] For example, Figure 1dis the time domain waveform of the shaping filter with a filter width of 8, an interpolation multiple of 16, and a roll-off factor of 0.15. Assume that 10 consecutive constellation mapping signals a0, a1, a2, a3, a4, a5, a6, a7, a8, and a9 pass through the shaping filter. Assume that at time t0, the 9 constellation mapping signals a1 to a9 are multiplied by c0, c2, c4, c6, c8, c10, c12, c14, and c16 respectively. It is known that c0, c2, c4, c6, c10, c12, c14, and c16 are all 0. At this time, the output of the filter is actually a5*c8, that is, at time t0, the shaping filter outputs the symbol data a5; at time t1 after 16 sampling cycles, a0 to a 8These 9 constellation mapping signals are multiplied by c0, c2, c4, c6, c8, c10, c12, c14, c16 respectively, and the shaping filter outputs the symbol data a4; then at the middle moment of the two symbols a5 and a4, the actual output value of the shaping filter is the sum of the products of a1, a2, a3, a4, a5, a6, a7, a8 and c1, c3, c5, c7, c9, c11, c13, c15 respectively. Therefore, the calculation method of the symbol data at the middle moment of the two symbol data a5 and a4 can be used as the calculation method of the middle sampling point data between any two symbol data of the shaping signal (the same is true for the demodulated signal), and the calculated data of the middle sampling point is used as the ideal median data, then the difference between the data of the middle sampling point actually sampled and the ideal median data can reflect the phase deviation of the sampling clock. The calculation of the phase deviation is not affected by the positive or negative sign of the symbol, and after the synchronization is stable, the difference between the data of the middle sampling point actually sampled and the ideal median should be stable at around 0. Therefore, this characteristic can be used to achieve rapid and accurate detection of timing errors.

[0042] It should be noted that the above-mentioned method for calculating the ideal median data is only an example and is not limited in this embodiment.

[0043] like Figure 1e As shown, the timing error detection method matched to the shaping filter includes:

[0044] S110, acquiring a demodulated signal to be synchronized at a predetermined time, and inputting the demodulated signal to be synchronized at a predetermined time into an interpolation filter of the receiving end to output current round interpolation data.

[0045] The demodulated signal to be synchronized at the timing may refer to the signal input to the interpolation filter of the receiving end. The current round of interpolation data may refer to the signal data after the interpolation filter processes the demodulated signal to be synchronized at the timing.

[0046] In this embodiment, the timing error detection and synchronization processing of the demodulated signal to be synchronized cannot be completed after a simple round of feedback processing, so an interpolation filter can be used to process the demodulated signal to be synchronized and then output the current round of interpolation data.

[0047] In an optional implementation, inputting the demodulated signal to be synchronized at the timing into the interpolation filter of the receiving end to output the current round of interpolation data may include: obtaining a first number of symbol data from the demodulated signal to be synchronized at the timing, and obtaining the interpolation coefficients of the previous round; obtaining the current round of interpolation data according to the first number of symbol data, the interpolation coefficients of the previous round and the preset interpolation data output rules of the interpolation filter.

[0048] The first number may refer to the number of symbol data of the demodulated signal to be synchronized when the data interpolation requirement is met. The previous round of interpolation coefficients may refer to the interpolation coefficients of the interpolation filter calculated by the receiving end in the previous round of feedback processing.

[0049] For example, assume that four symbol data x(n), x(n-1), x(n-2), and x(n-3) are obtained from the demodulated signal to be synchronized, and the interpolation coefficients are u k Indicates that the preset interpolation data output rule can be: in, In this embodiment, since the interpolation coefficients are all generated by the count overflow data of the control oscillator, the value range of uk can be [-1, 0].

[0050] S120 , obtaining ideal median data and actual median data between two adjacent target symbol data in the current round of interpolation data, and determining a median error according to the ideal median data and the actual median data.

[0051] Among them, two adjacent target symbol data may refer to two adjacent symbol data determined according to the error calculation requirement, for example, referring to the above-mentioned Figure 1d The calculation principle of the ideal median data of the shaping filter time domain waveform, for example, two adjacent target symbol data can be determined as two symbols a4 and a5. The ideal median data can refer to the ideal median corresponding to the influence of the shaping filter at the middle moment of the two adjacent target symbol data. The actual median data can refer to the data actually sampled at the middle moment of the two adjacent target symbol data during the current round of interpolation data sampling.

[0052] In this embodiment, the ideal data affected by the shaping filter at the middle moment between the two symbol data a4 and a5 can be calculated, and the data actually sampled at the middle moment between the two symbol data a4 and a5 (that is, the actual median data) can be obtained, and then the error between the ideal median data and the actual median data between the two symbol data a4 and a5 can be calculated as the median error.

[0053] In an optional implementation, obtaining ideal median data and actual median data between two adjacent target symbol data in the current round of interpolated data may include: determining the symbol clock and median clock corresponding to the current round of interpolated data; sampling the current round of interpolated data according to the symbol clock to obtain a second number of consecutive symbol data; calculating the ideal median data between two target symbol data in the second number of symbol data based on the second number of symbol data and the time domain waveform of the shaping filter; sampling the current round of interpolated data according to the median clock to obtain actual median data at the same time as the ideal median data.

[0054] The symbol clock may refer to the sampling clock of each symbol data in the current round of interpolated data. The median clock may refer to the sampling clock of the intermediate moment data of two adjacent target symbol data in the current round of interpolated data. The second number may refer to the sampling number of each symbol data in the current round of interpolated data determined according to the calculation requirements of the median data. Figure 1d According to the calculation principle of the ideal median data of the shaping filter time domain waveform, the second number of symbol data can be 8 symbol data. Correspondingly, the two target symbol data can refer to the 4th symbol data and the 5th symbol data.

[0055] In this embodiment, the sampling clock of the symbol data of the current round of interpolation data and the sampling clock of the median data can be determined, so that the current round of interpolation data is sampled according to the symbol clock to obtain the second number of symbol data. Further, according to the second number of symbol data and the time domain waveform of the shaping filter, the ideal median data between two target symbol data in the second number of symbol data is calculated with reference to the calculation principle of the ideal median data, and the current round of interpolation data is sampled according to the median clock to obtain the actual median data at the same time as the ideal median data.

[0056] Exemplarily, the current round of interpolation data is sampled according to the symbol clock timing to obtain 8 consecutive symbol data, and the ideal median data between the 4th symbol and the 5th symbol in the 8 symbol data is calculated according to the median calculation formula, and the calculation formula is: Among them, d0~d7 can correspond to Figure 1d c1, c3, c5, c7, c9, c11, c13, c15, x0 is the later sampled symbol data, and x7 is the earlier sampled symbol data. It should be noted that in the actual implementation, since d0 is the same as d7 (i.e. Figure 1d c1 is the same as c15), d1 is the same as d6 (i.e. Figure 1d c3 is the same as c13), d2 is the same as d5 (i.e. Figure 1d c5 and c11 are the same), d3 and d4 are the same (i.e. Figure 1dc7 and c9 are the same), you can first add x0 and x7, x1 and x6, x2 and x5, x3 and x4, and then multiply the sum with d0, d1, d2, and d3 respectively to get the ideal median data between the 4th symbol and the 5th symbol to save hardware resources.

[0057] Based on the above optional implementation, determining the symbol clock and median clock corresponding to the current round of interpolated data may include: obtaining a sampling clock corresponding to the current round of interpolated data; determining the symbol clock and median clock based on the binary frequency division of the sampling clock, wherein the median clock is inversely proportional to the symbol clock.

[0058] In this embodiment, the sampling clock corresponding to the current round of interpolation data may be the sampling clock of the current round of interpolation data calculated in the previous round or a preset initial sampling clock. The symbol clock and the median clock may be determined based on the sampling clock. To adapt to the calculation delay of the interpolation filter, the sampling clock may be delayed for multiple data cycles to generate the symbol clock and the median clock. Specifically, the symbol clock and the median clock may be determined based on the frequency division of the sampling clock by two. It should be noted that the median clock is in antiphase with the symbol clock.

[0059] In an optional implementation, determining the median error based on the ideal median data and the actual median data may include: by err=err i +err q =(m i -z i )*sign i +(m q -z q )*sign q Calculate the median error; where z represents the ideal median data; m represents the actual median data; sign represents the changing trend of the sampling symbols before and after the median. When the previous symbol is greater than the next symbol, the value is 1, otherwise it is -1; i represents the real part of the baseband signal, and q represents the imaginary part of the baseband signal.

[0060] S130, calculating the current round phase deviation control coefficient for the digital controlled oscillator at the receiving end according to the median error.

[0061] In an optional implementation, the current phase deviation control coefficient is calculated for the digital controlled oscillator at the receiving end according to the median error, which may include: wn(0)=wn(-1)+err off -itg off Calculate the current wheel phase deviation control coefficient; where, Among them, 0 represents the current round calculation value, -1 represents the previous round calculation value, off represents the offset value, err represents the median error, wn represents the phase deviation control coefficient, and wn 0represents the ideal fixed phase deviation control coefficient, which is the inverse of 1 / 2 of the signal interpolation multiple. sum and itg represent the phase deviation integral. c1 and c2 both represent the control coefficient, which is related to the actual signal amplitude, signal-to-noise ratio and control parameters of the numerically controlled oscillator.

[0062] S140, using a digitally controlled oscillator to generate a current round of interpolation coefficients for an interpolation filter according to the current round of phase deviation control coefficients to adjust the interpolation data phase, and to generate a current round of sampling clocks to detect timing phase errors of sampling points of the interpolation data.

[0063] In this embodiment, the digitally controlled oscillator can generate a current round sampling clock according to the current round phase deviation control coefficient to detect the timing phase error of the interpolation data sampling clock, and generate a current round interpolation coefficient while outputting the current round sampling clock, so as to enable the interpolation filter to adjust the interpolation data phase.

[0064] For example, Figure 1f A schematic diagram of the working principle of a digitally controlled oscillator is provided for this embodiment. In an MPSK demodulation system with 8x interpolation, the sampling clock should be twice the symbol clock to facilitate the acquisition of the symbol clock and the median clock. The digitally controlled oscillator counts according to the symbol clock, and each symbol clock counts 0.25, and is reset when the count reaches 1. When the transmitting end clock is synchronized with the receiving end clock and the positioning is synchronized, the data should be sampled once every four symbols. Figure 1f As shown by the blue arrow. When the timing error detection module detects the phase error and outputs the phase deviation control coefficient as 0.05, the count of each symbol clock becomes 0.25+0.25=0.5. After 4 symbol clocks, the counter becomes 1.2, that is, the timing error detection module expects to obtain the data of the 4th symbol clock moment and the 5th symbol clock moment with an offset of 0.2 times the symbol clock position, but due to the ADC (Analog-to-Digital Converter) sampling problem, it can actually only obtain the data of the 4th symbol clock moment, that is, 1.0. The digitally controlled oscillator transmits this overflow 0.2 to the interpolation filter, so that the interpolation filter shifts the data back by 0.2 times the data clock to obtain the expected data.

[0065] The technical solution of the embodiment of the present invention obtains the demodulated signal to be synchronized at the timing, and inputs the demodulated signal to be synchronized at the timing into the interpolation filter of the receiving end to output the current round of interpolation data; obtains the ideal median data and the actual median data between two adjacent target symbol data in the current round of interpolation data, and determines the median error according to the ideal median data and the actual median data; calculates the current round of phase deviation control coefficient for the numerically controlled oscillator of the receiving end according to the median error; uses the numerically controlled oscillator to generate the current round of interpolation coefficient for the interpolation filter according to the current round of phase deviation control coefficient to adjust the phase of the interpolation data, and generates the current round of sampling clock to detect the timing phase error of the sampling point of the interpolation data, and adopts the technical means of calculating the ideal median data for the interpolation data to calculate the median error according to the ideal median data and the actual median data, so as to realize the timing phase error detection based on the median error, solves the problem that the prior art ignores the influence of the transmitter shaping filter on the baseband waveform, resulting in a slow synchronization speed of the receiving end and a large synchronization error, and cannot be applied to a high-order phase modulation system, adapts to the high-order phase modulation system, improves the synchronization speed and reduces the synchronization error.

[0066] Optionally, the timing error detection method matched to the shaping filter of this embodiment may further include: generating a corresponding synchronization signal for the demodulated signal to be timed synchronized.

[0067] In order to enable those skilled in the art to better understand the timing error detection method matched to the shaping filter of this embodiment, Figure 2 A schematic block diagram of a receiving end provided in an embodiment of the present invention. It includes an interpolation filter, a timing error detection module and a digitally controlled oscillator. The timing error detection module consists of three processes: median calculation, error calculation and filtering correction. The interpolation filter adopts a cubic interpolator based on the Farrow structure, which is used to process the demodulated signal and output interpolation data; the median calculation process obtains the sampling median (ideal median data and actual median data) according to the interpolation data, the error calculation process calculates the median error according to the sampling median, and the filtering correction process calculates the phase deviation control coefficient according to the median error; the digitally controlled oscillator is responsible for adjusting the sampling clock according to the phase deviation control coefficient, and generating the interpolation coefficient for the interpolation filter to do phase fine-tuning.

[0068] Embodiment 2

[0069] Figure 3 This is a schematic diagram of the structure of a timing error detection device matched to a shaping filter provided in the second embodiment of the present invention, which can be configured at the receiving end of a phase modulation and demodulation system. Figure 3 As shown, the device includes: an interpolation data acquisition module 310, a median error determination module 320, a phase deviation control coefficient calculation module 330 and a timing error detection module 340. Among them:

[0070] The interpolation data acquisition module 310 is used to acquire the demodulated signal to be synchronized at the timing, and input the demodulated signal to be synchronized at the timing into the interpolation filter of the receiving end to output the current round of interpolation data;

[0071] A median error determination module 320 is used to obtain ideal median data and actual median data between two adjacent target symbol data in the current round of interpolation data, and determine a median error according to the ideal median data and the actual median data;

[0072] A phase deviation control coefficient calculation module 330, configured to calculate a current round of phase deviation control coefficients for a digitally controlled oscillator at the receiving end according to the median error;

[0073] The timing error detection module 340 is used to use the digitally controlled oscillator to generate the current round interpolation coefficient for the interpolation filter according to the current round phase deviation control coefficient to adjust the interpolation data phase, and generate the current round sampling clock to detect the timing phase error of the interpolation data sampling point.

[0074] The technical solution of the embodiment of the present invention obtains the demodulated signal to be synchronized at the timing, and inputs the demodulated signal to be synchronized at the timing into the interpolation filter of the receiving end to output the current round of interpolation data; obtains the ideal median data and the actual median data between two adjacent target symbol data in the current round of interpolation data, and determines the median error according to the ideal median data and the actual median data; calculates the current round of phase deviation control coefficient for the numerically controlled oscillator of the receiving end according to the median error; uses the numerically controlled oscillator to generate the current round of interpolation coefficient for the interpolation filter according to the current round of phase deviation control coefficient to adjust the phase of the interpolation data, and generates the current round of sampling clock to detect the timing phase error of the sampling point of the interpolation data, and adopts the technical means of calculating the ideal median data for the interpolation data to calculate the median error according to the ideal median data and the actual median data, so as to realize the timing phase error detection based on the median error, solves the problem that the prior art ignores the influence of the transmitter shaping filter on the baseband waveform, resulting in a slow synchronization speed of the receiving end and a large synchronization error, and cannot be applied to a high-order phase modulation system, adapts to the high-order phase modulation system, improves the synchronization speed and reduces the synchronization error.

[0075] Optionally, the interpolation data acquisition module 310 may be specifically used for:

[0076] Acquire a first number of symbol data from the demodulated signal to be synchronized at a certain time, and acquire a previous round of interpolation coefficients;

[0077] The current round of interpolation data is obtained according to the first number of symbol data, the previous round of interpolation coefficients and the preset interpolation data output rule of the interpolation filter.

[0078] Optionally, the median error determination module 320 may include:

[0079] A clock determination unit, used to determine a symbol clock and a median clock corresponding to the current round of interpolation data;

[0080] A symbol data acquisition unit, configured to sample the current round of interpolation data according to the symbol clock timing to acquire a second number of consecutive symbol data;

[0081] an ideal median data calculation unit, configured to calculate an ideal median data between two target symbol data in the second number of symbol data according to the second number of symbol data and the time domain waveform of the shaping filter;

[0082] The actual median data acquisition unit is used to sample the current round of interpolation data according to the median clock timing to acquire the actual median data at the same time as the ideal median data.

[0083] Optionally, the clock determination unit may be specifically used for:

[0084] Obtaining a sampling clock corresponding to the current round of interpolation data;

[0085] The symbol clock and the median clock are determined according to a frequency division of the sampling clock by two, and the median clock is in opposite phase to the symbol clock.

[0086] Optionally, the median error determination module 320 may further include a median error calculation unit, which is used to:

[0087] By err = err i +err q =(m i -z i )*sign i +(m q -z q )*sign q Calculating the median error;

[0088] Among them, z represents the ideal median data; m represents the actual median data; sign represents the changing trend of the sampling symbols before and after the median. When the previous symbol is greater than the next symbol, the value is 1, otherwise it is -1; i represents the real part of the baseband signal, and q represents the imaginary part of the baseband signal.

[0089] Optionally, the phase deviation control coefficient calculation module 330 may be specifically used for:

[0090] pass Calculating the current wheel phase deviation control coefficient;

[0091] Among them, 0 represents the current round calculation value, -1 represents the previous round calculation value, off represents the offset value, err represents the median error, wn represents the phase deviation control coefficient, and wn 0 represents the ideal fixed phase deviation control coefficient, which is the inverse of 1 / 2 of the signal interpolation multiple, sum and itg represent the phase deviation integral, c1 and c2 both represent the control coefficient, which is related to the actual signal amplitude, signal-to-noise ratio and the control parameters of the digital controlled oscillator.

[0092] Optionally, the timing error detection device matched to the shaping filter may further include a synchronization signal generating module, which is used to:

[0093] A corresponding synchronization signal is generated for the demodulated signal to be synchronized.

[0094] The timing error detection device matched to the shaping filter provided in the embodiment of the present invention can execute the timing error detection method matched to the shaping filter provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0095] Embodiment 3

[0096] Figure 4 A schematic diagram of an electronic device 400 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers or various forms of mobile devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0097] like Figure 4 As shown, the electronic device 400 includes at least one processor 401, and a memory connected to the at least one processor 401 in communication, such as a read-only memory (ROM) 402, a random access memory (RAM) 403, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 401 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 402 or the computer program loaded from the storage unit 408 to the random access memory (RAM) 403. In the RAM 403, various programs and data required for the operation of the electronic device 400 can also be stored. The processor 401, the ROM 402, and the RAM 403 are connected to each other via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0098] Multiple components in the electronic device 400 are connected to the I / O interface 405, including: an input unit 406, such as a keyboard, a mouse, etc.; an output unit 407, such as various types of displays, speakers, etc.; a storage unit 408, such as a disk, an optical disk, etc.; and a communication unit 409, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 409 allows the electronic device 400 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0099] Processor 401 may be a variety of general and / or dedicated processing components with processing and computing capabilities. Some examples of processor 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. Processor 401 performs the various methods and processes described above, such as a timing error detection method matched to a shaping filter.

[0100] In some embodiments, the timing error detection method matched to the shaping filter can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 408. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 400 via the ROM 402 and / or the communication unit 409. When the computer program is loaded into the RAM 403 and executed by the processor 401, one or more steps of the timing error detection method matched to the shaping filter described above can be performed. Alternatively, in other embodiments, the processor 401 can be configured to perform the timing error detection method matched to the shaping filter by any other appropriate means (for example, by means of firmware).

[0101] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0102] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0103] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0104] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0105] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0106] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0107] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0108] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A timing error detection method matched to a shaping filter, applied to a receiving end of a phase modulation and demodulation system, characterized in that: include: Acquire a demodulated signal to be synchronized at a certain time, and input the demodulated signal to be synchronized at a certain time into an interpolation filter at the receiving end to output current round interpolation data; Acquire ideal median data and actual median data between two adjacent target symbol data in the current round of interpolation data, and determine a median error according to the ideal median data and the actual median data; Calculating a current round phase deviation control coefficient for a digitally controlled oscillator at the receiving end according to the median error; The digital controlled oscillator is used to generate a current round of interpolation coefficients for the interpolation filter according to the current round of phase deviation control coefficients to adjust the interpolation data phase, and to generate a current round of sampling clocks to detect the timing phase error of the interpolation data sampling points.

2. The method according to claim 1, characterized in that Inputting the demodulated signal to be synchronized at the timing into the interpolation filter of the receiving end to output the current round of interpolation data, comprising: Acquire a first number of symbol data from the demodulated signal to be synchronized at a certain time, and acquire a previous round of interpolation coefficients; The current round of interpolation data is obtained according to the first number of symbol data, the previous round of interpolation coefficients and the preset interpolation data output rule of the interpolation filter.

3. The method according to claim 1, characterized in that Acquiring ideal median data and actual median data between two adjacent target symbol data in the current round of interpolation data, including: Determine a symbol clock and a median clock corresponding to the current round of interpolation data; sampling the current round of interpolation data according to the symbol clock timing to obtain a second number of consecutive symbol data; Calculating ideal median data between two target symbol data in the second number of symbol data according to the second number of symbol data and the time domain waveform of the shaping filter; The current round of interpolated data is sampled according to the median clock timing to obtain actual median data at the same time as the ideal median data.

4. The method according to claim 3, characterized in that Determining a symbol clock and a median clock corresponding to the current round of interpolation data includes: Obtaining a sampling clock corresponding to the current round of interpolation data; The symbol clock and the median clock are determined according to a frequency division of the sampling clock by two, and the median clock is in opposite phase to the symbol clock.

5. The method according to claim 3, characterized in that: Determining a median error according to the ideal median data and the actual median data includes: By err = err i +err q =(m i -z i )*sign i +(m q -z q )*sign q Calculating the median error; Among them, z represents the ideal median data; m represents the actual median data; sign represents the changing trend of the sampling symbols before and after the median. When the previous symbol is greater than the next symbol, the value is 1, otherwise it is -1; i represents the real part of the baseband signal, and q represents the imaginary part of the baseband signal.

6. The method according to claim 1, characterized in that Calculating a current phase deviation control coefficient for a numerically controlled oscillator at the receiving end according to the median error includes: err off =(err(0)-err(-1))·c1 i know off =wn(-1)-wn0 itg=sum·c2 itg off =itg(0)-itg(-1) By wn(0)=wn(-1)+err off -itg off Calculating the current wheel phase deviation control coefficient; Among them, 0 represents the current round calculation value, -1 represents the previous round calculation value, off represents the offset value, err represents the median error, wn represents the phase deviation control coefficient, wn0 represents the ideal fixed phase deviation control coefficient, which is the inverse of 1 / 2 of the signal interpolation multiple, sum and itg represent the phase deviation integral, c1 and c2 both represent the control coefficient, which is related to the actual signal amplitude, signal-to-noise ratio and the control parameters of the digital controlled oscillator.

7. The method according to claim 6, characterized in that Also includes: A corresponding synchronization signal is generated for the demodulated signal to be synchronized.

8. A timing error detection device matched to a shaping filter, configured at a receiving end of a phase modulation and demodulation system, characterized in that: include: An interpolation data acquisition module, used for acquiring a demodulated signal to be synchronized at a certain time, and inputting the demodulated signal to be synchronized at a certain time into the interpolation filter of the receiving end to output the current round of interpolation data; A median error determination module, used to obtain ideal median data and actual median data between two adjacent target symbol data in the current round of interpolation data, and determine the median error according to the ideal median data and the actual median data; A phase deviation control coefficient calculation module, used for calculating the current round phase deviation control coefficient for the digital controlled oscillator of the receiving end according to the median error; The timing error detection module is used to use the digital controlled oscillator to generate the current round interpolation coefficient for the interpolation filter according to the current round phase deviation control coefficient to adjust the interpolation data phase, and generate the current round sampling clock to detect the timing phase error of the interpolation data sampling point.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute a timing error detection method matched to a shaping filter according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement a timing error detection method matched to a shaping filter according to any one of claims 1 to 7 when executed.

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