Video image moving method and system based on FPGA
By introducing video input module and video image reconstruction module in the FPGA system, using frame synchronization signals and row synchronization signals to match, the problem of large consumption of external field of video images in the FPGA chip is solved, and arbitrary displacement and resource saving of video images are achieved.
Patent Information
- Application Number
- CN202510002221.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-04-25
AI Technical Summary
In FPGA chips, especially without external memory, it becomes difficult to realize the out-of-field movement of video images. Conventional methods will result in excessive consumption of FPGA resources and cannot meet the needs of multifunctional and low-cost.
By introducing video input module, mobile parameter reception module, trigger module and video image reconstruction module in the FPGA system, the frame synchronization signal, row synchronization signal and video data signal are used to match, and a new frame synchronization signal and row synchronization signal are generated, thereby realizing arbitrary displacement of the video image and reducing the consumption of FPGA resources.
It realizes the rapid and efficient displacement of video images without additional memory in the FPGA system, which reduces the consumption of FPGA resources and reduces hardware costs.
Smart Images
Figure CN119893010A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of video image processing, and relates to a video image moving method and system based on FPGA. Background Art
[0002] In video image processing, due to the requirements of the field of view of the device, it is often necessary to move the image up, down, left or right. The movement of the video image can be simply divided into movement within the field of view and movement outside the field of view. In FPGA, movement within the field of view is mainly achieved by controlling the effective interval of the frame line synchronization signal. It does not require a large amount of data caching, and can realize the selection of each field of view position window. Movement outside the field of view requires data caching. If the movement amount is small, distributed RAM or block RAM is generally used for data caching. If the movement amount is large, external memory is generally used for data caching, such as SDRAM and DDR memory devices, and the video image is moved by controlling the address of the read and write memory.
[0003] FPGA chips usually have a large amount of RAM resources, and the chip can be plugged into various storage devices, making the movement of video images simple. As the number of video image processing functions increases, the demand for resources is increasing. At the same time, devices are also pursuing multi-functions and low costs, resulting in increasingly tight chip resources. In particular, when some devices do not have external memory, they also need to meet the needs of video movement in all directions, making it impossible for conventional methods to achieve the functional requirements of video image movement. Summary of the invention
[0004] In view of this, the purpose of the present invention is to provide a method and system for moving video images based on FPGA, which can realize the video moving function in the FPGA real-time video system without large storage hardware, and the method does not increase the consumption of FPGA resources due to the large amount of movement. The overall hardware cost is reduced, resource consumption is saved, and the movement of video with arbitrary displacement is realized.
[0005] In order to achieve the above object, the present invention provides the following technical solutions:
[0006] A video image moving system based on FPGA, comprising:
[0007] The video input module is used to collect video image data. The FPGA decodes the video image data into a frame synchronization signal FVAL, a line synchronization signal LVAL and a video data signal DATA;
[0008] The motion parameter receiving module is used to analyze the video image motion parameters. The motion parameters are divided into two directions, including the vertical motion position line number h and the horizontal motion position pixel w;
[0009] A trigger module, used to generate a reference signal for a new frame line synchronization signal of a video;
[0010] The video image reconstruction module generates a new frame synchronization signal FVALS and a line synchronization signal LVALS from the movement parameters and the trigger signal, matches the new frame and line synchronization signal with the video input signal for frame and line synchronization, and outputs the reconstructed video image data;
[0011] The video output module is used to output the reconstructed video image data.
[0012] Furthermore, in the video input module, the collected video image data is image frame sequence data after the FPGA converts the serial data output by the sensor into parallel data, or is the video output by other modules.
[0013] Furthermore, the movement parameters include external command configuration, parameter configuration read from the internal memory, default parameters, and the like.
[0014] Furthermore, the reference signal includes an external synchronization signal, a frame signal or a periodic signal, etc.
[0015] Furthermore, in the video image reconstruction module, the frame-row synchronization start time is used by the FPGA to generate a new frame-row synchronization signal and count; the matching of the frame-row synchronization includes the matching of the frame signal, the row signal and the image data.
[0016] Furthermore, in the video image reconstruction module, the specific steps of video reconstruction are:
[0017] (1) Counting the frame line synchronization start time T according to the trigger signal, the movement parameter and the frame line synchronization signal;
[0018] T=T1+T2+T3+alf0
[0019] Among them, T1, T2 and T3 are all clock counts under the same clock source, and T1 represents the time interval count from the trigger signal to the next occurrence of input video frame synchronization;
[0020] T2 represents the delay clock count in the vertical direction:
[0021] T2=h*w_max*alf1
[0022] Among them, h represents the pixels moving up and down, w_max represents the count from the beginning to the end of a line, when the image moves up, alf1 is a positive number 1, when it moves down, alf1 is a negative number -1;
[0023] T3 represents the delay clock count in the horizontal direction:
[0024] T3=w*alf2
[0025] Among them, w represents the left and right movement of pixels. When the image moves to the left, alf2 is a positive number 1, and when the image moves to the right, alf2 is a negative number -1;
[0026] alf0, alf1, and alf2 represent the stable time of the clock. If the trigger signal and the frame line synchronization signal have a stable time relationship, alf0 is 0. Otherwise, the frame line synchronization signal of the trigger signal has an unstable time relationship, and the data buffering needs to be stabilized through RAM or FIFO memory.
[0027] (2) After the trigger signal is generated, after time T, the frame synchronization signal FVALS and the line synchronization signal LVALS of a frame of image are generated again according to the demand;
[0028] (3) Matching of image data and frame line synchronization signal.
[0029] The beneficial effect of the present invention is that the present invention utilizes the idea of matching the original image with the target image to effectively solve the FPGA's reliance on large storage devices to achieve video image movement, that is, the system of the present invention can achieve fast and efficient video movement of arbitrary displacement without the need for additional memory in the FPGA, thereby greatly reducing the consumption of FPGA resources.
[0030] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:
[0032] Figure 1 It is a structural block diagram of the video image moving system based on FPGA of the present invention;
[0033] Figure 2 It is a video reconstruction flow chart of the video image moving method based on FPGA of the present invention;
[0034] Figure 3 An example diagram of a video image moving method;
[0035] Figure 4 A system diagram of an embodiment of a method for moving a video image. DETAILED DESCRIPTION
[0036] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.
[0037] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.
[0038] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.
[0039] See also Figure 1 to Figure 4 The present invention provides a video image moving system based on FPGA, such as Figure 1 As shown, the system includes:
[0040] The video input module is used to collect video image data. The FPGA decodes the video image data into a frame synchronization signal FVAL, a line synchronization signal LVAL, and a video data signal DATA.
[0041] The movement parameter receiving module is used to receive the movement parameters. The movement parameters are divided into two directions: the vertical movement position line number h and the horizontal movement position pixel w.
[0042] The trigger module is used to generate a reference signal for a line synchronization signal of a new video frame.
[0043] The video image reconstruction module generates new frame synchronization signals FVALS and LVALS from the movement parameters and the trigger signal, matches the new synchronization signals with the video input signals, and outputs the reconstructed video data.
[0044] The video output module is used to output the reconstructed video image data.
[0045] The embodiment of the present invention provides a video reconstruction flow chart of a video image moving method, such as Figure 2 and Figure 3 As shown, the process includes:
[0046] (1) Counting the frame line synchronization start time T according to the trigger signal, the movement parameter and the frame line synchronization signal;
[0047] T=T1+T2+T3+alf0
[0048] Among them, T1, T2 and T3 are all clock counts under the same clock source, and T1 represents the time interval count from the trigger signal to the next occurrence of input video frame synchronization;
[0049] Where T2 represents the delay clock count in the vertical direction:
[0050] T2=h*w_max*alf1
[0051] Among them, h represents the pixels moving up and down, w_max represents the count from the beginning to the end of a line, when the image moves up, alf1 is a positive number 1, when it moves down, alf1 is a negative number -1;
[0052] Where T3 represents the delayed clock count in the horizontal direction:
[0053] T3=w*alf2
[0054] Among them, w represents the left and right movement of pixels. When the image moves to the left, alf2 is a positive number 1, and when the image moves to the right, alf2 is a negative number -1;
[0055] alf0, alf1, and alf2 represent the stable time of the clock. If the trigger signal and the frame synchronization signal have a stable time relationship, alf0 is 0. Otherwise, the frame synchronization signal of the trigger signal has an unstable time relationship, and the data buffering needs to be stabilized through RAM or FIFO memory.
[0056] (2) After the trigger signal is generated, after the time T, the frame synchronization signal FVALS and the line synchronization signal LVALS of a frame of image are generated again according to the demand;
[0057] (3) Matching of image data and frame line synchronization signal.
[0058] like Figure 4 FIG. 1 is a video moving example diagram of the video image moving method according to an embodiment of the present invention, wherein S301 represents an input video image frame, Figure 4Two example situations S302 and S303 are shown.
[0059] S302 indicates that the video moves w1 pixels to the right and h1 pixels downward. The matched frame-line synchronization uses FVALS and LVALS. When the frame-line signal of S302 is valid and the frame-line signal of S301 is invalid, the output data uses the default data or inputs other data. When the frame-line signals of S302 and S301 are valid at the same time, the output data uses the data of S301. When S302 is invalid and the frame-line signal of S301 is valid, the data is discarded.
[0060] S303 means the video moves w2 pixels to the left and h2 pixels upward. The matched frame line synchronization uses FVALS and LVALS. When S301 is valid and 303 is invalid, the data is discarded. When S301 and S303 frame line signals are valid at the same time, the output data uses the data of S301. When S303 is valid and S301 is invalid, the output data uses the default data or inputs other data.
[0061] The present invention also provides a system diagram of an embodiment of a video image moving method of the present invention, such as Figure 4 As shown:
[0062] Step S401, the user can set the video image movement parameters through the host computer;
[0063] Step S402, the sensor converts the optical signal into a digital signal and inputs it into the FPGA to generate video image data;
[0064] Step S403, the FPGA processing board generates a trigger signal, receives and analyzes the video movement parameters sent by the host computer, receives the video image data output by the sensor, generates frame-line synchronization of the new image, and performs frame-line matching of the image data to generate the moved video image;
[0065] Step S404: The PC displays the moved data generated by the FPGA in front of the user.
[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.
Claims
1. A video image moving system based on FPGA, characterized in that: The system includes: The video input module is used to collect video image data. The FPGA decodes the video image data into a frame synchronization signal FVAL, a line synchronization signal LVAL and a video data signal DATA; The motion parameter receiving module is used to analyze the video image motion parameters. The motion parameters are divided into two directions, including the vertical motion position line number h and the horizontal motion position pixel w; A trigger module, used to generate a reference signal for a new frame line synchronization signal of a video; The video image reconstruction module generates a new frame synchronization signal FVALS and a line synchronization signal LVALS from the movement parameters and the trigger signal, matches the new frame and line synchronization signal with the video input signal for frame and line synchronization, and outputs the reconstructed video image data; The video output module is used to output the reconstructed video image data.
2. The video image moving system according to claim 1, characterized in that: In the video input module, the collected video image data is image frame sequence data after the serial data output by the sensor is converted into parallel data by FPGA, or is the video output by other modules.
3. The video image moving system according to claim 1, characterized in that: The movement parameters include external command configuration, parameter configuration read from the internal memory and default parameters.
4. The video image moving system according to claim 1, characterized in that: The reference signal includes an external synchronization signal, a frame signal or a periodic signal.
5. The video image moving system according to claim 1, characterized in that: In the video image reconstruction module, the frame-row synchronization start time is used for FPGA to generate a new frame-row synchronization signal and count; the matching of the frame-row synchronization includes the matching of the frame signal, the row signal and the image data.
6. The video image moving system according to claim 1, characterized in that: In the video image reconstruction module, the specific steps of video reconstruction are: (1) Counting the frame line synchronization start time T according to the trigger signal, the movement parameter and the frame line synchronization signal; T=T1+T2+T3+alf0 Among them, T1, T2 and T3 are all clock counts under the same clock source, and T1 represents the time interval count from the trigger signal to the next occurrence of input video frame synchronization; T2 represents the delay clock count in the vertical direction: T2=h*w_max*alf1 Among them, h represents the pixels moving up and down, w_max represents the count from the beginning to the end of a line, when the image moves up, alf1 is a positive number 1, when it moves down, alf1 is a negative number -1; T3 represents the delay clock count in the horizontal direction: T3=w*alf2 Among them, w represents the left and right movement of pixels. When the image moves to the left, alf2 is a positive number 1, and when the image moves to the right, alf2 is a negative number -1; alf0, alf1, and alf2 represent the stable time of the clock. If the trigger signal and the frame line synchronization signal have a stable time relationship, alf0 is 0. Otherwise, the frame line synchronization signal of the trigger signal has an unstable time relationship, and the data buffering needs to be stabilized through RAM or FIFO memory. (2) After the trigger signal is generated, after time T, the frame synchronization signal FVALS and the line synchronization signal LVALS of a frame of image are generated again according to the demand; (3) Matching of image data and frame line synchronization signal.