HDMI video coding method and device based on FPGA

Abstract

The invention relates to an HDMI video coding method and device based on an FPGA, and the method comprises the steps: carrying out the time sequence synchronization of a to-be-coded first video signal according to a target video time sequence, and obtaining a second video signal; according to a minimum differential transmission signal algorithm, encoding the second video signal to obtain first data of three channels; performing bit width conversion processing on the first data of the three channels to obtain second data of the three channels; the second data of the three channels and a preset clock constant are input into the high-speed transceiver for parallel-to-serial processing, HDMI video signals corresponding to the first video signals are output, and the HDMI video signals comprise data signals of the three channels and clock signals of one channel. The HDMI video coding method based on the FPGA provided by the embodiment of the invention not only supports high resolution, but also is convenient to implement, so that the resource occupancy rate and the power consumption of the FPGA can be effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of aviation display technology, and in particular to an HDMI video encoding method and device based on FPGA. Background Art

[0002] At present, most display interfaces in aviation display systems are HDMI (High Definition Multimedia Interface) interfaces, which are mainly implemented through dedicated integrated HDMI video encoders. In related technologies, in order to save hardware design costs, HDMI video encoding is performed through FPGA (Field Programmable Gate Array).

[0003] There are two main traditional ways of encoding HDMI videos through FPGA. One is suitable for HDMI video encoding with a resolution of 1080P. It first implements TMDS (Transmission Minimized Differential Signing) encoding through the internal logic of the FPGA, and then performs parallel-to-serial conversion and output through the OSerdes of the common I / O (Input / Output) pins. This method supports HDMI video encoding with a maximum resolution of 1080P, but is not suitable for HDMI video encoding with a resolution greater than 1080P.

[0004] Another way is to use the HDMI transmission related IP core (Intellectual Property core, intellectual property core) provided by the FPGA manufacturer to encode the HDMI video. However, this method requires the IP core to be configured, which is not only relatively complex in configuration logic, but also occupies more FPGA resources and consumes more power when implementing the function. Summary of the invention

[0005] In view of this, a HDMI video encoding method and device based on FPGA are proposed.

[0006] In a first aspect, an embodiment of the present application provides an FPGA-based HDMI video encoding method, the method comprising: performing timing synchronization on a first video signal to be encoded according to a target video timing to obtain a second video signal, the target video timing being a video timing with the same resolution as the first video signal generated by the FPGA according to a target clock, the target clock being a user clock with the same frequency as the first video signal output by a high-speed transceiver; encoding the second video signal according to a minimized differential transmission signal algorithm to obtain three-channel first data; performing bit width conversion processing on the three-channel first data to obtain three-channel second data, the first data having a bit width of 10 bits and the second data having a bit width of 20 bits; inputting the three-channel second data and a preset clock constant into the high-speed transceiver for parallel-to-serial processing, and outputting an HDMI video signal corresponding to the first video signal, the HDMI video signal including three-channel data signals and one-channel clock signal.

[0007] In some possible implementations, the method of performing timing synchronization on a first video signal to be encoded according to a target video timing to obtain a second video signal includes: writing the first video signal to a preset storage area according to a data valid signal of the first video signal to be encoded; and reading data from the storage area according to the target video timing to obtain a second video signal.

[0008] In some possible implementations, the storage area includes a first frame storage area, a second frame storage area, and a third frame storage area, the first video signal includes video signals of multiple video frames, the second video signal includes video signals of multiple synchronized video frames, and the writing of the first video signal into a preset storage area according to a data valid signal of the first video signal to be encoded includes: storing the video signal of the i-th video frame into the first frame storage area, storing the video signal of the i+1-th video frame into the second frame storage area, and storing the video signal of the i+2-th video frame into the third frame storage area in sequence according to the order of the multiple video frames, wherein i is an integer and i=3j+1, and j is an integer and j≥0;

[0009] The method of reading data from the storage area according to the target video timing to obtain a second video signal includes: in the process of storing the video signal of the i+1th video frame into the second frame storage area, reading data from the first frame storage area according to the target video timing to obtain the video signal of the i+1th video frame after synchronization; in the process of storing the video signal of the i+2th video frame into the third frame storage area, reading data from the second frame storage area according to the target video timing to obtain the video signal of the i+1th video frame after synchronization; in the process of storing the video signal of the i+3th video frame into the second frame storage area, reading data from the third frame storage area according to the target video timing to obtain the video signal of the i+2th video frame after synchronization.

[0010] In some possible implementations, the method of performing timing synchronization on the first video signal to be encoded according to the target video timing to obtain the second video signal includes: writing the first video signal to be encoded into a first first-in-first-out queue; and reading data from the first first-in-first-out queue according to the target video timing to obtain the second video signal.

[0011] In some possible implementations, the first data of the three channels include the first data of the first channel, the first data of the second channel and the first data of the third channel, and the encoding of the second video signal according to the minimized differential transmission signal algorithm to obtain the first data of the three channels includes: encoding the red component data, the data valid signal and the first control signal in the second video signal according to the minimized differential transmission signal algorithm to obtain the first data of the first channel; encoding the green component data, the data valid signal and the second control signal in the second video signal according to the minimized differential transmission signal algorithm to obtain the first data of the second channel; encoding the blue component data, the data valid signal and the third control signal in the second video signal according to the minimized differential transmission signal algorithm to obtain the first data of the third channel.

[0012] In some possible implementations, the first data is parallel data with a bit width of 10 bits, and the red component data, the data valid signal and the first control signal in the second video signal are encoded according to the minimized differential transmission algorithm to obtain the first data of the first channel, including: obtaining 8-bit data from the red component data, the data valid signal and the first control signal in the second video signal, and performing an XOR operation on the 8-bit data to obtain the first 8-bit data out of 10 bits; setting the 9th bit data to 1; setting the 10th bit according to the number of 1s and 0s in the encoded parallel data; or, obtaining 8-bit data from the red component data, the data valid signal and the first control signal in the second video signal, and performing an XOR operation on the 8-bit data to obtain the first 8-bit data out of 10 bits; setting the 9th bit data to 0; and setting the 10th bit according to the number of 1s and 0s in the encoded parallel data.

[0013] In some possible implementations, the bit width conversion processing is performed on the first data of the three channels to obtain the second data of the three channels, including: for the first data of any channel, the first data is written into a second first-in-first-out queue; each time, two first data are read from the second first-in-first-out queue for bit width splicing to obtain the second data of the channel.

[0014] In some possible implementations, the second data of the three channels and a preset clock constant are input into the high-speed transceiver for parallel-to-serial processing, and an HDMI video signal corresponding to the first video data is output, including: inputting the second data of the first channel into the first channel of the high-speed transceiver, inputting the second data of the second channel into the second channel of the high-speed transceiver, inputting the second data of the third channel into the third channel of the high-speed transceiver, and synchronously inputting a preset clock constant into the fourth channel of the high-speed transceiver; and performing parallel-to-serial processing on the second data and clock constant of the three channels input by the high-speed transceiver, and outputting an HDMI video signal corresponding to the first video signal.

[0015] In a second aspect, an embodiment of the present application provides an FPGA-based HDMI video encoding device, the device comprising: a synchronization module, for performing timing synchronization on a first video signal to be encoded according to a target video timing to obtain a second video signal, wherein the target video timing is a video timing with the same resolution as the first video signal generated by the FPGA according to a target clock, and the target clock is a user clock with the same frequency as the first video signal output by a high-speed transceiver; an encoding module, for encoding the second video signal according to a minimized differential transmission signal algorithm to obtain three-channel first data; a bit width conversion module, for performing bit width conversion processing on the three-channel first data to obtain three-channel second data, wherein the bit width of the first data is 10 bits, and the bit width of the second data is 20 bits; a parallel-to-serial module, for inputting the three-channel second data and a preset clock constant into the high-speed transceiver for parallel-to-serial processing, and outputting an HDMI video signal corresponding to the first video signal, wherein the HDMI video signal includes three-channel data signals and one-channel clock signal.

[0016] The HDMI video encoding method based on FPGA in the embodiment of the present application can first synchronize the video signal to be encoded to the clock domain of the high-speed transceiver, then perform TMDS encoding on the synchronized video signal to obtain three-channel video data, then perform bit width conversion on the three-channel video data, and input the three-channel video data after bit width conversion and the preset clock constant into the high-speed transceiver, and realize the transmission of HDMI video encoding through the high-speed transceiver. This encoding method is not only easy to implement, but also can effectively reduce the resource occupancy and power consumption of FPGA.

[0017] The HDMI video encoding method based on FPGA in the embodiment of the present application can realize HDMI video encoding with a resolution of up to 4K@60Hz (the resolution can be backward compatible), so as to meet the display resolution requirements of mainstream aviation display systems and can be widely used in aviation airborne display systems. In addition, the HDMI video encoding method based on FPGA in the embodiment of the present application can also effectively improve the development efficiency of HDMI video encoding, reduce the number of integrated HDMI video encoders used, and thus reduce the power consumption and cost of the airborne cockpit display system.

[0018] These and other aspects of the present application will become more apparent from the following description of the embodiment(s). BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present application and, together with the description, serve to explain the principles of the present application.

[0020] Figure 1 A flow chart of an FPGA-based HDMI video encoding method according to an embodiment of the present application is shown.

[0021] Figure 2 A schematic diagram of an HDMI video encoding method based on FPGA according to an embodiment of the present application is shown.

[0022] Figure 3 A block diagram of an HDMI video encoding device based on FPGA according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0024] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0025] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0026] In order to solve the above technical problems, the present application provides an HDMI video encoding method based on FPGA, the method comprising: performing timing synchronization on a first video signal to be encoded according to a target video timing to obtain a second video signal, the target video timing is a video timing with the same resolution as the first video signal generated by the FPGA according to a target clock, and the target clock is a user clock with the same frequency as the first video signal output by a high-speed transceiver; encoding the second video signal according to a minimized differential transmission signal algorithm to obtain three-channel first data; performing bit width conversion processing on the three-channel first data to obtain three-channel second data, the bit width of the first data is 10 bits, and the bit width of the second data is 20 bits; inputting the three-channel second data and a preset clock constant into the high-speed transceiver for parallel-to-serial processing, and outputting an HDMI video signal corresponding to the first video signal, the HDMI video signal including three-channel data signals and one-channel clock signal.

[0027] The HDMI video encoding method based on FPGA in the embodiment of the present application can first synchronize the video signal to be encoded to the clock domain of the high-speed transceiver, then perform TMDS encoding on the synchronized video signal to obtain three-channel video data, then perform bit width conversion on the three-channel video data, and input the three-channel video data after bit width conversion and the preset clock constant into the high-speed transceiver, and realize the transmission of HDMI video encoding through the high-speed transceiver. This encoding method is not only easy to implement, but also can effectively reduce the resource occupancy and power consumption of FPGA.

[0028] The HDMI video encoding method based on FPGA in the embodiment of the present application can realize HDMI video encoding with a resolution of up to 4K@60Hz (the resolution can be backward compatible), so as to meet the display resolution requirements of mainstream aviation display systems and can be widely used in aviation airborne display systems. In addition, the HDMI video encoding method based on FPGA in the embodiment of the present application can also effectively improve the development efficiency of HDMI video encoding, reduce the number of integrated HDMI video encoders used, and thus reduce the power consumption and cost of the airborne cockpit display system.

[0029] The FPGA-based HDMI video encoding method of the embodiment of the present application can be applied to the FPGA inside the aviation display system, and the FPGA includes a high-speed transceiver, namely a GT (Gigabit Transceiver) transceiver.

[0030] Figure 1 FIG. 1 is a flow chart showing a HDMI video encoding method based on FPGA according to an embodiment of the present application. Figure 1 , the FPGA-based HDMI video encoding method comprises:

[0031] Step S11, performing timing synchronization on the first video signal to be encoded according to the target video timing to obtain a second video signal.

[0032] The first video signal to be encoded is a video signal captured by a video capture device (such as a camera, etc.). In the debugging stage of the aviation display system, the first video signal to be encoded may also be a test video signal stored locally in the FPGA. The present application does not limit the specific source of the first video signal.

[0033] The original timing of the first video signal to be encoded may not be synchronized with the video timing in the user clock domain of the high-speed transceiver. In order to improve stability, before TMDS encoding, the first video signal can be synchronized according to the target video timing to obtain the second video signal. Among them, the target video timing is the video timing with the same resolution as the first video signal generated by the FPGA according to the target clock, and the target clock is the user clock with the same frequency as the first video signal output by the high-speed transceiver. In other words, the timing before synchronization is the original timing of the first video signal, and the timing after synchronization is the target video timing.

[0034] The resolution of the second video signal is the same as that of the first video signal. For example, if the resolution of the first video signal is 2560×1024@60Hz, the resolution of the second video signal obtained after timing synchronization is also 2560×1024@60Hz. The difference between the second video signal and the first video signal is that the timing may be different.

[0035] In some possible implementations, step S11 may include: writing the first video signal to be encoded into a preset storage area according to a data valid signal of the first video signal; and reading data from the storage area according to a target video timing to obtain a second video signal.

[0036] When the first video signal is synchronized with the timing, the first video signal can be first written into a preset storage area according to the data enable signal (DE) of the first video signal to be encoded at the original timing of the first video signal. The preset storage area can be a storage area in a double data rate (DDR) memory, or a storage area in other memories, which is not limited in the present application. Then, data can be read from the storage area according to the target video timing to obtain the second video signal. In this way, the first video signal to be encoded can be synchronized to the target video timing.

[0037] In some possible implementations, the preset storage area includes a first frame storage area, a second frame storage area, and a third frame storage area, and the first video signal to be encoded includes video signals of multiple video frames. When the first video signal is time-sequentially synchronized, the video signal of the i-th video frame can be stored in the first frame storage area, the video signal of the i+1-th video frame can be stored in the second frame storage area, and the video signal of the i+2-th video frame can be stored in the third frame storage area in the order of the multiple video frames, where i is an integer and i=3j+1, and j is an integer and j≥0.

[0038] In the process of storing the video signal of the i+1th video frame into the second frame storage area, data is read from the first frame storage area according to the target video timing to obtain the video signal of the i+1th video frame after synchronization. In the process of storing the video signal of the i+2th video frame into the third frame storage area, data is read from the second frame storage area according to the target video timing to obtain the video signal of the i+1th video frame after synchronization. In the process of storing the video signal of the i+3th video frame into the first frame storage area, data is read from the third frame storage area according to the target video timing to obtain the video signal of the i+2th video frame after synchronization. Then the video signals of the synchronized multiple video frames are determined as the second video signal.

[0039] It should be noted that when writing data to the first frame storage area, the second frame storage area and the third frame storage area, the original timing of the first video signal is used, and when reading data from the first frame storage area, the second frame storage area and the third frame storage area, the target video timing is used.

[0040] In this way, the read operation of the frame storage area follows the write operation of the frame storage area, so that the read and write polling operation of the frame storage area can be realized. Specifically, the third frame storage area is read while writing the first frame storage area, and after the first frame storage area is written, the second frame storage area is written, and after the third frame storage area is read, it is determined whether the first frame storage area is written. If it is written, the first frame storage area is read, and the polling operation is continuously performed in this way.

[0041] In some possible implementations, step S11 may include: writing the first video signal to be encoded into a first first-in-first-out queue; and reading data from the first first-in-first-out queue according to a target video timing to obtain a second video signal.

[0042] When the first video signal is synchronized in time, a first FIFO (First Input First Output) can be pre-set, and the first FIFO is an asynchronous FIFO with different read and write timings. The first video signal can be written into the first FIFO according to the original timing of the first video signal, and then the data can be read from the first FIFO according to the target video timing to obtain the second video data. In this way, the first video signal can be synchronized in time based on the asynchronous FIFO queue.

[0043] Step S12: encoding the second video signal according to a differential transmission signal minimization algorithm to obtain three-channel first data.

[0044] When encoding the second video signal, the three color (red, green, blue) component data, the data valid signal DE and the control signal (such as the horizontal synchronization signal HSY, the vertical synchronization signal VSY, etc.) in the second video signal can be encoded according to the minimized differential transmission signal algorithm (TMDS algorithm) to obtain the first data of three channels. Each first data is parallel data with a bit width of 10 bits.

[0045] In some possible implementations, the first data of the three channels include the first data of the first channel, the first data of the second channel, and the first data of the third channel. The bit width of the first data of each channel is 10 bits, the first 8 bits are the pixel data in the second video signal; the 9th bit is the operation flag bit, which is 1 if the first 8 bits are obtained by XOR operation, and is 0 if the first 8 bits are obtained by XOR operation; the 10th bit is the DC balance bit.

[0046] In some possible implementations, step S12 may include: encoding the red component data, the data valid signal and the first control signal in the second video signal according to the minimized differential transmission signal algorithm to obtain the first data of the first channel; encoding the green component data, the data valid signal and the second control signal in the second video signal according to the minimized differential transmission signal algorithm to obtain the first data of the second channel; encoding the blue component data, the data valid signal and the third control signal in the second video signal according to the minimized differential transmission signal algorithm to obtain the first data of the third channel.

[0047] The red component data, data valid signal and first control signal (including horizontal synchronization signal HSY and vertical synchronization signal VSY, etc.) in the second video signal can be TMDS encoded to obtain the first data of the first channel. When performing TMDS encoding, 8-bit data can be first obtained from the red component data, data valid signal and first control signal in the second video signal. Then, an XOR operation is performed on the 8-bit data to obtain the first 8-bit data in 10 bits, and the 9th bit data is set to 1; or, an XOR operation is performed on the 8-bit data to obtain the first 8-bit data in 10 bits, and the 9th bit data is set to 0. Then, according to the number of 1s and 0s in the encoded parallel data, the 10th bit is set. If the number of 1s in the encoded parallel data is greater than the number of 0s, the 10th bit is set to 0, and if the number of 0s in the encoded parallel data is greater than the number of 1s, the 10th bit is set to 1, thereby achieving the effect of DC balance. Among them, the encoded parallel data refers to all the encoded parallel data before this TMDS encoding. It should be noted that the value setting method of the 10th bit is only exemplarily described here. Those skilled in the art may also set the value of the 10th bit in other ways, and this application does not impose any restrictions on this.

[0048] The green component data, the data valid signal and the second control signal in the second video signal can be TMDS encoded to obtain the first data of the second channel. Since the HDMI video encoding method based on FPGA in the embodiment of the present application only involves HDMI video encoding and does not involve audio encoding, the second control signal is empty and takes a value of 00 during encoding. When performing TMDS encoding, 8-bit data can be first obtained from the green component data, the data valid signal and the second control signal in the second video signal. Then, an XOR operation is performed on the 8-bit data to obtain the first 8-bit data in 10 bits, and the 9th bit data is set to 1; or, an XOR operation is performed on the 8-bit data to obtain the first 8-bit data in 10 bits, and the 9th bit data is set to 0. Then, the 10th bit is set according to the number of 1s and 0s in the encoded parallel data. If the number of 1s in the encoded parallel data is greater than the number of 0s, the 10th bit is set to 0, and if the number of 0s in the encoded parallel data is greater than the number of 1s, the 10th bit is set to 1, thereby achieving the effect of DC balance.

[0049] The blue component data, the data valid signal and the third control signal in the second video signal can be TMDS encoded to obtain the first data of the third channel. Since the HDMI video encoding method based on FPGA in the embodiment of the present application only involves HDMI video encoding and does not involve audio encoding, the third control signal is empty and takes a value of 00 when encoded. When performing TMDS encoding, 8-bit data can be first obtained from the blue component data, the data valid signal and the second control signal in the second video signal. Then, an XOR operation is performed on the 8-bit data to obtain the first 8-bit data in 10 bits, and the 9th bit data is set to 1; or, an XOR operation is performed on the 8-bit data to obtain the first 8-bit data in 10 bits, and the 9th bit data is set to 0. Then, the 10th bit is set according to the number of 1s and 0s in the encoded parallel data. If the number of 1s in the encoded parallel data is greater than the number of 0s, the 10th bit is set to 0, and if the number of 0s in the encoded parallel data is greater than the number of 1s, the 10th bit is set to 1, thereby achieving the effect of DC balance.

[0050] Step S13, performing bit width conversion processing on the first data of the three channels to obtain second data of the three channels.

[0051] Since the minimum bit width of parallel data in the high-speed transceiver is 20 bits, and the first data of each channel is parallel data with a bit width of 10 bits, it is necessary to perform bit width conversion processing on the first data of each channel. The second data of each channel can be spliced ​​as two 10-bits to obtain the second data of the corresponding channel. The second data is parallel data with a bit width of 20 bits.

[0052] In some possible implementations, step S13 may include: for the first data of any channel, writing the first data into a second first-in-first-out queue; reading two first data from the second first-in-first-out queue each time for bit width splicing to obtain the second data of the channel.

[0053] When the first data of each channel is subjected to bit width conversion processing, a second first-in-first-out queue can be pre-set, and the second first-in-first-out queue is a synchronous FIFO, and its read and write timing is the same. For the first data of any channel, the first data can be written into the second first-in-first-out queue, and then two first data are read from the second first-in-first-out queue each time for bit width splicing to obtain the second data of the channel. In this way, the first data of each channel can be subjected to bit width conversion processing based on the synchronous FIFO queue.

[0054] Step S14, inputting the second data of the three channels and the preset clock constant into the high-speed transceiver for parallel-to-serial processing, and outputting an HDMI video signal corresponding to the first video signal.

[0055] After obtaining the second data of the three channels, the second data of the three channels and the preset clock constant can be input into the high-speed transceiver for parallel-to-serial processing, and the HDMI video signal corresponding to the first video signal is obtained through the high-speed transceiver. Among them, the HDMI video signal is a four-channel signal, including three-channel data signals and one-channel clock signal.

[0056] In some possible implementations, step S14 may include: inputting the second data of the first channel into the first channel of the high-speed transceiver, inputting the second data of the second channel into the second channel of the high-speed transceiver, inputting the second data of the third channel into the third channel of the high-speed transceiver, and synchronously inputting a preset clock constant into the fourth channel of the high-speed transceiver; performing parallel-to-serial processing on the second data and clock constants of the three channels input through the high-speed transceiver, and outputting an HDMI video signal corresponding to the first video signal.

[0057] The second data of the three channels and the preset clock constant can be input into the four channels of the same GUAD of the high-speed transceiver. Specifically, the second data of the first channel can be input into the first channel of the high-speed transceiver, the second data of the second channel can be input into the second channel of the high-speed transceiver, the second data of the third channel can be input into the third channel of the high-speed transceiver, and the preset clock constant can be input into the fourth channel of the high-speed transceiver synchronously; then the second data and clock constant of the three channels input can be processed by the high-speed transceiver to convert parallel to serial, and the HDMI video signal corresponding to the first video signal can be output. Among them, the first channel, the second channel, the third channel, and the fourth channel of the high-speed transceiver are located in the same GUAD of the high-speed transceiver.

[0058] The preset clock constant is 00000111110000011111. After the high-speed transceiver parallel-to-serial processing, the clock constant corresponds to two pixel clock cycles, and is consistent with the output of the high-speed transceiver after being spliced ​​with two pixels (each pixel corresponds to 10 bits of data of each data channel) of the data channel (including the first channel, the second channel and the third channel). Therefore, the data and clock phases can be guaranteed to be consistent.

[0059] It should be noted that when setting up the high-speed transceiver, it is necessary to pay attention to setting the internal and external data bit widths to 20, the encoding mode to none, and then set the line rate (LineRate) according to the reference clock and the resolution of the first video signal. For example, assuming that the resolution of the first video signal is 2560×1024@60Hz, when setting up the high-speed transceiver, the internal and external data bit widths can be set to 20, and the encoding mode can be none. Since the reference clock corresponding to the resolution of 2560×1024@60Hz is 216MHz, the line rate (Line Rate) can be set to 2.16Gbps.

[0060] It should be noted that the FPGA-based HDMI video encoding method of the embodiment of the present application only involves HDMI video encoding and does not involve audio encoding.

[0061] Figure 2 FIG. 1 is a schematic diagram showing a HDMI video encoding method based on FPGA according to an embodiment of the present application. Figure 2 When performing HDMI video encoding based on FPGA, the first video signal 21 to be encoded can first be subjected to timing synchronization processing 41 according to the target video timing to obtain the second video signal 22, wherein the target video timing is the video timing with the same resolution as the first video signal 21 generated by the FPGA according to the target clock, and the target clock is the user clock with the same frequency as the first video signal 21 output by the high-speed transceiver.

[0062] Then, TSDM encoding 42 is performed on the second video signal 22 to obtain first data of three channels, namely, first data 231 of the first channel, first data 232 of the second channel, and first data 233 of the third channel. Then, bit width conversion processing 43 is performed on the first data of each channel to obtain second data of three channels, namely, second data 241 of the first channel, second data 242 of the second channel, and second data 243 of the third channel.

[0063] Afterwards, the second data of the three channels (the second data 241 of the first channel, the second data 242 of the second channel and the second data 243 of the third channel) and the preset clock constant 244 are input into the high-speed transceiver 44 for parallel-to-serial processing, and the HDMI video signal corresponding to the first video signal 21 is output through the high-speed transceiver 45. The HDMI video signal is a four-channel signal, including an HDMI video signal 251 of the first channel, an HDMI video signal 252 of the second channel, an HDMI video signal 253 of the third channel and an HDMI video clock signal 254.

[0064] The HDMI video encoding method based on FPGA in the embodiment of the present application can effectively save hardware design costs and reduce product power consumption; and its design process is relatively simple, which is convenient for practical engineering application development. It has been verified that the FPGA resource occupancy rate of the HDMI video encoding method based on FPGA in the embodiment of the present application is 1 / 5 of the resource occupancy rate when the IP core provided by the FPGA manufacturer is used for HDMI video encoding. It is beneficial to improve the logic timing inside the FPGA in a large-scale FPGA development system and has a wide range of application value.

[0065] Moreover, as aviation display systems (such as airborne cockpit display systems) develop towards high resolution and intelligence, HDMI video interfaces are not only used in external interfaces of airborne displays, but are also widely used in internal video interfaces of airborne displays. The FPGA-based HDMI video encoding method of the embodiment of the present application is not only relatively simple to develop, and can effectively implement HDMI video encoding or DVI video encoding, but also can effectively reduce the power consumption of single boards and products in hardware design, and effectively reduce the use cost of hardware devices by reducing the use of integrated HDMI video encoders. Therefore, the FPGA-based HDMI video encoding method of the embodiment of the present application has great application prospects in the field of aviation display systems.

[0066] It can be understood that the above-mentioned various method embodiments mentioned in this application can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, this application will not go into details. Those skilled in the art can understand that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined by its function and possible internal logic.

[0067] In addition, the present application also provides an FPGA-based HDMI video encoding device, which can be used to implement any FPGA-based HDMI video encoding method provided in the present application. The corresponding technical solutions and descriptions are referred to in the corresponding records of the method part and will not be repeated here.

[0068] Figure 3 FIG. 4 is a block diagram of an HDMI video encoding device based on FPGA according to an embodiment of the present application. Figure 3 , the FPGA-based HDMI video encoding device comprises:

[0069] A synchronization module 31 is used to perform timing synchronization on the first video signal to be encoded according to a target video timing to obtain a second video signal, wherein the target video timing is a video timing with the same resolution as the first video signal generated by the FPGA according to a target clock, and the target clock is a user clock with the same frequency as the first video signal output by a high-speed transceiver;

[0070] The encoding module 32 is used to encode the second video signal according to a minimized differential transmission signal algorithm to obtain three-channel first data;

[0071] A bit width conversion module 33 is used to perform bit width conversion processing on the first data of the three channels to obtain second data of the three channels, wherein the bit width of the first data is 10 bits, and the bit width of the second data is 20 bits;

[0072] The parallel-to-serial module 34 is used to input the second data of the three channels and the preset clock constant into the high-speed transceiver for parallel-to-serial processing, and output an HDMI video signal corresponding to the first video signal, wherein the HDMI video signal includes three-channel data signals and one-channel clock signal.

[0073] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the device, system, method and computer program product according to multiple embodiments of the present application. In this regard, each square frame in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the functions marked in the square frame can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square frames can actually be executed substantially in parallel, and they can also be executed in reverse order sometimes, depending on the functions involved.

[0074] It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented by hardware that performs the corresponding function or action (such as a circuit or ASIC (Application Specific Integrated Circuit)), or can be implemented by a combination of hardware and software, such as firmware.

[0075] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0076] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those of ordinary skill in the art without departing from the scope of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A HDMI video encoding method based on FPGA, characterized in that: The method comprises: According to the target video timing, the first video signal to be encoded is synchronized to obtain a second video signal, wherein the target video timing is a video timing with the same resolution as the first video signal generated by the FPGA according to the target clock, and the target clock is a user clock with the same frequency as the first video signal output by the high-speed transceiver; According to a minimized differential transmission signal algorithm, the second video signal is encoded to obtain three-channel first data; Performing bit width conversion processing on the first data of the three channels to obtain second data of the three channels, wherein the bit width of the first data is 10 bits, and the bit width of the second data is 20 bits; The second data of the three channels and the preset clock constant are input into the high-speed transceiver for parallel-to-serial processing, and an HDMI video signal corresponding to the first video signal is output, wherein the HDMI video signal includes three channels of data signals and one channel of clock signal.

2. The method according to claim 1, characterized in that The step of performing timing synchronization on the first video signal to be encoded according to the target video timing to obtain the second video signal comprises: Writing the first video signal to be encoded into a preset storage area according to a data valid signal of the first video signal; According to the target video timing, data is read from the storage area to obtain a second video signal.

3. The method according to claim 2, characterized in that The storage area includes a first frame storage area, a second frame storage area, and a third frame storage area, the first video signal includes video signals of multiple video frames, and the second video signal includes video signals of multiple synchronized video frames. The step of writing the first video signal to be encoded into a preset storage area according to the data valid signal of the first video signal to be encoded comprises: According to the order of the plurality of video frames, the video signal of the i-th video frame is sequentially stored in the first frame storage area, the video signal of the i+1-th video frame is stored in the second frame storage area, and the video signal of the i+2-th video frame is stored in the third frame storage area, wherein i is an integer and i=3j+1, j is an integer and j≥0; The step of reading data from the storage area according to the target video timing to obtain a second video signal comprises: In the process of storing the video signal of the i+1th video frame into the second frame storage area, data is read from the first frame storage area according to the target video timing to obtain the video signal of the i+1th video frame after synchronization; in the process of storing the video signal of the i+2th video frame into the third frame storage area, data is read from the second frame storage area according to the target video timing to obtain the video signal of the i+1th video frame after synchronization; in the process of storing the video signal of the i+3th video frame into the second frame storage area, data is read from the third frame storage area according to the target video timing to obtain the video signal of the i+2th video frame after synchronization.

4. The method according to claim 1, characterized in that The step of performing timing synchronization on the first video signal to be encoded according to the target video timing to obtain the second video signal comprises: Writing a first video signal to be encoded into a first first-in-first-out queue; According to the target video timing, data is read from the first FIFO queue to obtain a second video signal.

5. The method according to claim 1, characterized in that The first data of the three channels include the first data of the first channel, the first data of the second channel and the first data of the third channel. The step of encoding the second video signal according to the minimized differential transmission signal algorithm to obtain three-channel first data includes: According to a minimized differential transmission signal algorithm, the red component data, the data valid signal and the first control signal in the second video signal are encoded to obtain first data of the first channel; According to a minimized differential transmission signal algorithm, the green component data, the data valid signal and the second control signal in the second video signal are encoded to obtain the first data of the second channel; According to a differential transmission signal minimization algorithm, the blue component data, the data valid signal and the third control signal in the second video signal are encoded to obtain the first data of the third channel.

6. The method according to claim 5, characterized in that The first data is parallel data with a bit width of 10 bits, The method of encoding the red component data, the data valid signal and the first control signal in the second video signal according to the minimized differential transmission algorithm to obtain the first data of the first channel includes: Obtain 8 bits of data from the red component data, the data valid signal and the first control signal in the second video signal, and perform an XOR operation on the 8 bits of data to obtain the first 8 bits of data in the 10 bits; set the 9th bit of data to 1; and set the 10th bit according to the number of 1s and 0s in the encoded parallel data; or, Obtain 8 bits of data from the red component data, the data valid signal and the first control signal in the second video signal, and perform an XOR operation on the 8 bits of data to obtain the first 8 bits of data out of 10 bits; set the 9th bit of data to 0; and set the 10th bit according to the number of 1s and 0s in the encoded parallel data.

7. The method according to claim 1, characterized in that The performing bit width conversion processing on the first data of the three channels to obtain second data of the three channels includes: For first data of any channel, writing the first data into a second first-in-first-out queue; Each time, two first data are read from the second FIFO queue to perform bit width splicing to obtain the second data of the channel.

8. The method according to claim 1, characterized in that Inputting the second data of the three channels and the preset clock constant into the high-speed transceiver for parallel-to-serial processing, and outputting the HDMI video signal corresponding to the first video data, including: Input the second data of the first channel into the first channel of the high-speed transceiver, input the second data of the second channel into the second channel of the high-speed transceiver, input the second data of the third channel into the third channel of the high-speed transceiver, and synchronously input a preset clock constant into the fourth channel of the high-speed transceiver; The high-speed transceiver performs parallel-to-serial processing on the input three-channel second data and clock constant, and outputs an HDMI video signal corresponding to the first video signal.

9. An HDMI video encoding device based on FPGA, characterized in that: The device comprises: A synchronization module, used to perform timing synchronization on the first video signal to be encoded according to a target video timing to obtain a second video signal, wherein the target video timing is a video timing with the same resolution as the first video signal generated by the FPGA according to a target clock, and the target clock is a user clock with the same frequency as the first video signal output by a high-speed transceiver; An encoding module, used for encoding the second video signal according to a minimized differential transmission signal algorithm to obtain three-channel first data; A bit width conversion module, used for performing bit width conversion processing on the first data of the three channels to obtain second data of the three channels, wherein the bit width of the first data is 10 bits, and the bit width of the second data is 20 bits; The parallel-to-serial module is used to input the second data of the three channels and a preset clock constant into the high-speed transceiver for parallel-to-serial processing, and output an HDMI video signal corresponding to the first video signal, wherein the HDMI video signal includes three-channel data signals and one-channel clock signal.

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