Hidden conductor layer stacking structure and preparation method thereof

Abstract

The invention provides a hidden conductor layer stacked structure and a preparation method thereof, and the method comprises the steps: firstly preparing a first hidden conductor layer structure which comprises an inner hidden conductor layer and at least one additional layer, and forming a second hidden conductor layer structure of an outer hidden conductor layer on a double-sided copper-clad carrier plate; then the two first hidden conductor layer structures are pressed on the two opposite faces of the second hidden conductor layer structure respectively, then the detachable copper foil is peeled off from the center carrier plate, two intermediate structures are obtained, blind holes are formed in the intermediate structures, and then a full-board electroplated layer at least filling the blind holes is formed; according to the method, the blind hole is etched to remove the whole-board electroplated layer and the detachable copper foil outside the blind hole until the outer hidden conductor layer is exposed, so that the hidden conductor layer stacking structure is finally prepared, the packaging structure has more I / O interfaces for interconnection and operation in a limited area, and the requirement for gradual precision of substrate wiring design is met.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board manufacturing, and in particular to a hidden conductor layer stacking structure and a preparation method thereof. Background Art

[0002] With the vigorous development of electronic technology, electronic products are developing in the direction of high speed, high integration and high reliability. Correspondingly, higher technical requirements are put forward for packaging substrates. Embedded Trace Substrate (ETS) is an electronic product that buries the line in an insulating substrate. Due to its own process conditions, the buried line layer (hidden conductor layer) must be made by removable copper foil. Therefore, the main feature of the product after the board is removed is that one side is buried and the other side is made by conventional process. In order to adapt to the rapid development of high-performance chips, the substrate needs to arrange more lines in a limited area to realize the interconnection and operation of more I / O interfaces of the chip, which also drives the further refinement of the line. The advantage of the ETS process is that the line is buried in the substrate on the basis of the semi-additive method or the improved semi-additive method, thereby breaking through the influence of wet flash etching on the line shape, and finally ensuring the line width and realizing the refinement of the line. While realizing the refinement of the line, the requirements for process equipment are basically the same as those of the improved additive method and the additive method. However, the ETS process has inherent defects, and it is difficult to make multiple hidden conductor layers. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a hidden conductor layer stacking structure and a preparation method thereof, so as to solve the problem that it is difficult to manufacture multiple hidden conductor layers in the prior art.

[0004] To achieve the above-mentioned object and other related objects, the present invention provides a hidden conductor layer stacking structure and a preparation method thereof, the preparation method comprising:

[0005] S1, providing two first hidden conductor layer structures and a second hidden conductor layer structure; wherein the first hidden conductor layer structure comprises an inner hidden conductor layer and at least one build-up layer, wherein the inner hidden conductor layer and the outer build-up layer in the build-up layer are respectively located on two opposite sides of the first hidden conductor layer structure; a method for forming the second hidden conductor layer structure comprises: firstly providing a double-sided copper-clad carrier board, wherein the double-sided copper-clad carrier board comprises a central carrier board and two detachable copper foils located on two opposite sides of the central carrier board; then forming an outer hidden conductor layer on a side of the detachable copper foil away from the central carrier board, thereby obtaining the second hidden conductor layer structure;

[0006] S2, using a lamination method to press the two inner hidden conductor layers of the first hidden conductor layer structure onto the two outer hidden conductor layers of the second hidden conductor layer structure through a dielectric layer, thereby achieving the pressing of the second hidden conductor layer structure onto the two first hidden conductor layer structures;

[0007] S3, peeling the detachable copper foil from the central carrier to obtain two intermediate structures;

[0008] S4, forming a blind hole on the intermediate structure, wherein the blind hole penetrates the detachable copper foil, the outer hidden conductor layer and the dielectric layer to expose the surface of the inner hidden conductor layer;

[0009] S5, forming a full-plate electroplating layer that at least fills the blind hole;

[0010] S6, etching and removing the entire plate plating layer and the removable copper foil outside the blind hole until the outer hidden conductor layer is exposed.

[0011] Optionally, the hidden conductor layer stacking structure includes more than three hidden conductor layers; and a method for forming the more than three hidden conductor layers includes:

[0012] S7, replacing the first hidden conductor layer structure in step S1 with the structure obtained after step S6, the outermost hidden conductor layer of the structure replaces the inner hidden conductor layer of the first hidden conductor layer structure in step S1, and repeating steps S1 to S6;

[0013] S8, repeat step S7 until the required number of hidden conductor layers is obtained.

[0014] Optionally, the surface roughness of the detachable copper foil away from the central carrier board is less than 1 μm.

[0015] Furthermore, the method of forming the outer hidden conductor layer on a side of the detachable copper foil away from the central carrier board includes:

[0016] S11, attaching a first dry film to a side of the detachable copper foil away from the central carrier board;

[0017] S12, exposing the first dry film;

[0018] S13, performing a post-exposure baking process on the first dry film;

[0019] S14, developing the first dry film to define a pattern of the outer hidden conductor layer;

[0020] S15, forming the outer hidden conductor layer on the detachable copper foil by electroplating;

[0021] S16, removing the first dry film;

[0022] The interval time from the end of exposure in step S12 to the post-exposure baking process in step S13 is less than 30 seconds; and the spray pressure of the developer during development in step S14 is set to 0.6 bar to 1.0 bar.

[0023] Optionally, before respectively pressing the two first hidden conductor layer structures onto the two opposite surfaces of the second hidden conductor layer structure in step S2, the step also includes a step of roughening the surface of the outer hidden conductor layer away from the central carrier and the surface of the removable copper foil away from the central carrier, so that the roughness of the surface of the removable copper foil away from the central carrier is 0.2μm to 0.5μm.

[0024] Optionally, the method of forming a full-board electroplating layer that at least fills the blind hole in step S5 includes:

[0025] S51, removing the residue in the blind hole;

[0026] S52, forming an electroplating seed layer on the inner surface of the blind hole and the surface of the detachable copper foil by using a PVD process;

[0027] S53, attaching a second dry film on the surface of the outer build-up layer;

[0028] S54, forming the full-board electroplating layer on the electroplating seed layer, wherein the full-board electroplating layer at least fills the blind hole;

[0029] The method of etching and removing the entire plate plating layer and the removable copper foil outside the blind hole until the outer hidden conductor layer is exposed in step S6 includes:

[0030] S61, etching the full-board electroplating layer, the electroplating seed layer and the detachable copper foil outside the blind hole until the outer hidden conductor layer is exposed;

[0031] S62, removing the second dry film.

[0032] Optionally, the method of forming a full-board electroplating layer that at least fills the blind hole in step S5 includes:

[0033] S51, removing the residue in the blind hole;

[0034] S52, forming a first copper plating layer on the inner surface of the blind hole and the surface of the detachable copper foil away from the central carrier, and forming a second copper plating layer on the surface of the outer build-up layer;

[0035] S53, attaching a third dry film on the surface of the second copper layer;

[0036] S54, forming the full-board electroplating layer on the first copper layer, wherein the full-board electroplating layer at least fills the blind hole;

[0037] The method of etching and removing the entire plate plating layer and the removable copper foil outside the blind hole until the outer hidden conductor layer is exposed in step S6 includes:

[0038] S61, using a flash etching method to etch the material layer on the outer hidden conductor layer to a first flash etching thickness; wherein the first flash etching thickness is the sum of the thickness of the full-board electroplating layer on the outer hidden conductor layer, the thickness of the first copper layer and the thickness of the detachable copper foil minus the difference between the thickness of the second copper layer;

[0039] S62, removing the third dry film;

[0040] S63, using a flash etching method to simultaneously etch away the remaining material layer on the outer hidden conductor layer and the second copper layer.

[0041] Optionally, after step S6, the method further includes performing a solder resist treatment and / or a surface treatment on two opposite sides of the hidden conductor layer stacking structure.

[0042] Optionally, before step S2, the method further includes forming a first pressing and aligning target in the first hidden conductor layer structure, and forming a second pressing and aligning target at a corresponding position in the second hidden conductor layer structure.

[0043] Further, the method of step S2 includes:

[0044] S21, capturing the first pressing and aligning target and the second pressing and aligning target by X-ray;

[0045] S22, performing hot-melt positioning on the first pressing and aligning target and the second pressing and aligning target by an automatic hot-melt alignment machine;

[0046] S23, respectively pressing two of the first hidden conductor layer structures onto two opposite surfaces of the second hidden conductor layer structure.

[0047] Furthermore, the second pressing and aligning target is formed before the outer hidden conductor layer is formed on a side of the detachable copper foil away from the central carrier.

[0048] Furthermore, the method for forming the second pressing and aligning target includes an etching method or a laser copper burning method.

[0049] Furthermore, the method for forming the second pressing and aligning target in the second hidden conductor layer structure includes:

[0050] When the outer hidden conductor layer is formed on the side of the detachable copper foil away from the central carrier, a second pressing and alignment target pattern is simultaneously formed;

[0051] The conductive layer around the second pressing and aligning target pattern is removed to form the second pressing and aligning target.

[0052] Furthermore, an etching method or a laser copper burning method is used to remove the conductive layer around the lower portion of the second pressing and aligning target pattern.

[0053] The present invention also provides a hidden conductor layer stacking structure, which is prepared by using any of the preparation methods of the hidden conductor layer stacking structure described above, and the hidden conductor layer stacking structure includes an outer hidden conductor layer and at least one inner hidden conductor layer.

[0054] As described above, the hidden conductor layer stacking structure and preparation method of the present invention are as follows: first, a first hidden conductor layer structure including an inner hidden conductor layer and at least one added layer is prepared, and a second hidden conductor layer structure including an outer hidden conductor layer is formed on a double-sided copper-clad carrier board; the two first hidden conductor layer structures are respectively pressed onto the two opposite sides of the second hidden conductor layer structure; the removable copper foil is then peeled off from the central carrier board to obtain two intermediate structures; a blind hole is formed on the intermediate structure, which penetrates the removable copper foil, the outer hidden conductor layer and the dielectric layer to expose the surface of the inner hidden conductor layer; then, a full-board electroplating layer at least filling the blind hole is formed; and the full-board electroplating layer and the removable copper foil outside the blind hole are etched away until the outer hidden conductor layer is exposed, thereby finally preparing a hidden conductor layer stacking structure, so that the packaging structure has more I / O interfaces for interconnection and operation in a limited area, which meets the needs of increasingly sophisticated substrate wiring design. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 It is a schematic flow chart of a method for preparing a hidden conductor layer stacking structure of the present invention.

[0056] Figure 2 A schematic cross-sectional structure diagram of a first hidden conductor layer structure according to an example of the present invention is shown.

[0057] Figures 3 to 8 It is a schematic cross-sectional structure diagram of each step in the preparation process of the second hidden conductor layer structure according to an example of the present invention.

[0058] Fig. 9 It is a schematic cross-sectional structure diagram of a second hidden conductor layer structure and two first hidden conductor layer structures after being pressed together according to an example of the present invention.

[0059] Fig.10 Display as Fig. 9The pressed structure shown is peeled off to obtain a schematic diagram of the cross-sectional structure of two intermediate structures.

[0060] Fig.11 Displayed as Fig.10 Schematic diagram of the cross-sectional structure of a blind hole formed on an intermediate structure.

[0061] Figures 12 to 15 and Fig.17 Shown is a schematic structural diagram of the steps in a method of forming a full-board electroplating layer that at least fills the blind holes and etching away the full-board electroplating layer and the removable copper foil outside the blind holes until the outer hidden conductor layer is exposed according to an example of the present invention.

[0062] Fig.16 It is a schematic cross-sectional structure diagram showing a height difference between the outer hidden conductor layer and the dielectric layer of the present invention.

[0063] Figures 18 to 23 Shown is a structural schematic diagram of the steps in another example of the present invention for forming a full-board electroplating layer that at least fills the blind holes and etching away the full-board electroplating layer and the removable copper foil outside the blind holes until the outer hidden conductor layer is exposed.

[0064] Fig.24 Show as pair Fig.17 or Fig.23 Schematic diagram of the cross-sectional structure of the obtained structure with solder mask treatment and surface treatment on two opposite sides.

[0065] Fig.25 It is a schematic cross-sectional structure diagram of a first hidden conductor layer structure having a first pressing and alignment target formed thereon according to an example of the present invention.

[0066] Fig.26 A schematic cross-sectional structure diagram of a method for forming a second pressing and alignment target according to an example of the present invention is shown.

[0067] Fig. 27 Display as Fig.26 The second hidden conductor layer structure having a second pressing and aligning target is formed in the Fig.25 A schematic diagram of the cross-sectional structure of the first hidden conductor layer structure after lamination in which a first lamination alignment target is formed.

[0068] Figure 28-29 It is a schematic structural diagram showing the steps of forming a second pressing and alignment target according to another example of the present invention.

[0069] Fig.30 Display as Fig.29 The second hidden conductor layer structure having a second pressing and aligning target is formed in the Fig.25A schematic diagram of the cross-sectional structure of the first hidden conductor layer structure after lamination in which a first lamination alignment target is formed.

[0070] Fig.31 It is a schematic cross-sectional structure diagram of the hidden conductor layer stacking structure of the present invention.

[0071] Component number description

[0072] 1 Structure of the first hidden conductor layer

[0073] 10 Inner hidden conductor layer

[0074] 11 Adding layers

[0075] 110 inner layer

[0076] 111 External layer

[0077] 2. Structure of the second hidden conductor layer

[0078] 20 Center carrier

[0079] 21 Core board copper cladding

[0080] 22 Removable copper foil

[0081] 23 Outer hidden conductor layer

[0082] 24 Dielectric layer

[0083] 25 Electroplating seed layer

[0084] 26 First dry film

[0085] 27 Full board plating

[0086] 28 Solder mask

[0087] 29 Surface treatment layer

[0088] 3 Intermediate structure

[0089] 30 Second copper layer

[0090] 31 First copper layer

[0091] 32 Second dry film

[0092] 33 Third dry film

[0093] 34 Blind hole

[0094] 41 First pressing and alignment target

[0095] 42 Second pressing and positioning target

[0096] 420 Second pressing and alignment target pattern DETAILED DESCRIPTION

[0097] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0098] See also Figures 1 to 31 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0099] This embodiment provides a method for preparing a hidden conductor layer stacking structure. Figure 1 As shown, the preparation method comprises:

[0100] S1, providing two first hidden conductor layer structures and a second hidden conductor layer structure; wherein the first hidden conductor layer structure comprises an inner hidden conductor layer and at least one build-up layer, wherein the inner hidden conductor layer and the outer build-up layer in the build-up layer are respectively located on two opposite sides of the first hidden conductor layer structure; a method for forming the second hidden conductor layer structure comprises: firstly providing a double-sided copper-clad carrier board, wherein the double-sided copper-clad carrier board comprises a central carrier board and two detachable copper foils located on two opposite sides of the central carrier board; then forming an outer hidden conductor layer on a side of the detachable copper foil away from the central carrier board, thereby obtaining the second hidden conductor layer structure;

[0101] S2, using a lamination method to press the two inner hidden conductor layers of the first hidden conductor layer structure onto the two outer hidden conductor layers of the second hidden conductor layer structure through a dielectric layer, thereby achieving the pressing of the second hidden conductor layer structure onto the two first hidden conductor layer structures;

[0102] S3, peeling the detachable copper foil from the central carrier to obtain two intermediate structures;

[0103] S4, forming a blind hole on the intermediate structure, wherein the blind hole penetrates the detachable copper foil, the outer hidden conductor layer and the dielectric layer to expose the surface of the inner hidden conductor layer;

[0104] S5, forming a full-plate electroplating layer that at least fills the blind hole;

[0105] S6, etching and removing the entire plate plating layer and the removable copper foil outside the blind hole until the outer hidden conductor layer is exposed.

[0106] The preparation method of the hidden conductor layer stacking structure of the present embodiment is as follows: first, a first hidden conductor layer structure including an inner hidden conductor layer and at least one build-up layer is prepared, and a second hidden conductor layer structure including an outer hidden conductor layer is formed on a double-sided copper-clad carrier board; the two first hidden conductor layer structures are respectively pressed onto two opposite sides of the second hidden conductor layer structure; the removable copper foil is then peeled off from the central carrier board to obtain two intermediate structures; a blind hole is formed on the intermediate structure, which penetrates the removable copper foil, the outer hidden conductor layer and the dielectric layer to expose the surface of the inner hidden conductor layer; then, a full-board electroplating layer at least filling the blind hole is formed; and the full-board electroplating layer and the removable copper foil outside the blind hole are etched away until the outer hidden conductor layer is exposed, thereby finally preparing the hidden conductor layer stacking structure, so that the packaging structure has more I / O interfaces for interconnection and operation in a limited area, which meets the needs of increasingly sophisticated substrate wiring design.

[0107] The method for preparing the hidden conductor layer stacking structure of this embodiment is described in detail below with reference to the specific drawings.

[0108] like Figure 2 and Figure 8 As shown, firstly, step S1 is performed to provide two first hidden conductor layer structures 1 (such as Figure 2 As shown) and a second hidden conductor layer structure 2 (as shown Figure 8 As shown); wherein the first hidden conductor layer structure 1 includes an inner hidden conductor layer 10 and at least one build-up layer 11, the inner hidden conductor layer 10 and the outer build-up layer 111 in the build-up layer 11 are respectively located on two opposite sides of the first hidden conductor layer structure 1; the method for forming the second hidden conductor layer structure 2 includes: as Figure 3 As shown, firstly, a double-sided copper-clad carrier is provided, wherein the double-sided copper-clad carrier comprises a central carrier 20 and two detachable copper foils 22 located on opposite sides of the central carrier 20; Figure 8 As shown, an outer hidden conductor layer 23 is then formed on a side of the detachable copper foil 22 away from the central carrier 20 to obtain the second hidden conductor layer structure 2.

[0109] As a specific example, a method for preparing the first hidden conductor layer structure 1 includes:

[0110] First, a double-sided copper-clad substrate is provided, wherein the double-sided copper-clad substrate comprises a central substrate and carrier copper foils formed on two opposite sides of the central substrate;

[0111] Then, the inner hidden conductor layer 10 is formed on the surface of the carrier copper foil away from the central substrate to obtain a double-sided circuit board including a hidden conductor layer, and then the build-up layer 11 is formed on the surface of the inner hidden conductor layer 10 away from the central substrate, and the carrier copper foil is peeled off from the central substrate to obtain two of the first hidden conductor layer structures 1.

[0112] The number of layers of the build-up layer 11 may be, for example, 1 or more layers. Figure 2 As shown, this embodiment is described by taking the build-up layer 11 as two layers, specifically, the build-up layer 11 includes an inner build-up layer 110 and an outer build-up layer 111. Specifically, the build-up layer 11 can be prepared by a process such as a subtractive process (Tenting), a modified semi-additive process (mSAP) or a semi-additive process (SAP). The number of layers and the preparation process of the build-up layer 11 are not specifically limited here.

[0113] The double-sided copper-clad carrier plays a role of rigid support in the process of manufacturing the hidden conductor layer stacking structure. As an example, Figure 3 As shown, the double-sided copper-clad carrier includes the central carrier 20 and two removable copper foils 22 located on opposite sides of the central carrier 20, and a core copper clad layer 21 is provided between the removable copper foils 22 and the central carrier 20. In the subsequent board removal step, the removable copper foils 22 can be peeled off from the core copper clad layer 21.

[0114] As a specific example, Figures 5 to 7 As shown, the method of forming the outer hidden conductor layer 23 on the side of the removable copper foil 22 away from the central carrier 20 includes:

[0115] S11, attaching a first dry film 26 to a side of the detachable copper foil 22 away from the central carrier 20;

[0116] S12, exposing the first dry film 26;

[0117] S13, performing a post-exposure baking process on the first dry film 26; the baking temperature may be, for example, 100° C. to 120° C.;

[0118] S14, such as Figure 5 As shown, the first dry film 26 is developed to define the pattern of the outer hidden conductor layer 23;

[0119] S15, such as Figure 6 As shown, the outer hidden conductor layer 23 is formed on the removable copper foil 22 by electroplating;

[0120] S16, such as Figure 7 As shown, the first dry film 26 is removed.

[0121] In the existing technology, such as Figure 4 As shown, before forming the outer hidden conductor layer 23 , the surface of the removable copper foil 22 away from the central carrier 20 is generally roughened to enhance the adhesion of the subsequent dry film on the removable copper foil 22 and improve the film forming quality of the outer hidden conductor layer 23 .

[0122] However, in the subsequent step S2, when the inner hidden conductor layers 10 of the two first hidden conductor layer structures 1 are pressed together with the two outer hidden conductor layers 23 of the second hidden conductor layer structure 2 through the dielectric layer 24 by a lamination method (e.g. Fig. 9 As shown in FIG. 1 , the higher the surface roughness of the detachable copper foil 22 away from the central carrier board 20, that is, the higher the surface roughness of the detachable copper foil 22 attached to the dielectric layer 24, the more the dielectric layer 24 enters the surface of the detachable copper foil 22. When the hidden conductor layer stacking structure is subsequently manufactured, Fig.14 and Fig.15 As shown, the removable copper foil 22 needs to be etched to expose the outer hidden conductor layer 23. In an ideal state, the removable copper foil 22 can be etched away. However, since the removable copper foil 22 and the dielectric layer 24 have a lot of mutual corrosion on the bonding surface, the actual process requires more removable copper foil 22 to be etched away (it is necessary to etch away the removable copper foil 22 that has been corroded into the dielectric layer 24). Therefore, the outer hidden conductor layer 23 will be etched, resulting in a height difference between the outer hidden conductor layer 23 and the dielectric layer 24 (as shown in FIG. Fig.16 As shown in the figure, the higher the surface roughness of the removable copper foil 22 away from the central carrier 20, the more difficult it is to control the etching process, which will make the height difference between the outer hidden conductor layer 23 and the dielectric layer 24 larger, that is, the RD value (Relative Difference) is more difficult to control, affecting the welding of components.

[0123] Therefore, the RD value can be controlled by reducing the surface roughness of the removable copper foil 22 away from the central carrier 20. Figure 4 As shown, the surface roughness of the removable copper foil 22 away from the central carrier 20 is set to be less than 1 μm. The lower the surface roughness of the removable copper foil 22 away from the central carrier 20, the smaller the mutual corrosion amount at the surface where the dielectric layer 24 and the removable copper foil 22 are attached, and the smaller the required etching thickness is during the subsequent etching process, which can effectively reduce the RD value.

[0124] However, the lower the surface roughness of the removable copper foil 22 away from the central carrier 20, the weaker the bonding force between the removable copper foil 22 and the first dry film 26 in step S11. Therefore, when the outer hidden conductor layer 23 is formed on the removable copper foil 22 by electroplating in step S15, there is a risk of plating penetration, especially for fine circuits, because the bottom of the first dry film 26 has fewer contact positions with the removable copper foil 22 and is more likely to fall off.

[0125] In this regard, in this embodiment, the interval time between the end of exposure in step S12 and the post-exposure baking process in step S13 is preferably set to be less than 30 seconds, and the conveying speed between step S12 and step S13 can be set to 0.9m / min to 1.1m / min, for example. The purpose is to enhance the adhesion of the first dry film 26 by controlling the polymerization state of the first dry film 26 and reduce the non-uniformity of the first dry film 26 during the development process. In addition, the spray pressure of the developer during the development in step S14 is set to 0.6bar to 1.0bar, so as to use a lower spray pressure to ensure that the first dry film 26 is not impacted and falls off during development.

[0126] like Figure 1 and Fig. 9 As shown, step S2 is then performed, in which the inner hidden conductor layers 10 of the two first hidden conductor layer structures 1 are respectively pressed onto the two outer hidden conductor layers 23 of the second hidden conductor layer structure 2 through the dielectric layer 24 by a lamination method, so as to achieve the pressing of the second hidden conductor layer structure 2 and the two first hidden conductor layer structures 1.

[0127] As an example, Figure 8As shown, before the two first hidden conductor layer structures 1 are respectively pressed onto the two opposite surfaces of the second hidden conductor layer structure 2 in step S2, the step also includes a step of roughening the surface of the outer hidden conductor layer 23 away from the central carrier 20 and the surface of the detachable copper foil 22 away from the central carrier 20. The roughening method can be selected according to actual needs. For example, brown oxidation roughening can be used. OxideProcess, also known as brown oxidation treatment or brown anodizing treatment, is a metal surface treatment process) or a copper surface super-roughening method. In this embodiment, a low micro-etching amount roughening method is preferably used. The low micro-etching amount roughening method can be exemplarily a physical roughness plus chemical organic film treatment method, specifically, it can be treated by physical methods such as sandblasting, laser etching, mechanical polishing, etc. to increase the roughness of the surface of the removable copper foil 22 away from the central carrier 20, and then a layer of organic film is deposited on its surface by a chemical method to increase the surface viscosity, so that the roughness of the surface of the removable copper foil 22 away from the central carrier 20 is 0.2μm~0.5μm. After the treatment, the surface of the removable copper foil 22 away from the central carrier 20 is relatively flat, and the mutual bite amount of the dielectric layer 24 and the removable copper foil 22 at the surface where the dielectric layer 24 and the removable copper foil 22 are attached is small. When undergoing the subsequent etching process, the smaller the etching thickness required, the more effectively the RD value can be reduced.

[0128] like Figure 1 and Fig.10 As shown, step S3 is then performed to peel off the detachable copper foil 22 from the central carrier board 20 to obtain two intermediate structures 3.

[0129] like Fig.10 As shown, if the core copper clad layer 21 is provided between the detachable copper foil 22 and the central carrier 20 , the detachable copper foil 22 can be peeled off from the core copper clad layer 21 .

[0130] like Figure 1 and Fig.11 As shown, step S4 is then performed: forming a blind hole 34 on the intermediate structure 3 , wherein the blind hole 34 penetrates the detachable copper foil 22 , the outer hidden conductor layer 23 and the dielectric layer 24 to expose the surface of the inner hidden conductor layer 10 .

[0131] As an example, the blind hole 34 may be formed by a method including but not limited to laser drilling.

[0132] like Figure 1 and Fig.14 As shown, step S5 is then performed to form a full-board electroplating layer 27 that at least fills the blind hole 34 .

[0133] As an example, the thickness of the full-board electroplating layer 27 outside the blind hole 34 is generally 1 μm to 8 μm, which can be adjusted according to needs and is not excessively limited here.

[0134] like Figure 1 and Fig.17 As shown, step S6 is then performed to etch and remove the full-board electroplating layer 27 and the detachable copper foil 22 outside the blind hole 34 until the outer hidden conductor layer 23 is exposed.

[0135] So far, the formation Fig.17 The hidden conductor layer stacking structure is shown.

[0136] As a specific example, Figure 12 to Figure 14 As shown, the method for forming the full-plate electroplating layer 27 that at least fills the blind hole 34 in step S5 includes:

[0137] S51, removing the residue in the blind hole 34; illustratively, plasma treatment may be used to remove the residue in the blind hole 34;

[0138] S52, such as Fig.12 As shown, a PVD process is used to form an electroplating seed layer 25 on the inner surface of the blind hole 34 and the surface of the removable copper foil 22;

[0139] S53, such as Fig.13 As shown, a second dry film 32 is attached to the surface of the outer build-up layer 111; the second dry film 32 is a dry film resistant to electroplating liquid, which can protect the pattern of the outer build-up layer 111 from being damaged when the full-board electroplating layer 27 is formed by electroplating;

[0140] S54, such as Fig.14 As shown, the full-board electroplating layer 27 is formed on the electroplating seed layer 25, and the full-board electroplating layer 27 at least fills the blind hole 34;

[0141] like Fig.15 and Fig.17 As shown, the method of etching and removing the full-board electroplating layer 27 and the removable copper foil 22 outside the blind hole 34 in step S6 until the outer hidden conductor layer 23 is exposed includes:

[0142] S61, such as Fig.15 As shown, the full-board electroplating layer 27, the electroplating seed layer 25 and the removable copper foil 22 outside the blind hole 34 are etched until the outer hidden conductor layer 23 is exposed;

[0143] S62, such as Fig.17 As shown, the second dry film 32 is removed.

[0144] As another specific example, Figures 18 to 20 As shown, the method for forming the full-plate electroplating layer 27 that at least fills the blind hole 34 in step S5 includes:

[0145] S51, removing the residue in the blind hole 34; illustratively, plasma treatment may be used to remove the residue in the blind hole 34;

[0146] S52, such as Fig.18 As shown, a first copper plating layer 31 is formed on the inner surface of the blind hole 34 and the surface of the removable copper foil 22 away from the central carrier 20, and a second copper plating layer 30 is formed on the surface of the outer build-up layer 111; the thickness of the first copper plating layer 31 and the second copper plating layer 30 can be the same or different, and are generally between 0.5μm and 1.0μm.

[0147] S53, such as Fig.19 As shown, a third dry film 33 is attached to the surface of the second copper-plated layer 30; the third dry film 33 is a dry film resistant to electroplating liquid, which can protect the pattern of the second copper-plated layer 30 from being damaged when the full-board electroplating layer 27 is formed by electroplating;

[0148] S54, such as Fig. 20 As shown, the full-board electroplating layer 27 is formed on the first copper layer 31, and the full-board electroplating layer 27 at least fills the blind hole 34;

[0149] like Figure 21 to Figure 23 As shown, the method of etching and removing the full-board electroplating layer 27 and the removable copper foil 22 outside the blind hole 34 in step S6 until the outer hidden conductor layer 23 is exposed includes:

[0150] S61, such as Fig.21 As shown, the material layer on the outer hidden conductor layer 23 is etched by a flash etching method to a first flash etching thickness; wherein the first flash etching thickness is the difference between the sum of the thickness of the full-board electroplating layer 27, the thickness of the first copper layer 31 and the thickness of the removable copper foil 22 on the outer hidden conductor layer 23 and the thickness of the second copper layer 30; as an example, the sum of the thickness of the full-board electroplating layer 27, the thickness of the first copper layer 31 and the thickness of the removable copper foil 22 is A, the thickness of the second copper layer 30 is B, and the first flash etching thickness is (AB).

[0151] S62, such as Fig. 22 As shown, the third dry film 33 is removed;

[0152] S63, such as Fig.23 As shown, the flash etching method is used to continue etching the two opposite sides of the obtained structure to remove the remaining material layer on the second copper layer 30 and the outer hidden conductor layer 23.

[0153] This method can better monitor and control the quality of the etching step, timely discover and correct potential defects, and make the method of forming the full-board electroplating layer 27 and etching the full-board electroplating layer 27 more mass-producible. At the same time, through precise control of the etching thickness, the height difference between the outer hidden conductor layer 23 and the dielectric layer 24 can also be effectively reduced.

[0154] As an example, Fig.24 As shown, after step S6, the process generally further includes the step of performing solder resist treatment and / or surface treatment on two opposite sides of the hidden conductor layer stacking structure.

[0155] Specifically, Fig.24 As shown, solder resist treatment is adopted to form solder resist layers 28 on opposite sides of the hidden conductor layer stacking structure to prevent the occurrence of solder bridging short circuit, oxidation and corrosion; surface treatment is adopted to first perform micro-etching treatment on the conductor layers on opposite sides of the hidden conductor layer stacking structure and then perform anti-oxidation surface treatment to form a surface treatment layer 29 to avoid oxidation of the conductor layer surface, thereby affecting its electrical properties.

[0156] In addition, after step S6, a step of inspecting the obtained structure is generally included, for example, AOI inspection (automatic optical inspection) or LSCM inspection (laser confocal microscopy inspection) can be used to ensure that the quality of the hidden conductor layer stacking structure meets preset standards and specifications.

[0157] like Fig.17 As shown, the hidden conductor layers in the hidden conductor layer stacking structure are the inner hidden conductor layer 10 and the outer hidden conductor layer 23, that is, the hidden conductor layers in the hidden conductor layer stacking structure are two layers, that is, based on steps S1 to S6, the longitudinal stacking of one hidden conductor layer on the basic hidden conductor structure can be achieved. Based on this, when the hidden conductor layer stacking structure in practice requires longitudinal stacking of more than three hidden conductor layers, the longitudinal stacking of multiple hidden conductor layers can be achieved based on multiple cycles of steps S1 to S6. As an example, when the hidden conductor layer stacking structure includes more than three hidden conductor layers; the method for forming the more than three hidden conductor layers includes:

[0158] S7, replacing the first hidden conductor layer structure 1 described in step S1 with the structure obtained after step S6, the outermost hidden conductor layer of the structure replaces the inner hidden conductor layer 10 of the first hidden conductor layer structure described in step S1, and repeating steps S1 to S6;

[0159] S8, repeat step S7 until the required number of hidden conductor layers is obtained.

[0160] In step S2, when the second hidden conductor layer structure 2 is pressed together with the two first hidden conductor layer structures 1, how to ensure the accurate alignment of the second hidden conductor layer structure 2 and the first hidden conductor layer structure 1 during the pressing process is a major difficulty in the manufacturing process. Inaccurate alignment will directly lead to problems such as hole breakage when the blind hole 34 is formed by laser after pressing (such as Fig.11 As shown), for this, a positioning target can be made for precise positioning before pressing. Specifically, before step S2, a first pressing and positioning target 41 (as shown) can be formed in the first hidden conductor layer structure 1. Fig.25 As shown), and forming a second pressing and aligning target 42 (as shown) at a corresponding position in the second hidden conductor layer structure 2 Fig.26 or Fig.29 shown).

[0161] Among them, the plane dimensions of the first pressing alignment target 41 and the second pressing alignment target 42 can be adjusted according to the actual alignment parameters, and the number of the first pressing alignment target 41 and the second pressing alignment target 42 needs to be designed according to the size of the actual designed product, and no excessive restrictions are made here.

[0162] When the first pressing and aligning target 41 and the second pressing and aligning target 42 are set, as a preferred example, the method of step S2 includes:

[0163] S21, capturing the first pressing and aligning target 41 and the second pressing and aligning target 42 by X-rays;

[0164] S22, hot-melt positioning the first pressing and aligning target 41 and the second pressing and aligning target 42 by an automatic hot-melt alignment machine;

[0165] S23, such as Fig. 27 and Fig.30 As shown, two of the first hidden conductor layer structures 1 are pressed onto two opposite sides of the second hidden conductor layer structure 2 respectively.

[0166] As an example, Fig.25 As shown, the first pressing and aligning target 41 can be formed simultaneously when the inner hidden conductor layer 10 of the first hidden conductor layer structure 1 is formed.

[0167] As an example, Fig.26 As shown, the second pressing and aligning target 42 may be formed before the outer hidden conductor layer 23 is formed on the side of the detachable copper foil 22 away from the central carrier 20 .

[0168] As an example, the method for forming the second pressing and aligning target 42 includes etching or laser copper burning. Fig.26As shown, the conductive layer around the second pressing and aligning target 42 can be removed by etching or laser copper burning. If an automatic hot melt machine is used to hot melt the first pressing and aligning target 41 and the second pressing and aligning target 42, all conductive layers in the longitudinal direction of the second pressing and aligning target 42 except the second pressing and aligning target 42 must be removed. Fig. 27 As shown, two of the first hidden conductor layer structures 1 are pressed onto two opposite sides of the second hidden conductor layer structure 2 respectively.

[0169] As another specific example, Fig.28 and Fig.29 As shown, the method for forming the second pressing and aligning target 42 in the second hidden conductor layer structure 2 includes:

[0170] like Fig.28 As shown, when the outer hidden conductor layer 23 is formed on the side of the removable copper foil 22 away from the central carrier, a second pressing and alignment target pattern 420 is formed at the same time;

[0171] like Fig.29 As shown, the conductive layer around the lower part of the second pressing and aligning target pattern 420 is removed to form the second pressing and aligning target 42. For example, the conductive layer around the lower part of the second pressing and aligning target pattern 420 can be removed by etching or laser copper burning. If an automatic hot-melt alignment machine is used to perform hot-melt positioning on the first pressing and aligning target 41 and the second pressing and aligning target 42, all conductive layers except the second pressing and aligning target 42 in the longitudinal direction of the second pressing and aligning target 42 are also removed.

[0172] Furthermore, if Fig.30 As shown, two of the first hidden conductor layer structures 1 are pressed onto two opposite sides of the second hidden conductor layer structure 2 respectively.

[0173] This embodiment also provides a hidden conductor layer stacking structure, such as Fig.31 As shown, the hidden conductor layer stacking structure is prepared by the preparation method of the hidden conductor layer stacking structure described in the above embodiment. The hidden conductor layer stacking structure of this embodiment includes an outer hidden conductor layer 23 and at least one inner hidden conductor layer 10, so that the packaging structure has more I / O interfaces for interconnection and operation in a limited area, adapting to the demand for increasingly sophisticated substrate wiring design.

[0174] In summary, the present invention provides a hidden conductor layer stacking structure and a preparation method thereof, by first preparing a first hidden conductor layer structure including an inner hidden conductor layer and at least one added layer, and a second hidden conductor layer structure forming an outer hidden conductor layer on a double-sided copper-clad carrier, and then respectively pressing the two first hidden conductor layer structures on the opposite sides of the second hidden conductor layer structure, and then peeling the removable copper foil from the central carrier to obtain two intermediate structures, forming blind holes on the intermediate structures, which penetrate the removable copper foil, the outer hidden conductor layer and the dielectric layer to expose the surface of the inner hidden conductor layer, and then forming a full-board electroplating layer that at least fills the blind holes, and etching and removing the full-board electroplating layer and the removable copper foil outside the blind holes until the outer hidden conductor layer is exposed, thereby finally preparing a hidden conductor layer stacking structure, so that the packaging structure has more I / O interfaces for interconnection and operation in a limited area, and adapts to the requirements of the increasingly sophisticated substrate wiring design. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0175] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a hidden conductor layer stacking structure, characterized in that: The preparation method comprises: S1, providing two first hidden conductor layer structures and a second hidden conductor layer structure; wherein the first hidden conductor layer structure comprises an inner hidden conductor layer and at least one build-up layer, wherein the inner hidden conductor layer and the outer build-up layer in the build-up layer are respectively located on two opposite sides of the first hidden conductor layer structure; a method for forming the second hidden conductor layer structure comprises: firstly providing a double-sided copper-clad carrier board, wherein the double-sided copper-clad carrier board comprises a central carrier board and two detachable copper foils located on two opposite sides of the central carrier board; then forming an outer hidden conductor layer on a side of the detachable copper foil away from the central carrier board, thereby obtaining the second hidden conductor layer structure; S2, using a lamination method to press the two inner hidden conductor layers of the first hidden conductor layer structures onto the two outer hidden conductor layers of the second hidden conductor layer structure through a dielectric layer, thereby achieving the pressing of the second hidden conductor layer structure onto the two first hidden conductor layer structures; S3, peeling the detachable copper foil from the central carrier to obtain two intermediate structures; S4, forming a blind hole on the intermediate structure, wherein the blind hole penetrates the detachable copper foil, the outer hidden conductor layer and the dielectric layer to expose the surface of the inner hidden conductor layer; S5, forming a full-plate electroplating layer that at least fills the blind hole; S6, etching and removing the entire plate plating layer and the removable copper foil outside the blind hole until the outer hidden conductor layer is exposed.

2. The method for preparing a hidden conductor layer stacking structure according to claim 1, characterized in that: The hidden conductor layer stacking structure includes more than three hidden conductor layers; and the method for forming the more than three hidden conductor layers includes: S7, replacing the first hidden conductor layer structure in step S1 with the structure obtained after step S6, the outermost hidden conductor layer of the structure replaces the inner hidden conductor layer of the first hidden conductor layer structure in step S1, and repeating steps S1 to S6; S8, repeat step S7 until the required number of hidden conductor layers is obtained.

3. The method for preparing a hidden conductor layer stacking structure according to claim 1, characterized in that: The surface roughness of the detachable copper foil away from the central carrier is less than 1 μm.

4. The method for preparing a hidden conductor layer stacking structure according to claim 3, characterized in that: The method of forming the outer hidden conductor layer on a side of the detachable copper foil away from the central carrier comprises: S11, attaching a first dry film to a side of the detachable copper foil away from the central carrier board; S12, exposing the first dry film; S13, performing a post-exposure baking process on the first dry film; S14, developing the first dry film to define a pattern of the outer hidden conductor layer; S15, forming the outer hidden conductor layer on the detachable copper foil by electroplating; S16, removing the first dry film; The interval time from the end of exposure in step S12 to the post-exposure baking process in step S13 is less than 30 seconds; and the spray pressure of the developer during development in step S14 is set to 0.6 bar to 1.0 bar.

5. The method for preparing a hidden conductor layer stacking structure according to claim 1, characterized in that: Before the two first hidden conductor layer structures are respectively pressed onto the two opposite surfaces of the second hidden conductor layer structure in step S2, the step also includes a step of roughening the surface of the outer hidden conductor layer away from the central carrier and the surface of the removable copper foil away from the central carrier, so that the roughness of the surface of the removable copper foil away from the central carrier is 0.2μm to 0.5μm.

6. The method for preparing a hidden conductor layer stacking structure according to claim 1, characterized in that: The method of forming a full-plate electroplating layer that at least fills the blind hole in step S5 includes: S51, removing the residue in the blind hole; S52, forming an electroplating seed layer on the inner surface of the blind hole and the surface of the detachable copper foil by using a PVD process; S53, attaching a second dry film on the surface of the outer build-up layer; S54, forming the full-board electroplating layer on the electroplating seed layer, wherein the full-board electroplating layer at least fills the blind hole; The method of etching and removing the entire plate plating layer and the removable copper foil outside the blind hole until the outer hidden conductor layer is exposed in step S6 includes: S61, etching the full-board electroplating layer, the electroplating seed layer and the detachable copper foil outside the blind hole until the outer hidden conductor layer is exposed; S62, removing the second dry film.

7. The method for preparing a hidden conductor layer stacking structure according to claim 1, characterized in that: The method of forming a full-plate electroplating layer that at least fills the blind hole in step S5 includes: S51, removing the residue in the blind hole; S52, forming a first copper plating layer on the inner surface of the blind hole and the surface of the detachable copper foil away from the central carrier, and forming a second copper plating layer on the surface of the outer build-up layer; S53, attaching a third dry film on the surface of the second copper layer; S54, forming the full-board electroplating layer on the first copper layer, wherein the full-board electroplating layer at least fills the blind hole; The method of etching and removing the entire plate plating layer and the removable copper foil outside the blind hole until the outer hidden conductor layer is exposed in step S6 includes: S61, using a flash etching method to etch the material layer on the outer hidden conductor layer to a first flash etching thickness; wherein the first flash etching thickness is the sum of the thickness of the full-board electroplating layer on the outer hidden conductor layer, the thickness of the first copper layer and the thickness of the detachable copper foil minus the difference between the thickness of the second copper layer; S62, removing the third dry film; S63, using a flash etching method to simultaneously etch away the remaining material layer on the outer hidden conductor layer and the second copper layer.

8. The method for preparing a hidden conductor layer stacking structure according to claim 1, characterized in that: After step S6, the method further includes performing solder resist treatment and / or surface treatment on two opposite sides of the hidden conductor layer stacking structure.

9. The method for preparing a hidden conductor layer stacking structure according to claim 1, characterized in that: Before step S2, the method further includes forming a first pressing and aligning target in the first hidden conductor layer structure, and forming a second pressing and aligning target at a corresponding position in the second hidden conductor layer structure.

10. The method for preparing a hidden conductor layer stacking structure according to claim 9, characterized in that: The method of step S2 includes: S21, capturing the first pressing and aligning target and the second pressing and aligning target by X-ray; S22, performing hot-melt positioning on the first pressing and aligning target and the second pressing and aligning target by an automatic hot-melt alignment machine; S23, respectively pressing two of the first hidden conductor layer structures onto two opposite surfaces of the second hidden conductor layer structure.

11. The method for preparing a hidden conductor layer stacking structure according to claim 9, characterized in that: The second pressing and aligning target is formed before the outer hidden conductor layer is formed on a side of the detachable copper foil away from the central carrier.

12. The method for preparing a hidden conductor layer stacking structure according to claim 11, characterized in that: The method of forming the second pressing and aligning target includes etching or laser copper burning.

13. The method for preparing a hidden conductor layer stacking structure according to claim 9, characterized in that: The method for forming the second pressing and aligning target in the second hidden conductor layer structure includes: When the outer hidden conductor layer is formed on the side of the detachable copper foil away from the central carrier, a second pressing and alignment target pattern is simultaneously formed; The conductive layer around the second pressing and aligning target pattern is removed to form the second pressing and aligning target.

14. The method for preparing a hidden conductor layer stacking structure according to claim 13, characterized in that: The conductive layer around the lower portion of the second pressing and aligning target pattern is removed by etching or laser copper burning.

15. A hidden conductor layer stacking structure, characterized in that: The hidden conductor layer stacking structure is prepared by the preparation method of the hidden conductor layer stacking structure as claimed in any one of claims 1 to 14, wherein the hidden conductor layer stacking structure comprises an outer hidden conductor layer and at least one inner hidden conductor layer.

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