Semiconductor device and method of manufacturing the same, storage system

Abstract

The application discloses a semiconductor device, a preparation method thereof, and a storage system. The semiconductor device comprises a first semiconductor structure comprising a first storage array and a first source structure located at one side of the first storage array along a first direction; and a second semiconductor structure comprising a second storage array and a second source structure located at one side of the second storage array along the first direction, and the first source structure and the second source structure are bonded. The preparation method comprises the following steps: forming a first semiconductor structure comprising a first storage array and a first source structure, the first source structure being located at one side of the first storage array along a first direction; forming a second semiconductor structure comprising a second storage array and a second source structure, the second source structure being located at one side of the second storage array along the first direction; and bonding the first source structure and the second source structure.

Description

Technical Field

[0001] The embodiments of this application relate to the field of semiconductor technology, and in particular to semiconductor devices and their fabrication methods and storage systems. Background Technology

[0002] As semiconductor manufacturing processes shrink feature sizes and memory device densities increase, 3D memory has emerged. To improve the storage capacity per unit area of ​​3D memory, the number of stacked layers in the 3D memory stack-up structure is constantly increasing. However, with the increase in the number of stacked layers, the aspect ratio of the vias also increases, leading to increased difficulty in processes such as etching and filling the vias, and making it difficult to control the overlay accuracy. This necessitates the introduction of more advanced equipment, resulting in a significant increase in cost.

[0003] Currently, how to increase the storage capacity per unit area of ​​3D memory without significantly increasing costs is one of the technical problems that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The semiconductor devices, their fabrication methods, and storage systems provided in this application can solve or partially solve the above-mentioned deficiencies or other deficiencies in the prior art.

[0005] The semiconductor device provided according to the first aspect of this application includes:

[0006] A first semiconductor structure includes a first memory array and a first source structure located on one side of the first memory array along a first direction; and

[0007] The second semiconductor structure includes a second memory array and a second source structure located on one side of the second memory array along the first direction, wherein the first source structure and the second source structure are bonded together.

[0008] The method for fabricating a semiconductor device according to the second aspect of this application includes:

[0009] A first semiconductor structure is formed, comprising a first memory array and a first source structure, wherein the first source structure is located on one side of the first memory array along a first direction;

[0010] A second semiconductor structure is formed, comprising a second memory array and a second source structure, wherein the second source structure is located on one side of the second memory array along the first direction; and

[0011] The first source structure and the second source structure are bonded together.

[0012] According to the storage system provided in the third aspect of this application, the storage system includes a controller and the semiconductor device described above, the controller being coupled to the semiconductor device and used to control the semiconductor device to store data.

[0013] The semiconductor device provided in this application connects the first source structure of a first semiconductor structure with the second source structure of a second semiconductor structure by bonding them together. In other words, by achieving a common source connection between the first and second semiconductor structures, not only can the number of stacked layers of the entire semiconductor device be increased, thereby improving the storage capacity per unit area, but the bonding of the first and second semiconductor structures allows for independent fabrication processes. Since the number of stacked layers for each of the first and second semiconductor structures is relatively small compared to the entire semiconductor device, the individual fabrication processes for the first and second semiconductor structures are less complex. While ensuring overlay accuracy, the first and second semiconductor structures can be fabricated using existing equipment without the need for more advanced equipment. Furthermore, bonding the first and second semiconductor structures also achieves stress balance between the individual semiconductor structures.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0015] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of the application. In the drawings:

[0016] Figures 1 to 14 These are schematic diagrams illustrating a method for fabricating a semiconductor device according to one embodiment of this application.

[0017] Figure 15 This is a partial schematic diagram of a first source structure (second source structure) according to one embodiment of this application;

[0018] Figure 16 This is a schematic flowchart of a method for fabricating a semiconductor device according to one embodiment of this application;

[0019] Figure 17 This is a block diagram of a system having semiconductor devices according to one embodiment of this application;

[0020] Figure 18 This is a schematic diagram of a memory card having semiconductor devices according to one embodiment of this application; and

[0021] Figure 19 This is a schematic diagram of a solid-state driver with semiconductor devices according to one embodiment of this application.

[0022] Figure label:

[0023] 100. First semiconductor structure; 200. Second semiconductor structure;

[0024] 301. First memory array; 302. Second memory array; 310. Channel structure;

[0025] 311. Functional layer; 312. Channel layer; 313. Channel dielectric layer;

[0026] 320. First contact structure; 330. Second contact structure; 331. Contact conductive layer;

[0027] 332. Contact dielectric layer; 340. Third contact structure; 350. Fourth contact structure;

[0028] 400, First source layer; 410, First bonding layer; 411, First bonding contact;

[0029] 412. First conductive barrier layer; 413. First insulating layer; 414. First dielectric barrier layer;

[0030] 500, First interconnect layer; 510, First substrate; 610, First conductive structure;

[0031] 611. First connecting portion; 612. First conductive protrusion; 620. Second conductive structure;

[0032] 621. Second connecting part; 622. Second conductive protrusion; 630. Insulating part;

[0033] 700. Second source layer; 710. Second bonding layer; 711. Second bonding contact;

[0034] 712. Second conductive barrier layer; 713. Second insulating layer; 714. Second dielectric barrier layer;

[0035] 801, Third semiconductor structure; 802, Fourth semiconductor structure; 810, Second interconnect layer;

[0036] 820, Second substrate; 830, Trench isolation structure; 840, Source; 850, Drain;

[0037] 860, Channel; 871, Gate dielectric layer; 872, Gate conductive layer; 880, Well region;

[0038] 890. Fifth contact structure; 900. System; 901. Memory system;

[0039] 902. Semiconductor device; 903. Memory controller; 904. Main unit;

[0040] 910. Memory card; 911. Memory card connector; 920. SSD;

[0041] 921. SSD connector. Detailed Implementation

[0042] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0044] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0045] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0046] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0047] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0048] Furthermore, in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a range smaller than that of the structure below or above. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. Furthermore, in this application, the use of "connection" or "joint" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context.

[0049] To increase the storage capacity per unit area of ​​3D memory, multiple-deck technology is typically used to fabricate it. However, as the number of stacked layers increases, the aspect ratio of the vias also increases, leading to greater difficulty in processes such as etching and filling the vias, and making it harder to control the overlay accuracy. Taking a stacked structure comprising N sub-stacked structures as an example, the fabrication method of a three-dimensional memory includes: stacking a first sub-stacked structure on one side of a substrate; forming M first sub-channel holes that penetrate the first sub-stacked structure and extend into the substrate in the first sub-stacked structure; filling the first sub-channel holes with sacrificial material; forming a second sub-stacked structure on the side of the first sub-stacked structure away from the substrate; forming M second sub-channel holes that penetrate the second sub-stacked structure and correspond one-to-one with the first sub-channel holes in the second sub-stacked structure; filling the second sub-channel holes with sacrificial material; continuing to form subsequent sub-stacked structures and sub-channel holes in the same manner until an Nth sub-stacked structure and M Nth sub-channel holes penetrating the Nth sub-stacked structure are formed; removing the sacrificial material filled in the remaining sub-channel holes based on the Nth sub-channel holes, such that the vertically adjacent sub-channel holes in the N sub-stacked structures are at least partially aligned with each other to obtain M channel holes; and sequentially forming a functional layer, a channel layer, and a channel dielectric layer in the channel holes to form a channel structure, wherein the functional layer may include an ONO structure. In the above steps, the deposition process of the sub-stack structure involves heat treatment. As the number of sub-stack structures increases, heat treatment can cause the previously formed sub-stack structures to bend, affecting the overlay accuracy (OVL) of the subsequent sub-channel via overlay process, thus increasing the alignment error between adjacent sub-channel vias. Furthermore, to achieve the connection between the functional layers of each channel structure and the subsequently formed source layer, subsequent processes require the removal of the substrate and part of the ONO structure of the channel structure to expose part of the channel layer. However, reduced overlay accuracy of the sub-channel vias may lead to over-etching or leakage during the removal of the substrate and part of the ONO structure. Currently, the common approach is to introduce more advanced equipment to improve overlay accuracy and thus solve these problems, but this significantly increases costs.

[0050] To address at least some of the aforementioned problems, this application provides a semiconductor device. Figures 12 to 15 The diagram illustrates the structure of a semiconductor device according to different embodiments of this application. The semiconductor device includes a first semiconductor structure 100 and a second semiconductor structure 200. The first semiconductor structure 100 includes a first memory array 301 and a first source structure located on one side of the first memory array 301 along a first direction (z-direction). The second semiconductor structure 200 includes a second memory array 302 and a second source structure located on one side of the second memory array 302 along the first direction (z-direction). The first source structure and the second source structure are bonded together.

[0051] This application's embodiments bond the first source structure of the first semiconductor structure 100 to the second source structure of the second semiconductor structure 200. In other words, by achieving a common source connection between the first semiconductor structure 100 and the second semiconductor structure 200, not only can the number of stacked layers of the entire semiconductor device be increased, thereby improving the storage capacity per unit area of ​​the entire semiconductor device, but also the bonding of the first semiconductor structure 100 and the second semiconductor structure 200 allows for independent fabrication processes. Compared to the entire semiconductor device, the number of stacked layers for each of the first semiconductor structure 100 and the second semiconductor structure 200 is relatively small, resulting in lower fabrication difficulty for each. While ensuring overlay accuracy, the first semiconductor structure 100 and the second semiconductor structure 200 can be fabricated using existing equipment without the need for more advanced equipment. Furthermore, bonding the first semiconductor structure 100 and the second semiconductor structure 200 also achieves stress balance between the various semiconductor structures.

[0052] It should be noted that the first source structure and the second source structure in the embodiments of this application can be completely identical or different. The first source structure may include a first source layer 400, and the second source structure may include a second source layer 700. The first source layer 400 and the second source layer 700 can be directly bonded or bonded based on a bonding layer. If the first source layer 400 and the second source layer 700 are directly bonded, then both the first and second source structures are single-layer structures; if the first source layer 400 and the second source layer 700 are bonded based on a bonding layer, then the first source structure and / or the second source structure are multilayer structures. Compared with other methods, direct bonding can allow the first semiconductor structure 100 and the second semiconductor structure 200 to have lower deformation, smaller connection spacing, and less residual stress.

[0053] As an example, such as Figure 5 and Figure 7 As shown, the first source structure includes a first source layer 400 and a first bonding layer 410, with a first bonding contact 411 disposed within the first bonding layer 410. The second source structure includes a second source layer 700 and a second bonding layer 710, with a second bonding contact 711 disposed within the second bonding layer 710. The first bonding layer 410 and the second bonding layer 710 are in contact, as are the first bonding contact 411 and the second bonding contact 711. The materials of the first source layer 400 and the second source layer 700 may include, but are not limited to, polycrystalline silicon. The materials of the first bonding contact 411 and the second bonding contact 711 may include, but are not limited to, at least one of tungsten, cobalt, copper, aluminum, and silicides. The first bonding layer 410 and the second bonding layer 710 may be a single-layer structure or a multi-layer structure; they may be the same or different, and this application does not limit their specific structures.

[0054] For example, such as Figure 5 As shown, when the first bonding contact 411 is a metal contact such as a copper contact, in order to prevent the metal particles of the first bonding contact 411 from diffusing into the first source layer 400, the first bonding layer 410 may include a first conductive barrier layer 412 and a first insulating layer 413. The first conductive barrier layer 412 is located on the side of the first source layer 400 away from the first memory array 301, and the first insulating layer 413 is located on the side of the first conductive barrier layer 412 away from the first source layer 400. In other words, the first conductive barrier layer 412 is located between the first source layer 400 and the first insulating layer 413. The first bonding contact 411 penetrates the first insulating layer 413 along the first direction (z direction) and extends into the first conductive barrier layer 412. Therefore, after the first bonding layer 410 and the second bonding layer 710 are bonded together, the first bonding surface of the first bonding layer 410 coincides with the second bonding surface of the second bonding layer 710. The first bonding surface is the surface of the first insulating layer 413 away from the first conductive barrier layer 412, and the second bonding surface is the surface of the second bonding layer 710 away from the second memory array 302. The material of the first conductive barrier layer 412 may include, but is not limited to, metal silicides and / or metals. If the first conductive barrier layer 412 includes a metallic material, then that metallic material is different from the metallic material of the first bonding contact 411.

[0055] For example, when the first bonding contact 411 is a metal contact such as a copper contact, in order to prevent the metal particles of the first bonding contact 411 from diffusing at the bonding interface between the first bonding layer 410 and the second bonding layer 710, the first bonding layer 410 may include a first insulating layer 413 and a first dielectric barrier layer 414. The first insulating layer 413 is located on the side of the first source layer 400 away from the first memory array 301, and the first dielectric barrier layer 414 is located on the side of the first insulating layer 413 away from the first source layer 400. The first bonding contact 411 penetrates the first dielectric barrier layer 414 and the first insulating layer 413 along the first direction (z direction). Therefore, after the first bonding layer 410 and the second bonding layer 710 are bonded together, the first bonding surface of the first bonding layer 410 coincides with the second bonding surface of the second bonding layer 710. The first bonding surface is the surface of the first dielectric barrier layer 414 away from the first insulating layer 413, and the second bonding surface is the surface of the second bonding layer 710 away from the second memory array 302. The material of the first dielectric barrier layer 414 may include, but is not limited to, silicon nitride and / or doped silicon nitride.

[0056] For example, when the first bonding contact 411 is a metal contact such as a copper contact, in order to prevent the metal particles of the first bonding contact 411 from diffusing into the first source layer 400, and also to prevent the metal particles of the first bonding contact 411 from diffusing into the bonding interface between the first bonding layer 410 and the second bonding layer 710, the first bonding layer 410 may include a first conductive barrier layer 412, a first insulating layer 413 and a first dielectric barrier layer 414. The first conductive barrier layer 412 is located on the side of the first source layer 400 away from the first memory array 301, the first insulating layer 413 is located on the side of the first conductive barrier layer 412 away from the first source layer 400, and the first dielectric barrier layer 414 is located on the side of the first insulating layer 413 away from the first conductive barrier layer 412. In other words, the first insulating layer 413 is located between the first conductive barrier layer 412 and the first dielectric barrier layer 414. The first bonding contact 411 passes through the first dielectric barrier layer 414 and the first insulating layer 413 sequentially along the first direction (z direction) and extends into the first conductive barrier layer 412. Thus, after the first bonding layer 410 and the second bonding layer 710 are bonded together, the first bonding surface of the first bonding layer 410 coincides with the second bonding surface of the second bonding layer 710. The first bonding surface is the surface of the first dielectric barrier layer 414 away from the first insulating layer 413, and the second bonding surface is the surface of the second bonding layer 710 away from the second memory array 302.

[0057] Similarly, for example, when the second bonding contact 711 is a metal contact such as a copper contact, in order to prevent the metal particles of the second bonding contact 711 from diffusing into the second source layer 700, the second bonding layer 710 may include a second conductive barrier layer 712 and a second insulating layer 713. The second conductive barrier layer 712 is located on the side of the second source layer 700 away from the second memory array 302, and the second insulating layer 713 is located on the side of the second conductive barrier layer 712 away from the second source layer 700. In other words, the second conductive barrier layer 712 is located between the second source layer 700 and the second insulating layer 713. The second bonding contact 711 penetrates the second insulating layer 713 along the first direction (z direction) and extends into the second conductive barrier layer 712. Therefore, after the first bonding layer 410 and the second bonding layer 710 are bonded together, the first bonding surface of the first bonding layer 410 coincides with the second bonding surface of the second bonding layer 710. The first bonding surface is the surface of the first bonding layer 410 away from the first source layer 400, and the second bonding surface is the surface of the second insulating layer 713 away from the second conductive barrier layer 712. The material of the second conductive barrier layer 712 may include, but is not limited to, metal silicides and / or metals. If the second conductive barrier layer 712 includes a metallic material, then that metallic material is different from the metallic material of the second bonding contact 711.

[0058] For example, when the second bonding contact 711 is a metal contact such as a copper contact, in order to prevent the metal particles of the second bonding contact 711 from diffusing at the bonding interface between the first bonding layer 410 and the second bonding layer 710, the second bonding layer 710 may include a second insulating layer 713 and a second dielectric barrier layer 714. The second insulating layer 713 is located on the side of the second source layer 700 away from the second memory array 302, and the second dielectric barrier layer 714 is located on the side of the second insulating layer 713 away from the second source layer 700. The second bonding contact 711 penetrates the second dielectric barrier layer 714 and the second insulating layer 713 along the first direction (z direction). Therefore, after the first bonding layer 410 and the second bonding layer 710 are bonded together, the first bonding surface of the first bonding layer 410 coincides with the second bonding surface of the second bonding layer 710. The first bonding surface is the surface of the first bonding layer 410 away from the first source layer 400, and the second bonding surface is the surface of the second dielectric barrier layer 714 away from the second insulating layer 713. The material of the second dielectric barrier layer 714 may include, but is not limited to, silicon nitride and / or doped silicon nitride.

[0059] For example, when the second bonding contact 711 is a metal contact such as a copper contact, in order to prevent the metal particles of the second bonding contact 711 from diffusing into the second source layer 700, and also to prevent the metal particles of the second bonding contact 711 from diffusing at the bonding interface between the first bonding layer 410 and the second bonding layer 710, the second bonding layer 710 may include a second conductive barrier layer 712, a second insulating layer 713, and a second dielectric barrier layer 714. The second conductive barrier layer 712 is located on the side of the second source layer 700 away from the second memory array 302, the second insulating layer 713 is located on the side of the second conductive barrier layer 712 away from the second source layer 700, and the second dielectric barrier layer 714 is located on the side of the second insulating layer 713 away from the second conductive barrier layer 712. In other words, the second insulating layer 713 is located between the second conductive barrier layer 712 and the second dielectric barrier layer 714. The second bonding contact 711 passes through the second dielectric barrier layer 714 and the second insulating layer 713 sequentially along the first direction and extends into the second conductive barrier layer 712. Thus, after the first bonding layer 410 and the second bonding layer 710 are bonded together, the first bonding surface of the first bonding layer 410 coincides with the second bonding surface of the second bonding layer 710. The first bonding surface is the surface of the first bonding layer 410 away from the first source layer 400, and the second bonding surface is the surface of the second dielectric barrier layer 714 away from the second insulating layer 713.

[0060] It should be noted that the various forms of the first source structure and the second source structure mentioned above can be combined arbitrarily, as long as the desired result of the technical solution disclosed in this application can be achieved, and this application does not impose any restrictions on this.

[0061] The preceding text primarily illustrated the possible structural forms of the first and second source structures when the first source layer 400 and the second source layer 700 are bonded based on a bonding layer. The following section introduces the possible structural forms of the first and second source structures when the first source layer 400 and the second source layer 700 are directly bonded.

[0062] For example, such as Figure 11 , Figure 15 As shown in (a) and 15(b), the first source structure includes a first source layer 400 and a first conductive structure 610 located within the first source layer 400. The first conductive structure 610 extends along a second direction (x-direction) perpendicular to the first direction. The first conductive structure 610 includes a first connection portion 611 extending along the second direction (x-direction) and at least one first conductive protrusion 612 connected to the first connection portion 611. The first conductive protrusion 612 is located on the side of the first connection portion 611 facing the first memory array 301, while the side of the first connection portion 611 away from the first memory array 301 is exposed on the surface of the first source layer 400. In other words, the first connection portion 611 penetrates the first source layer 400 along the first direction (z-direction) in a direction away from the first conductive protrusion 612. The first conductive protrusion 612 can be as follows: Figure 15 (a) shows a direction that penetrates the first source layer 400 away from the first connection portion 611, or as shown in the diagram. Figure 15 (b) shows that it does not penetrate the first source layer 400. Similarly, the second source structure includes a second source layer 700 and a second conductive structure 620 located within the second source layer 700. The second conductive structure 620 extends along a second direction (x direction) and includes a second connection portion 621 extending along the second direction (x direction) and at least one second conductive protrusion 622 connected to the second connection portion 621. The second conductive protrusion 622 is located on the side of the second connection portion 621 facing the second memory array 302, and the side of the second connection portion 621 away from the second memory array 302 is exposed on the surface of the second source layer 700. In other words, the second connection portion 621 penetrates the second source layer 700 along the first direction, in a direction away from the second conductive protrusion 622. The second conductive protrusion 622 can be as follows: Figure 15 (a) shows the penetration of the second source layer 700 in a direction away from the second connection portion 621, or as shown in the diagram. Figure 15(b) shows that the second source layer 700 is not penetrated. Therefore, after the first source layer 400 and the second source layer 700 are bonded together, the surface of the first source layer 400 away from the first memory array 301 and the surface of the second source layer 700 away from the second memory array 302 overlap, and the surface of the first connection portion 611 exposed on the first source layer 400 and the surface of the second connection portion 621 exposed on the second source layer 700 at least partially overlap. The materials of the first connection portion 611, the second connection portion 621, the first conductive bump 612, and the second conductive bump 622 may include, but are not limited to, at least one of tungsten, cobalt, copper, aluminum, and silicides.

[0063] For example, such as Figure 15 As shown in (c) to 15(f), the first conductive structure 610 includes a plurality of first connection portions 611 and first conductive protrusions 612 corresponding to the first connection portions 611. The plurality of first connection portions 611 are spaced apart along a second direction (x direction) within the first source layer 400. The side of the first connection portion 611 away from the first memory array 301 is exposed on the surface of the first source layer 400. At least one first conductive protrusion 612 is provided on the side of the first connection portion 611 facing the first memory array 301. The first conductive protrusion 612 can be as follows: Figure 15 (c) As shown, it can penetrate the first source layer 400 in a direction away from the first connection portion 611, or as shown in the diagram. Figure 15 (d) shows that it does not penetrate the first source layer 400. Furthermore, as shown... Figure 15 (e) and Figure 15 As shown in (f), an insulating portion 630 may also be provided between two adjacent first connection portions 611. Similarly, the second conductive structure 620 includes second connection portions 621 corresponding to the first connection portions 611 and second conductive protrusions 622 corresponding to the second connection portions 621. Multiple second connection portions 621 are spaced apart along the second direction (x direction). The side of the second connection portion 621 away from the second memory array 302 is exposed on the surface of the second source layer 700. At least one second conductive protrusion 622 is provided on the side of the second connection portion 621 facing the second memory array 302. The second conductive protrusion 622 can be as follows: Figure 15 (c) shows the penetration of the second source layer 700 in a direction away from the second connection portion 621, or as shown in the diagram. Figure 15 (d) shows that it does not penetrate the second source layer 700. Furthermore, as shown... Figure 15 (e) and Figure 15As shown in (f), an insulating portion 630 may also be provided between two adjacent second connection portions 621. Thus, after the first source layer 400 and the second source layer 700 are bonded together, the surface of the first source layer 400 away from the first memory array 301 and the surface of the second source layer 700 away from the second memory array 302 overlap, and the surface of the first connection portion 611 exposed on the first source layer 400 at least partially overlaps with the surface of the corresponding second connection portion 621 exposed on the second source layer 700. By providing a plurality of first connection portions 611 spaced apart along a second direction (x-direction) in the first source layer 400 and correspondingly providing a plurality of second connection portions 621 in the second source layer 700, the internal stress of the first source structure and the second source structure can be reduced. Furthermore, since the stress generated by insulating materials is negative and the stress generated by metal materials is positive, when the first connecting part 611 and the second connecting part 621 are metal structures, the insulation part 630 can be provided between two adjacent first connecting parts 611 and between two adjacent second connecting parts 621 to achieve stress balance.

[0064] In some embodiments, such as Figure 5 As shown, a third semiconductor structure 801 is disposed on the side of the first memory array 301 away from the first source structure. The third semiconductor structure 801 includes a first peripheral circuit connected to the first memory array 301. As an example, such as... Figure 4 and Figure 5 As shown, the first memory array 301 includes a first contact structure 320, one end of which is connected to a first source structure, and the other end is connected to a first peripheral circuit. In this embodiment, by bonding the first source structure of the first semiconductor structure 100 to the second source structure of the second semiconductor structure 200, the first semiconductor structure 100 and the second semiconductor structure 200 can share the first peripheral circuit through the first contact structure 320.

[0065] In some embodiments, a fourth semiconductor structure 802 is disposed on the side of the second memory array 302 away from the second source structure. The fourth semiconductor structure 802 includes a second peripheral circuit connected to the second memory array 302. As an example, the second memory array 302 includes a second contact structure 330, one end of which is connected to the second source structure, and the other end of which is connected to the second peripheral circuit. In this embodiment, by bonding the first source structure of the first semiconductor structure 100 to the second source structure of the second semiconductor structure 200, the first semiconductor structure 100 and the second semiconductor structure 200 can share the second peripheral circuit through the second contact structure 330.

[0066] The first peripheral circuit and the second peripheral circuit may include, but are not limited to, at least one of high-voltage devices, low-voltage devices, and ultra-low-voltage devices. The high-voltage devices may include, but are not limited to, at least one of row decoders, column decoders, word line drivers, and bit line drivers; the low-voltage devices may include, but are not limited to, page buffers or logic devices; and the ultra-low-voltage devices may include, but are not limited to, I / O circuits. High-voltage devices typically operate at voltages greater than 3.3V, for example, 5V to 30V. For example, the operating voltage of a high-voltage device could be 5V, 10V, 15V, 20V, 25V, or 30V. Low-voltage devices typically operate at voltages between 1.3V and 3.3V. For example, the operating voltage of a low-voltage device could be 1.3V, 1.8V, 2.3V, 2.8V, or 3.3V. Ultra-low-voltage devices typically operate at voltages lower than 1.3V, for example, 0.9V to 1.2V. For example, the operating voltage of an ultra-low-voltage device could be 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V, or 1.2V. It should be noted that the operating voltage of a high-voltage, low-voltage, or ultra-low-voltage device can also be any value between any two of the above voltage values. Those skilled in the art should understand that the description of the operating voltage ranges of high-voltage, low-voltage, and ultra-low-voltage devices above is for better understanding of this solution and does not constitute a limitation of this application.

[0067] In some embodiments, the first memory array 301 and the second memory array 302 may both include a stacked structure and a channel structure 310, with the channel structure 310 penetrating the stacked structure along a first direction (z-direction). Since forming the channel structure 310 typically requires etching channel holes, and due to the characteristics of the etching process, the size of the channel hole, i.e., the aperture, gradually decreases along the etching direction during etching. Therefore, the final channel structure 310 has different dimensions at its two ends. That is, the channel structure 310 includes a first end and a second end disposed opposite each other along the first direction (z-direction). Along a direction perpendicular to the first direction (z-direction), the size of the first end of the channel structure 310 is smaller than the size of its second end. In other words, on a plane perpendicular to the first direction (z-direction), the projected area of ​​the first end of the channel structure 310 is smaller than the projected area of ​​its second end. Thus, the relative size of the two ends of the channel structure 310 can characterize the etching direction of the channel hole, i.e., the formation direction of the channel structure 310. The channel structure 310 of the first memory array 301 and the channel structure 310 of the second memory array 302 can be formed in the same or different directions.

[0068] For example, such as Figure 9 As shown, the first end of the channel structure 310 of the first memory array 301 is closer to the first source structure than its second end, and the first end of the channel structure 310 of the second memory array 302 is also closer to the first source structure than its second end. Figure 9Using the orientation shown as a reference, in order to form the aforementioned channel structure 310, the channel holes of the first memory array 301 are etched along the negative z-axis direction, i.e., from top to bottom, and the channel holes of the second memory array 302 are etched along the positive z-axis direction, i.e., from bottom to top. For example, as... Figure 10 As shown, the first end of the channel structure 310 of the first memory array 301 is farther away from the first source structure relative to its second end, and the first end of the channel structure 310 of the second memory array 302 is also farther away from the first source structure relative to its second end. Figure 10 Using the orientation shown as a reference, in order to form the aforementioned channel structure 310, when etching the channel holes, the channel holes of the first memory array 301 are etched along the positive z-axis direction, i.e., from bottom to top, and the channel holes of the second memory array 302 are etched along the negative z-axis direction, i.e., from top to bottom. It can be seen that... Figure 9 and Figure 10 The channel structure 310 of the first memory array 301 and the channel structure 310 of the second memory array 302 are formed in opposite directions.

[0069] For example, the first end of the channel structure 310 of the first memory array 301 is closer to the first source structure than its second end, while the first end of the channel structure 310 of the second memory array 302 is farther away from the first source structure than its second end. To form the aforementioned channel structure 310, the channel holes of the first memory array 301 are etched along the negative z-axis direction, i.e., from top to bottom, and the channel holes of the second memory array 302 are etched along the negative z-axis direction, i.e., from top to bottom. Similarly, the first end of the channel structure 310 of the first memory array 301 is farther away from the first source structure than its second end, while the first end of the channel structure 310 of the second memory array 302 is closer to the first source structure than its second end. To form the aforementioned channel structure 310, the channel holes of the first memory array 301 are etched along the positive z-axis direction, i.e., from bottom to top, and the channel holes of the second memory array 302 are etched along the positive z-axis direction, i.e., from bottom to top. As can be seen, in the above situation, the channel structure 310 of the first memory array 301 and the channel structure 310 of the second memory array 302 are formed in the same direction.

[0070] In some embodiments, the stacked structure may include a connection region and a core region having multiple channel structures 310 formed thereon, the connection region being located on at least one side of the core region along a second direction (x-direction). The connection region may be a stepped structure or a non-stepped structure; for example, in an SCT (Staircase Contact) architecture, the connection region does not need to be stepped. The stacked structure may include gate layers and third insulating layers alternately stacked along a first direction, the gate layers and third insulating layers may be arranged in pairs or unpaired. As an example, the stacked structure may include, but is not limited to, 64 pairs, 128 pairs, or more than 128 pairs of gate layers and third insulating layers; this application does not limit this. Figure 4 As shown, the channel structure 310 may include a functional layer 311 and a channel layer 312. The functional layer 311 may include a barrier layer, a charge trapping layer, and a tunneling layer sequentially disposed along the second direction (x direction). The material of the channel layer 312 may include, but is not limited to, semiconductor materials such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The materials of the barrier layer and the tunneling layer may be, but are not limited to, silicon oxide, and the material of the charge trapping layer may be, but is not limited to, silicon nitride. In other words, the functional layer 311 may have an ONO structure. In the embodiments of this application, both the functional layer 311 and the channel layer 312 can be formed by a thin film deposition process. The thin film deposition process may be, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination of the above processes.

[0071] In this configuration, the functional layer 311 and channel layer 312 of the channel structure 310, along with the corresponding portions of the gate layer of the stacked structure and a portion of the gate layer, together constitute a memory cell. Multiple memory cells are connected in series along the stacking direction of the stacked structure, i.e., the first direction (z-direction), to form a memory string. Memory cells located in the same row, i.e., distributed along the second direction (x-direction), can be connected to the same word line. The remaining portion of the gate layer can serve as the word line for multiple memory cells in the corresponding memory string. Each memory string, i.e., the memory cells in the same column, can be connected to the same bit line. Under the voltage control of the corresponding word line, charge carriers in the channel layer 312 of the memory cell enter the charge trapping layer of the functional layer 311, or charge carriers in the charge trapping layer of the functional layer 311 retreat back to the channel layer 312, thereby realizing the programming or erasure of the memory cell. When the first peripheral circuit and / or the second peripheral circuit includes a page buffer, a word line driver, and I / O circuitry, the page buffer is connected to the bit line to apply a bit line voltage to the bit line. The bit line voltage corresponds to the data DATA to be programmed, and the data DATA may include multiple bits of data. During a read operation, the page buffer can sense the data DATA stored in the selected memory cell via the bit line and output the sensed data DATA to the I / O circuit. The word line driver connects to the word line via word line contacts to apply a word line voltage to the word line, thereby performing an erase operation on the memory cell corresponding to that word line.

[0072] In some embodiments, such as Figure 1 As shown, the first memory array 301 includes a third contact structure 340 corresponding to its gate layer, one end of the third contact structure 340 being connected to the corresponding gate layer and the other end being connected to the first peripheral circuit; and / or, the second memory array 302 includes a fourth contact structure 350 corresponding to its gate layer, one end of the fourth contact structure 350 being connected to the corresponding gate layer and the other end being connected to the second peripheral circuit.

[0073] In addition, such as Figure 16 As shown, this application also provides a method 1000 for fabricating a semiconductor device, the method comprising:

[0074] S100: Form a first semiconductor structure 100 including a first memory array 301 and a first source structure, wherein the first source structure is located on one side of the first memory array 301 along a first direction (z direction);

[0075] S200: A second semiconductor structure 200 is formed, including a second memory array 302 and a second source structure, wherein the second source structure is located on one side of the second memory array 302 along a first direction (z direction);

[0076] S300, the first source structure and the second source structure are bonded together.

[0077] The following is a detailed description of each step in the fabrication method of the semiconductor device in the embodiments of this application.

[0078] Step S100

[0079] In step S100, a first semiconductor structure 100 is formed, which includes a first memory array 301 and a first source structure. The first source structure can be a single-layer structure or a multi-layer structure.

[0080] In some embodiments, step S100 may include: Figure 1 As shown, a first storage array 301 is formed; as Figure 4 As shown, a first source layer 400 is formed on one side of the first storage array 301; as Figure 5 As shown, a first bonding layer 410 is formed on the side of the first source layer 400 away from the first memory array 301; a first bonding contact 411 is formed on the side of the first bonding layer 410 away from the first source layer 400 and within the first bonding layer 410.

[0081] Besides the methods described above, the first semiconductor structure 100 can also be formed using other methods. For example, step S100 of forming the first semiconductor structure 100 may include: forming a first memory array 301; forming a first source layer 400 on one side of the first memory array 301; and forming a first conductive structure 610 (see [reference]) from the side of the first source layer 400 away from the first memory array 301. Figure 11 ).

[0082] As an example, the step of forming the first memory array 301 may include: forming a stacked structure (not shown) on one side of the first substrate 510, the stacked structure including a third insulating layer and a sacrificial layer alternately stacked along a first direction (z direction). The third insulating layer and the sacrificial layer may be formed on one side of the first substrate 510 by a thin film deposition process, which may be, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination of the above processes. The first substrate 510 may include, but is not limited to, single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide and other group III-V compounds. The material of the third insulating layer may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride. The material of the third insulating layer may also include high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide. The material of the sacrificial layer may include, but is not limited to, silicon oxynitride, polycrystalline silicon, or polycrystalline germanium. As an example, in this embodiment, the material of the third insulating layer is silicon oxide, and the material of the sacrificial layer is silicon nitride. A channel hole is etched along a first direction (z-direction) on the side of the stacked structure away from the first substrate 510. The channel hole penetrates the stacked structure and extends into the first substrate 510. The channel hole can be formed by a dry etching process, a combination of dry and wet etching processes, or a patterning process. The patterning process includes photolithography, cleaning, and chemical mechanical polishing. A barrier layer is formed on the inner wall of the channel hole to block charge outflow. The material of the barrier layer may include, but is not limited to, silicon oxide, silicon nitride, a high-k dielectric material, or any combination thereof. A charge trapping layer is formed on the side of the barrier layer away from the inner wall of the channel hole to store charge; wherein the material of the charge trapping layer may include, but is not limited to, silicon nitride, silicon oxynitride, silicon, or any combination thereof. A tunneling layer is formed on the side of the charge trapping layer away from the barrier layer; wherein the material of the tunneling layer may include, but is not limited to, silicon oxide or silicon nitride. A channel layer 312 is formed on the side of the tunneling layer away from the charge trapping layer to transport the required charge carriers, i.e., electrons or holes; wherein the material of the channel layer 312 may include, but is not limited to, amorphous silicon, polycrystalline silicon, or monocrystalline silicon. A dielectric material is filled within the pores formed by the channel layer 312 to form a channel dielectric layer 313; wherein the material of the channel dielectric layer 313 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, spin-coated glass, carbon-doped oxides, etc.A channel plug (not shown) is formed on the side of the channel dielectric layer 313 away from the first substrate 510, in contact with the channel layer 312. The material of the channel plug can be the same as that of the channel layer 312. Gate line slits (GLS) are etched along a first direction (z-direction) on the side of the stacked structure away from the first substrate 510. The sacrificial layer is replaced with a gate layer through the gate line slits to form a stacked structure. The material of the gate layer can be, but is not limited to, polysilicon, tungsten, aluminum, titanium, copper, cobalt, tungsten nitride, or any combination thereof.

[0083] Furthermore, the step of forming the first memory array 301 may further include: etching a first contact hole along a first direction (z-direction) on the side of the stacked structure away from the first substrate 510, wherein the first contact hole at least penetrates the stacked structure; in other words, the first contact hole may extend into the first substrate 510 or may not extend into the first substrate 510; forming a contact dielectric layer 332 on the inner wall of the first contact hole; and filling the gap formed by the contact dielectric layer 332 with conductive material to form a contact conductive layer 331. The first contact structure 320 includes the contact conductive layer 331 and the contact dielectric layer 332.

[0084] As an example, such as Figure 3 and Figure 4 As shown, the step of forming a first source layer 400 on one side of the first memory array 301 may include: removing a first substrate 510 to expose a portion of the channel structure 310 extending to the first substrate 510; wherein the first substrate 510 may be removed by dry etching and / or wet etching processes; removing the functional layer 311 of the exposed channel structure 310 to expose a portion of the channel layer 312; forming a first source layer 400 on the side of the stacked structure where the first substrate 510 has been removed; the first source layer 400 may be formed by a thin film deposition process, which may be, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination of the above processes. The portion of the channel layer 312 exposed on one side of the stacked structure contacts the first source layer 400, thereby increasing the contact area between the channel layer 312 and the first source layer 400 and reducing their contact resistance. Since the functional layer 311 and the portion of the channel layer 312 corresponding to the gate layer of the stacked structure, as well as a portion of the gate layer, together constitute a memory cell, and multiple memory cells are connected in series along the stacking direction of the stacked structure, i.e., the first direction (z direction), to form a memory string, all memory strings in the same memory block can be electrically connected to the first source layer 400.

[0085] As an example, such as Figure 5 As shown, the steps of forming the first bonding layer 410 may include: forming a first conductive barrier layer 412 on the side of the first source layer 400 away from the first memory array 301; forming a first insulating layer 413 on the side of the first conductive barrier layer 412 away from the first source layer 400; and forming a first dielectric barrier layer 414 on the side of the first insulating layer 413 away from the first conductive barrier layer 412. It should be noted that the steps of forming the first conductive barrier layer 412 and / or the first dielectric barrier layer 414 may be omitted during the formation of the first bonding layer 410; in other words, the first bonding layer 410 may not include the first conductive barrier layer 412 and / or the first dielectric barrier layer 414. When the first bonding layer 410 includes a first conductive barrier layer 412, a first insulating layer 413, and a first dielectric barrier layer 414, the step of forming the first bonding contact 411 may include: forming a first contact hole that sequentially penetrates the first dielectric barrier layer 414 and the first insulating layer 413 and extends to the first conductive barrier layer 412; and filling the first contact hole with a conductive material to form the first bonding contact 411.

[0086] As an example, the steps of forming the first conductive structure 610 may include: forming a first conductive hole extending along a first direction (z-direction) in a second region of the first source layer 400, the first conductive hole may penetrate the first source layer 400 or not; forming a first conductive trench in a first region of the first source layer 400, the depth of the first conductive trench along the first direction being less than the depth of the first conductive hole along the first direction; and filling the first conductive hole and the first conductive trench with conductive material to form the first conductive structure 610. The first region and the second region are regions of the first source layer 400 away from the surface of the first memory array 301, and the second region is located within the first region.

[0087] Step S200

[0088] In step S200, a second semiconductor structure 200 is formed, which includes a second memory array 302 and a second source structure. The second source structure can be a single-layer structure or a multi-layer structure.

[0089] In some embodiments, step S200 may include: Figure 1 As shown, a second storage array 302 is formed; as Figure 4 As shown, a second source layer 700 is formed on one side of the second memory array 302; as Figure 5 As shown, a second bonding layer 710 is formed on the side of the second source layer 700 away from the second memory array 302; a second bonding contact 711 is formed on the side of the second bonding layer 710 away from the second source layer 700 and within the second bonding layer 710.

[0090] In addition to the methods described above, the second semiconductor structure 200 can also be formed using other methods. For example, step S200 of forming the second semiconductor structure 200 may include: forming a second memory array 302; forming a second source layer 700 on one side of the second memory array 302; and forming a second conductive structure 620 on the side of the second source layer 700 away from the second memory array 302.

[0091] As an example, the step of forming the second memory array 302 may include forming a stacked structure on one side of the first substrate 510, the stacked structure including a third insulating layer and a sacrificial layer alternately stacked along a first direction (z direction). A channel via is etched along a first direction on the side of the stacked structure away from the first substrate 510. The channel via penetrates the stacked structure and extends into the first substrate 510. A barrier layer is formed on the inner wall of the channel via to block charge outflow. A charge trapping layer is formed on the side of the barrier layer opposite to the inner wall of the channel via to store charge. A tunneling layer is formed on the side of the charge trapping layer opposite to the barrier layer. A channel layer 312 is formed on the side of the tunneling layer opposite to the charge trapping layer to transport the required charge carriers, i.e., electrons or holes. A dielectric material is filled into the aperture formed by the channel layer 312 to form a channel dielectric layer 313. A channel plug (not shown) is formed on the side of the channel dielectric layer 313 away from the first substrate 510 to contact the channel layer 312. A gate line slit (GLS) is etched along the first direction on the side of the stacked structure away from the first substrate 510. The sacrificial layer is replaced with a gate layer through the gate line slit to form a stacked structure.

[0092] Furthermore, the step of forming the second memory array 302 may also include: etching a second contact hole along a first direction on the side of the stacked structure away from the first substrate 510, wherein the second contact hole at least penetrates the stacked structure; in other words, the second contact hole may extend into the first substrate 510 or may not extend into the first substrate 510; forming a contact dielectric layer 332 on the inner wall of the second contact hole; and filling the gap formed by the contact dielectric layer 332 with conductive material to form a contact conductive layer 331. The second contact structure 330 includes a contact conductive layer 331 and a contact dielectric layer 332 (see...). Figure 3 ).

[0093] As an example, the step of forming a second source layer 700 on one side of the second memory array 302 may include: removing a first substrate 510 to expose a portion of the channel structure 310 extending to the first substrate 510; wherein the first substrate 510 may be removed by dry etching and / or wet etching processes; removing the functional layer 311 of the exposed channel structure 310 to expose a portion of the channel layer 312; forming a second source layer 700 on the side of the stacked structure where the first substrate 510 has been removed; the second source layer 700 may be formed by a thin film deposition process, which may be, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination of the above processes. The portion of the channel layer 312 exposed on one side of the stacked structure contacts the second source layer 700, thereby increasing the contact area between the channel layer 312 and the second source layer 700 and reducing their contact resistance.

[0094] As an example, such as Figure 5 As shown, the steps for forming the second bonding layer 710 may include: forming a second conductive barrier layer 712 on the side of the second source layer 700 away from the second memory array 302; forming a second insulating layer 713 on the side of the second conductive barrier layer 712 away from the second source layer 700; and forming a second dielectric barrier layer 714 on the side of the second insulating layer 713 away from the second conductive barrier layer 712. It should be noted that the steps of forming the second conductive barrier layer 712 and / or the second dielectric barrier layer 714 may be omitted during the formation of the second bonding layer 710; in other words, the second bonding layer 710 may not include the second conductive barrier layer 712 and / or the second dielectric barrier layer 714. When the second bonding layer 710 includes a second conductive barrier layer 712, a second insulating layer 713, and a second dielectric barrier layer 714, the step of forming the second bonding contact 711 may include: forming a second contact hole that sequentially penetrates the second dielectric barrier layer 714 and the second insulating layer 713 and extends to the second conductive barrier layer 712; and filling the second contact hole with a conductive material to form the second bonding contact 711.

[0095] As an example, the steps of forming the second conductive structure 620 may include: forming a second conductive hole extending along a first direction in a second region of the second source layer 700, the second conductive hole may penetrate the second source layer 700 or not; forming a second conductive trench in a first region of the second source layer 700, the depth of the second conductive trench along the first direction being less than the depth of the second conductive hole along the first direction; and filling the second conductive hole and the second conductive trench with conductive material to form the second conductive structure 620. The first region and the second region are regions of the second source layer 700 away from the surface of the second memory array 302, and the second region is located within the first region.

[0096] In some embodiments, such as Figure 1 As shown, the fabrication method may further include: forming a first interconnect layer 500 on the side of the stacked structure of the first memory array 301 and / or the second memory array 302 away from the first substrate 510; forming a first interconnect structure, a second interconnect structure, and a third interconnect structure penetrating the first interconnect layer 500 along a first direction in the first interconnect layer 500. The first interconnect structure of the first semiconductor structure 100 is connected to the channel plug of its channel structure 310, the second interconnect structure is connected to the first contact structure 320, and the third interconnect structure is connected to the third contact structure 340. The first interconnect structure of the second semiconductor structure 200 is connected to the channel plug of its channel structure 310, the second interconnect structure is connected to the second contact structure 330, and the third interconnect structure is connected to the fourth contact structure 350.

[0097] Step S300

[0098] In step S300, the first source structure and the second source structure are bonded. As an example, an Xtacking bonding process can be used to bond the first source structure and the second source structure. Xtacking refers to achieving alignment bonding of the bonding structures between different devices in the same process step, thereby realizing the electrical connection between the two devices. Figure 6 and Figure 7 As shown, when the first source structure includes a first source layer 400, a first conductive barrier layer 412, a first insulating layer 413, a first dielectric barrier layer 414, and a first bonding contact 411, and the second source structure includes a second source layer 700, a second conductive barrier layer 712, a second insulating layer 713, a second dielectric barrier layer 714, and a second bonding contact 711, after the first and second source structures are bonded together, the surface of the first dielectric barrier layer 414 away from the first insulating layer 413 coincides with the surface of the second dielectric barrier layer 714 away from the second insulating layer 713, and the first bonding contact 411 contacts the corresponding second bonding contact 711. Figure 11 and Figure 12As shown, when the first source structure includes a first source layer 400 and a first conductive structure 610, and the second source structure includes a second source layer 700 and a second conductive structure 620, after the first source structure and the second source structure are bonded together, the surface of the first source layer 400 away from the first memory array 301 and the surface of the second source layer 700 away from the second memory array 302 overlap, and the first conductive structure 610 and the corresponding second conductive structure 620 are in contact.

[0099] In addition, such as Figures 2 to 9 As shown, the fabrication method may further include: forming a third semiconductor structure 801; bonding the third semiconductor structure 801 to the side of the first semiconductor structure 100 away from the second semiconductor structure 200; and / or forming a fourth semiconductor structure 802; bonding the fourth semiconductor structure 802 to the side of the second semiconductor structure 200 away from the first semiconductor structure 100.

[0100] As an example, such as Figure 2 As shown, the steps of forming the third semiconductor structure 801 may include: forming a plurality of transistors on a second substrate 820, at least a portion of which are located in the second substrate 820; forming a trench isolation structure 830 surrounding the active region of the transistors on the second substrate; forming a second interconnect layer 810 on the second substrate 820, the second interconnect layer 810 covering the side of the second substrate 820 where the transistors are formed and the side of the transistors away from the second substrate 820; forming a fourth interconnect structure and a fifth interconnect structure (not shown) penetrating the second interconnect layer 810, the end of the fourth interconnect structure near the second substrate 820 being connected to the transistors, and the ends of the fourth interconnect structure and the fifth interconnect structure away from the second substrate 820 being in contact with the first interconnect structure, the second interconnect structure, or the third interconnect structure of the first interconnect layer 500, respectively.

[0101] As an example, the step of forming a transistor on the second substrate 820 may include: forming a well region 880 in the second substrate 820; for example, if the transistor is an N-type transistor, an ion implantation or diffusion process can be used to form a P-type doped well, i.e., a P-well, in the second substrate 820, and the dopant can be a low-concentration P-type dopant such as boron (B); if the transistor is a P-type transistor, an ion implantation or diffusion process can be used to form an N-type doped well, i.e., an N-well, in the second substrate 820, and the dopant can be a low-concentration N-type dopant such as phosphorus (P), arsenic (As), and antimony (Sb). A drain 850 and a source 840 are formed in the well region 880. For example, if the transistor is an N-type transistor, the source 840 and drain 850 are formed in the second substrate 820 using N-type dopants such as phosphorus (P), arsenic (As), and antimony (Sb); if the transistor is a P-type transistor, the source 840 and drain 850 are formed in the second substrate 820 using P-type dopants such as boron (B). The portion of the well region 880 located between the source 840 and drain 850 forms a channel 860. A gate dielectric layer 871 and a gate conductive layer 872 are formed on one side of the second substrate 820. The gate structure, for example, can be formed by a thin-film deposition process on one side of the second substrate 820 to create a gate dielectric layer 871, and then by an etching process to remove a portion of the gate dielectric layer 871, leaving the remaining gate dielectric layer 871 located between the source 840 and the drain 850, i.e., covering the surface of the channel 860. A gate conductive layer 872 can also be formed on the side of the gate dielectric layer 871 facing away from the second substrate 820 by a thin-film deposition process, and then by an etching process to remove a portion of the gate conductive layer 872, leaving the remaining gate conductive layer 872 located between the source 840 and the drain 850 and covering the gate dielectric layer 871. The gate dielectric layer 871 can be made of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide, magnesium oxide, and tantalum oxide. The gate conductive layer 872 can be made of polysilicon, a conductive metal, or a conductive alloy. For example, the gate conductive layer 872 can be made of at least one of tungsten (W), titanium nitride (TiN), copper (Cu), and silver (Ag). It should be noted that the source 840 and drain 850 of the above transistor can also be directly formed in the second substrate 820. In other words, the above steps may not include the step of forming the well region 880.

[0102] In some embodiments, such as Figure 9 As shown, the step of forming the third semiconductor structure 801 may further include: etching a fifth contact hole corresponding to the fifth interconnect structure along a first direction on the side of the second substrate 820 away from the second interconnect layer 810, the fifth contact hole penetrating the second substrate 820; forming a dielectric layer on the inner wall of the fifth contact hole; and filling the gap formed in the dielectric layer 332 with conductive material to form the fifth contact structure 890.

[0103] It should be noted that the method for forming the fourth semiconductor structure 802 is similar to the method for forming the third semiconductor structure 801, and will not be described in detail here.

[0104] In addition, this application embodiment also provides a storage system, which includes a controller and the aforementioned semiconductor device. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0105] Figure 17 A block diagram of a system with semiconductor devices according to one embodiment of this application is shown. System 900 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with storage located therein. Figure 17 As shown, system 900 may include host 904 and memory system 901, the memory system 901 having one or more semiconductor devices 902 and memory controller 903. Host 904 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-a-chip (SoC), such as an application processor (AP). Host 904 may be configured to send or receive data from semiconductor device 902.

[0106] Semiconductor device 902 can be any semiconductor device disclosed in this application, such as Figure 13 or Figure 14 The semiconductor device is shown. According to some embodiments, a memory controller 903 is coupled to the semiconductor device 902 and the host 904, and is configured to control the semiconductor device 902. The memory controller 903 can manage data stored in the semiconductor device 902 and communicate with the host 904. For example, the memory controller 903 can be coupled to the semiconductor device 902, and the memory controller 903 can be configured to control the operation of the first memory array 301 and the second memory array 302 via a first peripheral circuit and a second peripheral circuit. In embodiments of this application, by bonding the first source structure of the first semiconductor structure 100 to the second source structure of the second semiconductor structure 200, the first semiconductor structure 100 and the second semiconductor structure 200 can share a first peripheral circuit via a first contact structure 320, and simultaneously share a second peripheral circuit via a second contact structure 330.

[0107] In some embodiments, the memory controller 903 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 903 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 903 can be configured to control the operation of the semiconductor device 902, such as read, erase, and program operations. The memory controller 903 can also be configured to manage various functions related to data stored in or to be stored in the semiconductor device 902, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 903 is further configured to process error correction codes (ECC) related to data read from or written to the semiconductor device 902. The memory controller 903 may also perform any other appropriate functions, such as formatting the semiconductor device 902. The memory controller 903 may communicate with external devices (e.g., the host 904) according to a specific communication protocol. For example, the memory controller 903 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0108] The memory controller 903 and one or more semiconductor devices 902 can be integrated into various types of memory devices, for example, contained within the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 901 can be implemented and packaged into different types of end electronic products. Figure 18 In one example shown, a memory controller 903 and a single semiconductor device 902 can be integrated into a memory card 910. The memory card 910 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 910 may further include a connection between the memory card 910 and a host computer (e.g., Figure 17 The memory card connector 911 is coupled to the host 904. Figure 19 In another example shown, a memory controller 903 and multiple semiconductor devices 902 can be integrated into a solid-state drive, i.e., an SSD 920. The SSD 920 may further include a connection between the SSD 920 and a host (e.g., Figure 17 The SSD connector 921 is coupled to the host 904. In some embodiments, the storage capacity and / or operating speed of the SSD 920 is higher than that of the memory card 910.

[0109] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. As an example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0110] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor structure includes a first memory array and a first source structure located on one side of the first memory array along a first direction. The first source structure includes a first source layer and a first bonding layer located on the side of the first source layer away from the first memory array. A first bonding contact is disposed in the first bonding layer. as well as The second semiconductor structure includes a second memory array and a second source structure located on one side of the second memory array along the first direction. The second source structure includes a second source layer and a second bonding layer located on the side of the second source layer away from the second memory array. A second bonding contact is disposed in the second bonding layer. The first bonding contact is in contact with the second bonding contact. The first source structure and the second source structure are bonded together. The first bonding layer includes a first conductive barrier layer and a first insulating layer. The first conductive barrier layer is located between the first source layer and the first insulating layer. The first bonding contact penetrates the first insulating layer along the first direction and extends into the first conductive barrier layer. and / or The second bonding layer includes a second conductive barrier layer and a second insulating layer. The second conductive barrier layer is located between the second source layer and the second insulating layer. The second bonding contact penetrates the second insulating layer along the first direction and extends into the second conductive barrier layer.

2. The semiconductor device according to claim 1, wherein, The materials of the first conductive barrier layer and / or the second conductive barrier layer include metal silicides and / or metals.

3. The semiconductor device according to claim 1 or 2, wherein, Both the first storage array and the second storage array include: Stacked structure; and A channel structure extends through the stacked structure along the first direction. The channel structure includes a first end and a second end disposed opposite to each other along the first direction. In a direction perpendicular to the first direction, the size of the first end of the channel structure is smaller than the size of its second end.

4. The semiconductor device according to claim 3, wherein, The first ends of the channel structures of the first memory array and the second memory array are both closer to or farther from the first source structure than their second ends; or, In one of the channel structures of the first memory array and the second memory array, the first end of one is closer to the first source structure relative to its second end, and the first end of the other is farther away from the first source structure relative to its second end.

5. The semiconductor device according to claim 3, wherein, A third semiconductor structure is disposed on the side of the first memory array away from the first source structure, and the third semiconductor structure includes a first peripheral circuit connected to the first memory array. and / or A fourth semiconductor structure is disposed on the side of the second memory array away from the second source structure, and the fourth semiconductor structure includes a second peripheral circuit connected to the second memory array.

6. The semiconductor device according to claim 5, wherein, The first storage array includes a first contact structure, one end of which is connected to the first source structure and the other end of which is connected to the first peripheral circuit. and / or The second memory array includes a second contact structure, one end of which is connected to the second source structure and the other end of which is connected to the second peripheral circuit.

7. The semiconductor device according to claim 5, wherein, The stacked structure includes a third insulating layer and a gate layer that are alternately stacked along the first direction; The first memory array includes a third contact structure disposed corresponding to its gate layer, one end of the third contact structure being connected to the corresponding gate layer and the other end being connected to the first peripheral circuit. and / or The second memory array includes a fourth contact structure corresponding to its gate layer, one end of which is connected to the corresponding gate layer and the other end of which is connected to the second peripheral circuit.

8. A semiconductor device, characterized in that, include: A first semiconductor structure includes a first memory array and a first source structure located on one side of the first memory array along a first direction. The first source structure includes a first source layer and a first bonding layer located on the side of the first source layer away from the first memory array. A first bonding contact is disposed in the first bonding layer. as well as The second semiconductor structure includes a second memory array and a second source structure located on one side of the second memory array along the first direction. The second source structure includes a second source layer and a second bonding layer located on the side of the second source layer away from the second memory array. A second bonding contact is disposed in the second bonding layer. The first bonding contact is in contact with the second bonding contact. The first source structure and the second source structure are bonded together. The first bonding layer includes a first insulating layer and a first dielectric barrier layer. The first dielectric barrier layer is located on the side of the first insulating layer away from the first source layer. The first bonding contact penetrates the first dielectric barrier layer and the first insulating layer along the first direction. and / or The second bonding layer includes a second insulating layer and a second dielectric barrier layer. The second dielectric barrier layer is located on the side of the second insulating layer away from the second source layer. The second bonding contact penetrates the second dielectric barrier layer and the second insulating layer along the first direction.

9. The semiconductor device according to claim 8, wherein, The material of the first dielectric barrier layer and / or the second dielectric barrier layer includes silicon nitride and / or doped silicon nitride.

10. The semiconductor device according to claim 8 or 9, wherein, Both the first storage array and the second storage array include: Stacked structure; and A channel structure extends through the stacked structure along the first direction. The channel structure includes a first end and a second end disposed opposite to each other along the first direction. In a direction perpendicular to the first direction, the size of the first end of the channel structure is smaller than the size of its second end.

11. The semiconductor device according to claim 10, wherein, The first ends of the channel structures of the first memory array and the second memory array are both closer to or farther from the first source structure than their second ends; or, In one of the channel structures of the first memory array and the second memory array, the first end of one is closer to the first source structure relative to its second end, and the first end of the other is farther away from the first source structure relative to its second end.

12. The semiconductor device according to claim 10, wherein, A third semiconductor structure is disposed on the side of the first memory array away from the first source structure, and the third semiconductor structure includes a first peripheral circuit connected to the first memory array. and / or A fourth semiconductor structure is disposed on the side of the second memory array away from the second source structure, and the fourth semiconductor structure includes a second peripheral circuit connected to the second memory array.

13. The semiconductor device according to claim 12, wherein, The first storage array includes a first contact structure, one end of which is connected to the first source structure and the other end of which is connected to the first peripheral circuit. and / or The second memory array includes a second contact structure, one end of which is connected to the second source structure and the other end of which is connected to the second peripheral circuit.

14. The semiconductor device according to claim 12, wherein, The stacked structure includes a third insulating layer and a gate layer that are alternately stacked along the first direction; The first memory array includes a third contact structure disposed corresponding to its gate layer, one end of the third contact structure being connected to the corresponding gate layer and the other end being connected to the first peripheral circuit. and / or The second memory array includes a fourth contact structure corresponding to its gate layer, one end of which is connected to the corresponding gate layer and the other end of which is connected to the second peripheral circuit.

15. A semiconductor device, characterized in that, include: A first semiconductor structure includes a first memory array and a first source structure located on one side of the first memory array along a first direction; as well as The second semiconductor structure includes a second memory array and a second source structure located on one side of the second memory array along the first direction, wherein the first source structure and the second source structure are bonded together. The first source structure includes a first source layer and a first conductive structure located within the first source layer. The first conductive structure extends along a second direction perpendicular to the first direction. The second source structure includes a second source layer and a second conductive structure located within the second source layer. The second conductive structure extends along the second direction. The first conductive structure is in contact with the second conductive structure.

16. The semiconductor device according to claim 15, wherein, The first conductive structure includes a first connection portion extending along the second direction and at least one first conductive protrusion connected to the first connection portion. The first conductive protrusion is located on the side of the first connection portion facing the first memory array, and the side of the first connection portion away from the first memory array is exposed on the surface of the first source layer; and / or The second conductive structure includes a second connection portion extending along the second direction and at least one second conductive protrusion connected to the second connection portion. The second conductive protrusion is located on the side of the second connection portion facing the second memory array, and the side of the second connection portion away from the second memory array is exposed on the surface of the second source layer.

17. The semiconductor device according to claim 16, wherein, Along the first direction, the first conductive protrusion penetrates the first source layer in a direction away from the first connection portion; and / or Along the first direction, the second conductive protrusion penetrates the second source layer in a direction away from the second connection portion.

18. The semiconductor device according to claim 16, wherein, The first source layer has a plurality of first connection portions spaced apart along the second direction, and / or the second source layer has a plurality of second connection portions spaced apart along the second direction.

19. The semiconductor device according to claim 18, wherein, An insulating portion is provided between two adjacent first connecting portions and / or two adjacent second connecting portions.

20. The semiconductor device according to any one of claims 15 to 19, wherein, Both the first storage array and the second storage array include: Stacked structure; and A channel structure extends through the stacked structure along the first direction. The channel structure includes a first end and a second end disposed opposite to each other along the first direction. In a direction perpendicular to the first direction, the size of the first end of the channel structure is smaller than the size of its second end.

21. The semiconductor device according to claim 20, wherein, The first ends of the channel structures of the first memory array and the second memory array are both closer to or farther from the first source structure than their second ends; or, In one of the channel structures of the first memory array and the second memory array, the first end of one is closer to the first source structure relative to its second end, and the first end of the other is farther away from the first source structure relative to its second end.

22. The semiconductor device according to claim 20, wherein, A third semiconductor structure is disposed on the side of the first memory array away from the first source structure, and the third semiconductor structure includes a first peripheral circuit connected to the first memory array. and / or A fourth semiconductor structure is disposed on the side of the second memory array away from the second source structure, and the fourth semiconductor structure includes a second peripheral circuit connected to the second memory array.

23. The semiconductor device according to claim 22, wherein, The first storage array includes a first contact structure, one end of which is connected to the first source structure and the other end of which is connected to the first peripheral circuit. and / or The second memory array includes a second contact structure, one end of which is connected to the second source structure and the other end of which is connected to the second peripheral circuit.

24. The semiconductor device according to claim 22, wherein, The stacked structure includes a third insulating layer and a gate layer that are alternately stacked along the first direction; The first memory array includes a third contact structure disposed corresponding to its gate layer, one end of the third contact structure being connected to the corresponding gate layer and the other end being connected to the first peripheral circuit. and / or The second memory array includes a fourth contact structure corresponding to its gate layer, one end of which is connected to the corresponding gate layer and the other end of which is connected to the second peripheral circuit.

25. A method for fabricating a semiconductor device, characterized in that, include: A first semiconductor structure is formed, comprising a first memory array and a first source structure, wherein the first source structure is located on one side of the first memory array along a first direction; A second semiconductor structure is formed, including a second memory array and a second source structure, wherein the second source structure is located on one side of the second memory array along the first direction; as well as The first source structure and the second source structure are bonded together; The formation of a first semiconductor structure including a first memory array and a first source structure and / or the formation of a second semiconductor structure including a second memory array and a second source structure includes: Form a storage array; A source layer is formed on one side of the memory array; A bonding layer is formed on the side of the source layer away from the memory array; and A bonding contact is formed within the bonding layer from the side of the bonding layer away from the source layer; Forming a bonding layer on the side of the source layer away from the memory array includes: A conductive barrier layer is formed on the side of the source layer away from the memory array; and An insulating layer is formed on the side of the conductive barrier layer away from the source layer; The bonding contacts extend into the conductive barrier layer.

26. A method for fabricating a semiconductor device, characterized in that, include: A first semiconductor structure is formed, comprising a first memory array and a first source structure, wherein the first source structure is located on one side of the first memory array along a first direction; A second semiconductor structure is formed, including a second memory array and a second source structure, wherein the second source structure is located on one side of the second memory array along the first direction; as well as The first source structure and the second source structure are bonded together; The formation of a first semiconductor structure including a first memory array and a first source structure and / or the formation of a second semiconductor structure including a second memory array and a second source structure includes: Form a storage array; A source layer is formed on one side of the memory array; A bonding layer is formed on the side of the source layer away from the memory array; and A bonding contact is formed within the bonding layer from the side of the bonding layer away from the source layer; Forming a bonding layer on the side of the source layer away from the memory array includes: An insulating layer is formed on the side of the source layer away from the memory array; and A dielectric barrier layer is formed on the side of the insulating layer away from the source layer; The bonding contact penetrates both the dielectric barrier layer and the insulating layer.

27. A method for fabricating a semiconductor device, characterized in that, include: A first semiconductor structure is formed, comprising a first memory array and a first source structure, wherein the first source structure is located on one side of the first memory array along a first direction; A second semiconductor structure is formed, including a second memory array and a second source structure, wherein the second source structure is located on one side of the second memory array along the first direction; as well as The first source structure and the second source structure are bonded together; The formation of a first semiconductor structure including a first memory array and a first source structure and / or the formation of a second semiconductor structure including a second memory array and a second source structure includes: Form a storage array; A source layer is formed on one side of the memory array; and A conductive structure is formed on the side of the source layer away from the memory array. The conductive structure is located within the source layer and extends along a second direction perpendicular to the first direction.

28. The method for fabricating a semiconductor device according to claim 27, wherein, The surface of the source layer away from the memory array includes a first region and at least one second region located within the first region; The formation of a conductive structure from the side of the source layer away from the memory array includes: A conductive hole extending along the first direction is formed in the second region; A conductive groove is formed in the first region, the depth of the conductive groove along the first direction being less than the depth of the conductive hole along the first direction; and The conductive holes and the conductive grooves are filled with conductive material to form the conductive structure.

29. A storage system, characterized in that, The storage system includes a controller and a semiconductor device according to any one of claims 1 to 7, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data; Alternatively, the storage system includes a controller and a semiconductor device according to any one of claims 8 to 14, the controller being coupled to the semiconductor device and used to control the semiconductor device to store data; Alternatively, the storage system may include a controller and a semiconductor device according to any one of claims 15 to 24, the controller being coupled to the semiconductor device and used to control the semiconductor device to store data.

Images