Method for manufacturing semiconductor device, semiconductor device, and storage system

Abstract

The disclosure provides a semiconductor device preparation method, a semiconductor device and a storage system, and relates to the technical field of semiconductor chips, and aims to solve the problem of poor stability of the semiconductor device. The semiconductor device preparation method comprises the following steps: forming a storage stack structure, the storage stack structure comprising a laminated structure and a plurality of channel structures, the plurality of channel structures penetrating the laminated structure along a laminating direction of the laminated structure, and each channel structure comprising a channel portion. A plurality of strip-shaped conductive portions are formed on one side surface of the laminated structure along the laminating direction, the plurality of strip-shaped conductive portions extending along a first direction intersecting the laminating direction, and the plurality of strip-shaped conductive portions being arranged at intervals in a second direction. Part of at least one strip-shaped conductive portion is removed, so that the remaining part of the strip-shaped conductive portion constitutes a plurality of channel contact portions arranged at intervals along the first direction, and the channel contact portions are in contact with the channel portions. The above semiconductor device is applied to a three-dimensional memory to realize data reading and writing operations.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a preparation method of semiconductor device, semiconductor device and storage system. BACKGROUND

[0002] As the feature size of the storage unit approaches the lower limit of the process, the planar process and manufacturing technology become challenging and costly, which causes the storage density of the 2D or planar NAND flash memory to approach the upper limit.

[0003] To overcome the limitations of the 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND), which improves the storage density by arranging the storage units three-dimensionally above the substrate.

[0004] As the number of stacked layers of the storage unit in the three-dimensional memory becomes higher and the distance between the storage units becomes smaller, the existing preparation method of the three-dimensional memory can cause poor stability of the semiconductor device. SUMMARY

[0005] Embodiments of the present disclosure provide a preparation method of semiconductor device, semiconductor device and storage system, aiming to solve the problem of poor stability of the semiconductor device.

[0006] To achieve the above-mentioned purpose, embodiments of the present disclosure adopt the following technical solutions:

[0007] In one aspect, a preparation method of semiconductor device is provided, the method comprising: forming a storage stack structure, the storage stack structure comprising a stacked structure and a plurality of channel structures, the plurality of channel structures penetrating the stacked structure along a stacking direction of the stacked structure, each channel structure comprising a channel portion; forming a plurality of strip-shaped conductive portions on a side surface of the stacked structure along the stacking direction, the plurality of strip-shaped conductive portions extending along a first direction intersecting the stacking direction, and the plurality of strip-shaped conductive portions being arranged in a second direction at intervals. The second direction intersects the first direction, and the second direction intersects the stacking direction. Removing part of at least one strip-shaped conductive portion, so that the remaining part of the strip-shaped conductive portion constitutes a plurality of channel contact portions arranged in the first direction at intervals. The channel contact portion is in contact with the channel portion.

[0008] The preparation method of the semiconductor device provided by the above embodiments of the present disclosure forms a plurality of strip-shaped conductive parts on the surface of the side of the stack structure away from the substrate. When the strip-shaped conductive parts are covered and aligned with a row of channel parts in the extension direction of the strip-shaped conductive parts, the strip-shaped conductive parts provided by the present disclosure have a larger contact window, which can improve the accuracy of the alignment and coverage between the strip-shaped conductive parts and the row of channel parts. Then, based on the aforementioned strip-shaped conductive parts, part of the strip-shaped conductive parts is removed to form channel contact parts arranged at intervals and in contact with the channel parts. The embodiments of the present disclosure can control the position and length of the removed part of the strip-shaped conductive part according to the position of the channel part, control the position and length of the channel contact part remaining in the strip-shaped conductive part, and further improve the accuracy of the contact between the channel contact part and the corresponding channel part, thereby improving the electrical connection effect between the channel contact part and the channel part, and further improving the stability of the semiconductor device.

[0009] In some embodiments, before forming the plurality of strip-shaped conductive parts on the surface of the side of the stack structure along the stacking direction, the method further comprises: forming a first insulating layer on the surface of the side of the stack structure along the stacking direction. Forming the plurality of strip-shaped conductive parts on the surface of the side of the stack structure along the stacking direction comprises: forming a first mask layer on the first insulating layer, the first mask layer comprising a plurality of first openings. Forming a plurality of strip-shaped grooves in the first insulating layer by using the plurality of first openings of the first mask layer, the strip-shaped grooves exposing the channel parts. Forming the plurality of strip-shaped conductive parts in the plurality of strip-shaped grooves.

[0010] In some embodiments, removing part of the at least one strip-shaped conductive part so that the remaining part of the strip-shaped conductive part constitutes a plurality of channel contact parts arranged at intervals along the first direction comprises: forming a second mask layer, the second mask layer covering the first mask layer and the plurality of strip-shaped conductive parts, the second mask layer comprising a plurality of second openings. Removing part of the at least one strip-shaped conductive part by using the plurality of second openings of the second mask layer to form a plurality of separation grooves. The plurality of separation grooves separate the remaining part of the strip-shaped conductive part into a plurality of channel contact parts.

[0011] In some embodiments, the plurality of second openings are arranged in multiple rows, the plurality of second openings in a row are arranged in sequence along the first direction, and the multiple rows of second openings are arranged in sequence along the second direction. The plurality of second openings in a row are arranged at intervals on the strip-shaped conductive part.

[0012] In some embodiments, the distance between two adjacent second openings in the first direction is a separation groove pitch, and at least two separation groove pitches are not equal.

[0013] In some embodiments, the method for preparing a semiconductor device further comprises: filling an insulating material in the plurality of separation grooves. Removing the first mask layer and the second mask layer.

[0014] In some embodiments, the method for manufacturing a semiconductor device further comprises: forming a second insulating layer on a side of the plurality of channel contact portions facing away from the stack structure, forming a connection hole on the second insulating layer, and forming a connection portion in the connection hole, the connection portion being in contact with the channel contact portion. A third insulating layer is formed on a side of the second insulating layer facing away from the stack structure, and a connection groove is formed on the third insulating layer. A conductive wire is formed in the connection groove.

[0015] In another aspect, a semiconductor device is provided, comprising: a memory stack structure and a plurality of spaced-apart channel contact portions. The memory stack structure comprises a stack structure and a plurality of channel structures, the plurality of channel structures penetrating the stack structure along a stacking direction of the stack structure, each channel structure comprising a channel portion. The plurality of spaced-apart channel contact portions are disposed on a side surface of the stack structure along the stacking direction, the channel contact portions being in contact with the channel portions. At least two of the channel contact portions have different widths in a first direction, the first direction being transverse to the stacking direction.

[0016] In some embodiments, the channel contact portion comprises two first surfaces oppositely disposed along the stacking direction and a plurality of side surfaces connected to the first surfaces, wherein at least one of the plurality of side surfaces extends along a first direction and at least one of the plurality of side surfaces extends along a second direction.

[0017] In some embodiments, the number of the first side surfaces is two, and the two first side surfaces are oppositely disposed along the second direction. The number of the second side surfaces is two, and the two second side surfaces are oppositely disposed along the first direction.

[0018] In some embodiments, the first side surfaces of the plurality of channel contact portions spaced apart along the first direction and located on the same side of the first surface along the second direction are coplanar.

[0019] In some embodiments, a cross section of the channel contact portion on a reference plane is rectangular or quasi-rectangular, wherein the reference plane is perpendicular to the stacking direction.

[0020] In some embodiments, an area of a cross section of the channel portion on a reference plane is smaller than an area of a cross section of the channel contact portion on the reference plane.

[0021] In some embodiments, the semiconductor device further comprises: a plurality of connection portions. The plurality of connection portions are disposed on a side of the channel contact portion facing away from the stack structure, one connection portion being in contact with one channel contact portion, and an area of a cross section of the connection portion on a reference plane is smaller than an area of a cross section of the channel contact portion on the reference plane.

[0022] In some embodiments, the semiconductor device further comprises: a plurality of conductive wires. The plurality of conductive wires are disposed on a side of the plurality of connection portions facing away from the plurality of channel contact portions, and one conductive wire is in contact with at least one connection portion.

[0023] In some embodiments, the semiconductor device further includes peripheral devices. The peripheral devices are electrically connected to the conductive lines.

[0024] In another aspect, a storage system is provided, comprising: a semiconductor device and a controller as described above. The controller is coupled to the semiconductor device to control the semiconductor device to store data.

[0025] In another aspect, an electronic device is provided, including the storage system described above.

[0026] It is understood that the beneficial effects of the semiconductor devices, three-dimensional memories, storage systems and electronic devices provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor device preparation method described above, and will not be repeated here. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0028] Figure 1 Structural block diagrams of electronic devices provided in some embodiments of this disclosure;

[0029] Figure 2A This is a schematic diagram of the structure of a storage device provided in some embodiments of this disclosure;

[0030] Figure 2B This is a schematic diagram of the structure of another storage device provided in some embodiments of this disclosure;

[0031] Figure 3 A three-dimensional structural schematic diagram of a three-dimensional memory provided in some embodiments of this disclosure;

[0032] Figure 4 Cross-sectional views of a three-dimensional memory provided for some embodiments of this disclosure;

[0033] Figure 5 for Figure 3 A cross-sectional view of a string of memory cells along section line AA' in the memory;

[0034] Figure 6 for Figure 5 Equivalent circuit diagram of the memory cell string;

[0035] Figure 7AThis is a top view of a semiconductor device according to an embodiment of the present disclosure;

[0036] Figure 7B A top view of a semiconductor device according to another embodiment of this disclosure;

[0037] Figure 7C A top view of a semiconductor device according to yet another embodiment of this disclosure;

[0038] Figures 8A-8B A flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this disclosure;

[0039] Figures 9A-9E Cross-sectional views corresponding to some steps in the fabrication method of a semiconductor device provided in some embodiments of this disclosure;

[0040] Figures 10A-10C The above view shows some steps of a method for fabricating a semiconductor device according to some embodiments of this disclosure.

[0041] Figure 11 A flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this disclosure;

[0042] Figure 12 A top view of a semiconductor device provided for some embodiments of this disclosure;

[0043] Figure 13 This is a schematic diagram of the structure of the channel contact portion provided in some embodiments of this disclosure. Detailed Implementation

[0044] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0045] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0046] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0047] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0048] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0049] Figure 1 The diagram below shows a structural block diagram of an electronic device 9000 provided in some embodiments of this disclosure. The electronic device 9000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0050] like Figure 1As shown, the electronic device 9000 may include a storage system 910 and a host 920. The storage system 910 can be integrated into various types of storage devices 900, such as memory cards. These memory cards include any of the following: PC cards (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) cards, SmartMedia (SM) cards, memory sticks, Multimedia Cards (MMC), Secure Digital Memory Cards (SD cards), and Universal Flash Storage (UFS). In other words, the storage system 910 can be applied to and packaged into different types of electronic products.

[0051] The host 920 may include a processor of the electronic device 9000, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The host 920 may be configured to send data to or receive data from the memory 911.

[0052] In some embodiments, the storage system 910 may have one or more memories 911 and a controller 912. For example, the controller 912 may be configured to operate in a low duty cycle environment, such as with an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment with an SSD or eMMC, which is used as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. Or, in some examples, the controller 912 is coupled to the memory 911 and the host 920 and is configured to control data in the memory 911 while also being able to communicate with external devices (e.g., the host).

[0053] Figure 2A This is a schematic diagram of the structure of a storage device 900 provided in some embodiments of the present disclosure. Figure 2B This is a schematic diagram of the structure of another storage device 900 provided in some embodiments of this disclosure.

[0054] See Figure 2A and Figure 2BStorage device 900 may include storage system 910 and interface 913, wherein the number of memories 911 in storage system 910 may be one or more. For example, Figure 2A The following diagram uses a single memory chip, 911, as an example. Figure 2B The diagram illustrates six memories 911 as an example. The controller 912 manages the data stored in each memory 911 and communicates with a host 920 external to the storage device 900 via an interface 913. The controller 912 can be configured to control the operation of each memory 911, such as read, write, and refresh operations. The controller 912 can also be configured to manage various functions related to the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management.

[0055] In some implementations, controller 912 is also configured to determine the maximum memory capacity available to the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Controller 912 may also perform any other suitable functions. Controller 912 can communicate with external devices (e.g., host 920) according to a specific communication protocol. For example, controller 912 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnection (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0056] Figure 3 This is a schematic diagram of the three-dimensional structure of a three-dimensional memory provided in some embodiments of this disclosure. Figure 4 Cross-sectional view of a three-dimensional memory provided for some embodiments of this disclosure.

[0057] See Figure 3 and Figure 4The memory 911 may include a memory stack structure 12, a source layer SL coupled to the memory stack structure 12, and peripheral devices 13 coupled to the memory stack structure 12. The peripheral devices 13 may be disposed on the side of the memory stack structure 12 away from the source layer SL.

[0058] The source layer SL may include a semiconductor material, such as single-crystal silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or completely doped. For example, the source layer SL may include doped regions doped with p-type dopant. The source layer SL may also include undoped regions.

[0059] The memory stack structure 12 may include arrayed strings of memory cell transistors (referred to herein as “memory cell strings”, such as NAND memory cell strings) 400. A source layer SL may be coupled to the source ends of multiple memory cell strings 400.

[0060] Figure 5 for Figure 3 A cross-sectional view of a string of memory cells along section line AA' in the memory. Figure 6 for Figure 5 Equivalent circuit diagram of the storage cell string.

[0061] See Figure 5 and Figure 6 The storage cell string 400 may include a channel structure 122 and multiple gate lines G, which may be arranged around the channel structure 122.

[0062] For example, the channel structure 122 may include a support portion 1226 and a channel layer 1222, a tunneling layer 1225, a charge trapping layer 1224 and a charge blocking layer 1221 sequentially disposed around the support portion 1226.

[0063] In some examples, the channel structure 122 may also include a channel portion 1223, wherein the channel portion 1223 is connected between the channel layer 1222 and the channel contact portion 1331.

[0064] The storage cell string 400 may include multiple transistors T, for example Figure 6 In the T1 to T6 configuration, each transistor T can be configured as a memory cell, and these transistors T are connected together to form a memory cell string.

[0065] A transistor T (e.g., each transistor T) may be formed by a gate line G and a portion of the channel structure 122 surrounded by the gate line G. The gate line G is configured to control the on-state of the transistor.

[0066] It should be noted that, Figures 3-6 The number of transistors shown is merely illustrative; the storage cell string of the three-dimensional memory provided in this disclosure may also include other numbers of transistors, such as 4, 16, 32, or 64. In this disclosure, the number of transistors in the storage cell string is not limited.

[0067] Furthermore, along the third direction Z, the lowermost gate line among the multiple gate lines G (e.g., the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source select gate SGS. The source select gate SGS is configured to control the conduction state of transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 400. The uppermost gate line among the multiple gate lines G (e.g., the gate line furthest from the source layer SL among the multiple gate lines G) is constructed as a drain select gate SGD. The drain select gate SGD is configured to control the conduction state of transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 400. The middle gate line among the multiple gate lines G can be constructed as multiple word lines WL, such as word lines WL0, WL1, WL2, and WL3. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (e.g., transistor T) in the memory cell string 400 can be completed.

[0068] See also Figure 3 and Figure 4 In some embodiments, the memory stack structure 12 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include the drain (i.e., bit line BL) of the memory cell string 400, which may be coupled to the semiconductor channel of at least one transistor T in the memory cell string 400.

[0069] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292. The contacts may include, for example, bit line contacts BL-CNT and drain select gate contacts SGD-CNT. The bit line contacts BL-CNT are coupled to the bit line BL. For example, the bit line contacts BL-CNT may include a connection portion 160 and a channel contact portion 1331.

[0070] The drain select gate contact SGD-CNT is coupled to the drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include multiple interconnect lines, such as bit lines BL and word line interconnect lines WL-CL coupled to word lines WL. The materials of the first interconnect conductor layer 291 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and combinations of one or more high-dielectric-constant insulating materials, or other suitable materials.

[0071] Peripheral device 13 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0072] Specifically, in some embodiments, the peripheral device 13 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuit may include the transistor 120.

[0073] The substrate 110 can be made of single-crystal silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0074] The peripheral interconnect layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other via contacts. The materials of the second interconnect conductor layers 132 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as silicon oxide, silicon nitride, and combinations of one or more high dielectric constant insulating materials, or other suitable materials.

[0075] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, enabling coupling between the memory stack structure 12 and the peripheral device 13. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuitry in the peripheral device 13 can be coupled to the memory cell string in the semiconductor device 10 to achieve the transmission of electrical signals between the peripheral circuitry and the memory cell string. In some possible implementations, an bonding interface 500 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, through which the peripheral interconnect layer 130 and the array interconnect layer 290 can be bonded and coupled to each other.

[0076] Figure 7A This is a top view of a semiconductor device 10 according to an embodiment of the present disclosure; Figure 7B A top view of a semiconductor device 10 according to another embodiment of this disclosure; Figure 7C A top view of a semiconductor device 10 according to yet another embodiment of this disclosure.

[0077] See Figure 7A The channel contact portion 1331 is provided in the channel portion 1223 (e.g. Figure 4 As shown, a connection portion 160 is disposed on the channel contact portion 1331, and a bit line BL is disposed on the connection portion 160. During the fabrication of the semiconductor device 10, it is necessary to ensure precise contact between the channel contact portion 1331 and the channel portion 1223, precise contact between the connection portion 160 and the channel contact portion 1331, and precise contact between the bit line BL and the connection portion 160, thereby ensuring the stability of the semiconductor device 10. However, in the stacking direction, the stress accumulated during the process can cause misalignment between two adjacent stacked film layers, resulting in alignment deviations. For example, the channel contact portion 1331 and the channel portion 1223 may shift due to stress, causing a misalignment between parts of the channel contact portion 1331 and the channel portion 1223, thus affecting the electrical connection between them. Similarly, see [reference needed]. Figure 7BThe connection portion 160 and the channel contact portion 1331 may deviate due to stress accumulated during the manufacturing process. Similarly, the bit line BL and the connection portion 160 may deviate due to stress accumulated during the manufacturing process.

[0078] In one embodiment, to improve the deviation between the channel contact portion 1331 and the channel portion 1223, the position of the channel contact portion 1331 can be adjusted during the fabrication of the channel contact portion 1331, thereby reducing the deviation between the channel contact portion 1331 and the channel portion 1223. Therefore, during the fabrication of the channel contact portion 1331, it is necessary to modify the mask required for fabricating the channel contact portion 1331.

[0079] However, in the subsequent fabrication of the connector 160, SADP (Self-aligned Double Pattering) technology will be used. At this time, the position of the connector 160 will change with the change of the position of the channel contact 1331. Therefore, it is necessary to modify the mask required for fabricating the connector 160 during the fabrication process.

[0080] Similarly, in order to ensure precise contact between the bit line BL and the connector 160, it is also necessary to modify the mask required when fabricating the bit line BL.

[0081] In summary, in one embodiment, in order to ensure the stability of the semiconductor device 10, it is necessary to modify the mask required for fabricating the channel contact portion 1331, the mask required for fabricating the connection portion 160, and the mask required for fabricating the bit line BL, which makes the fabrication process of the semiconductor device 10 more complicated.

[0082] See Figure 7C During the fabrication of bit line BL, due to the small width of bit line BL, it is easy to cause bit line BL to break after modifying the mask required for fabrication of bit line BL.

[0083] Based on this, the present disclosure provides a method for fabricating a semiconductor device 10.

[0084] Figures 8A to 8B This is a flowchart illustrating a method for fabricating a semiconductor device 10 according to some embodiments of the present disclosure. Figures 9A to 9E Cross-sectional views corresponding to some steps in the fabrication method of semiconductor device 10 provided in some embodiments of this disclosure.

[0085] Please see Figure 8A The method for fabricating semiconductor device 10 includes the following steps S1 to S3.

[0086] S1. A storage stack structure is formed, which includes a stack structure and multiple channel structures. The multiple channel structures penetrate the stack structure along the stacking direction of the stack structure, and each channel structure includes a channel section.

[0087] Please see Figure 9A The storage stack structure 12 can be formed on the substrate 11. The substrate 11 can be a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. The material of the substrate 11 can also be a compound semiconductor. For example, the substrate 11 can be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate, etc. The substrate 11 of this disclosure can also be fabricated using other semiconductor materials commonly used in the art.

[0088] In some embodiments, the plurality of channel structures 122 of the storage stack structure 12 are arranged in rows at intervals along a first direction X and in columns at intervals along a second direction Y. The plurality of channel portions 1223 on the top of the plurality of channel structures 122 are arranged in rows at intervals along the first direction X and in columns at intervals along the second direction Y.

[0089] For example, step S1 may include steps S11 to S14 as described below.

[0090] S11. An initial stacked structure is formed on a substrate, wherein the initial stacked structure may include a plurality of initial gate dielectric layers and gate replacement layers alternately stacked along the stacking direction Z.

[0091] "Alternating stacking" refers to the process of forming an initial gate dielectric layer 1211 on the substrate 11, forming a gate replacement layer on the initial gate dielectric layer 1211, and then forming an initial gate dielectric layer 1211 on the gate replacement layer, and so on.

[0092] In the initial stacked structure, the initial gate dielectric layer 1211 and the gate replacement layer can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof thin film deposition processes, and this disclosure does not limit them.

[0093] The initial gate dielectric layer 1211 can have the same or different thicknesses, and the multiple gate replacement layers can also have the same or different thicknesses. The thicknesses of the initial gate dielectric layer 1211 and the gate replacement layers can be set according to specific process requirements. In practical applications, the gate replacement layer can be removed and replaced by a conductive material in subsequent processes to form the gate layer 1212, i.e., the word line WL (e.g., ...).Figure 4 (As shown).

[0094] For example, the material of the initial gate dielectric layer 1211 can be silicon oxide, and the material of the gate replacement layer can be silicon nitride.

[0095] S12. Etch the initial stacked structure to form a channel hole that penetrates the initial stacked structure and extends to the substrate in the stacking direction Z.

[0096] For example, in step S12, the formation process of the channel via can be a dry etching process or a wet etching process. The formed channel via penetrates the substrate 11 in the stacking direction Z and exposes a portion of the substrate 11. In other examples, the communication via can extend into the substrate 11.

[0097] S13. A channel structure is formed within the channel hole. The channel structure may include a charge blocking layer, a charge trapping layer, a tunneling layer, a channel layer, and a support. The charge blocking layer, charge trapping layer, and tunneling layer may be combined to form a functional layer.

[0098] In step S13, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to sequentially form a functional layer 1220 and a channel layer 1222 on the sidewall of the channel hole. The charge blocking layer 1221 is used to block the outflow of charge stored in the charge trapping layer 1224. The charge trapping layer 1224 can tunnel through the tunneling layer 1225 under voltage to achieve writing and erasing of memory data. For example, the material of the charge blocking layer 1221 can be silicon oxide, the material of the charge trapping layer 1224 can be a nitride, and the material of the tunneling layer 1225 can be an oxide. The material of the support portion 1226 can include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride (e.g., silicon oxynitride). Alternatively, chemical mechanical polishing (CMP) can be used to planarize the top surface of the support portion 1226 within the channel hole. The top surface of the channel hole support 1226 refers to the surface of the channel hole support 1226 that is away from the substrate 11.

[0099] In this embodiment, the channel structure 122 further includes a channel portion 1223, wherein the channel portion 1223 is located at one end of the channel structure 122 away from the substrate 11, and the channel portion 1223 is electrically connected to the channel layer 1222.

[0100] S14. Replace the gate replacement layer with the gate line layer.

[0101] The gate replacement layer in the initial stacked structure is removed to form a gate gap, and then a conductive material is filled in the gate gap to form a gate layer 1212. At this time, multiple gate layers 1212 and multiple initial gate dielectric layers 1211 are alternately stacked to form a stacked structure 121.

[0102] Figures 10A-10C The above view shows some steps of a method for fabricating a semiconductor device 10 according to some embodiments of this disclosure.

[0103] S2. Multiple strip-shaped conductive portions are formed on one surface of the laminated structure along the stacking direction. The multiple strip-shaped conductive portions extend along a first direction intersecting the stacking direction, and are spaced apart in a second direction. The second direction intersects the first direction and the stacking direction.

[0104] Please see Figure 9B In step S2, a plurality of strip-shaped conductive portions 140 are formed on the surface of the stacked structure 121 away from the substrate 11.

[0105] Please see Figure 10A Each strip conductive portion 140 extends along the first direction X, and multiple strip conductive portions 140 are arranged at intervals in the second direction Y.

[0106] For example, multiple strip conductive sections 140 can be arranged in parallel.

[0107] In some examples, each strip conductive portion 140 is associated with a row of channel portions 1223 (e.g., Figure 9B (As shown) Contact.

[0108] For example, the strip conductive portion 140 includes a first conductive material, which may include tungsten and / or copper.

[0109] Please see Figure 8B In some embodiments, step S20 may be included before step S2 described above.

[0110] S20. A first insulating layer is formed on one side surface of the laminated structure along the stacking direction.

[0111] For example, a first insulating layer 170 may be formed on the side of the stacked structure 121 away from the substrate 11 using CVD, PVD, ALD, or any combination thereof thin film deposition processes.

[0112] For example, the material of the first insulating layer 170 may include one or more of the following: silicon nitride layer, silicon oxynitride layer, aluminum oxide layer, and zirconium oxide layer.

[0113] Please continue reading. Figure 8BIf step S2 is preceded by step S20, then step S2 may include the following steps S21 to S23.

[0114] S21. A first mask layer is formed on the first insulating layer, the first mask layer including a plurality of first openings.

[0115] For example, in step S21, a first photoresist layer is formed on the side of the first insulating layer 170 away from the substrate 11, and the first photoresist layer is exposed and developed to pattern the first photoresist layer. At this time, a plurality of first openings can be formed in the first photoresist layer. The patterned first photoresist layer can serve as a first mask layer with a plurality of first openings.

[0116] Each first opening extends along a first direction X, and multiple first openings are spaced apart in the Y direction.

[0117] As an example, multiple first openings can be set in parallel.

[0118] S22. Using multiple first openings in the first mask layer, multiple strip grooves are formed in the first insulating layer, and the strip grooves expose the channel portion.

[0119] In step S22, the first insulating layer 170 is etched based on multiple first openings to form multiple strip grooves. For example, dry etching can be used to etch the first insulating layer 170 to form the strip grooves. The depth of the strip grooves is not less than the thickness of the first insulating layer 170, thereby exposing the channel portion 1223 so that the subsequent filler in the strip grooves can contact and electrically connect with the channel portion 1223.

[0120] Each of the strips extends along the first direction X, and multiple strips are spaced apart in the Y direction.

[0121] As an example, multiple strips can be arranged in parallel.

[0122] S23. Multiple strip-shaped conductive parts are formed in multiple strip-shaped grooves.

[0123] In some embodiments, a plurality of strip-shaped grooves are filled with a first conductive material to form a plurality of strip-shaped conductive portions 140. For example, the first conductive material may include tungsten and copper.

[0124] In steps S21 to S23, the size of the strip groove is relatively large, so the groove section 1223 is more easily exposed, thereby reducing the difficulty of the manufacturing process.

[0125] In some embodiments, step S23 may include the following steps S231 to S232.

[0126] S231. Deposit a first conductive material, which fills the strip groove and covers the first insulating layer.

[0127] For example, in step S231, a first conductive material may be deposited using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0128] S232, Remove the first conductive material deposited on the first insulating layer.

[0129] For example, in step S232, chemical mechanical polishing (CMP) can be used to remove the first conductive material on the first insulating layer. Since the first conductive material of the strip groove can also be removed, the surface of the strip conductive portion away from the channel portion 1223 can be planarized.

[0130] After completing step S2, step S3 can be executed.

[0131] S3. Remove at least one portion of the strip conductive portion, so that the remaining portion of the strip conductive portion constitutes a plurality of channel contact portions spaced apart along the first direction, and the channel contact portions contact each other.

[0132] For example, each strip conductive portion 140 can be etched using a dry etching method, so that the portion remaining after etching forms a channel contact portion 1331. Then, the channel contact portion 1331 is used to contact the channel portion 1223 to achieve an electrical connection between the film layer where the channel contact portion 1331 is located and the film layer where the channel portion 1223 is located.

[0133] In step S232, the surface of the strip conductive portion facing away from the channel portion 1223 is flattened, which facilitates the formation of the connecting portion 160 on the channel contact portion 1331.

[0134] In this embodiment, the strip conductive portion 140 has a large area, which is beneficial for achieving alignment and contact between the strip conductive portion 140 and the row channel portion 1223.

[0135] After the strip conductive portion 140 is formed, the strip conductive portion 140 can be etched to form the channel contact portion 1331, and then the connecting portion 160 can be formed on the channel contact portion 1331. When etching the strip conductive portion 140, the etching position of the strip conductive portion 140 can be adjusted according to the position of the channel portion 1223 and the position of the connecting portion 160. That is, the position of the portion of the strip conductive portion 140 removed in step S3 can be adjusted, thereby adjusting the width of the remaining channel contact portion 1331 in the first direction X. This allows the remaining channel contact portion 1331 in step S3 to contact both its corresponding channel portion 1223 and its corresponding connecting portion 160. This reduces the offset between the channel contact portion 1331 and the channel portion 1223, as well as the offset between the channel contact portion 1331 and the connecting portion 160, thereby improving the reliability of the electrical connection between the channel contact portion 1331 and the channel portion 1223, and the reliability of the electrical connection between the channel contact portion 1331 and the connecting portion 160. This improves the stability of the semiconductor device 10.

[0136] In addition, in this embodiment of the present disclosure, in step S3 above, when removing at least one portion of the strip conductive portion 140, a mask layer is used to etch the strip conductive portion 140 to form the channel contact portion 1331. In step S3, the position and size of the channel contact portion 1331 retained in step S3 can be determined according to the position of the channel portion 1223 and the position of the connection portion 160. Therefore, in the process of fabricating the semiconductor device 10, the structure of the mask required for fabricating the channel contact portion 1331 can be modified, without modifying the structure of the mask required for fabricating the connection portion 160, or the structure of the mask required for subsequently forming the bit line BL, thereby reducing the fabrication process difficulty of the semiconductor device 10.

[0137] Please continue reading. Figure 8B In some examples, step S3 may include steps S31 to S32 as described below.

[0138] S31. A second mask layer is formed, which covers the first mask layer and a plurality of strip-shaped conductive parts; the second mask layer includes a plurality of second openings.

[0139] See Figure 10B In some embodiments, a second photoresist layer is formed on the side of the first mask layer and the plurality of strip conductive portions 140 away from the substrate 11, and the second photoresist layer is exposed, developed, and patterned to form a plurality of second openings 150 in the second photoresist layer. Thus, the patterned second photoresist layer serves as a second mask layer having a plurality of second openings 150.

[0140] Among them, multiple second openings 150 are arranged in a row along the first direction X, and multiple rows of second openings 150 are arranged in a row along the second direction Y, and can expose part of the strip conductive part 140.

[0141] S32. Using multiple second openings in the second mask layer, remove a portion of at least one strip conductive portion to form multiple slots, which divide the remaining portion of the strip conductive portion into multiple channel contact portions.

[0142] See Figure 10B In some embodiments, the strip conductive portion 140 can be etched in the stacking direction using a dry etching method based on the multiple second openings 150, thereby forming multiple slots 151. The depth of the multiple slots 151 is greater than or equal to the thickness of the strip conductive portion 140, thereby cutting off the strip conductive portion 140 and dividing the remaining portion of the strip conductive portion 140 into multiple independent channel contact portions 1331.

[0143] In step S32, the position of the second opening 150 and the width of the second opening 150 in the first direction X can be adjusted according to the position of the channel portion 1223 and the position of the connecting portion 160, thereby adjusting the width of the retained channel contact portion 1331 in the first direction X. This allows the channel contact portion 1331 to contact both its corresponding channel portion 1223 and its corresponding connecting portion 160, thereby reducing the offset between the channel contact portion 1331 and the channel portion 1223, as well as the offset between the channel contact portion 1331 and the connecting portion 160. This improves the reliability of the electrical connection between the channel contact portion 1331 and the channel portion 1223, and the reliability of the electrical connection between the channel contact portion 1331 and the connecting portion 160, thereby improving the stability of the semiconductor device 10. Among them, the channel portion 1223 corresponding to the channel contact portion 1331 is the channel portion 1223 that contacts and is electrically connected to the channel contact portion 1331, and the connecting portion 160 corresponding to the channel contact portion 1331 is the connecting portion 160 that contacts and is electrically connected to the channel contact portion 1331.

[0144] In addition, in this embodiment of the present disclosure, in steps S31 and S32 above, when removing at least one portion of the strip conductive portion 140, it is necessary to etch the strip conductive portion 140 using a second mask layer to form the channel contact portion 1331. In step S3, the position and size of the channel contact portion 1331 retained in step S3 can be determined according to the position of the channel portion 1223 and the position of the connection portion 160. Therefore, in the process of fabricating the semiconductor device 10, the structure of the second mask layer can be modified without modifying the structure of the mask required for fabricating the connection portion 160, or the structure of the mask required for subsequently forming the bit line BL. This reduces the fabrication process difficulty of the semiconductor device 10 and shortens the fabrication cycle.

[0145] In some embodiments, after step S3 described above, steps S41 and S42 may also be included.

[0146] S41. Fill multiple compartments with insulating material.

[0147] For example, an insulating layer material can be filled using a deposition process, and the filling insulating material may include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride materials (e.g., silicon oxynitride). This configuration insulates the adjacent channel contacts 1331 by filling the spacer 151 with insulating material.

[0148] In some embodiments, step S41 may include the following steps S411 to S412.

[0149] S411, Deposit insulating material, the insulating material is filled in multiple slots.

[0150] Insulation between the contact portions 1331 of two adjacent channels is achieved by filling the groove 151 with insulating material.

[0151] S412. Remove the insulating material deposited on the trench contact area.

[0152] For example, in step S412, chemical mechanical polishing can be used to remove the insulating material on the channel contact portion 1331. At the same time, since the insulating material protruding on the upper surface of the partition groove 151 can also be removed, the surface of the strip conductive portion 140 facing away from the channel portion 1223 can be flattened to facilitate subsequent operations.

[0153] After completing step S41, step S42 can be executed.

[0154] S42, Remove the first mask layer and the second mask layer.

[0155] In some embodiments, during the planarization process of the top surface of the insulating material by chemical mechanical polishing, excess insulating material, the first mask layer, and the second mask layer can be removed simultaneously. In this case, step S42 can be completed in the same process as step S412. The excess insulating material removed in step S42 refers to the insulating material located on the second mask layer and the insulating material protruding from the channel contact portion 1331.

[0156] In other embodiments, the first mask layer may be removed after step S232, and the insulating material and the second mask layer may be removed after step S412.

[0157] Please continue reading. Figure 10B Multiple second openings 150 are arranged in multiple rows. In one row, multiple second openings 150 are arranged sequentially along the first direction X, and in multiple rows, multiple second openings 150 are arranged sequentially along the second direction Y. Among them, the multiple second openings 150 in one row are arranged at intervals on the strip conductive part 140.

[0158] In some embodiments, the plurality of channel structures 122 of the storage stack structure 12 are arranged in rows at intervals along a first direction X and in columns at intervals along a second direction Y. By forming a plurality of second openings 150 arranged in rows at intervals along the first direction X and arranged in multiple rows at intervals along the second direction Y, after removing the portions of the plurality of strip conductive portions 140 corresponding to the plurality of second openings 150, the remaining portions of the plurality of strip conductive portions 140 (i.e., the plurality of channel contact portions 1331) can be arranged at intervals in the first direction X and arranged at intervals in the second direction Y, and it is ensured that the plurality of channel contact portions 1331 and the channel portions 1223 on the top surface of the plurality of channel structures 122 away from the substrate 11 are precisely covered.

[0159] Please continue reading. Figure 10B and Figure 10C The distance between two adjacent second openings 150 in the first direction X is the slot spacing H1, and at least the two slot spacings H1 are not equal.

[0160] For example, the groove spacing H1 is the width of the channel contact portion 1331 in the first direction X. The two groove spacings H1 are not equal, so that the widths H2 of the two channel contact portions 1331 in the first direction X are not equal.

[0161] This embodiment utilizes the spacing H1 between a plurality of second openings 150 arranged at intervals in the first direction X to adjust the width of the channel contact portion 1331 in the first direction X, thereby compensating for the alignment deviation caused by the stress and improving the alignment accuracy between the channel contact portion 1331 and the channel portion 1223. For example, in the plurality of second openings 150 arranged at intervals in a row, the size of each spacing H1 can be pre-designed based on the alignment deviation between the corresponding channel portions 1223 and the connecting portions 160. By adjusting the spacing H1, the size of the channel contact portion 1331 is adjusted, thereby compensating for the alignment deviation of each channel contact portion 1331, enabling the channel contact portion 1331 to be electrically connected to the corresponding channel portion 1223 and the connecting portion 160. Since the alignment deviations between the corresponding channel portions 1223 and the connecting portions 160 can be different, the size of each channel contact portion 1331 can be different, that is, the size of each slot spacing H1 in the second mask can be different, thereby improving the flexibility of the second mask in correcting the position (or size) of the channel contact portion 1331.

[0162] Figure 11 A flowchart illustrating another method for fabricating a semiconductor device according to some embodiments of this disclosure; Figure 12 This is a top view of a semiconductor device provided for some embodiments of this disclosure.

[0163] See Figure 11 and Figure 12 The method for fabricating semiconductor device 10 also includes steps S5 to S8.

[0164] S5. A second insulating layer is formed on the side of the multiple channel contact portion away from the stacked structure, and a connection hole is formed on the second insulating layer.

[0165] Please see Figure 9D In step S5, the second insulating layer 180 is also located on the side of the first insulating layer 170 that is away from the stacked structure 121.

[0166] In some embodiments, a second insulating layer 180 may be deposited on the side of the plurality of channel contacts 1331 opposite to the stacked structure 121 using any one or more of existing conventional thin film deposition processes, such as CVD, PVD and ALD.

[0167] For example, the material of the second insulating layer 180 can be any suitable insulating material, such as oxides, nitrides, etc.

[0168] The material of the second insulating layer 180 may be the same as or different from that of the first insulating layer 170, and the thickness of the second insulating layer 180 may be the same as or different from that of the first insulating layer 170.

[0169] In step S5, a connection hole can be formed on the second insulating layer 180 by an etching process, wherein the depth of the connection hole is greater than or equal to the thickness of the second insulating layer 180, thereby exposing the channel contact portion 1331.

[0170] S6. A connecting portion is formed inside the connecting hole, and the connecting portion contacts the channel contact portion.

[0171] In step S6, a second conductive material can be filled into the connection hole to form a connection portion 160 (as shown in 9D). For example, the filling second conductive material may include tungsten or copper. Then, chemical mechanical polishing can be used to planarize the top surface of the conductive material and remove excess second conductive material.

[0172] S7. A third insulating layer is formed on the side of the second insulating layer away from the stacked structure, and a connecting groove is formed on the third insulating layer.

[0173] In step S7, a third insulating layer 171 can be deposited on the side of the second insulating layer 180 away from the stacked structure 121 using any one or more conventional thin film deposition processes, such as CVD, PVD, and ALD. For example, the material of the third insulating layer 171 can be any suitable insulating material, such as oxides, nitrides, etc. The material of the third insulating layer 171 can be the same as or different from that of the first insulating layer 170 and the second insulating layer 180; the thickness of the third insulating layer 171 can be the same as or different from that of the first insulating layer 170 and the second insulating layer 180. A connection trench is formed on the third insulating layer 171 by etching, the depth of which is greater than or equal to the thickness of the third insulating layer 171, thereby exposing the connection portion 160.

[0174] The connecting groove is strip-shaped and extends along the second direction Y, and multiple strip-shaped grooves are arranged sequentially along the first direction X.

[0175] S8. Form conductive lines within the connecting groove.

[0176] See Figure 12 In step S8, a third conductive material can be filled into the connecting groove to form a conductive line 190. For example, the filling third conductive material may include tungsten and copper. Alternatively, chemical mechanical polishing can be used to planarize the top surface of the third conductive material, removing excess material. The formed conductive line 190 contacts the connecting portion 160, achieving an electrical connection.

[0177] Wherein, the conductive line 190 can be the bit line BL provided in some of the above embodiments (such as... Figure 3 (As shown).

[0178] Based on the semiconductor device fabrication methods provided in the above embodiments, this disclosure also provides a semiconductor device 10, which can be fabricated by the above-described semiconductor device fabrication methods.

[0179] See Figure 9E The semiconductor device 10 may include a memory stack structure 12 and a plurality of spaced-apart channel contacts 1331. The memory stack structure 12 includes a stacked structure 121 and a plurality of channel structures 122. The plurality of channel structures 122 penetrate the stacked structure 121 along its stacking direction, and each channel structure 122 includes a channel portion 1223. The plurality of spaced-apart channel contacts 1331 are disposed on one surface of the stacked structure 121 along its stacking direction, and the channel contacts 1331 contact the channel portions 1223. At least two channel contacts 1331 have different widths in a first direction, which intersects the stacking direction.

[0180] The semiconductor device 10 provided in this embodiment is made by the preparation method of the semiconductor device 10 provided in some of the above embodiments. Therefore, the semiconductor device 10 provided in this embodiment has all the beneficial effects of the preparation method of the semiconductor device 10 provided in some of the above embodiments, which will not be elaborated here.

[0181] The plurality of channel contact portions 1331 formed in this embodiment have different widths in the first direction X. When fabricating the channel contact portions 1331, the width of at least a portion of the channel contact portions 1331 in the first direction X can be adjusted according to the offset between the film layers adjacent to the channel contact portion 1331 (e.g., channel portion 1223 or connecting portion 160). This results in different widths of the channel contact portions 1331 in the first direction X, thereby improving the coverage accuracy between the channel contact portion 1331 and its adjacent film layers, improving the reliability of the electrical connection between the channel contact portion 1331 and the channel portion 1223, and improving the reliability of the electrical connection between the channel contact portion 1331 and the connecting portion 160, thereby improving the stability of the semiconductor device 10.

[0182] Meanwhile, in this embodiment of the present disclosure, when adjusting the mask size corresponding to the channel contact portion 1331, the offset of the subsequent connecting portion 160 is pre-included. This ensures that the channel contact portion 1331 is aligned with the channel portion 1223 and also with the connecting portion 160. This eliminates the need for subsequent adjustments to the mask structure corresponding to the connecting portion 160, effectively reducing process difficulty, shortening the production cycle, and reducing production costs.

[0183] Figure 13 This is a schematic diagram of the structure of the channel contact portion 1331 provided in some embodiments of this disclosure. It should be noted that, inFigure 13 The diagram only shows a portion of the groove contact section 1331.

[0184] In some embodiments, the channel contact portion 1331 includes two first surfaces 1332 disposed opposite to each other in the stacking direction Z and a plurality of side surfaces connected to the first surfaces 1332, wherein at least one of the plurality of side surfaces includes a first side surface 1333 extending in the first direction X and a second side surface 1334 extending in the second direction Y.

[0185] For example, the first side 1333 can be a plane, and the second side 1334 can be a plane.

[0186] See Figure 10B and Figure 13 The channel contact portion 1331 can be obtained by etching the strip-shaped conductive portion 140; that is, the portion remaining after etching the strip-shaped conductive portion 140 constitutes the channel contact portion 1331. Based on the structural features of the strip-shaped conductive portion 140, the channel contact portion 1331 formed based on the strip-shaped conductive portion 140 may include two first surfaces 1332 disposed opposite to each other in the stacking direction Z, a first side surface 1333 extending along the first direction X, and a second side surface 1334 extending along the second direction Y. For example, the two first surfaces 1332 are respectively used to contact the channel portion 1223 and the connecting portion 160 corresponding to the channel contact portion 1331.

[0187] In some embodiments, there are two first sides 1333, and the two first sides 1333 are arranged opposite to each other in the second direction Y. For example, the two first sides 1333 are arranged in parallel.

[0188] There are two second sides 1334, and the two second sides 1334 are arranged opposite each other in the first direction X. For example, the two second sides 1334 are arranged parallel to each other.

[0189] Please continue reading. Figure 10B and Figure 13 Based on the formation process of the channel contact portion 1331 and the structural features of the strip conductive portion 140, the channel contact portion 1331 formed based on the strip conductive portion 140 may include two second side surfaces 1334 disposed opposite to each other in the first direction X, and two first side surfaces 1333 disposed opposite to each other in the second direction Y. For example, the two second side surfaces 1334 and the first side surfaces 1333 are used to enclose the two first surfaces 1332 to form a three-dimensional channel contact portion 1331.

[0190] In some embodiments, among a plurality of channel contact portions 1331 spaced apart in the first direction X, the first side surfaces 1333 located on the same side of the first surface 1332 in the second direction Y are coplanar.

[0191] For example, the first surface 1332 may include a first side and a first side edge disposed opposite to each other in the second direction Y. The first side surface 1333 may include a first side surface 1333a and a first side surface 1333b disposed opposite to each other in the second direction Y. The first side surface 1333a is connected to the first side edge of the first surface 1332; the first side surface 1333b is connected to the second side edge of the first surface 1332. For example, in a plurality of channel contact portions 1331 in a row, the plurality of first side surfaces 1333a of the plurality of channel contact portions 1331 are coplanar, and the plurality of first side surfaces 1333b of the plurality of channel contact portions 1331 are coplanar.

[0192] In this embodiment, since the multiple first side surfaces 1333a and 1333b of the multiple channel contact portions 1331 are coplanar, the width of the multiple channel contact portions 1331 in the second direction Y remains consistent. This reduces the possibility of alignment deviation between the channel contact portions 1331 and the channel portion 1223 when forming the multiple channel contact portions 1331 in step S3 of the above embodiment, and improves the accuracy of alignment between the connecting portion 160 and the channel contact portion 1331 in the subsequent film layer. The width of the channel contact portion 1331 in the second direction Y is equal to the distance between the two first side surfaces.

[0193] In some embodiments, the cross-section of the channel contact portion 1331 on the reference plane is rectangular or quasi-rectangular, wherein the reference plane is perpendicular to the stacking direction.

[0194] For example, a plane perpendicular to the stacking direction Z is used as a reference plane. Projecting the channel contact portion 1331 onto the reference plane yields a rectangular or rectangular-like projection of the channel contact portion 1331 onto the reference plane. That is, the cross-section of the channel contact portion 1331 on the reference plane is rectangular or rectangular-like. The rectangle can be either a square or a rectangle. Specifically, the rectangle can be a standard rectangle, in which case the included angle between two adjacent sides is a right angle. In a rectangular-like shape, two adjacent straight sides are perpendicular to each other, and the intersection of the two straight sides forms an arc.

[0195] This embodiment of the present disclosure sets the cross-section of the channel contact portion 1331 on the reference plane to be rectangular or quasi-rectangular, which effectively increases the contact surface of the channel contact portion 1331, which is beneficial for the alignment and coverage when the connecting portion 160 is formed subsequently, and improves the accuracy of the alignment between the connecting portion 160 and the channel contact portion 1331.

[0196] In some embodiments, the area of ​​the cross-section of the channel portion 1223 on the reference plane is smaller than the area of ​​the cross-section of the channel contact portion 1331 on the reference plane.

[0197] For example, when projecting onto the reference plane in a direction perpendicular to the reference plane, the orthographic projection of the channel portion 1223 onto the reference plane is within the range of the orthographic projection of the channel contact portion 1331 onto the reference plane.

[0198] With this configuration, when the channel contact portion 1331 contacts the channel portion 1223, the contact surface of the channel contact portion 1331 is larger than the contact surface of the channel portion 1223, which is conducive to achieving precise coverage of the channel portion 1331 over the channel portion 1223 and improving the accuracy of the alignment between the channel contact portion 1331 and the channel portion 1223.

[0199] In some embodiments, the semiconductor device 10 may further include: a plurality of connection portions 160, the plurality of connection portions 160 being disposed on the side of the channel contact portion 1331 away from the stacked structure 121, one connection portion 160 contacting one channel contact portion 1331, and the area of ​​the cross section of the connection portion 160 on the reference plane being smaller than the area of ​​the cross section of the channel contact portion 1331 on the reference plane.

[0200] For example, when projecting onto the reference plane in a direction perpendicular to the reference plane, the orthographic projection of the connecting portion 160 onto the reference plane is within the range of the orthographic projection of the channel contact portion 1331 onto the reference plane.

[0201] With this configuration, when the connecting part 160 contacts the channel contact part 1331, the contact surface of the channel contact part 1331 is larger than the contact surface of the connecting part 160. This facilitates the placement of the connecting part 160 on the channel contact part 1331, improves the alignment accuracy between the connecting part 160 and the channel contact part 1331, and further enhances the electrical connection effect between the connecting part 160 and the channel contact part 1331.

[0202] In some embodiments, the semiconductor device 10 may further include multiple conductive lines 190 disposed on the side of the multiple connection portions 160 opposite to the multiple channel contact portions 1331, with one conductive line 190 contacting at least one connection portion 160. For example, the multiple conductive lines 190 may be used as multiple bit lines in the semiconductor device 10. With this configuration, the conductive lines 190 can achieve electrical connection with the connection portions 160, and thus, through the connection with peripheral circuits, achieve electrical connection between the entire semiconductor device 10 and other devices.

[0203] The semiconductor device 10 provided in some of the above embodiments can be a three-dimensional memory 911 or a part of a three-dimensional memory 911. For example, the semiconductor device 10 can be a memory stack structure 12.

[0204] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A storage stack structure is formed, the storage stack structure includes a stack structure and a plurality of channel structures, the plurality of channel structures penetrate the stack structure along the stacking direction of the stack structure, and each channel structure includes a channel portion; A plurality of strip-shaped conductive portions are formed on one side surface of the stacked structure along the stacking direction. The plurality of strip-shaped conductive portions extend along a first direction intersecting the stacking direction, and the plurality of strip-shaped conductive portions are spaced apart in a second direction, which intersects the first direction and the stacking direction. At least one portion of a strip conductive portion is removed, such that the remaining portion of the strip conductive portion constitutes a plurality of channel contact portions spaced apart along the first direction, the channel contact portions contacting the channel portions.

2. The preparation method according to claim 1, characterized in that, Before forming a plurality of strip-shaped conductive portions on one side surface of the stacked structure along the stacking direction, the method further includes: A first insulating layer is formed on one surface of the stacked structure along the stacking direction; The formation of multiple strip-shaped conductive portions on one side surface of the stacked structure along the stacking direction includes: A first mask layer is formed on the first insulating layer, the first mask layer including a plurality of first openings; Using multiple first openings in the first mask layer, multiple strip grooves are formed in the first insulating layer, and the strip grooves expose the channel portion; The plurality of strip-shaped conductive portions are formed within the plurality of strip-shaped grooves.

3. The preparation method according to claim 2, characterized in that, The step of removing a portion of at least one strip-shaped conductive portion, such that the remaining portion of the strip-shaped conductive portion constitutes a plurality of channel contact portions spaced apart along the first direction, includes: A second mask layer is formed, which covers the first mask layer and the plurality of strip conductive portions; the second mask layer includes a plurality of second openings; Using multiple second openings in the second mask layer, a portion of at least one strip-shaped conductive portion is removed to form multiple slots, which divide the remaining portion of the strip-shaped conductive portion into multiple channel contact portions.

4. The preparation method according to claim 3, characterized in that, The plurality of second openings are arranged in multiple rows, and the plurality of second openings in a row of second openings are arranged sequentially along the first direction, and the multiple rows of second openings are arranged sequentially along the second direction. Among them, multiple second openings in a row of second openings are arranged at intervals on the strip conductive part.

5. The preparation method according to claim 3, characterized in that, The distance between two adjacent second openings in the first direction is the slot spacing, and at least two slot spacings are not equal.

6. The preparation method according to claim 3, characterized in that, Also includes: The plurality of slots are filled with insulating material; Remove the first mask layer and the second mask layer.

7. The preparation method according to any one of claims 1-6, characterized in that, Also includes: A second insulating layer is formed on the side of the plurality of channel contact portions away from the stacked structure, and a connection hole is formed on the second insulating layer; A connecting portion is formed within the connecting hole, and the connecting portion contacts the channel contact portion; A third insulating layer is formed on the side of the second insulating layer away from the stacked structure, and a connecting groove is formed on the third insulating layer; Conductive wires are formed within the connecting groove.

8. A semiconductor device, characterized in that, include: A storage stacking structure, the storage stacking structure including a stacked structure and a plurality of channel structures, the plurality of channel structures penetrating the stacked structure along the stacking direction of the stacked structure, each channel structure including a channel portion; Multiple spaced-apart channel contact portions are disposed on one side surface of the stacked structure along the stacking direction, the channel contact portions contacting the channel portions, wherein at least two of the channel contact portions have different widths in a first direction, the first direction intersecting the stacking direction.

9. The semiconductor device according to claim 8, characterized in that, The channel contact portion includes two first surfaces disposed opposite to each other in the stacking direction and a plurality of side surfaces connected to the first surfaces, wherein at least one of the plurality of side surfaces includes a first side surface extending along the first direction and a second side surface extending along a second direction; the second direction intersects the first direction and the stacking direction.

10. The semiconductor device according to claim 9, characterized in that, The number of first sides is two, and the two first sides are arranged opposite to each other in the second direction; The number of the second side is two, and the two second sides are arranged opposite to each other in the first direction.

11. The semiconductor device according to claim 9, characterized in that, Among the plurality of channel contact portions spaced apart in the first direction, the first side surface located on the same side of the first surface in the second direction is coplanar.

12. The semiconductor device according to claim 9, characterized in that, The cross-section of the channel contact portion on the reference plane is rectangular or rectangular, wherein the reference plane is perpendicular to the stacking direction.

13. The semiconductor device according to claim 12, characterized in that, The area of ​​the channel portion on the reference plane is smaller than the area of ​​the channel contact portion on the reference plane.

14. The semiconductor device according to any one of claims 8-13, characterized in that, Also includes: Multiple connecting portions are disposed on the side of the channel contact portion away from the stacked structure, one connecting portion contacts one channel contact portion, and the area of ​​the cross section of the connecting portion on the reference plane is smaller than the area of ​​the cross section of the channel contact portion on the reference plane.

15. The semiconductor device according to claim 14, characterized in that, Also includes: Multiple conductive lines are disposed on the side of the multiple connecting portions opposite to the multiple channel contact portions, and one conductive line contacts at least one of the connecting portions.

16. The semiconductor device according to claim 15, characterized in that, Also includes: Peripheral devices are electrically connected to the conductive lines.

17. A storage system, characterized in that, include: The semiconductor device as described in any one of claims 8-16; A controller is coupled to the semiconductor device to control the semiconductor device to store data.

18. An electronic device, characterized in that, Including the storage system as described in claim 17.

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