Memory structure and method for forming the same

Abstract

A memory structure and a method for forming the same include: providing a substrate comprising a plurality of active regions and isolation regions located on either side of the active regions; sequentially forming a first sub-floating gate layer and a control gate dielectric layer on the active regions; using a first photoresist layer having a connection opening pattern as a mask, etching the control gate dielectric layer until the surface of the first sub-floating gate layer is exposed, thereby forming a connection opening; forming a control gate layer on the control gate dielectric layer, with the control gate layer completely filling the connection opening; using a second photoresist layer having an isolation opening pattern as a mask, etching the control gate layer and the control gate dielectric layer until the surface of the first sub-floating gate layer is exposed, thereby forming an isolation opening, a control gate, and a second sub-floating gate layer, wherein the control gate and the second sub-floating gate layer are located on either side of the isolation opening. A second sub-floating gate layer is added to the first sub-floating gate layer, thereby increasing the thickness of the floating gate and the etching window of the floating gate, thereby avoiding perforation and electrical breakdown caused by excessively thin floating gates.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a memory structure and a method for forming the same. Background Art

[0002] Flash products usually require a Charge Pump circuit to provide erase and write power. The Pump circuit uses a "pumping capacitor" to boost the power supply voltage to the required erase and write voltage.

[0003] Capacitors are common passive components in integrated circuit chips. For example, in ETOX Flash devices, PIP capacitors (Poly-Insolator-Poly) are used to save costs. Specifically, a Poly-Poly-Sub Stack structure is formed by stacking a first PIP capacitor consisting of CG (control gate) / ONO (control gate dielectric layer) / FG (floating gate) with a second PIP capacitor consisting of FG (floating gate) / TUNOX (floating gate dielectric layer) / Sub-well (substrate). By applying voltage to the FG (floating gate), CG (control gate), and Sub-well (substrate), the first and second PIP capacitors are connected in parallel to achieve a higher capacitance value.

[0004] However, there are still many problems with capacitors in current memory structures. Summary of the Invention

[0005] The technical problem solved by the present invention is how to improve the performance of the capacitor in the memory structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a memory structure, comprising: providing a substrate, the substrate comprising a plurality of active regions and isolation regions located on both sides of the active regions; sequentially forming a first sub-floating gate layer and a control gate dielectric layer on the active regions; forming a first photoresist layer on the control gate dielectric layer; developing and exposing the first photoresist layer to form a first photoresist layer having a connection opening pattern; using the first photoresist layer having the connection opening pattern as a mask, etching the control gate dielectric layer until the surface of the first sub-floating gate layer is exposed to form a connection opening; forming a control gate layer on the control gate dielectric layer, and the control gate layer The gate layer fills the connection opening; a second photoresist layer is formed on the control gate layer; the second photoresist layer is developed and exposed to form a second photoresist layer with an isolation opening pattern; the second photoresist layer with the isolation opening pattern is used as a mask to etch the control gate layer and the control gate dielectric layer until the surface of the first sub-floating gate layer is exposed to form an isolation opening, a control gate and a second sub-floating gate layer, wherein the control gate and the second sub-floating gate layer are located on both sides of the isolation opening, and the second sub-floating gate layer, the control gate and the isolation opening are adjacent, the second sub-floating gate layer and the isolation opening are adjacent, and the first sub-floating gate layer and the second sub-floating gate layer constitute a floating gate.

[0007] Optionally, the thickness of the first sub-floating gate layer ranges from 450 angstroms to 700 angstroms, the thickness of the second sub-floating gate layer ranges from 1500 angstroms to 1900 angstroms, and the thickness of the control gate ranges from 1950 angstroms to 2600 angstroms.

[0008] Optionally, the process of etching the control gate layer is dry etching, and the process parameters are: etching gas is C x F x , one or more combinations of HBr, CL2, O2, Ar and He, the etching gas flow rate is 4 sccm to 220 sccm, the bias voltage is 50 V to 250 V, the etching pressure is 5 mTorr to 60 mTorr, and the etching time is 8 s to 65 s.

[0009] Optionally, the process of etching the control gate dielectric layer under the isolation opening is dry etching, and the process parameters are: etching gas is C x F x , O2, Ar and He, the etching gas flow rate is 4 sccm to 200 sccm, the bias voltage is 0V to 400V, the etching pressure is 4mTorr to 40mTorr, and the etching time is 6s to 33s.

[0010] Optionally, after the step of etching the control gate dielectric layer under the isolation opening, the method further includes: depositing an interlayer dielectric layer on the substrate; etching the interlayer dielectric layer to form contact holes located on the control gate, the second sub-floating gate layer and the substrate; filling the contact holes with conductive material to form conductive plugs, wherein the conductive plugs are located on the control gate, the second sub-floating gate layer and the substrate.

[0011] Optionally, before the step of forming the first sub-floating gate layer, the method further includes: forming a floating gate dielectric layer on the substrate; after the step of forming the first sub-floating gate layer, the method further includes: etching the isolation region until the sidewall surface of the first sub-floating gate layer is exposed.

[0012] Optionally, the material of the control gate dielectric layer is a combination of silicon nitride and silicon oxide.

[0013] Correspondingly, the present invention also provides a memory structure, comprising: a substrate, the substrate including a plurality of active areas and isolation areas located on both sides of the active areas; a first sub-floating gate layer located on the substrate; a control gate dielectric layer located on the first sub-floating gate layer, the control gate dielectric layer having a connection opening and an isolation opening, the connection opening exposing the surface of the first sub-floating gate layer, and the isolation opening exposing the surface of the first sub-floating gate layer; a control gate located on the control gate dielectric layer; a second sub-floating gate layer, the second sub-floating gate layer located on the connection opening being flush with the control gate, and the second sub-floating gate layer being isolated from the control gate by the isolation opening, the first sub-floating gate layer and the second sub-floating gate layer constituting a floating gate.

[0014] Optionally, the thickness of the first sub-floating gate layer ranges from 450 angstroms to 700 angstroms, the thickness of the second sub-floating gate layer ranges from 1500 angstroms to 1900 angstroms, and the thickness of the control gate ranges from 1950 angstroms to 2600 angstroms.

[0015] Optionally, the memory structure further includes: a floating gate dielectric layer located on the substrate.

[0016] Optionally, the memory structure further includes: an interlayer dielectric layer located on the substrate; and a conductive plug located in the interlayer dielectric layer, and the conductive plug is located on the control gate, the second sub-floating gate layer and the substrate.

[0017] Optionally, the material of the control gate dielectric layer is a combination of silicon nitride and silicon oxide.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] The technical solution of the present invention provides a method for forming a memory structure, which forms a connection opening on the control gate dielectric layer to expose the surface of the first sub-floating gate layer, so that when the control gate layer is subsequently formed, part of the control gate layer can contact the surface of the first sub-floating gate layer. Subsequently, an isolation opening is formed in the control gate layer to divide the control gate layer into a control gate located on the control gate dielectric layer and a second sub-floating gate layer located on the first sub-floating gate layer. Compared with the prior art, the present invention adds a second sub-floating gate layer on the basis of the first sub-floating gate layer, thereby increasing the thickness of the floating gate. When a contact hole is subsequently formed on the floating gate, an etching window for the floating gate is increased, thereby avoiding perforation and electrical breakdown caused by excessive thinness of the floating gate, thereby improving the performance of the capacitor in the storage structure. Moreover, the top surface of the floating gate is flush with the control gate, and only one photomask is required to form the contact hole, thereby simplifying the process steps.

[0020] The memory structure provided by the technical solution of the present invention comprises a first sub-floating gate layer and a second sub-floating gate layer, thereby increasing the thickness of the floating gate. When a contact hole is subsequently formed on the floating gate, an etching window of the floating gate is increased, thereby avoiding perforation and electrical breakdown caused by excessively thin floating gates, and improving the performance of the capacitor in the storage structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural diagram of a memory structure;

[0022] Figure 2 It is a structural diagram of another memory structure;

[0023] Figures 3 to 12 Schematic diagram of the memory structure formation process in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0025] For the current memory structure formation method, please refer to Figure 1, providing a substrate 100, the substrate 100 including a plurality of active areas 102 and isolation areas 101 located on both sides of the active areas 102; forming a floating gate dielectric layer, a floating gate 103, a control gate dielectric layer and a control gate 104 in sequence on the active areas 102; forming an interlayer dielectric layer on the substrate 100; etching the interlayer dielectric layer until the surface of the control gate is exposed to form a first contact hole; etching the interlayer dielectric layer 105, the control gate 104 and the control gate dielectric layer until the surface of the floating gate is exposed to form a second contact hole; etching the interlayer dielectric layer until the surface of the substrate 100 is exposed to form a third contact hole; forming a conductive plug 106 in the first contact hole, the second contact hole and the third contact hole.

[0026] In the above scheme, the control gate 104, the control gate dielectric layer and the floating gate 103 constitute a first PIP capacitor, the floating gate 103, the floating gate dielectric layer and the substrate 100 constitute a second PIP capacitor, the conductive plug in the first contact hole is used to be electrically connected to the first PIP capacitor, and the conductive plug in the second contact hole is used to be electrically connected to the second PIP capacitor.

[0027] Please refer to Figure 2 Since the PIP capacitor belongs to the ISO region and the floating gate is thin, when etching to form the second contact hole, the floating gate under the control gate dielectric layer will be etched, causing the floating gate to be etched through (e.g. Figure 2 107 in the figure), which leads to electrical breakdown and affects the performance of the capacitor in the memory structure. Moreover, the situation where the floating gate is etched through cannot be detected during the chip yield test, resulting in capacitor failure.

[0028] In order to solve the above technical problems, the technical solution of the present invention provides a memory structure and a method for forming the same. By dividing the control gate layer into a control gate located on the control gate dielectric layer and a second sub-floating gate layer located on the first sub-floating gate layer, compared with the existing technology, the present invention adds a second sub-floating gate layer on the basis of the first sub-floating gate layer, thereby increasing the thickness of the floating gate. When a contact hole is subsequently formed on the floating gate, an etching window for the floating gate is increased, thereby avoiding the problem of perforation and electrical breakdown caused by the floating gate being too thin, thereby improving the performance of the capacitor in the storage structure; and the top surface of the floating gate is flush with the control gate, and only one mask is required to form the contact hole subsequently, thereby simplifying the process steps.

[0029] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] Please refer to Figure 3, providing a substrate 200 , wherein the substrate 200 includes a plurality of active regions 202 and isolation regions 201 located on both sides of the active regions 202 .

[0031] In this embodiment, the substrate 200 is made of silicon.

[0032] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0033] In one embodiment of the present invention, the step of forming the isolation region 201 includes: etching the substrate 200 to form an isolation trench (not shown in the figure) located in the active region 202; and depositing an isolation material in the isolation trench to form the isolation region 201.

[0034] In this embodiment, the process of etching the substrate 200 includes a dry etching process.

[0035] In this embodiment, the deposition forming method includes: one or more of thermal oxidation, rapid thermal annealing, chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition.

[0036] In this embodiment, the material of the isolation region 201 includes silicon oxide.

[0037] In an embodiment of the present invention, after forming the isolation region 201 , the method further includes: forming a floating gate dielectric layer 203 on the substrate 200 .

[0038] In this embodiment, the floating gate dielectric layer 203 is formed by one or more methods selected from the group consisting of chemical vapor deposition, physical vapor deposition, atomic layer deposition, and jet vapor deposition.

[0039] In this embodiment, the material of the floating gate dielectric layer 203 includes one or more of silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0040] Please refer to Figure 4 , a first sub-floating gate layer 2041 is formed on the active area 202 and the isolation area 201 .

[0041] In this embodiment, the first sub-floating gate layer 2041 is formed by one or more methods selected from the group consisting of chemical vapor deposition, physical vapor deposition, atomic layer deposition, and jet vapor deposition.

[0042] In this embodiment, the material of the first sub-floating gate layer 2041 includes: a combination of one or more of single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0043] Please refer to Figure 5 , the first sub-floating gate layer 2041 is planarized until the surface of the isolation region 201 is exposed.

[0044] In some embodiments of the present invention, the planarization treatment method includes: mechanical polishing, chemical polishing, fluid polishing, chemical mechanical polishing, etc.

[0045] Specifically, in this embodiment, the planarization method is chemical mechanical polishing. Unlike traditional purely mechanical or purely chemical polishing methods, chemical mechanical polishing utilizes a combination of chemical and mechanical forces to avoid the surface damage caused by mechanical polishing alone and the shortcomings of chemical polishing alone, such as slow polishing speed, poor surface flatness, and poor polishing consistency. Chemical mechanical polishing is widely used for high-planarization at the nanoscale on a variety of materials.

[0046] Please refer to Figure 6 , etching the isolation region 201 until the sidewall surface of the first sub-floating gate layer 2041 is exposed; and forming a control gate dielectric layer 205 on the active region 202 and the isolation region 201 .

[0047] In some embodiments of the present invention, the material of the control gate dielectric layer 205 is a combination of silicon nitride and silicon oxide.

[0048] In a specific embodiment, the control gate dielectric layer 205 is an ONO structure.

[0049] In this embodiment, the isolation region 201 is etched to expose the sidewall surface of the first sub-floating gate layer 2041 , so as to increase the coupling area between the control gate and the floating gate to be formed subsequently.

[0050] In this embodiment, the control gate dielectric layer 205 is formed by one or more methods selected from the group consisting of chemical vapor deposition, physical vapor deposition, atomic layer deposition, and jet vapor deposition.

[0051] Please refer to Figure 7 , etching and removing the control gate dielectric layer 205 on the insulating layer.

[0052] Please refer to Figure 8, forming a first photoresist layer (not shown in the figure) on the control gate dielectric layer 205; developing and exposing the first photoresist layer to form a first photoresist layer (not shown in the figure) having a connection opening 2051 pattern; using the first photoresist layer having the connection opening 2051 pattern as a mask, etching the control gate dielectric layer 205 until the surface of the first sub-floating gate layer 2041 is exposed, thereby forming a connection opening 2051.

[0053] The connection opening 2051 is used to accommodate the second sub-floating gate layer 2042 formed subsequently, and connect the second sub-floating gate layer 2042 and the first sub-floating gate layer 2041 together.

[0054] In some embodiments of the present invention, the process of etching the control gate dielectric layer 205 is dry etching, and the process parameters are: the etching gas is C x F x , O2, Ar and He, the etching gas flow rate is 10 sccm to 20 sccm, the bias voltage is 200 V to 300 V, the etching pressure is 30 mTorr to 40 mTorr, and the etching time is 25s to 35s.

[0055] Please refer to Figure 9 , a control gate layer 206 is formed on the control gate dielectric layer 205 , and the control gate layer 206 completely fills the connection opening 2051 .

[0056] Before the step of forming the control gate layer 206 , the method further includes: removing the control gate dielectric layer 205 on the surface of the isolation region 201 .

[0057] In this embodiment, the control gate dielectric layer 205 is formed by one or more methods selected from the group consisting of chemical vapor deposition, physical vapor deposition, atomic layer deposition, and jet vapor deposition.

[0058] In this embodiment, the material of the control gate layer 206 includes: a combination of one or more of single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0059] Please refer to Figure 10 , forming a second photoresist layer (not shown in the figure) on the control gate layer 206; developing and exposing the second photoresist layer to form a second photoresist layer (not shown in the figure) having an isolation opening 2061 pattern; using the second photoresist layer having the isolation opening 2061 pattern as a mask, etching the control gate layer 206 until the surface of the control gate dielectric layer 205 is exposed, thereby forming the isolation opening 2061.

[0060] In some embodiments of the present invention, the process of etching the control gate layer 206 is dry etching, and the process parameters are: the etching gas is Cx F x , one or more combinations of HBr, CL2, O2, Ar and He, the etching gas flow rate is 4 sccm to 220 sccm, the bias voltage is 50 V to 250 V, the etching pressure is 5 mTorr to 60 mTorr, and the etching time is 8 s to 65 s.

[0061] Please refer to Figure 11 , continue to use the second photoresist layer with the isolation opening 2061 pattern as a mask to etch the control gate dielectric layer 205 until the surface of the first sub-floating gate layer 2041 is exposed, forming the isolation opening 2061, the control gate 2062 and the second sub-floating gate layer 2042, the control gate 2062 and the second sub-floating gate layer 2042 are located on both sides of the isolation opening 2061, and the second sub-floating gate layer 2042, the control gate and the isolation opening 2061 are adjacent, the second sub-floating gate layer 2042 and the isolation opening 2061 are adjacent to the second sub-floating gate layer 2042, and the first sub-floating gate layer 2041 and the second sub-floating gate layer 2042 constitute the floating gate 204.

[0062] The isolation opening 2061 is used to separate the control gate layer 206 into the control gate and the second sub-floating gate.

[0063] In some embodiments of the present invention, the thickness of the first sub-floating gate layer 2041 ranges from 450 angstroms to 700 angstroms, the thickness of the second sub-floating gate layer 2042 ranges from 1500 angstroms to 1900 angstroms, and the thickness of the control gate 2062 ranges from 1950 angstroms to 2600 angstroms.

[0064] In the above scheme, the cumulative thickness of the first sub-floating gate layer 2041 and the thickness of the second sub-floating gate layer 2042 can increase the thickness of the floating gate 204, thereby increasing the etching window of the floating gate 204, avoiding the problem of perforation and electrical breakdown caused by the floating gate 204 being too thin, and improving the performance of the capacitor in the storage structure.

[0065] In this embodiment, the control gate 2062, the control gate dielectric layer 205 and the floating gate 204 constitute a first PIP capacitor, the floating gate 204, the floating gate dielectric layer 203 and the substrate 200 constitute a second PIP capacitor, and the first PIP capacitor and the second PIP capacitor are connected in parallel.

[0066] In a specific embodiment, it also includes: etching and removing the control gate dielectric layer 205 on the side of the second sub-floating gate layer 2042 away from the isolation opening 2061, so that the first sub-floating gate layer 2041 is exposed on both sides of the second sub-floating gate layer 2042 to isolate the second sub-floating gate layer 2042 and the control gate 2062.

[0067] In some embodiments of the present invention, the process of etching the control gate dielectric layer 205 under the isolation opening 2061 is dry etching, and the process parameters are: the etching gas is C x F x , O2, Ar and He, the etching gas flow rate is 4 sccm to 200 sccm, the bias voltage is 0V to 400V, the etching pressure is 4 mTorr to 40mTorr, and the etching time is 6s to 33s.

[0068] In other embodiments of the present invention, the further embodiment further includes: performing ion implantation on the substrate 200 to form a well region (not shown in the figure) within the substrate and source / drain regions (not shown in the figure) within the well region.

[0069] Specifically, the type of ions implanted into the well region is opposite to the type of ions implanted into the source / drain region.

[0070] In one embodiment, the type of the implanted ions in the well region is N-type, and the type of the implanted ions in the source / drain region is P-type.

[0071] In another embodiment, the type of the implanted ions in the well region is P-type, and the type of the implanted ions in the source / drain region is N-type.

[0072] In this embodiment, the doping ions in the source / drain region include: oxygen ions and / or nitrogen ions

[0073] In other embodiments, the method further includes forming a metal silicide layer (not shown in the figure) on the surface of the source / drain region, the control gate, and the surface of the second sub-floating gate layer.

[0074] In some embodiments of the present invention, the step of forming the metal silicide layer includes: forming a metal layer on the top surface of the storage gate and the surface of the source / drain region; performing an annealing process to cause the metal layer to react with the substrate, the top surface of the control gate and the top surface of the second sub-floating gate layer to form a metal silicide layer.

[0075] In this embodiment, the method for forming the metal layer is a physical vapor deposition process, and the parameters of the physical vapor deposition process are: a deposition rate of 350 angstroms per minute to 450 angstroms per minute, and a deposition time of 12 seconds to 20 seconds.

[0076] The metal layer is made of nickel-platinum alloy, titanium or cobalt, and the thickness of the metal layer is in a range of 80 angstroms to 130 angstroms.

[0077] In this embodiment, the metal layer, the control gate, the top surface of the second sub-floating gate layer and the substrate surface are subjected to an annealing process so that the metal layer, the control gate, the top surface of the second sub-floating gate layer and the substrate surface react to form a metal silicide layer.

[0078] In this embodiment, the steps of performing annealing process treatment include: performing a first sub-annealing process treatment on the metal layer, the control gate, the top surface of the second sub-floating gate layer and the surface of the substrate, so that the metal layer and the top surface of the control gate and the second sub-floating gate layer and the surface of the substrate react to form a high-resistance metal silicide layer; performing a second sub-annealing process treatment on the high-resistance metal silicide layer to cause the high-resistance metal silicide layer to undergo a phase change reaction to form a metal silicide layer.

[0079] In this embodiment, the first annealing process adopts a rapid thermal annealing furnace, and the process parameters of the first annealing process are: annealing temperature of 200° C. to 350° C., and annealing time of 15 seconds to 45 seconds.

[0080] In this embodiment, the second annealing process adopts a rapid thermal annealing furnace, and the process parameters of the second annealing process are: annealing temperature of 300° C. to 600° C., and time of 15 seconds to 45 seconds.

[0081] In this embodiment, after the first partial annealing process, the method further includes: removing the first metal layer that does not react with silicon by wet etching to prevent bridging and causing circuit short circuit.

[0082] The temperature of the first sub-annealing process is lower than the temperature of the second sub-annealing process. In the first sub-annealing process, the annealing temperature is 200°C to 350°C. The first metal layer will only react with the top surface of the storage gate and the surface of the substrate 200200 to form a high-resistance metal silicide layer. If the annealing temperature is outside the range of 200°C to 350°C, it will cause the first metal layer to react incompletely or over-react with the top surface of the storage gate and the surface of the substrate 200200.

[0083] In the second annealing process, the annealing temperature is 300°C to 600°C, which converts the high-resistance metal silicide layer into a low-resistance metal silicide layer. If the annealing temperature is outside the range of 300°C to 600°C, the high-resistance metal silicide layer will not be completely converted into a low-resistance metal silicide layer.

[0084] In the above scheme, two annealing processes are used to form the metal silicide layer, avoiding the problem of short circuit caused by generating a low-resistance metal silicide layer through only one annealing process. Specifically, the process temperature under the single annealing process will be very high. In such a high-temperature environment, silicon can diffuse along the grain boundaries of the metal silicide layer 306, resulting in excessive growth of the metal silicide layer above the silicon oxide boundary, and subsequent wet etching cannot remove the metal silicide layer on the oxide, causing a short circuit.

[0085] In this embodiment, the material of the metal silicide layer is NiSi containing Pt, and the thickness of the metal silicide layer ranges from 200 angstroms to 400 angstroms.

[0086] Please refer to Figure 12 , depositing an interlayer dielectric layer 207 on the substrate 200; etching the interlayer dielectric layer 207 to form a contact hole (not shown in the figure) located on the control gate 2062, the second sub-floating gate layer 2042, and the substrate 200; filling the contact hole with a conductive material to form a conductive plug 208, and the conductive plug 208 is located on the control gate 2062, the second sub-floating gate layer 2042, and the substrate 200.

[0087] In this embodiment, the top surface of the control gate 2062 serves as the upper plate of the first PIP capacitor. A conductive plug 208 is formed on the top surface of the control gate 2062 to lead out the upper plate of the first PIP capacitor. The top surface of the floating gate 204 serves as the upper plate of the second PIP capacitor. A conductive plug 208 is formed on the top surface of the floating gate 204 to lead out the upper plate of the second PIP capacitor.

[0088] In one embodiment of the present invention, a conductive material is filled into the interlayer dielectric layer 207 through a deposition process to form a conductive plug 208 .

[0089] In this embodiment, the conductive plug 208 is formed by a chemical vapor deposition process or a physical vapor deposition process.

[0090] In this embodiment, the conductive plug 208 is made of copper, aluminum, or tungsten.

[0091] In this embodiment, since the tops of the floating gate 204 and the control gate 2062 are flush, contact holes can be formed on the control gate 2062, the second sub-floating gate layer 2042 and the substrate 200 simultaneously through one mask, thereby simplifying the process steps.

[0092] In summary, by forming the connection opening 2051 on the control gate dielectric layer 205, the surface of the first sub-floating gate layer 2041 is exposed, so that when the control gate layer 206 is subsequently formed, part of the control gate layer 206 can contact the surface of the first sub-floating gate layer 2041. Subsequently, an isolation opening 2061 is formed in the control gate layer 206 to divide the control gate layer 206 into a control gate 2062 located on the control gate dielectric layer 205 and a second sub-floating gate layer 2062 located on the first sub-floating gate layer 2041. 042. Compared with the prior art, the present invention adds a second sub-floating gate layer 2042 on the basis of the first sub-floating gate layer 2041, thereby increasing the thickness of the floating gate 204. When a contact hole is subsequently formed on the floating gate 204, an etching window for the floating gate is increased, thereby avoiding the problem of perforation and electrical breakdown caused by the floating gate 204 being too thin, thereby improving the performance of the capacitor in the storage structure; and the top surface of the floating gate 204 is flush with the control gate 2062, and only one mask is required to form the contact hole subsequently, thereby simplifying the process steps.

[0093] Please refer to Figure 12 The present invention further provides a memory structure, comprising: a substrate 200, the substrate 200 comprising a plurality of active regions 202 and isolation regions 201 located on both sides of the active regions 202; a first sub-floating gate layer 2041 located on the substrate 200; a control gate dielectric layer 205 located on the first sub-floating gate layer 2041, the control gate dielectric layer 205 having a connection opening 2051 and an isolation opening 2061, the connection opening 2051 exposing the surface of the first sub-floating gate layer 2041. The surface of the first sub-floating gate layer 2041 is exposed by the isolation opening 2061; the control gate 2062 is located on the control gate dielectric layer 205; the second sub-floating gate layer 2042 is located on the connection opening 2051, the second sub-floating gate layer 2042 is flush with the control gate 2062, and the second sub-floating gate layer 2042 is isolated from the control gate by the isolation opening 2061, and the first sub-floating gate layer 2041 and the second sub-floating gate layer 2042 constitute a floating gate 2041.

[0094] In this embodiment, the thickness of the first sub-floating gate layer 2041 ranges from 450 angstroms to 700 angstroms, the thickness of the second sub-floating gate layer 2042 ranges from 1500 angstroms to 1900 angstroms, and the thickness of the control gate 2062 ranges from 1950 angstroms to 2600 angstroms.

[0095] In this embodiment, the memory structure further includes a floating gate dielectric layer 203 located on the substrate 200 .

[0096] In this embodiment, the memory structure further includes: an interlayer dielectric layer 207 located on the substrate 200; and a conductive plug 208 located on the interlayer dielectric layer 207, and the conductive plug 208 is located on the control gate 2062, the second sub-floating gate layer 2042 and the substrate 200.

[0097] In this embodiment, the material of the control gate dielectric layer 205 is a combination of silicon nitride and silicon oxide.

[0098] In the above scheme, the floating gate includes a first sub-floating gate layer 2041 and a second sub-floating gate layer 2042, which increases the thickness of the floating gate 204. When a contact hole is subsequently formed on the floating gate 204, the etching window of the floating gate 204 is increased, avoiding the problem of perforation and electrical breakdown caused by the floating gate 204 being too thin, thereby improving the performance of the capacitor in the storage structure.

[0099] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a memory structure, characterized in that: include: Providing a substrate, wherein the substrate includes a plurality of active regions and isolation regions located on both sides of the active regions; forming a first sub-floating gate layer and a control gate dielectric layer in sequence on the active area; forming a first photoresist layer on the control gate dielectric layer; Developing and exposing the first photoresist layer to form a first photoresist layer having a connection opening pattern; Using the first photoresist layer having the connection opening pattern as a mask, etching the control gate dielectric layer until the surface of the first sub-floating gate layer is exposed to form a connection opening; forming a control gate layer on the control gate dielectric layer, wherein the control gate layer completely fills the connection opening; forming a second photoresist layer on the control gate layer; developing and exposing the second photoresist layer to form a second photoresist layer having an isolation opening pattern; Using a second photoresist layer having an isolation opening pattern as a mask, the control gate layer and the control gate dielectric layer are etched until the surface of the first sub-floating gate layer is exposed to form an isolation opening, a control gate, and a second sub-floating gate layer. The control gate and the second sub-floating gate layer are located on both sides of the isolation opening, and the second sub-floating gate layer, the control gate, and the isolation opening are adjacent to each other, and the second sub-floating gate layer and the isolation opening are adjacent to each other. The first sub-floating gate layer and the second sub-floating gate layer constitute a floating gate.

2. The method for forming a memory structure according to claim 1, wherein: The thickness of the first sub-floating gate layer ranges from 450 angstroms to 700 angstroms, the thickness of the second sub-floating gate layer ranges from 1500 angstroms to 1900 angstroms, and the thickness of the control gate ranges from 1950 angstroms to 2600 angstroms.

3. The method for forming a memory structure according to claim 1, wherein: The process of etching the control gate layer is dry etching, and the process parameters are: etching gas is C x F x , one or more combinations of HBr, CL2, O2, Ar and He, the etching gas flow rate is 4 sccm to 220 sccm, the bias voltage is 50 V to 250 V, the etching pressure is 5 mTorr to 60 mTorr, and the etching time is 8 s to 65 s.

4. The method for forming a memory structure according to claim 1, wherein: The process of etching the control gate dielectric layer under the isolation opening is dry etching, and the process parameters are: etching gas is C x F x , O2, Ar and He, the etching gas flow rate is 4 sccm to 200 sccm, the bias voltage is 0V to 400V, the etching pressure is 4 mTorr to 40mTorr, and the etching time is 6s to 33s.

5. The method for forming a memory structure according to claim 3, wherein: After the step of etching the control gate dielectric layer below the isolation opening, the method further includes: depositing an interlayer dielectric layer on the substrate; Etching the interlayer dielectric layer to form contact holes on the control gate, the second sub-floating gate layer, and the substrate; A conductive material is filled into the contact hole to form a conductive plug, wherein the conductive plug is located on the control gate, the second sub-floating gate layer and the substrate.

6. The method for forming a memory structure according to claim 1, wherein: Before the step of forming the first sub-floating gate layer, the method further includes: forming a floating gate dielectric layer on the substrate; After the step of forming the first sub-floating gate layer, the method further includes: The isolation region is etched until the sidewall surface of the first sub-floating gate layer is exposed.

7. The method for forming a memory structure according to claim 1, wherein: The material of the control gate dielectric layer is a combination of silicon nitride and silicon oxide.

8. A memory structure, characterized in that: include: A substrate comprising a plurality of active regions and isolation regions located on both sides of the active regions; A first sub-floating gate layer, located on the substrate; a control gate dielectric layer located on the first sub-floating gate layer, the control gate dielectric layer having a connection opening and an isolation opening, the connection opening exposing a surface of the first sub-floating gate layer, and the isolation opening exposing a surface of the first sub-floating gate layer; a control gate located on the control gate dielectric layer; The second sub-floating gate layer is located on the connection opening and is flush with the control gate. The second sub-floating gate layer is isolated from the control gate through the isolation opening. The first sub-floating gate layer and the second sub-floating gate layer constitute a floating gate.

9. The memory structure according to claim 8, wherein: The thickness of the first sub-floating gate layer ranges from 450 angstroms to 700 angstroms, the thickness of the second sub-floating gate layer ranges from 1500 angstroms to 1900 angstroms, and the thickness of the control gate ranges from 1950 angstroms to 2600 angstroms.

10. The memory structure according to claim 8, wherein: Also includes: A floating gate dielectric layer is located on the substrate.

11. The memory structure according to claim 8, wherein: Also includes: an interlayer dielectric layer located on the substrate; and a conductive plug located in the interlayer dielectric layer, wherein the conductive plug is located on the control gate, the second sub-floating gate layer and the substrate.

12. The memory structure according to claim 8, wherein: The material of the control gate dielectric layer is a combination of silicon nitride and silicon oxide.

Images