Preparation method of sub-nano node transistor based on non-EUV technology

Abstract

The invention discloses a preparation method of a sub-nanometer node transistor based on a non-EUV technology, and the method comprises the steps: enabling a source electrode, a drain electrode and an electrode isolation layer of the transistor to be manufactured in three steps, enabling the distance between the source electrode and the drain electrode to be determined by the thickness of the isolation layer, and achieving the transistor with the ultra-short channel length of 1-10 nanometers. Aiming at the problems of low single precision, expensive equipment and the like of an EUV photoetching scheme, lateral ALD growth of a medium on the side wall of an electrode is realized by utilizing the surface hydrophilicity difference between a semiconductor and the electrode, the medium is used as an electrode isolation layer, and the channel length of the transistor is controlled through the growth thickness of the medium; due to the control advantage of the ALD method on the thickness of the medium, the single process precision is 1 nanometer and is far superior to the single process precision of the existing EUV photoetching equipment, the microelectronic manufacturing process flow is greatly simplified, and the device yield is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic sub-nanometer advanced technology node manufacturing, and specifically relates to a method for preparing a sub-nanometer node transistor using non-EUV technology. Background Art

[0002] The integrated circuit industry has been following Moore's Law for many years, using a generation-by-generation miniaturization method to continuously improve the integration and performance of silicon-based chips. So far, silicon-based Moore's Law has reached its peak, and the actual channel length of silicon-based transistors ends at 12 nanometers, that is, the 1-nanometer technology node. Two-dimensional van der Waals semiconductors can continuously miniaturize the channel length to below 10 nanometers, making them an important candidate material for subsequent sub-nanometer technology nodes.

[0003] The minimum line width of transistors in microelectronics processes is mainly determined by the wavelength of the lithography machine. Currently, the single exposure accuracy of extreme ultraviolet (EUV) lithography is 13 nanometers. Therefore, the use of EUV solutions to prepare transistors with a channel length of sub-10 nanometers (especially 3 to 7 nanometers) requires multiple exposures, which greatly affects the process complexity and device yield. Other methods for large-scale preparation of ultra-short channel transistors have also been reported, but they generally have problems such as low process resolution, poor controllability, and CMOS compatibility.

[0004] For example, DJ Beesley et al. disclosed in the paper "Sub-15-nm patterning of asymmetric metal electrodes and devices by adhesion lithography", Nat. Commun, 5, 3933 (2014) a method for preparing sub-15 nanometer ultra-short metal electrode pairs and short-channel transistors by orderly and compact self-assembly of organic molecules on the sidewalls of gold electrodes. Since the method relies on factors such as the affinity between the terminal chemical bonds of organic molecules and the metal electrodes and the coverage of the sidewall self-assembly, it has problems such as poor material universality and low process yield.

[0005] For example, R. Wu et al. disclosed in the paper "Bilayer Tungsten Diselenide Transistors with On-state Currents Exceeding 1.5 Milliamperes per Micrometer", Nat. Electron., 5, 497 (2022) a scheme for obtaining ultrashort electrode pairs using nanoscale cracks in two-dimensional materials, achieving a minimum electrode spacing of 2 nanometers. Due to the large randomness of the natural crack positions and distances of the material, this scheme is not compatible with large-scale preparation processes.

[0006] Chinese patent CN117594449A (publication date: February 23, 2024) discloses a vertical self-aligned dual-gate transistor and a method for preparing the same, which relates to the field of semiconductor device technology and solves the problem of high manufacturing cost of thin-film transistors in the prior art. The method comprises the following steps: sequentially forming a stack of a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, and a third metal layer, wherein the first metal layer and the third metal layer are the source and the drain, respectively, and the second metal layer is the gate; etching the stack to form a groove to expose the first metal layer; oxidizing the sidewall of the second metal layer at the groove in the stack after etching to form a first gate dielectric and a second gate dielectric; filling the groove with semiconductor material to form a channel layer; and forming a channel passivation layer on the channel layer by deposition technology.

[0007] Chinese patent CN118486711A (publication date: August 13, 2024) discloses a silicon carbide trench gate insulated gate bipolar transistor and a method for manufacturing the same, which relates to the field of semiconductor device technology. The silicon carbide trench gate insulated gate bipolar transistor includes an emitter region, a base region, a drift layer and a substrate arranged in stacked contact, the four forming a PNPN structure or an NPNP structure; the device structure forms heteroepitaxial single crystal silicon doping at the bottom and sidewall of the trench through selective epitaxial growth technology, which significantly improves the device channel carrier mobility.

[0008] After searching, it was found that although there are currently a small number of patents on methods for preparing transistors, there is still a gap in methods for preparing sub-nanometer transistors.

[0009] In summary, there is still a lack of low-cost, high-precision, CMOS process-compatible manufacturing methods for sub-nanometer node ultra-short channel transistors and arrays. Summary of the invention

[0010] In order to solve the above technical problems, the present invention provides a method for preparing a sub-nanometer node transistor using non-EUV technology.

[0011] A method for preparing a sub-nanometer node transistor using non-EUV technology comprises the following steps:

[0012] Step S1, preparing a semiconductor and gate-controlled composite structure: the semiconductor and gate-controlled composite structure is a multilayer structure or silicon on an insulating layer prepared by ion implantation;

[0013] Step S2, making a source metal electrode: making a source electrode on one side of the transistor on the semiconductor and gate-controlled composite structure;

[0014] Step S3, making an electrode isolation layer: according to the difference in hydrophilicity and hydrophobicity between the semiconductor and the source electrode, an electrode isolation layer is selectively deposited on the side wall of the source electrode using atomic layer deposition (ALD) technology;

[0015] Step S4, making a drain metal electrode: making a drain electrode on the other side of the transistor close to the source electrode covered with the electrode isolation layer, so as to form a single ultra-short channel transistor between the source electrode, the electrode isolation layer and the drain electrode.

[0016] Furthermore, the thickness of the electrode isolation layer in step S3 is precisely controlled to be between 1 and 10 nanometers, preferably between 3 and 7 nanometers.

[0017] Furthermore, if top gate control needs to be added, the preparation method further includes step S5: surface planarization; removing excess surface material through a surface planarization process to obtain a flat upper surface to facilitate subsequent processes.

[0018] Furthermore, when the semiconductor and gate-controlled composite structure in step S1 is a multilayer structure, the preparation method includes the following steps:

[0019] Step S101, preparing a bottom gate: preparing a metal bottom gate on an insulating substrate;

[0020] Step S102, preparing a bottom gate dielectric: preparing a bottom gate dielectric on the metal bottom gate;

[0021] Step S103, preparing semiconductor channel material: preparing semiconductor channel material on the bottom gate dielectric.

[0022] Furthermore, the insulating substrate in step S101 includes one or more of sapphire, low-resistance silicon, silicon on insulator, silicon with a surface insulating layer, and a chip with a surface insulating layer;

[0023] The metal bottom gate is a global gate or a local gate.

[0024] Furthermore, in step S102, the bottom gate dielectric is a high-κ dielectric, and its preparation method includes one or more of atomic layer deposition, chemical vapor deposition, physical vapor deposition, pulsed laser deposition, and electron beam evaporation;

[0025] The high-κ medium includes one or more of HfO2, Al2O3, Ta2O5, TiO2, La2O3, and HfZrO4.

[0026] Furthermore, the method for preparing the semiconductor channel material on the bottom gate dielectric in step S103 includes one or more of deposition, transfer, and ion implantation.

[0027] Furthermore, the semiconductor channel material in step S103 is a semiconductor with a bandgap, including one or more of two-dimensional metal chalcogenides, Si, Ge, carbon nanotubes, GaAs, GaN, SiC, diamond, and ZnO;

[0028] The preparation method of the semiconductor channel material includes one or more of mechanical transfer, bonding, chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation, and ion implantation.

[0029] Furthermore, when the semiconductor channel material 203 in step S103 is a hydrophobic semiconductor, no hydrophobic treatment is required; when the semiconductor channel material 203 is a hydrophilic semiconductor, a hydrophobic treatment is performed.

[0030] Further, the source electrode in step S2 includes one or more of two-dimensional layered metal, Ni, Cr, Au, Ag, Cu, Co, Ru, Pt, Pd, Sb, Bi, and Al;

[0031] Further, the electrode isolation layer in step S3 includes one or more of HfO2, SiO2, Al2O3, Ta2O5, TiO2, La2O3, HfZrO4, and organic medium;

[0032] Further, the drain electrode in step S4 includes one or more of two-dimensional layered metal, Ni, Cr, Au, Ag, Cu, Co, Ru, Pt, Pd, Sb, Bi, and Al;

[0033] The width and patterning of the source electrode and the drain electrode are produced by deep ultraviolet or electron beam lithography; the number of lithography times is single or multiple.

[0034] Compared with the prior art, the advantages and effects of the present invention are as follows:

[0035] 1. The present invention provides a method for manufacturing sub-nanometer node transistors without EUV technology, which uses low-cost ALD equipment instead of expensive EUV lithography to define the minimum line width of transistors, greatly saving process costs.

[0036] 2. The present invention provides a method for manufacturing sub-nanometer node transistors using non-EUV technology, by separately manufacturing the source electrode, the electrode isolation layer and the drain electrode so that the distance between the source and drain electrodes is determined by the thickness of the electrode isolation layer, thereby defining the channel length of the transistor.

[0037] 3. The present invention provides a non-EUV technology sub-nanometer node transistor manufacturing method, which adopts ALD dielectric thickness precise control and has a single process precision of 1 nanometer, which is much better than the single process precision (13 nanometers) of existing EUV lithography equipment, and can simplify the process flow and improve the device yield.

[0038] 4. The present invention provides an application of a method for manufacturing sub-nanometer node transistors using non-EUV technology. The method is compatible with existing microelectronic CMOS processes and is suitable for large-scale industrial applications.

[0039] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application so that it can be implemented in accordance with the contents of the specification, and to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following is a detailed description of the preferred embodiments of the present application in conjunction with the accompanying drawings as follows.

[0040] Based on the detailed description of the specific embodiments of the present application in combination with the accompanying drawings below, those skilled in the art will become more aware of the above and other objects, advantages and features of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In all drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale.

[0042] in:

[0043] Figure 1 The present invention is a method for preparing a sub-nanometer node transistor using non-EUV technology. Figure 1 ;

[0044] Figure 2 A schematic diagram of the sub-nanometer node transistor structure prepared by the present invention;

[0045] Figure 3 This is a cross-sectional TEM image of a 3-nanometer ultra-short channel length transistor prepared by the present invention;

[0046] Figure 4 A schematic diagram of a multilayer structure prepared by the present invention;

[0047] Figure 5 The present invention is a non-EUV technology sub-nanometer node transistor preparation process Figure 2 ;

[0048] Figure 6 It is a schematic diagram of the transistor structure after the surface flattening process in the present invention.

[0049] Figure numerals: 100 - semiconductor and gate-controlled composite structure; 200 - insulating substrate; 201 - metal bottom gate; 202 - bottom gate dielectric; 203 - semiconductor channel; 204 - source electrode; 205 - electrode isolation layer; 206 - drain electrode. DETAILED DESCRIPTION

[0050] To make the purpose, technical scheme and advantages of the embodiment of the present application clearer, the technical scheme in the embodiment of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present application. Obviously, the described embodiment is a part of the embodiment of the present application, rather than all of the embodiments. In the following description, specific details such as specific configuration and components are provided only to help fully understand the embodiments of the present application. Therefore, it should be clear to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. In addition, for clarity and brevity, the description of known functions and structures is omitted in the embodiment.

[0051] It should be understood that the references to "one embodiment" or "this embodiment" throughout the specification mean that the specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present application. Therefore, the references to "one embodiment" or "this embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0052] In addition, the present application may repeat reference numerals and / or letters in different examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0053] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist at the same time. The term " / and" in this article describes another type of association object relationship, indicating that there can be two relationships. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " in this article generally indicates that the previous and next associated objects are in an "or" relationship.

[0054] The term "at least one" in this article is merely a description of the association relationship of associated objects, indicating that there may be three relationships. For example, at least one of A and B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0055] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusions.

[0056] Example 1

[0057] This embodiment is a method for preparing sub-nanometer node transistors using non-EUV technology.

[0058] Please refer to Figure 1 , which is a preparation process of a sub-nanometer node transistor using non-EUV technology of the present invention Figure 1 .

[0059] A method for preparing a sub-nanometer node transistor using non-EUV technology comprises the following steps:

[0060] Step S1, preparing a semiconductor and gate-controlled composite structure 100: the semiconductor and gate-controlled composite structure 100 is a multi-layer structure or silicon on an insulating layer prepared by ion implantation.

[0061] Step S2 , manufacturing a source metal electrode 204 : manufacturing a source electrode 204 on one side of the transistor on the semiconductor and gate-controlled composite structure 100 .

[0062] Step S3 , manufacturing the electrode isolation layer 205 : using the atomic layer deposition ALD technology to selectively deposit the electrode isolation layer 205 on the sidewall of the source electrode 204 according to the different hydrophilicity and hydrophobicity of the composite structure 100 and the source electrode 204 .

[0063] Step S4, making a drain metal electrode 206: making the drain electrode 206 on the other side of the transistor close to the source electrode 204 covered with the electrode isolation layer 205, so as to form a single ultra-short channel transistor between the source electrode 204, the electrode isolation layer 205 and the drain electrode 206.

[0064] Furthermore, the thickness of the electrode isolation layer in step S3 is precisely controlled to be between 1 and 10 nanometers, preferably between 3 and 7 nanometers.

[0065] Please refer to Figure 2 , Figure 2This is a schematic diagram of the sub-nanometer node transistor structure prepared by the present invention. Above the semiconductor and gate-controlled composite structure 100, there are a source electrode 204, an electrode isolation layer 205 and a drain electrode 206. The electrode isolation layer 205 is between the source electrode 204 and the drain electrode 206, so that the distance between the source and drain electrodes is determined by the thickness of the electrode isolation layer, thereby defining the channel length of the transistor. In this schematic diagram, there are drain electrodes 206 on both sides of the source electrode 204, defining two transistors.

[0066] Please refer to Figure 3 , Figure 3 This is a cross-sectional TEM image of a single 3-nanometer ultra-short channel length transistor prepared according to the above method. The thickness of the electrode isolation layer 205 is precisely controlled at 3 nanometers.

[0067] The technical effect of this embodiment is to provide a sub-nanometer node transistor manufacturing method without EUV technology. Different from the electrode self-alignment technology of transistors, the source electrode, electrode isolation layer, and drain electrode in the transistor preparation method of the present invention are prepared independently in three steps. The electrode isolation layer adopts ALD dielectric thickness precise control, and the single process precision is 1 nanometer, which is much better than the single process precision of existing EUV lithography equipment (13 nanometers), which can simplify the process flow and improve the device yield. In addition, the use of low-cost ALD equipment instead of expensive EUV lithography to produce the minimum line width of transistors greatly saves process costs.

[0068] Example 2

[0069] Based on Example 1, this example is a method for preparing a multi-layer semiconductor and gate-controlled composite structure.

[0070] Please refer to Figure 4 , Figure 4 Schematic diagram of a multilayer structure prepared by the present invention; the preparation method of the multilayer structure comprises the following steps:

[0071] Step S101 , preparing a bottom gate: preparing a metal bottom gate 201 on an insulating substrate 200 .

[0072] Step S102 , preparing a bottom gate dielectric: preparing a bottom gate dielectric 202 on the metal bottom gate 201 .

[0073] Step S103 , preparing semiconductor channel material: preparing semiconductor channel material 203 on the bottom gate dielectric 202 .

[0074] Furthermore, the insulating substrate 200 in step S101 includes one or more of sapphire, low-resistance silicon, silicon on insulator, silicon with a surface insulating layer, and a chip with a surface insulating layer;

[0075] The metal bottom gate 201 is a global gate or a local gate.

[0076] Furthermore, in step S102, the bottom gate dielectric 202 is a high-κ dielectric, and its preparation method includes one or more of atomic layer deposition, chemical vapor deposition, physical vapor deposition, pulsed laser deposition, and electron beam evaporation;

[0077] The high-κ medium includes one or more of HfO2, Al2O3, Ta2O5, TiO2, La2O3, and HfZrO4.

[0078] Furthermore, the method for preparing the semiconductor channel material 203 on the bottom gate dielectric 202 in step S103 includes one or more of deposition, transfer, and ion implantation.

[0079] Furthermore, the semiconductor channel material 203 in step S103 is a semiconductor with a bandgap, including one or more of two-dimensional metal chalcogenides, Si, Ge, carbon nanotubes, GaAs, GaN, SiC, diamond, and ZnO;

[0080] The preparation method of the semiconductor channel material 203 includes one or more of mechanical transfer, bonding, chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation, and ion implantation.

[0081] Furthermore, the contact angle between the sidewall metal of the source electrode 204 and water is between 0-90°, which is hydrophilic, and the contact angle between the semiconductor channel material 203 and water is between 90-180°, which is hydrophobic.

[0082] Furthermore, when the semiconductor channel material 203 in step S103 is a hydrophobic semiconductor, no hydrophobic treatment is required; when the semiconductor channel material 203 is a hydrophilic semiconductor, hydrophobic treatment is performed.

[0083] The technical effect of this embodiment is as follows: according to the design and process requirements, the gate is defined as a global gate or a local gate; the channel material is pre-treated for hydrophobicity according to the situation, and the electrode isolation layer is controllably deposited on the electrode sidewall by utilizing the difference in hydrophilicity between the electrode sidewall and the semiconductor channel.

[0084] Example 3

[0085] Based on Example 1, this example is a further process consideration of a method for preparing a sub-nanometer node transistor using non-EUV technology, such as adding top gate control. Figure 5 , which is a preparation process of a sub-nanometer node transistor using non-EUV technology of the present invention Figure 2 Please refer to Figure 6 , Figure 6 Schematic diagram of a device after surface planarization.

[0086] Furthermore, in obtaining Figure 2After the sub-nanometer node transistor is formed, in order to further prepare a top gate composite structure to enhance the gate control capability of the channel, step S5 may be used to perform surface planarization to remove excess surface material.

[0087] Technical effect of this embodiment: The present invention provides a method for manufacturing sub-nanometer node transistors without EUV technology, which can further improve device performance by flattening the surface and then preparing a top-gate composite structure on the flat surface. The method is compatible with existing microelectronic CMOS processes and is suitable for large-scale industrial applications.

[0088] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a sub-nanometer node transistor using non-EUV technology, characterized in that: The following steps are included: Step S1, preparing a semiconductor and gate-controlled composite structure (100): the semiconductor and gate-controlled composite structure (100) is a multilayer structure or silicon on an insulating layer prepared by ion implantation; Step S2, making a source metal electrode (204): making a source electrode (204) on one side of the transistor on the semiconductor and gate-controlled composite structure (100); Step S3, manufacturing an electrode isolation layer (205): using an atomic layer deposition (ALD) technique to deposit an electrode isolation layer (205) on the side wall of the source electrode (204); Step S4, making a drain metal electrode (206): making a drain electrode (206) on the other side of the transistor close to the source electrode (204) coated with the electrode isolation layer (205), thereby forming an ultra-short channel transistor between the source electrode (204), the electrode isolation layer (205) and the drain electrode (206).

2. The method for preparing a sub-nanometer node transistor using non-EUV technology according to claim 1, characterized in that: The thickness of the electrode isolation layer (205) in step S3 is precisely controlled to be between 1 and 10 nanometers, preferably between 3 and 7 nanometers.

3. The method for preparing a sub-nanometer node transistor using non-EUV technology according to claim 1, characterized in that: If the preparation method needs to further increase top gate control, it also includes step S5: surface flattening; removing excess surface material through a surface flattening process to obtain a flat upper surface to facilitate subsequent processes.

4. The method for preparing a sub-nanometer node transistor using non-EUV technology according to claim 1, characterized in that: When the semiconductor and gate-controlled composite structure in step S1 is a multilayer structure, the preparation method comprises the following steps: Step S101, preparing a bottom gate; preparing a metal bottom gate (201) on an insulating substrate (200); Step S102, preparing a bottom gate dielectric; preparing a bottom gate dielectric (202) on the metal bottom gate (201); Step S103, preparing a semiconductor channel material; preparing a semiconductor channel material (203) on the bottom gate dielectric (202).

5. The method for preparing a sub-nanometer node transistor using non-EUV technology according to claim 4, characterized in that: The insulating substrate (200) in step S101 includes one or more of sapphire, low-resistance silicon, silicon on insulator, silicon with a surface insulating layer, and a chip with a surface insulating layer; The metal bottom gate (201) is a global gate or a local gate.

6. The method for preparing a sub-nanometer node transistor using non-EUV technology according to claim 4, characterized in that: The method for preparing the semiconductor channel material (203) on the bottom gate dielectric (202) in step S103 includes one or more of deposition, transfer, and ion implantation.

7. The method for preparing a sub-nanometer node transistor using non-EUV technology according to claim 4, characterized in that: In step S103, when the semiconductor channel material (203) is a hydrophobic semiconductor, no hydrophobic treatment is required; when the semiconductor channel material (203) is a hydrophilic semiconductor, hydrophobic treatment is required.

Images