A metal oxide thin film transistor and a method of manufacturing the same

Abstract

The application relates to an oxide thin film transistor, comprising a substrate; an active layer located above the substrate, comprising a channel region and source-drain regions; a hydrogen absorption layer located above the active layer, wherein a part of the hydrogen absorption layer located above the channel region is removed; a hydrogen-rich sealing insulation layer located above the hydrogen absorption layer, wherein a part of the hydrogen-rich sealing insulation layer located above the channel region is removed; a top gate dielectric layer located above the hydrogen-rich sealing insulation layer and the channel region of the active layer; a top gate located above the top gate dielectric layer; and a source electrode and a drain electrode respectively in contact with the hydrogen absorption layer on both sides of the channel region.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of microelectronics, in particular to a metal oxide thin film transistor and a preparation method thereof. BACKGROUND

[0002] Small size metal oxide semiconductor thin film transistors (TFTs) are widely used in consumer electronics such as smart wearable electronic products due to their high performance and high flexibility, and the performance requirements are becoming increasingly stringent.

[0003] Traditional metal oxide semiconductor thin film transistors (TFTs) mainly include a back gate structure and a self-aligned top gate structure. There is a large overlap capacitance between the source and drain and the gate of the back gate structure TFT. For the TFT device with continuously shrinking size, the overlap capacitance greatly affects the working speed. In contrast, the self-aligned gate-source / drain TFT structure is more suitable for small size TFT devices because there is no overlap capacitance. In the self-aligned gate-source / drain TFT structure, the high conductivity of the source and drain region is usually achieved by introducing a large number of defects through argon (Ar) plasma bombardment of the source and drain region. With the further shrinking of the TFT device size, the diffusion of the source and drain defects cannot be ignored, which causes the threshold voltage to negatively drift, thereby affecting the switching capability of the TFT device. In addition, the introduced source and drain defects have poor thermal stability, which limits the application of the top gate self-aligned TFT in three-dimensional integrated circuits with complex thermal processes. SUMMARY

[0004] To solve the technical problems in the prior art, the present application provides an oxide thin film transistor, which comprises: a substrate; an active layer located above the substrate and comprising a channel region and a source and drain region; a hydrogen absorption layer located above the active layer, wherein a portion of the hydrogen absorption layer located above the channel region is removed; a hydrogen-rich sealing insulation layer located above the hydrogen absorption layer, wherein a portion of the hydrogen-rich sealing insulation layer located above the channel region is removed; a top gate dielectric layer located above the hydrogen-rich sealing insulation layer and the channel region; a top gate located above the top gate dielectric layer; and a source and a drain respectively in contact with the hydrogen absorption layer on both sides of the channel region.

[0005] In particular, the key point of the structure of the oxide thin film transistor provided by the present application is that the hydrogen absorption layer can absorb hydrogen in the channel region and the hydrogen-rich sealing insulation layer, forming a highly resistive channel region and improving the conductivity of the source and drain region.

[0006] In particular, the oxide thin film transistor further comprises: a hydrogen barrier layer above the substrate; and a buffer layer above the hydrogen barrier layer; wherein the active layer is above the buffer layer.

[0007] In particular, the oxide thin film transistor further comprises: a hydrogen barrier layer above the substrate; and a buffer layer above the hydrogen barrier layer; wherein the active layer is above the buffer layer.

[0008] In particular, the oxide thin film transistor further comprises: a back gate electrode above the buffer layer; a back gate dielectric layer above the buffer layer and the back gate electrode; wherein the active layer is above the back gate dielectric layer.

[0009] In particular, the source and the drain are in contact with the source / drain regions below the hydrogen absorption layer, respectively.

[0010] In particular, the width of the top gate is greater than the width of the channel region.

[0011] In particular, the active layer material comprises amorphous metal oxide, and the hydrogen absorption layer material comprises indium-rich metal oxide.

[0012] In particular, the hydrogen-rich sealing insulating layer material comprises hydrogen-rich silicon nitride.

[0013] In particular, the top gate dielectric layer is a gas-permeable insulating material.

[0014] The application further provides a method for preparing an oxide thin film transistor, comprising: preparing a substrate; depositing an active layer above the substrate and patterning the active layer; depositing a hydrogen absorption layer above the active layer; depositing a hydrogen-rich sealing insulating layer above the hydrogen absorption layer; patterning the hydrogen absorption layer and the hydrogen-rich sealing insulating layer, removing the hydrogen absorption layer and the hydrogen-rich sealing insulating layer above the channel region to expose the channel region; depositing a top gate dielectric layer above the channel region of the active layer and the hydrogen-rich sealing insulating layer and performing an annealing operation; patterning the top gate dielectric layer and the hydrogen-rich sealing insulating layer to form source / drain electrode contact holes; depositing a metal layer above the top gate dielectric layer and patterning the metal layer to form a top gate, a source and a drain at least into the source / drain electrode contact holes.

[0015] In particular, the method for preparing an oxide thin film transistor further comprises: depositing a hydrogen barrier layer above the substrate; depositing a buffer layer above the hydrogen barrier layer; and depositing the active layer above the buffer layer and patterning the active layer.

[0016] The application further provides a preparation method of the oxide thin film transistor, comprising the following steps: preparing a substrate; depositing a buffer layer above the substrate; depositing a first metal layer on the buffer layer and performing patterning to form a back gate; depositing a back gate dielectric layer above the back gate and the buffer layer; depositing an active layer above the back gate dielectric layer and performing patterning on the active layer; depositing a hydrogen absorption layer above the active layer; depositing a hydrogen-rich sealing insulation layer above the hydrogen absorption layer; performing patterning on the hydrogen absorption layer and the hydrogen-rich sealing insulation layer, removing the hydrogen absorption layer and the hydrogen-rich sealing insulation layer above a channel region to expose the channel region; depositing a top gate dielectric layer above the channel region of the active layer and the hydrogen-rich sealing insulation layer and performing an annealing operation; performing patterning on the top gate dielectric layer and the hydrogen-rich sealing insulation layer to form a source-drain electrode contact hole; and depositing a second metal layer above the top gate dielectric layer and performing patterning to form a top gate and a source electrode and a drain electrode at least into the source-drain electrode contact hole.

[0017] In particular, the preparation method of the oxide thin film transistor further comprises: depositing a hydrogen blocking layer above the substrate; and depositing the buffer layer above the hydrogen blocking layer. BRIEF DESCRIPTION OF DRAWINGS

[0018] The preferred embodiments of the application will be further described below in detail with reference to the drawings, in which:

[0019] Figures la-lb is a structural cross-sectional view of a thin film transistor according to an embodiment of the application;

[0020] Figure 2 is a flowchart of a preparation method of a thin film transistor according to an embodiment of the application;

[0021] Figures 3a-3h is Figures la-lb a preparation state diagram of the thin film transistor of the embodiment shown;

[0022] Figures 4a-4b is a structural cross-sectional view of a thin film transistor according to another embodiment of the application;

[0023] Figure 5 is a flowchart of a preparation method of a thin film transistor according to another embodiment of the application;

[0024] Figures 6a-6h is Figures 4a-4b a preparation state diagram of the thin film transistor of the embodiment shown. DETAILED DESCRIPTION

[0025] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0026] In the following detailed description, reference will be made to the accompanying drawings, which form a part of this description. In the drawings, similar symbols in different drawings represent similar components. Various specific embodiments of the present application will be described in sufficient detail to enable one of ordinary skill in the art to make and use the technical solutions of the present application. It is to be understood that other embodiments can be utilized and structural, logical, or electrical changes can be made without departing from the scope of the present application.

[0027] The technologies, methods and devices known to those of ordinary skill in the relevant art can not be discussed in detail, but should be considered as part of the specification in appropriate cases. For the wires between the units in the drawings, only for the convenience of description, it represents that the units at least at the ends of the wires are in communication with each other, and is not intended to limit that the units without wires cannot communicate. In addition, the number of lines between two units is intended to represent at least the number of signals involved or at least the output ends between the two units, and is not intended to limit that the two units can only communicate with the signals as shown in the figure.

[0028] The transistor can refer to any structure of transistor, such as field effect transistor (FET) or bipolar transistor (BJT). When the transistor is a field effect transistor, according to the channel material, it can be hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, etc. According to whether the carrier is an electron or a hole, it can be divided into N-type transistor and P-type transistor, the control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the source or drain of the field effect transistor, and the control electrode or third electrode can be the gate; when the transistor is a bipolar transistor, the control electrode refers to the base of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, the corresponding second electrode can be the emitter or collector of the bipolar transistor, and the control electrode or third electrode can be the base. The transistor can be manufactured by amorphous silicon, polysilicon, oxide semiconductor, organic semiconductor, NMOS / PMOS process or CMOS process.

[0029] Figures la-lb is a structure cross-sectional view of an oxide thin film transistor according to an embodiment of the present application.

[0030] According to an embodiment, the oxide thin film transistor can include a substrate 101. In an embodiment of the present application, the substrate 101 can include a flexible insulating material such as PEN, PI, PET, or other flexible insulating material, or a rigid material such as silicon, glass, or other rigid material.

[0031] According to an embodiment, the oxide thin film transistor can further include an active layer 102 above the substrate 101. The active layer 102 can include amorphous indium gallium zinc oxide (a-IGZO), amorphous indium zinc oxide (a-IZO), amorphous indium gallium oxide (a-IGO), or other material, and the thickness of the active layer 102 can be not less than 1 nm. The active layer 102 can include a channel region 1021, a source region 1022, and a drain region 1023.

[0032] According to an embodiment, the oxide thin film transistor can further include a hydrogen absorption layer 103 above the active layer 102. The hydrogen absorption layer 103 can include two portions isolated from each other, and the hydrogen absorption layer above the channel region 1021 can be removed. The hydrogen absorption layer 103 can include a kind of metal oxide with high conductivity, such as indium zinc oxide (IZO) with high indium component or indium oxide (In2O3).

[0033] According to an embodiment, the oxide thin film transistor can further include a hydrogen-rich sealing insulating layer 104 above the hydrogen absorption layer 103. The hydrogen-rich sealing insulating layer 104 can include, for example, hydrogen-rich silicon nitride (Si3N4:H) or other material. The hydrogen-rich sealing insulating layer 104 can include two portions isolated from each other, and the hydrogen-rich sealing insulating layer above the channel region 1021 can be removed.

[0034] According to an embodiment, because hydrogen has high chemical activity, it can combine with oxygen in the metal oxide with high indium component to form H-O bond or combine with In to form In-H bond, so the hydrogen absorption layer 103 can absorb hydrogen impurities. In addition, the hydrogen absorption layer 103 can not only absorb hydrogen impurities in the channel region 1021 and the hydrogen-rich sealing insulating layer 104 to increase the carrier concentration of the source and drain regions, but also directly contact the metal oxide of the source and drain regions of the active layer 102 to further improve the conductivity of the source and drain regions.

[0035] According to one embodiment, the hydrogen absorption layer 103 can absorb hydrogen impurities from the hydrogen-rich sealing insulating layer 104 and the channel region 1021, ensuring a low hydrogen content in the channel region 1021, and forming a high-resistance channel region. The hydrogen absorption layer 103 absorbs hydrogen impurities, and the hydrogen content increases, while the hydrogen content in the source region 1022 and the drain region 1023 is low. Therefore, a concentration gradient is generated between the hydrogen content of the hydrogen absorption layer 103 and the source region 1022 and the drain region 1023. Under the influence of the concentration gradient and temperature, the hydrogen impurities absorbed by the hydrogen absorption layer 103 can diffuse to the source region 1022 and the drain region 1023, forming a high-conductivity source-drain region, thereby precisely regulating the distribution of hydrogen in the metal oxide, reducing the hydrogen content in the channel region 1021, and increasing the hydrogen content in the source region 1022 and the drain region 1023. Such a structure can improve the conductivity of the source-drain region, avoid the process of generating defects by plasma bombardment to form a high-conductivity source-drain region in the prior art, and avoid the influence of source-drain region defects on the channel region.

[0036] According to one embodiment, the oxide thin film transistor can further include a top gate dielectric layer 105 above the hydrogen-rich sealing insulating layer 104 and the channel region 1021. The material of the top gate dielectric layer 105 can include a material with air permeability, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO x ), etc. The hydrogen in the channel region 1021 can also be discharged outward during the preparation of the transistor through the top gate dielectric layer 105, ensuring a low hydrogen content in the channel region 1021.

[0037] According to one embodiment, the oxide thin film transistor can further include a top gate 106, the width of which is greater than the width of the channel region 1021. There is a certain amount of overlap between the top gate 106 and the source region 1022 and the drain region 1023. However, the introduction of the hydrogen-rich sealing insulating layer 104 with a thickness not less than 100 nm under the top gate dielectric layer 105 makes the overlap capacitance between the top gate 106 and the source region 1022 and the drain region 1023 negligible, forming a pseudo-self-aligned device structure.

[0038] According to one embodiment, the oxide thin film transistor can further include a source 107 and a drain 108. The material of the source 107 and the drain 108 can include metallic molybdenum (Mo) with a thickness not less than 20 nm.

[0039] According to one embodiment, as shown in Figure lb , the source 107 and the drain 108 can extend downward and directly contact the source-drain region in the active layer 102, respectively.

[0040] Figure 2 is a flow chart of a preparation method of a thin film transistor according to one embodiment of the present application. Figures 3a-3h isFigures la-lb A fabrication state diagram of the thin-film transistor in the illustrated embodiment.

[0041] Step 201: As Figure 3a As shown, substrate 301 is prepared.

[0042] Step 202: As Figure 3b As shown, an active layer 302 is deposited on a substrate 301. The active layer 302 material may include a-IGZO, a-IZO, a-IGO, etc., with a thickness of not less than 1 nm. The active layer is then patterned by photolithography to form active islands.

[0043] Step 203, as follows Figure 3c As shown, a hydrogen absorption layer 303 is deposited on the active layer 302. Since indium-rich materials have a strong ability to bind with hydrogen, the hydrogen absorption layer 303 material can include indium-rich metal oxides with good conductivity, such as IZO or In2O3 with high indium content, and the thickness is not less than 1 nm.

[0044] Step 204, as follows Figure 3d As shown, a hydrogen-rich sealing insulating layer 304 is deposited on the hydrogen absorption layer 303. The material of the hydrogen-rich sealing insulating layer 304 may include, for example, Si3N4:H, and the thickness is not less than 100 nm.

[0045] Step 205, as follows Figure 3e As shown, the hydrogen absorption layer 303 and the hydrogen-rich sealing insulation layer 304 are patterned, and part of the hydrogen absorption layer and the hydrogen-rich sealing insulation layer are removed to expose the channel region 3021.

[0046] Step 206, as follows Figure 3f As shown, a top gate dielectric layer 305 is deposited on the channel region 3021 and the hydrogen-rich sealing insulating layer 304. The material of the top gate dielectric layer 305 can be SiO2, Al2O3, or HfO. x The thickness is not less than 1 nm.

[0047] Step 207: Anneal the structure formed in the aforementioned process. The annealing temperature can be between 300℃ and 400℃, and the annealing atmosphere is oxygen (O2). During the annealing process, oxygen can enter the channel region 3021 of the active layer through the top gate dielectric layer 305, repairing defects such as oxygen vacancies and making the channel region 3021 highly resistive. At the same time, hydrogen impurities in the channel region 3021 can also be discharged outward through the top gate dielectric layer 305.

[0048] According to one embodiment, the hydrogen absorption layer 303 can absorb hydrogen impurities from the hydrogen-rich sealing insulating layer 304 and the middle channel region 3021, ensuring a low hydrogen content in the channel region 3021, and forming a high-resistance channel region. The hydrogen impurities absorbed by the hydrogen absorption layer 303 can diffuse to the source region 3022 and the drain region 3023 under the influence of concentration gradient and temperature, forming high-conductivity source and drain regions, thereby precisely regulating the distribution of hydrogen in the metal oxide, reducing the hydrogen content in the channel region 3021, and increasing the hydrogen content in the source region 3022 and the drain region 3023.

[0049] Step 208, as shown in the figure, patterns the top gate dielectric layer 305 and the hydrogen-rich sealing insulating layer 304 to form a source contact hole 3061 and a drain contact hole 3062. Figure 3g

[0050] According to one embodiment, the source contact hole 3061 and the drain contact hole 3062 can extend downward and directly contact the source and drain regions in the active layer 302, respectively.

[0051] Step 209, as shown in the figure, deposits a metal layer on the top gate dielectric layer 305 and in the source contact hole 3061 and the drain contact hole 3062, and patterns it to form a top gate 308, and a source 3071 and a drain 3072 at least into the source contact hole 3061 and the drain contact hole 3062. The material can be Mo, and the thickness is not less than 20 nm. Figure 3h According to one embodiment, step 209 can adopt another implementation, specifically including: depositing a metal electrode in the source contact hole 3061 and the drain contact hole 3062 and implementing a lift-off process to form the source 3071 and the drain 3072. Depositing a metal layer on the top gate dielectric layer 305 and patterning it to form the top gate 308.

[0052] According to one embodiment, the width of the top gate 308 is greater than the width of the channel region 3021, and there is a certain amount of overlap between the top gate 308 and the source region 3022 and the drain region 3023. However, the introduction of the hydrogen-rich sealing insulating layer 304 with a thickness of not less than 100 nm under the top gate dielectric layer 305 makes the overlap capacitance between the top gate 308 and the source region 3022 and the drain region 3023 negligible, forming a pseudo-self-aligned device structure.

[0053]

[0054] Figures 4a-4b is a structure sectional view of a dual-gate oxide thin film transistor according to one embodiment of the present application.

[0055] According to one embodiment, the dual-gate oxide thin film transistor can include a substrate 401.

[0056] ​​According to one embodiment, the dual-gate oxide thin-film transistor may further include a hydrogen barrier layer 402 located above the substrate 401, with a thickness of not less than 1 nm. According to one embodiment, the hydrogen barrier layer 402 material may include highly dense Al₂O₃, HfO… x , or HfO x Layering with Al2O3. Hydrogen is absorbed by Al2O3 and HfO. x After absorption, it reacts with Al2O3 and HfO. x The oxygen vacancies or oxygen atoms in the hydrogen layer reduce the amount of hydrogen that diffuses into the TFT. Therefore, the hydrogen barrier layer 402 can improve the hydrogen resistance of the TFT.

[0057] According to one embodiment, the dual-gate oxide thin-film transistor may further include a buffer layer 403, located above the hydrogen barrier layer 402, with a thickness greater than 1 nm. The material of the buffer layer 403 may include SiO2 or SiN. x Al2O3, HfO x etc., or a stack of the aforementioned materials.

[0058] According to one embodiment, the dual-gate oxide thin-film transistor may further include a back gate electrode 404 located above the buffer layer 403. The material of the back gate electrode 404 may include Mo.

[0059] According to one embodiment, the dual-gate oxide thin-film transistor may further include a back gate dielectric layer 405, located above the buffer layer 403 and the back gate electrode 404. The material of the back gate dielectric layer 405 may include SiO2, Al2O3, or HfO. x wait.

[0060] According to one embodiment, the dual-gate oxide thin-film transistor may further include an active layer 406 located above the back gate dielectric layer 405. The active layer 406 may be made of a-IGZO, amorphous a-IZO, a-IGO, etc., and has a thickness of not less than 1 nm. The active layer 406 may include a channel region 4061, a source region 4062, and a drain region 4063.

[0061] According to one embodiment, the dual-gate oxide thin-film transistor may further include a hydrogen absorption layer 407 located above the active layer 406. The hydrogen absorption layer 407 comprises two isolated portions, with the hydrogen absorption layer above the channel region 4061 being removed. The hydrogen absorption layer 407 may be made of an indium-rich metal oxide with good conductivity, such as IZO or In2O3 with a high indium content.

[0062] According to an embodiment, the dual-gate oxide thin film transistor can further include a hydrogen-rich sealing insulating layer 408 above the hydrogen-absorbing layer 407. The hydrogen-rich sealing insulating layer 408 can include, for example, Si3N4:H, etc. The hydrogen-rich sealing insulating layer 408 includes two portions isolated from each other, and the hydrogen-rich sealing insulating layer above the channel region 4061 is removed.

[0063] According to an embodiment, the hydrogen-absorbing layer 407 can absorb hydrogen impurities because hydrogen has a high chemical activity and can form H-O bonds with oxygen in the indium-rich metal oxide or In-H bonds with In. In addition, the hydrogen-absorbing layer 407 can directly contact the metal oxide of the source / drain region of the active layer 406 in addition to absorbing hydrogen impurities of the channel region 4061 and the hydrogen-rich sealing insulating layer 408, thereby further increasing the conductivity of the source / drain region.

[0064] According to an embodiment, the hydrogen-absorbing layer 407 can absorb hydrogen impurities from the hydrogen-rich sealing insulating layer 408 and the channel region 4061, thereby ensuring a low hydrogen content of the channel region 4061 and forming a high-resistance channel region. The hydrogen-absorbing layer 407 absorbs hydrogen impurities, and the hydrogen content is increased, whereas the hydrogen content in the source region 4062 and the drain region 4063 is low. Thus, a concentration gradient is generated between the hydrogen-absorbing layer 407 and the source region 4062 and the drain region 4063. The hydrogen impurities absorbed by the hydrogen-absorbing layer 407 can diffuse to the source region 4062 and the drain region 4063 due to the concentration gradient and temperature, thereby forming a high-conductivity source / drain region, and thus precisely controlling the distribution of hydrogen in the metal oxide, reducing the hydrogen content in the channel region 4061, and increasing the hydrogen content in the source region 4062 and the drain region 4063. Such a structure can increase the conductivity of the source / drain region, avoid the process of forming a high-conductivity source / drain region by plasma bombardment to generate defects in the existing scheme, and avoid the influence of defects in the source / drain region on the channel region.

[0065] According to an embodiment, the dual-gate oxide thin film transistor can further include a top gate dielectric layer 409 above the hydrogen-rich sealing insulating layer 408 and the channel region 4061. The material of the top gate dielectric layer 409 can include a material having gas permeability, such as SiO2, Al2O3, HfO x The hydrogen of the channel region 4061 can also be discharged outward through the top gate dielectric layer 409 during the preparation of the transistor, thereby ensuring a low hydrogen content of the channel region 4061.

[0066] According to one embodiment, the dual-gate oxide thin film transistor can further include a top gate 410, the width of which is greater than the width of the channel region 4061. There is a certain amount of overlap between the top gate 410 and the source region 4062 and the drain region 4063. However, the introduction of the hydrogen-rich sealing insulation layer 408 with a thickness of no less than 100 nm under the top gate dielectric layer 409 makes the overlap capacitance between the top gate 410 and the source region 4062 and the drain region 4063 negligible, forming a pseudo-self-aligned device structure.

[0067] According to one embodiment, the dual-gate oxide thin film transistor can further include a source 411 and a drain 412, the material of which can include Mo, and the thickness of which is no less than 20 nm.

[0068] According to one embodiment, as shown in Figure 4b , the source 411 and the drain 412 can extend downward and directly contact the source / drain regions in the active layer 406, respectively.

[0069] Figure 5 is a flow chart of a preparation method of a dual-gate oxide thin film transistor according to one embodiment of the present application. Figures 6a-6h is a state diagram of the preparation of a dual-gate oxide thin film transistor according to the embodiment shown in Figures 4a-4b

[0070] Step 501, prepare a substrate 601.

[0071] Step 502, deposit a hydrogen-blocking layer 602 on the substrate 601, the material of the hydrogen-blocking layer 602 can include high-density Al2O3, HfO x , or a stack of HfO x and Al2O3, with a thickness of no less than 1 nm. The hydrogen-blocking layer can improve the hydrogen resistance of the TFT.

[0072] Step 503, deposit a buffer layer 603 on the hydrogen-blocking layer 602, the material of which can be SiO2, SiN x , Al2O3, HfO x , or a stack of the foregoing materials, with a thickness of greater than 1 nm.

[0073] Step 504, as shown in Figure 6a , deposit a back gate electrode 604 on the buffer layer 603, the material of the back gate electrode 604 can include Mo, and the thickness of which is no less than 20 nm. The back gate electrode 604 is patterned to form a back gate electrode pattern.

[0074] Step 505, as shown in Figure 6b , deposit a back gate dielectric layer 605 on the buffer layer 603 and the back gate electrode 604, the material of the back gate dielectric layer 605 can include SiO2, Al2O3, HfO x ​a-IGZO, a-IZO, a-IGO, etc., with a thickness not less than 1 nm.

[0075] As shown in step 506, the active layer 606 is deposited on the back gate dielectric layer 605. The active layer 606 can include a-IGZO, a-IZO, a-IGO, etc., with a thickness not less than 1 nm. The active layer 606 is then patterned to form active islands. Figure 6c

[0076] As shown in step 507, the hydrogen absorption layer 607 is deposited on the active layer 606. The hydrogen absorption layer 607 can include a conductive indium-rich metal oxide, such as IZO with high indium content or In2O3.

[0077] As shown in step 508, the hydrogen-rich sealing insulating layer 608 is deposited on the hydrogen absorption layer 607. The hydrogen-rich sealing insulating layer 608 can include Si3N4:H, etc., with a thickness not less than 100 nm. Figure 6d As shown in step 509, the hydrogen absorption layer 607 and the hydrogen-rich sealing insulating layer 608 are patterned to remove part of the hydrogen absorption layer and the hydrogen-rich sealing insulating layer, exposing the channel region 6061.

[0078] Figure 6e As shown in step 510, the top gate dielectric layer 609 is deposited on the channel region 6061 and the hydrogen-rich sealing insulating layer 608. The top gate dielectric layer 609 can include SiO2, Al2O3, HfO x , etc., with a thickness not less than 1 nm.

[0079] As shown in step 511, the structure formed by the foregoing process is annealed at a temperature of 300-400°C in an O2 atmosphere. During the annealing process, oxygen can enter the channel region 6061 of the active layer through the top gate dielectric layer 609 to repair defects such as oxygen vacancies, thereby making the channel region 6061 highly resistive. At the same time, hydrogen impurities in the channel region 6061 can also be expelled outward through the top gate dielectric layer 609. Figure 6f According to an embodiment, the hydrogen absorption layer 607 can absorb hydrogen impurities from the hydrogen-rich sealing insulating layer 608 and the intermediate channel region 6061, ensuring a low hydrogen content in the channel region 6061 and forming a highly resistive channel region. Due to the influence of concentration gradient and temperature, the hydrogen impurities absorbed by the hydrogen absorption layer 607 will diffuse to the source region 6062 and the drain region 6063, forming highly conductive source and drain regions, thereby precisely regulating the distribution of hydrogen in the metal oxide, reducing the hydrogen content in the channel region 6061, and increasing the hydrogen content in the source region 6062 and the drain region 6063.

[0080] According to an embodiment, the hydrogen absorption layer 607 can absorb hydrogen impurities from the hydrogen-rich sealing insulating layer 608 and the intermediate channel region 6061, ensuring a low hydrogen content in the channel region 6061 and forming a highly resistive channel region. Due to the influence of concentration gradient and temperature, the hydrogen impurities absorbed by the hydrogen absorption layer 607 will diffuse to the source region 6062 and the drain region 6063, forming highly conductive source and drain regions, thereby precisely regulating the distribution of hydrogen in the metal oxide, reducing the hydrogen content in the channel region 6061, and increasing the hydrogen content in the source region 6062 and the drain region 6063.

[0081] According to an embodiment, the hydrogen absorption layer 607 can absorb hydrogen impurities from the hydrogen-rich sealing insulating layer 608 and the intermediate channel region 6061, ensuring a low hydrogen content in the channel region 6061 and forming a highly resistive channel region. Due to the influence of concentration gradient and temperature, the hydrogen impurities absorbed by the hydrogen absorption layer 607 will diffuse to the source region 6062 and the drain region 6063, forming highly conductive source and drain regions, thereby precisely regulating the distribution of hydrogen in the metal oxide, reducing the hydrogen content in the channel region 6061, and increasing the hydrogen content in the source region 6062 and the drain region 6063.

[0082] ​​Step 512, as follows Figure 6g As shown, the top gate dielectric layer 609 and the hydrogen-rich sealing insulating layer 608 are patterned to form source contact hole 6101 and drain contact hole 6102.

[0083] According to one embodiment, the source contact hole 6101 and the drain contact hole 6102 may extend downward and directly contact the source and drain regions in the active layer 606, respectively.

[0084] Step 513, as follows Figure 6h As shown, a metal layer is deposited on the top gate dielectric layer 609 and in the source contact hole 6101 and drain contact hole 6102, and patterned to form a top gate 612, and a source 6111 and a drain 6112 that extend into the source contact hole 6101 and drain contact hole 6102. The material can be Mo and the thickness is not less than 20 nm.

[0085] According to one embodiment, step 513 can be implemented in another way, specifically including: depositing metal electrodes in the source contact hole 6101 and the drain contact hole 6102 and performing a lift-off process to form the source 6111 and the drain 6112. Depositing a metal layer on the top gate dielectric layer 609 and patterning it to form the top gate 612.

[0086] According to one embodiment, the width of the top gate 612 is greater than the width of the channel region 6061, and there is a certain amount of overlap between the top gate 612 and the source region 6062 and the drain region 6063. However, a hydrogen-rich sealing insulating layer 608 with a thickness of not less than 100 nm is introduced under the top gate dielectric layer 609, making the overlap capacitance between the top gate 612 and the source region 6062 and the drain region 6063 negligible, forming a pseudo-self-aligned device structure.

[0087] The solution proposed in this application avoids the need for plasma bombardment to form the source / drain region, reducing the formation of defects in the source / drain region while ensuring the formation of a low-resistivity source / drain region. Furthermore, by controlling the thickness of the hydrogen-rich layer to a relatively large dimension, excessive gate-source-drain overlap capacitance can be avoided, preventing the formation of a pseudo-self-aligned transistor.

[0088] The above embodiments are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art can make various changes and modifications without departing from the scope of this application. Therefore, all equivalent technical solutions should also fall within the scope of this application.

Claims

1. An oxide thin film transistor, comprising: a substrate; an active layer over the substrate, comprising a channel region and source-drain regions, wherein the source-drain regions comprise hydrogen carriers; a hydrogen-trapping layer over the active layer, wherein a portion of the hydrogen-trapping layer over the channel region is removed; a hydrogen-rich encapsulation insulating layer over the hydrogen-trapping layer, wherein a portion of the hydrogen-rich encapsulation insulating layer over the channel region is removed; a top-gate dielectric layer over the hydrogen-rich encapsulation insulating layer and the channel region; a top gate over the top-gate dielectric layer; and a source and a drain in contact with the hydrogen-trapping layer on both sides of the channel region, respectively.

2. The oxide thin film transistor of claim 1, further comprising: a hydrogen-blocking layer over the substrate; and a buffer layer over the hydrogen-blocking layer; the active layer is over the buffer layer. wherein 3. The oxide thin film transistor of claim 2, further comprising: a back gate electrode over the buffer layer; and a back gate dielectric layer over the buffer layer and the back gate electrode; wherein the active layer is over the back gate dielectric layer.

4. The oxide thin film transistor of any one of claims 1 to 3, wherein the source and the drain are also in contact with the source-drain regions under the hydrogen-trapping layer, respectively.

5. The oxide thin film transistor of any one of claims 1 to 3, wherein a width of the top gate is greater than a width of the channel region.

6. The oxide thin film transistor of any one of claims 1 to 3, wherein the active layer material comprises an amorphous metal oxide, and the hydrogen-trapping layer material comprises an indium-rich metal oxide.

7. The oxide thin film transistor of any one of claims 1 to 3, wherein the hydrogen-rich encapsulation insulating layer material comprises hydrogen-rich silicon nitride.

8. The oxide thin film transistor of any one of claims 1 to 3, wherein the top-gate dielectric layer is a gas-permeable insulating material.

9. A method for fabricating an oxide thin film transistor, comprising: preparing a substrate; depositing an active layer over the substrate, and patterning the active layer; depositing a hydrogen-trapping layer over the active layer; depositing a hydrogen-rich encapsulation insulating layer over the hydrogen-trapping layer; patterning the hydrogen-trapping layer and the hydrogen-rich encapsulation insulating layer to remove the hydrogen-trapping layer and the hydrogen-rich encapsulation insulating layer over a channel region, exposing the channel region; depositing a top-gate dielectric layer over the channel region of the active layer and the hydrogen-rich encapsulation insulating layer, and performing an annealing process, wherein the hydrogen-trapping layer absorbs hydrogen from the channel region, and the absorbed hydrogen diffuses to source and drain regions under the influence of a hydrogen concentration gradient and temperature; patterning the top-gate dielectric layer and the hydrogen-rich encapsulation insulating layer to form source-drain electrode contact holes; and depositing a metal layer over the top-gate dielectric layer, and patterning the metal layer to form a top gate, and a source and a drain at least into the source-drain electrode contact holes.

10. The method for fabricating an oxide thin film transistor of claim 9, further comprising: depositing a hydrogen-blocking layer over the substrate; depositing a buffer layer over the hydrogen-blocking layer; ​ ​ and depositing the active layer over the buffer layer, the active layer being patterned.

11. A method of fabricating an oxide thin film transistor, comprising: fabricating a substrate; depositing a buffer layer over the substrate; depositing a first metal layer over the buffer layer and patterning the first metal layer to form a back gate; depositing a back gate dielectric layer over the back gate and the buffer layer; depositing an active layer over the back gate dielectric layer, the active layer being patterned; depositing a hydrogen sink layer over the active layer; depositing a hydrogen rich encapsulation layer over the hydrogen sink layer; patterning the hydrogen sink layer and the hydrogen rich encapsulation layer to remove the hydrogen sink layer and the hydrogen rich encapsulation layer over a channel region, exposing the channel region; depositing a top gate dielectric layer over the channel region of the active layer and the hydrogen rich encapsulation layer and performing an anneal operation, wherein the hydrogen sink layer absorbs hydrogen from the channel region, the hydrogen absorbed by the hydrogen sink layer diffusing to source and drain regions under the influence of a hydrogen concentration gradient and temperature; and patterning the top gate dielectric layer and the hydrogen rich encapsulation layer to form source and drain electrode contact holes; and depositing a second metal layer over the top gate dielectric layer and patterning the second metal layer to form a top gate, and source and drain electrodes at least into the source and drain electrode contact holes.

12. The method of fabricating an oxide thin film transistor of claim 11, further comprising: depositing a hydrogen barrier layer over the substrate; and depositing a buffer layer over the hydrogen barrier layer.

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