Thin film transistor, display substrate and preparation method of thin film transistor

Abstract

The embodiment of the invention provides a thin film transistor, a display substrate and a preparation method of the thin film transistor. The thin film transistor comprises a substrate, a first gate structure, a buffer layer, a channel structure, an insulating layer, a second gate structure, a dielectric layer, a first source and drain electrode structure and a second source and drain electrode structure, the first gate structure is arranged in the buffer layer, the channel structure is arranged in the insulating layer, the second gate structure is arranged in the dielectric layer, the first source and drain electrode structure is arranged on the side, away from the substrate, of the dielectric layer, and the first source and drain electrode structure is electrically connected with the channel structure and the first gate structure through via holes; the second source and drain electrode structure is arranged on one side, far away from the substrate, of the dielectric layer, and the second source and drain electrode structure is electrically connected with the channel structure through the via hole; the first gate structure comprises a first part and a second part which are connected in series, and the distances between the first part and the channel structure and between the second part and the channel structure are different. The stability of the oxide thin film transistor can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a thin film transistor, a display substrate and a method for preparing the thin film transistor. Background Art

[0002] Currently, the mainstream TFT (Thin Film Transistor) technologies include a-Si (amorphous silicon) technology, LTPS (Low Temperature Poly-Silicon) technology and Oxide technology. Among them, Oxide technology is gaining more and more attention due to its advantages such as low power consumption, low frame rate and high transmittance.

[0003] In common oxide display products such as LTPO (Low Temperature Polycrystalline Oxide) + products and full oxide products, when oxide TFT is used as a driving TFT, in order to more clearly distinguish the grayscale levels of different grayscales, a larger SS (Subthreshold Swing) and a Data range (value range) of low grayscale voltage subdivision are required. SS and Data range are related to the size of the capacitor. In related technologies, the oxide TFT structure is Figure 1 As shown in the figure, the smaller the thickness of the Ox-buffer (oxide buffer layer) between the Low gate (bottom gate) and the channel structure, the smaller the distance between the channel structure and the bottom gate, the larger the capacitance, and the larger the SS and Data range. However, at the same time, due to the increase in the electric field strength, the NBTS (Negative Bias Temperature Stress) will deteriorate (its value will increase), reducing the stability of the oxide TFT. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a thin film transistor, a display substrate and a method for manufacturing a thin film transistor to improve the stability of oxide thin film transistors. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides a thin film transistor, the thin film transistor comprising:

[0006] A substrate, a first gate structure, a buffer layer, a channel structure, an insulating layer, a second gate structure, a dielectric layer, a first source-drain structure, and a second source-drain structure;

[0007] The buffer layer is arranged on the substrate, the insulating layer is arranged on a side of the buffer layer away from the substrate, and the dielectric layer is arranged on a side of the insulating layer away from the substrate;

[0008] The first gate structure is arranged in the buffer layer, the channel structure is arranged in the insulating layer, the second gate structure is arranged in the dielectric layer, the first source-drain structure is arranged on a side of the dielectric layer away from the substrate, and the first source-drain structure is electrically connected to the channel structure and the first gate structure through a via, and the second source-drain structure is arranged on a side of the dielectric layer away from the substrate, and the second source-drain structure is electrically connected to the channel structure through a via;

[0009] The first gate structure includes a first portion and a second portion, the first portion and the second portion are connected in series, and the first portion and the second portion are at different distances from the channel structure.

[0010] In a possible implementation manner, the first portion is arranged in contact with the substrate, and a first distance exists between the second portion and the substrate.

[0011] In a possible implementation manner, the first distance ranges from 1000A to 2000A.

[0012] In a possible implementation manner, the thickness of the first portion and the second portion is 500A-1100A.

[0013] In a possible implementation manner, the first portion includes a first Ti layer and a first Mo layer, and the first Mo layer is located on a side of the first Ti layer away from the substrate; the second portion includes a second Ti layer and a second Mo layer, and the second Mo layer is located on a side of the second Ti layer away from the substrate;

[0014] The thickness of the first Ti layer and the second Ti layer ranges from 100A to 300A; the thickness of the first Mo layer and the second Mo layer ranges from 400A to 800A.

[0015] In a possible implementation manner, both the first portion and the second portion are arranged in contact with the substrate, and a thickness of the second portion is greater than a thickness of the first portion.

[0016] In a possible implementation manner, the thickness of the first portion is 500A-1100A, and the thickness of the second portion is 1100A-3300A.

[0017] In a possible implementation manner, the first portion includes a third Ti layer and a third Mo layer, and the third Mo layer is located on a side of the third Ti layer away from the substrate; the second portion includes a fourth Ti layer and a fourth Mo layer, and the fourth Mo layer is located on a side of the fourth Ti layer away from the substrate;

[0018] The thickness of the third Ti layer and the fourth Ti layer ranges from 100A to 300A; the thickness of the third Mo layer ranges from 400A to 800A, and the thickness of the fourth Mo layer ranges from 1000A to 3000A.

[0019] In a possible implementation manner, the first source-drain structure is a source electrode, and the second source-drain structure is a drain electrode;

[0020] The source electrode is electrically connected to the first portion through a via hole, or the source electrode is electrically connected to the second portion through a via hole.

[0021] In a possible implementation manner, a distance between the first portion and the channel structure ranges from 2800A to 6000A, and a distance between the second portion and the channel structure ranges from 600A to 1600A.

[0022] In a possible implementation, the buffer layer between the first portion and the channel structure and between the first portion and the insulating layer includes a first SiN layer and a first SiO layer, and the first SiO layer is located on a side of the first SiN layer away from the first portion; the buffer layer between the second portion and the channel structure and between the second portion and the insulating layer includes a second SiN layer and a second SiO layer, and the second SiO layer is located on a side of the second SiN layer away from the second portion;

[0023] The thickness of the first SiO layer ranges from 800A to 2000A, and the thickness of the first SiN layer ranges from 2000A to 4000A;

[0024] The thickness of the second SiO layer and the second SiN layer both range from 300 Å to 800 Å.

[0025] In a second aspect, an embodiment of the present application provides a display substrate, wherein the display substrate comprises a thin film transistor as described in any one of the first aspects.

[0026] In a third aspect, an embodiment of the present application provides a method for preparing a thin film transistor, the method comprising:

[0027] Preparing a first gate structure and a buffer layer on a substrate, wherein the first gate structure includes a first portion and a second portion, the first portion and the second portion are connected in series, and the distances between the upper surfaces of the first portion and the second portion and the substrate are different;

[0028] Sequentially preparing a channel structure, an insulating layer, a second gate structure and a dielectric layer on the buffer layer;

[0029] Opening via holes in the dielectric layer, the insulating layer, and the buffer layer;

[0030] A first source-drain structure and a second source-drain structure are prepared on the dielectric layer, wherein the first source-drain structure is electrically connected to the first gate structure and the channel structure through vias, and the second source-drain structure is electrically connected to the channel structure through vias.

[0031] In a possible implementation manner, the step of preparing a first gate structure and a buffer layer on a substrate includes:

[0032] A first buffer structure is prepared on a substrate, wherein an orthographic projection of the first buffer structure on the substrate is located in a first region, and a designed position of a second portion of the first gate structure falls within the first region;

[0033] Preparing a first portion of the first gate structure on the substrate, and preparing a second portion of the first gate structure on the first buffer structure, the first portion and the second portion being connected in series;

[0034] A remaining structure of a buffer layer is prepared, wherein the buffer layer includes the first buffer structure.

[0035] In a possible implementation manner, the step of preparing a first gate structure and a buffer layer on a substrate includes:

[0036] Preparing a first portion of a first gate structure and a second portion of the first gate structure on a substrate, wherein a thickness of the second portion is greater than a thickness of the first portion;

[0037] Prepare a buffer layer.

[0038] Beneficial effects of the embodiments of the present application:

[0039] The thin film transistor, display substrate and thin film transistor preparation method provided by the embodiments of the present application, the thin film transistor includes: a substrate, a first gate structure, a buffer layer, a channel structure, an insulating layer, a second gate structure, a dielectric layer, a first source-drain structure and a second source-drain structure; the buffer layer is arranged on the substrate, the insulating layer is arranged on the side of the buffer layer away from the substrate, and the dielectric layer is arranged on the side of the insulating layer away from the substrate; the first gate structure is arranged in the buffer layer, the channel structure is arranged in the insulating layer, the second gate structure is arranged in the dielectric layer, the first source-drain structure is arranged on the side of the dielectric layer away from the substrate, and the first source-drain structure is electrically connected to the channel structure and the first gate structure through a via hole, the second source-drain structure is arranged on the side of the dielectric layer away from the substrate, and the second source-drain structure is electrically connected to the channel structure through a via hole; the first gate structure includes a first part and a second part, the first part is connected in series with the second part, and the first part and the second part are at different distances from the channel structure. The first gate structure in the thin film transistor provided in the embodiment of the present application includes a first part and a second part, and the first part and the second part are at different distances from the channel structure. When analyzing the SS and Data range of the transistor, the part of the first gate structure that is at a smaller distance from the channel structure plays a dominant role, which can ensure a larger SS and Data range, thereby clearly distinguishing the grayscale levels of different gray levels; when analyzing the NBTS characteristics of the transistor, the part of the first gate structure that is at a larger distance from the channel structure plays a dominant role, and the electric field strength is smaller, which can ensure a smaller NBTS value, thereby improving the stability of the oxide thin film transistor.

[0040] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0042] Figure 1 is a schematic diagram of the structure of a thin film transistor in the related art;

[0043] Figure 2 A schematic diagram of the structure of a first thin film transistor provided in an embodiment of the present application;

[0044] Figure 3 A schematic diagram of the structure of a second thin film transistor provided in an embodiment of the present application;

[0045] Figure 4A schematic diagram of the structure of a third thin film transistor provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of the structure of a fourth thin film transistor provided in an embodiment of the present application;

[0047] Figure 6 A schematic diagram of the structure of a display substrate provided in an embodiment of the present application;

[0048] Figure 7 A schematic flow chart of a first method for preparing a thin film transistor provided in an embodiment of the present application;

[0049] Figure 8 A schematic flow chart of a second method for preparing a thin film transistor provided in an embodiment of the present application;

[0050] Fig. 9 A schematic flow chart of a third method for preparing a thin film transistor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0052] At present, the mainstream TFT technologies include a-Si technology, LTPS technology and oxide technology. Among them, oxide technology has attracted more and more attention due to its advantages such as low power consumption, low frame rate and high transmittance. In common oxide display products such as LTPO+ products and full oxide products, when oxide TFT is used as a driving TFT, in order to more clearly distinguish the grayscale levels of different gray levels, a larger SS and Data range are required. The SS and Data range are related to the size of the capacitor. The smaller the thickness of the Ox-buffer, the smaller the distance between the channel structure and the bottom gate, the larger the capacitance, and the larger the SS and Data range.

[0053] This is because the SS characteristics of oxide TFT are determined by the following formula (1):

[0054] Formula (1)

[0055] Among them, C fo represents the Ox-GI (oxide gate insulation layer) capacitance, C ch Represents the channel structure capacitance, C borepresents the Ox-buffer capacitance, T represents the temperature, q represents the unit charge, and K is the electrostatic force constant.

[0056] If the thickness of Ox-buffer decreases, that is, the distance between the channel structure and the bottom gate decreases, then C bo Increases. From formula (1), we can see that the SS of oxide TFT increases, and the data range also increases.

[0057] See also Figure 1 , is a schematic diagram of the structure of a thin film transistor in the related art, including a source, a drain, a top gate, a bottom gate and a channel structure. The distance between the channel structure and the bottom gate is a fixed value. When the distance is small, the SS and Data range are large. However, at the same time, due to the increase in electric field strength, the NBTS will deteriorate (its value will increase), reducing the stability of the OxideTFT. For example, the Ox-buffer is usually composed of SiN (silicon nitride) at the bottom and SiO (silicon monoxide) on the SiN. When the thickness of SiO in the Ox-buffer is 1000A and the thickness of SiN is 3000A, SS=0.13, NBTS=0.02, where A (angstrom) is the unit of length; when the thickness of SiO in the Ox-buffer is 500A and the thickness of SiN is 500A, SS=0.29, NBTS=3.17. It can be seen from this that as the thickness of the Ox-buffer decreases, its SS increases. At the same time, due to the increase in electric field strength, its NBTS deteriorates (its value increases).

[0058] How to improve the stability of oxide TFT while ensuring a large SS and Data range has become a problem that needs to be further solved. Based on this, the embodiments of the present application propose a thin film transistor, a display substrate and a method for preparing a thin film transistor.

[0059] In a first aspect of an embodiment of the present application, a thin film transistor is provided. Figure 2 , is a schematic diagram of the structure of a first thin film transistor provided in an embodiment of the present application, the thin film transistor comprising:

[0060] Substrate 1, first gate structure 2, buffer layer 3, channel structure 4, insulating layer 5, second gate structure 6, dielectric layer 7, first source-drain structure 8 and second source-drain structure 9. In one example, the thin film transistor provided in the embodiment of the present application further includes a protective layer 10.

[0061] Among them, the buffer layer 3 is arranged on the substrate 1, the insulating layer 5 is arranged on the side of the buffer layer 3 away from the substrate 1, and the dielectric layer 7 is arranged on the side of the insulating layer 5 away from the substrate 1; the first gate structure 2 is arranged in the buffer layer 3, the channel structure 4 is arranged in the insulating layer 5, the second gate structure 6 is arranged in the dielectric layer 7, the first source-drain structure 8 is arranged on the side of the dielectric layer 7 away from the substrate 1, and the first source-drain structure 8 is electrically connected to the channel structure 4 and the first gate structure 2 through a via, the second source-drain structure 9 is arranged on the side of the dielectric layer 7 away from the substrate 1, and the second source-drain structure 9 is electrically connected to the channel structure 4 through a via; the first gate structure 2 includes a first part 21 and a second part 22, the first part 21 and the second part 22 are connected in series, and the first part 21 and the second part 22 are at different distances from the channel structure 4.

[0062] The thin film transistor provided in the embodiment of the present application may be an oxide TFT, wherein the substrate 1 is located at the bottom layer, and the substrate 1 is mainly used to provide support and insulation functions. The material thereof may be glass or plastic, etc. The specific structure thereof may refer to the prior art, and this application does not make any specific limitation thereto.

[0063] The buffer layer 3 is located on the substrate 1. The buffer layer 3 is mainly used to improve the performance and reliability of the thin film transistor, and its material can be SiO, SiN, etc. In one example, the material of the buffer layer 3 includes both SiO and SiN.

[0064] The insulating layer 5 is located on the side of the buffer layer 3 away from the substrate 1. The insulating layer 5 mainly plays the role of electrical isolation, which can prevent the second gate structure 6 from directly contacting the channel structure 4, thereby controlling the flow of current in the channel structure 4. The material can be aluminum oxide or silicon oxide. In one example, the insulating layer 5 is composed of SiO, and its thickness ranges from 1000-1500A.

[0065] The dielectric layer 7 is located on the side of the insulating layer 5 away from the substrate 1. The dielectric layer 7 mainly plays an insulating role to prevent the second gate structure 6 from directly contacting the first source-drain structure 8 and the second source-drain structure 9. The material of the dielectric layer 7 can be aluminum oxide, silicon oxide, silicon nitride, etc. In one example, the material of the dielectric layer 7 includes both SiO and SiN, and SiN is located at the bottom, SiO is located on SiN, the thickness of SiO ranges from 1000-2000A, and the thickness of SiN ranges from 3000-4000A.

[0066] In one example, the thin film transistor provided in an embodiment of the present application also includes a protective layer 10, which is located on the dielectric layer 7 and can protect the entire transistor structure from the influence of the external environment. The protective layer 10 can be composed of a SiO2 thin film, and its specific structure can be referred to the prior art, and this application does not make any specific limitations on this.

[0067] In the embodiment of the present application, the first gate structure 2 is located in the buffer layer 3, the channel structure 4 is located in the insulating layer 5, the second gate structure 6 is located in the dielectric layer 7, the first source-drain structure 8 is located on the side of the dielectric layer 7 away from the substrate 1, and the first source-drain structure 8 is electrically connected to the channel structure 4 and the first gate structure 2 through vias, the second source-drain structure 9 is located on the side of the dielectric layer 7 away from the substrate 1, and the second source-drain structure 9 is electrically connected to the channel structure 4 through vias; the first gate structure 2 includes a first part 21 and a second part 22, the first part 21 and the second part 22 are connected in series, and the first part 21 and the second part 22 are at different distances from the channel structure 4.

[0068] In a possible implementation, the first gate structure 2 may be composed of Mo (molybdenum) and Ti (titanium), wherein Ti is located at the bottom of the first gate structure 2. The channel structure 4 may be IGZO (Indium Gallium Zinc Oxide), and the thickness of IGZO may be 200-400A. The second gate structure 6 may be an Ox gate (oxide gate), and its material may be composed of Mo and Ti, wherein Ti is located at the bottom of the second gate structure 6, the thickness of Mo is in the range of 2000-4000A, and the thickness of Ti is in the range of 100-500A. The first source-drain structure 8 and the second source-drain structure 9 may be composed of a Ti-Al (aluminum)-Ti structure, wherein Al is located between two layers of Ti, and the thicknesses of Ti, Al, and Ti are 500-1000A, 5000-7000A, and 500-1000A, respectively.

[0069] In a possible implementation, the first source-drain structure 8 is a source electrode, the second source-drain structure 9 is a drain electrode, and the source electrode is electrically connected to the first portion 21 through a via. In other embodiments, the source electrode may also be electrically connected to the second portion 22 through a via. Figure 2 As shown in , the first source-drain structure 8 (source electrode in this embodiment) is electrically connected to the first portion 21 through a via hole; see Figure 3 , is a schematic diagram of the structure of a second thin film transistor provided in an embodiment of the present application, wherein the first source-drain structure 8 (the source electrode in this embodiment) is electrically connected to the second part 22 through a via.

[0070] The first source-drain structure 8 of the embodiment of the present application is a source electrode, and the source electrode can be electrically connected to the first portion 21 or the second portion 22 , thereby improving the flexibility of the oxide thin film transistor design.

[0071] The first gate structure 2 in the embodiment of the present application includes a first portion 21 and a second portion 22, the first portion 21 and the second portion 22 are connected in series, and the first portion 21 and the second portion 22 are at different distances from the channel structure 4. When analyzing the SS and Data range of the oxide thin film transistor, the portion of the gate structure that is at a smaller distance from the channel structure plays a leading role. At this time, due to the increase in the capacitance of the buffer layer, it can be obtained from the above formula (1) that a larger SS and Data range can be guaranteed, thereby clearly distinguishing the grayscale levels of different grayscales; when analyzing the NBTS characteristics of the transistor, the portion of the gate structure that is at a larger distance from the channel structure plays a leading role, the electric field strength is weakened, and the NBTS value can be guaranteed to be smaller, thereby improving the stability of the oxide thin film transistor.

[0072] In a possible implementation, Figure 2 As shown in the figure, the first part 21 is arranged in contact with the substrate 1, and the second part 22 has a first distance from the substrate 1. In one example, a buffer structure is set between the second part 22 and the substrate 1, and the buffer structure is composed of SiO or SiN, and its thickness ranges from 1000-2000A. In this embodiment, the second part 22 has a first distance from the substrate 1. Since the first part 21 is arranged in contact with the substrate 1, it can be ensured that the first part 21 and the second part 22 are at different distances from the channel structure 4.

[0073] In a possible implementation manner, the first distance ranges from 1000A to 2000A.

[0074] In a possible implementation manner, the thickness of the first portion 21 and the second portion 22 is 500A-1100A.

[0075] In a possible implementation, the first portion 21 includes a first Ti layer and a first Mo layer, wherein the first Mo layer is located on a side of the first Ti layer away from the substrate 1; the second portion 22 includes a second Ti layer and a second Mo layer, wherein the second Mo layer is located on a side of the second Ti layer away from the substrate 1.

[0076] The thickness of the first Ti layer and the second Ti layer ranges from 100A to 300A; the thickness of the first Mo layer and the second Mo layer ranges from 400A to 800A. In this embodiment, the material of the first gate structure 2 is Ti and Mo, and the Ti layer is located at the bottom of the first gate structure 2, which can ensure that the first gate structure 2 has good conductivity and stability, and the thickness range of each layer can ensure that the thickness of the first part 21 and the second part 22 is 500A to 1100A.

[0077] In one possible implementation, see Figure 4, is a schematic diagram of the structure of a third thin film transistor provided in an embodiment of the present application, wherein the first portion 21 and the second portion 22 are both arranged in contact with the substrate 1 , and the thickness of the second portion 22 is greater than the thickness of the first portion 21 .

[0078] It can be understood that, as in the above embodiments Figure 2 and Figure 3 Similarly, in this embodiment, the first source-drain structure 8 can be a source electrode, the second source-drain structure 9 can be a drain electrode, and the source electrode is electrically connected to the first portion 21 through a via hole. In other embodiments, the source electrode is electrically connected to the second portion 22 through a via hole. Figure 4 As shown in , the first source-drain structure 8 (source electrode in this embodiment) is electrically connected to the first portion 21 through a via hole; see Figure 5 , is a schematic structural diagram of a fourth thin film transistor provided in an embodiment of the present application, wherein the first source-drain structure 8 (the source electrode in this embodiment) is electrically connected to the second portion 22 through a via.

[0079] In this embodiment, the thickness of the second portion 22 is greater than that of the first portion 21 . Since both the first portion 21 and the second portion 22 are arranged in contact with the substrate 1 , the first portion 21 and the second portion 22 are at different distances from the channel structure 4 .

[0080] In a possible implementation manner, the thickness of the first portion 21 is 500A-1100A, and the thickness of the second portion 22 is 1100A-3300A.

[0081] In a possible implementation, the first portion 21 includes a third Ti layer and a third Mo layer, wherein the third Mo layer is located on a side of the third Ti layer away from the substrate 1; the second portion 22 includes a fourth Ti layer and a fourth Mo layer, wherein the fourth Mo layer is located on a side of the fourth Ti layer away from the substrate 1;

[0082] The thickness of the third Ti layer and the fourth Ti layer ranges from 100A to 300A; the thickness of the third Mo layer ranges from 400A to 800A, and the thickness of the fourth Mo layer ranges from 1000A to 3000A. In this embodiment, the material of the first gate structure 2 is Ti and Mo, and the Ti layer is located at the bottom of the first gate structure 2, which can ensure that the first gate structure 2 has good conductivity and stability, and the thickness range of each layer can ensure that the thickness of the first part 21 is 500A to 1100A, and the thickness of the second part 22 is 1100A to 3300A.

[0083] In a possible implementation manner, the distance between the first portion 21 and the channel structure 4 ranges from 2800A to 6000A, and the distance between the second portion 22 and the channel structure 4 ranges from 600A to 1600A.

[0084] This embodiment specifically limits the value range of the distance between the first portion 21 and the channel structure 4 and the value range of the distance between the second portion 22 and the channel structure 4, which can improve the stability of the oxide thin film transistor while ensuring that the transistor has a larger SS and Datarange.

[0085] In a possible embodiment, the buffer layer between the first portion 21 and the channel structure 4 and between the first portion 21 and the insulating layer 5 includes a first SiN layer and a first SiO layer, wherein the first SiO layer is located on a side of the first SiN layer away from the first portion 21; the buffer layer between the second portion 22 and the channel structure 4 and between the second portion 22 and the insulating layer 5 includes a second SiN layer and a second SiO layer, wherein the second SiO layer is located on a side of the second SiN layer away from the second portion 22.

[0086] In this embodiment, the thickness of the first SiO layer ranges from 800A to 2000A, and the thickness of the first SiN layer ranges from 2000A to 4000A; the thickness of the second SiO layer and the second SiN layer ranges from 300A to 800A.

[0087] This embodiment defines the buffer layer between the two parts of the first gate structure and the channel structure and the insulating layer. Since the two parts of the first gate structure are at different distances from the channel structure, the thickness of the buffer layer in the middle is also different. The buffer layer in this embodiment includes a SiO layer and a SiN layer, wherein the SiO layer is located on the SiN layer. The value range of the thickness of each layer is limited respectively, which can improve the stability of the oxide thin film transistor while ensuring that the oxide thin film transistor has a larger SS and Data range.

[0088] In a second aspect, the present application provides a display substrate, see Figure 6 , is a schematic diagram of the structure of a display substrate provided in an embodiment of the present application, including a thin film transistor, and the thin film transistor is any thin film transistor described in the first aspect.

[0089] In a third aspect, the present invention provides a method for preparing a thin film transistor. Figure 7 , is a schematic flow chart of a first thin-film transistor manufacturing method provided in an embodiment of the present application, comprising the following steps S101 to S104.

[0090] Step S101: preparing a first gate structure and a buffer layer on a substrate.

[0091] The first gate structure includes a first part and a second part, the first part and the second part are connected in series, and the distances between the upper surfaces of the first part and the second part and the substrate are different.

[0092] Step S102: sequentially preparing a channel structure, an insulating layer, a second gate structure and a dielectric layer on the buffer layer.

[0093] Step S103: opening via holes in the dielectric layer, the insulating layer, and the buffer layer.

[0094] Step S104: preparing a first source-drain structure and a second source-drain structure on the dielectric layer.

[0095] The first source-drain structure is electrically connected to the first gate structure and the channel structure through vias, and the second source-drain structure is electrically connected to the channel structure through vias.

[0096] In a possible implementation, two vias may be provided in the dielectric layer and the insulating layer, namely the first via and the second via, and one via may be provided in the dielectric layer, the insulating layer and the buffer layer, namely the third via. The first source-drain structure is electrically connected to the first gate structure through the third via, the first source-drain structure is electrically connected to the channel structure through the first via, and the second source-drain structure is electrically connected to the channel structure through the second via. This embodiment realizes the electrical connection between the first source-drain structure and the first gate structure and the channel structure, and the electrical connection between the second source-drain structure and the channel structure by providing the first via, the second via and the third via.

[0097] In the embodiments of the present application, the specific process of the preparation method can refer to the prior art, such as the buffer layer, the insulating layer, and the dielectric layer can be prepared by CVD (Chemical Vapor Deposition) film-photo (graphic)-etching, patterning and other processes, and the first gate structure, the second gate structure, the first source-drain structure and the second source-drain structure can be prepared by sputter (sputtering) film-photo-etching, patterning and other processes. This application does not make specific restrictions on this. The specific structure and materials, thickness range and other embodiments of each part can be referred to the aforementioned thin film transistor embodiment, which will not be repeated here.

[0098] The first gate structure in the embodiment of the present application includes a first part and a second part, the first part and the second part are connected in series, and the first part and the second part are at different distances from the channel structure. When analyzing the SS and Data range of the oxide thin film transistor, the part of the gate structure that is at a smaller distance from the channel structure plays a leading role. At this time, due to the increase in the capacitance of the buffer layer, it can be obtained from the above formula (1) that a larger SS and Data range can be guaranteed, thereby clearly distinguishing the grayscale levels of different grayscales; when analyzing the NBTS characteristics of the transistor, the part of the gate structure that is at a larger distance from the channel structure plays a leading role, the electric field strength is weakened, and the NBTS value can be guaranteed to be smaller, thereby improving the stability of the oxide thin film transistor.

[0099] In one possible implementation, see Figure 8 , is a schematic flow chart of a second thin film transistor manufacturing method provided in an embodiment of the present application, wherein the aforementioned step S101 includes the following steps S101A-S101C.

[0100] Step S101A: preparing a first buffer structure on a substrate.

[0101] The orthographic projection of the first buffer structure on the substrate is located in the first region, and the designed position of the second part of the first gate structure falls within the first region.

[0102] Step S101B: preparing a first portion of a first gate structure on the substrate, and preparing a second portion of the first gate structure on the first buffer structure.

[0103] Wherein, the first part and the second part are connected in series.

[0104] Step S101C: preparing the remaining structure of the buffer layer.

[0105] Wherein, the buffer layer includes the first buffer structure.

[0106] In the embodiments of the present application, the specific process of the preparation method can refer to the prior art, such as the buffer layer can be prepared by CVD film-photo-etching, patterning and other processes, and the first gate structure can be prepared by sputter film-photo-etching, patterning and other processes, and the present application does not make specific limitations on this. The specific structure, materials, thickness range and other embodiments of the first part, the second part and the buffer layer of the first gate structure can be referred to the aforementioned thin film transistor embodiment, which will not be repeated here.

[0107] In the embodiment of the present application, the buffer layer includes a first buffer structure, and the orthographic projection of the first buffer structure on the substrate is located in the first region, the design position of the second part of the first gate structure falls within the first region, the first part of the first gate structure is prepared on the substrate, and the second part of the first gate structure is prepared on the first buffer structure, which can ensure that the first part and the second part of the first gate structure are at different distances from the channel structure.

[0108] In one possible implementation, see Fig. 9 , is a schematic flow chart of a third method for preparing a thin film transistor provided in an embodiment of the present application, wherein a first gate structure and a buffer layer are prepared on a substrate, and the aforementioned step S101 includes the following steps S101a-S101b.

[0109] Step S101a: preparing a first portion of a first gate structure and a second portion of the first gate structure on a substrate.

[0110] Wherein, the thickness of the second part is greater than the thickness of the first part.

[0111] Step S101b: preparing a buffer layer.

[0112] In the embodiments of the present application, the specific process of the preparation method can refer to the prior art, such as the buffer layer can be prepared by CVD film-photo-etching, patterning and other processes, and the first gate structure can be prepared by sputter film-photo-etching, patterning and other processes, and the present application does not make specific limitations on this. The specific structure, materials, thickness range and other embodiments of the first part, the second part and the buffer layer of the first gate structure can be referred to the aforementioned thin film transistor embodiment, which will not be repeated here.

[0113] In the present embodiment, the thickness of the second portion of the first gate structure is greater than the thickness of the first portion of the first gate structure. Since the first portion of the first gate structure and the second portion of the first gate structure are both prepared on the substrate, that is, the first portion of the first gate structure and the second portion of the first gate structure are both in contact with the substrate, it is possible to ensure that the first portion and the second portion of the first gate structure are at different distances from the channel structure.

[0114] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0115] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the display substrate and thin film transistor preparation method embodiments, since they are basically similar to the thin film transistor embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the thin film transistor embodiments.

[0116] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A thin film transistor, characterized in that: The thin film transistor comprises: A substrate, a first gate structure, a buffer layer, a channel structure, an insulating layer, a second gate structure, a dielectric layer, a first source-drain structure, and a second source-drain structure; The buffer layer is arranged on the substrate, the insulating layer is arranged on a side of the buffer layer away from the substrate, and the dielectric layer is arranged on a side of the insulating layer away from the substrate; The first gate structure is arranged in the buffer layer, the channel structure is arranged in the insulating layer, the second gate structure is arranged in the dielectric layer, the first source-drain structure is arranged on a side of the dielectric layer away from the substrate, and the first source-drain structure is electrically connected to the channel structure and the first gate structure through a via, and the second source-drain structure is arranged on a side of the dielectric layer away from the substrate, and the second source-drain structure is electrically connected to the channel structure through a via; The first gate structure includes a first portion and a second portion, the first portion and the second portion are connected in series, and the first portion and the second portion are at different distances from the channel structure.

2. The thin film transistor according to claim 1, characterized in that: The first portion is arranged in contact with the substrate, and the second portion has a first distance from the substrate.

3. The thin film transistor according to claim 2, characterized in that: The first distance ranges from 1000A to 2000A.

4. The thin film transistor according to claim 2, characterized in that: The thickness of the first portion and the second portion is 500A-1100A.

5. The thin film transistor according to claim 4, characterized in that: The first portion includes a first Ti layer and a first Mo layer, and the first Mo layer is located on a side of the first Ti layer away from the substrate; the second portion includes a second Ti layer and a second Mo layer, and the second Mo layer is located on a side of the second Ti layer away from the substrate; The thickness of the first Ti layer and the second Ti layer ranges from 100A to 300A; the thickness of the first Mo layer and the second Mo layer ranges from 400A to 800A.

6. The thin film transistor according to claim 1, characterized in that: The first portion and the second portion are both arranged in contact with the substrate, and the thickness of the second portion is greater than the thickness of the first portion.

7. The thin film transistor according to claim 6, characterized in that: The thickness of the first portion is 500A-1100A, and the thickness of the second portion is 1100A-3300A.

8. The thin film transistor according to claim 7, characterized in that: The first portion includes a third Ti layer and a third Mo layer, and the third Mo layer is located on a side of the third Ti layer away from the substrate; the second portion includes a fourth Ti layer and a fourth Mo layer, and the fourth Mo layer is located on a side of the fourth Ti layer away from the substrate; The thickness of the third Ti layer and the fourth Ti layer ranges from 100A to 300A; the thickness of the third Mo layer ranges from 400A to 800A, and the thickness of the fourth Mo layer ranges from 1000A to 3000A.

9. The thin film transistor according to claim 1, characterized in that: The first source-drain structure is a source electrode, and the second source-drain structure is a drain electrode; The source electrode is electrically connected to the first portion through a via hole, or the source electrode is electrically connected to the second portion through a via hole.

10. The thin film transistor according to claim 1, characterized in that: The distance between the first portion and the channel structure ranges from 2800A to 6000A, and the distance between the second portion and the channel structure ranges from 600A to 1600A.

11. The thin film transistor according to claim 10, characterized in that: The buffer layer between the first portion and the channel structure and between the first portion and the insulating layer comprises a first SiN layer and a first SiO layer, wherein the first SiO layer is located on a side of the first SiN layer away from the first portion; the buffer layer between the second portion and the channel structure and between the second portion and the insulating layer comprises a second SiN layer and a second SiO layer, wherein the second SiO layer is located on a side of the second SiN layer away from the second portion; The thickness of the first SiO layer ranges from 800A to 2000A, and the thickness of the first SiN layer ranges from 2000A to 4000A; The thickness of the second SiO layer and the second SiN layer both range from 300 Å to 800 Å.

12. A display substrate, characterized in that: The display substrate comprises the thin film transistor according to any one of claims 1-11.

13. A method for preparing a thin film transistor, characterized in that: The method comprises: Preparing a first gate structure and a buffer layer on a substrate, wherein the first gate structure includes a first portion and a second portion, the first portion and the second portion are connected in series, and the distances between the upper surfaces of the first portion and the second portion and the substrate are different; Sequentially preparing a channel structure, an insulating layer, a second gate structure and a dielectric layer on the buffer layer; Opening via holes in the dielectric layer, the insulating layer, and the buffer layer; A first source-drain structure and a second source-drain structure are prepared on the dielectric layer, wherein the first source-drain structure is electrically connected to the first gate structure and the channel structure through vias, and the second source-drain structure is electrically connected to the channel structure through vias.

14. The method according to claim 13, characterized in that The step of preparing a first gate structure and a buffer layer on a substrate includes: A first buffer structure is prepared on a substrate, wherein an orthographic projection of the first buffer structure on the substrate is located in a first region, and a designed position of a second portion of the first gate structure falls within the first region; Preparing a first portion of the first gate structure on the substrate, and preparing a second portion of the first gate structure on the first buffer structure, the first portion and the second portion being connected in series; A remaining structure of a buffer layer is prepared, wherein the buffer layer includes the first buffer structure.

15. The method according to claim 13, characterized in that The step of preparing a first gate structure and a buffer layer on a substrate includes: Preparing a first portion of a first gate structure and a second portion of the first gate structure on a substrate, wherein a thickness of the second portion is greater than a thickness of the first portion; Prepare a buffer layer.

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