Transistor device and light sensing device

Abstract

The present disclosure provides a transistor device including a substrate and a transistor. The transistor is arranged on the substrate and comprises a grid electrode, a grid dielectric layer, a semiconductor layer, a source electrode and a drain electrode. The gate dielectric layer is disposed on the gate. The semiconductor layer is disposed on the gate dielectric layer and includes a first region and a second region. The first region at least partially overlaps the gate in the normal direction of the substrate, the second region extends from the first region to the edge of the semiconductor layer, and the second region further includes a dopant relative to the first region. The source electrode and the drain electrode are arranged on the semiconductor layer and are electrically connected with the second region of the semiconductor layer. At least one of the source electrode and the drain electrode does not overlap with the gate electrode in the normal direction of the substrate. The invention further provides a light sensing device.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a transistor device and a light sensing device. Background Art

[0002] Top-gate transistors have relatively smaller gate-drain capacitance (Cgd) than bottom-gate transistors, and are therefore often used in light sensing devices; however, top-gate transistors have relatively poor radiation hardness compared to bottom-gate transistors.

[0003] Based on this, in the field of light sensing devices, how to design a transistor with both small gate / drain capacitance and good radiation resistance is one of the current goals. Summary of the invention

[0004] The present disclosure provides a transistor device, wherein the transistor has relatively small gate / drain capacitance and relatively good radiation resistance.

[0005] The transistor device disclosed herein includes a substrate and a transistor. The transistor is disposed on the substrate and includes a gate, a gate dielectric layer, a semiconductor layer, a source and a drain. The gate dielectric layer is disposed on the gate. The semiconductor layer is disposed on the gate dielectric layer and includes a first region and a second region. The first region at least partially overlaps with the gate in the normal direction of the substrate, and the second region extends from the first region to the edge of the semiconductor layer, and the second region further includes a dopant relative to the first region. The source and the drain are disposed on the semiconductor layer and are electrically connected to the second region of the semiconductor layer. At least one of the source and the drain does not overlap with the gate in the normal direction of the substrate.

[0006] The present disclosure provides a light sensing device, wherein the transistor has a relatively small gate / drain capacitance and relatively good radiation resistance.

[0007] The light sensing device disclosed in the present invention includes a substrate, a transistor and a light sensing element. The transistor is disposed on the substrate and includes a gate, a gate dielectric layer, a semiconductor layer, a source and a drain. The gate dielectric layer is disposed on the gate. The semiconductor layer is disposed on the gate dielectric layer, wherein the portion of the gate dielectric layer in contact with the semiconductor layer includes a silicon nitride-based material. The source and the drain are disposed on the semiconductor layer. The light sensing element is disposed on the substrate and coupled to the transistor. The threshold voltage offset of the transistor in the radiation resistance capability of the light sensing device is 0-8V.

[0008] Based on the above, in a transistor device (photosensing device) provided in an embodiment of the present disclosure, the drain does not overlap with the gate in the normal direction of the substrate, which can reduce the parasitic capacitance generated between the drain and the gate; or the portion of the gate dielectric layer in contact with the semiconductor layer includes a silicon nitride-based material, which can make the transistor in the transistor device (photosensing device) have relatively good radiation resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A It is a partial top view schematic diagram of the light sensing device of the first embodiment of the present disclosure;

[0010] Figure 1B Based on Figure 1A A schematic cross-sectional view of an embodiment taken along a section line A1-A1';

[0011] Figure 2A It is a partial top view schematic diagram of a light sensing device according to a second embodiment of the present disclosure;

[0012] Figure 2B Based on Figure 2A A schematic cross-sectional view of an embodiment taken along the section line A2-A2';

[0013] Figure 3A is a partial top view schematic diagram of a light sensing device according to a third embodiment of the present disclosure;

[0014] Figure 3B Based on Figure 3A A schematic cross-sectional view of an embodiment taken along the section line A3-A3';

[0015] Figure 4A is a partial top view schematic diagram of a light sensing device according to a fourth embodiment of the present disclosure;

[0016] Figure 4B Based on Figure 4A A schematic cross-sectional view of an embodiment taken along the section line A4-A4';

[0017] Figure 5A A partial top view of a transistor according to an embodiment of the present disclosure;

[0018] Figure 5B A partial top view schematic diagram of a transistor according to another embodiment of the present disclosure;

[0019] Fig. 6A is a schematic flow chart of a method for manufacturing a light sensing device according to an embodiment of the present disclosure;

[0020] Figure 6B is a schematic flow chart of a method for manufacturing a light sensing device according to another embodiment of the present disclosure;

[0021] Fig. 7AA partial cross-sectional schematic diagram showing a method for manufacturing a light sensing device using photoresists of different heights according to an embodiment;

[0022] Figure 7B for Fig. 7A A graph showing the relationship between the concentration distribution of the dopant in the semiconductor layer of an embodiment of the present invention;

[0023] Figure 7C for Fig. 7A A graph showing the relationship between the concentration distribution of the dopant in the semiconductor layer of another embodiment;

[0024] Fig.7D for Fig. 7A A graph showing the relationship between the concentration distribution of the dopant in the semiconductor layer of another embodiment;

[0025] Fig. 8A A partial cross-sectional schematic diagram showing a method for manufacturing a light sensing device using photoresists of different widths according to an embodiment;

[0026] Figure 8B for Fig. 8A A graph showing the relationship between the concentration distribution of the dopant in the semiconductor layer of an embodiment of the present invention;

[0027] Figure 8C for Fig. 8A A graph showing the relationship between the concentration distribution of the dopant in the semiconductor layer of another embodiment;

[0028] Fig.8D for Fig. 8A A graph showing the relationship between the concentration distribution of the dopant in the semiconductor layer of another embodiment;

[0029] Fig.9A is a characteristic curve diagram of drain current-gate voltage (Id-Vg) of a transistor in the light sensing device of the first embodiment of the present disclosure;

[0030] Fig. 9B is a characteristic curve diagram of drain current-gate voltage of the transistor in the light sensing device of Comparative Example 1. DETAILED DESCRIPTION

[0031] The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to facilitate the understanding of the readers and the simplicity of the drawings, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the drawings are only for illustration and are not intended to limit the scope of the present disclosure.

[0032] Certain words are used throughout the specification and the claims that follow to refer to specific components. It will be understood by those skilled in the art that electronic device manufacturers may refer to the same components by different names. It is not intended herein to distinguish between components that have the same function but different names. In the following specification and claims, words such as "include", "contain", "have" are open-ended words, and therefore should be interpreted as "including but not limited to..." Therefore, when the terms "include", "contain" and / or "have" are used in the description of the present disclosure, they specify the presence of corresponding features, regions, steps, operations and / or components, but do not exclude the presence of one or more corresponding features, regions, steps, operations and / or components.

[0033] Directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only referenced to the directions of the accompanying drawings. Therefore, the directional terms used are used to illustrate, not to limit the present disclosure. In the accompanying drawings, each figure shows the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these drawings should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged.

[0034] When a corresponding component (such as a film layer or region) is referred to as being "on another component", it may be directly on the other component, or other components may exist between the two. On the other hand, when a component is referred to as being "directly on another component", there is no component between the two. In addition, when a component is referred to as being "on another component", the two have a top-down relationship in a top-down direction, and the component may be above or below the other component, and the top-down relationship depends on the orientation of the device.

[0035] The terms "approximately," "equal," "equal," or "same," "substantially," or "approximately" are generally interpreted as within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range.

[0036] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify the elements. They do not imply or represent any previous ordinal numbers of the element (or elements), nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make the element with a certain name clearly distinguishable from another element with the same name. The claims and the specification may not use the same words. Accordingly, the first component in the specification may be the second component in the claim.

[0037] It should be noted that the following embodiments may replace, reorganize, or mix features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. Features between embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0038] The electrical connection or coupling described in the present disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there are switches, diodes, capacitors, inductors, other suitable components, or combinations of the above components between the endpoints of the components on the two circuits, but it is not limited to these.

[0039] In the present disclosure, the thickness, length and width can be measured by an optical microscope, and the thickness can be measured by a cross-sectional image in an electron microscope, but it is not limited to this. In addition, any two values ​​or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0040] The electronic device disclosed herein may include a detection device, a display device, an antenna device (such as a liquid crystal antenna), a light-emitting touch device, a splicing device, a device having other suitable functions, or a combination of devices having the above functions, but is not limited thereto. The electronic device includes a rollable or flexible electronic device, but is not limited thereto. The electronic device may, for example, include a liquid crystal, a light emitting diode (LED), a quantum dot (QD), fluorescence, phosphor, other suitable materials or a combination of the above. The light-emitting diode may, for example, include an organic light emitting diode (OLED), a micro light-emitting diode (micro-LED, mini-LED) or a quantum dot light-emitting diode (QLED, QDLED), but is not limited thereto. The electronic device may include an electronic component. The electronic component may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. The light-emitting diode may, for example, include an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED or a quantum dot light-emitting diode (quantum dot, QD, which may be, for example, QLED, QDLED) or other suitable materials or any combination of the above materials, but is not limited thereto. It should be noted that the electronic device may be any combination of the aforementioned, but is not limited thereto. In addition, the appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges or other suitable shapes. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, a shelf system, etc. to support a display device or a splicing device. It should be noted that the electronic device may be any combination of the aforementioned, but is not limited thereto. The electronic device may include multiple components, and at least two components may be assembled to form a composite component. The following will use a detection device as an electronic device to illustrate the contents of the present disclosure, but the present disclosure is not limited thereto.

[0041] Exemplary embodiments of the present disclosure are described below, and the same reference numerals are used in the drawings and the description to indicate the same or similar parts.

[0042] Figure 1A is a partial top view of the optical sensing device of the first embodiment of the present disclosure, and Figure 1B Based on Figure 1A A schematic cross-sectional view of an embodiment taken along the section line A1-A1'.

[0043] Please also refer to Figure 1A as well as Figure 1B The light sensing device 10a of this embodiment includes a transistor device TD1 and a photosensitive element PS. The light sensing device may be, for example, a direct X-ray sensing device or an indirect X-ray sensing device, but the present disclosure is not limited thereto.

[0044] In this embodiment, the transistor device TD1 includes a substrate SB and a transistor T1 , but the present disclosure is not limited thereto.

[0045] The material of the substrate SB may include, for example, a hard material, a soft material, or a combination thereof. For example, the material of the substrate SB may include quartz, sapphire, polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), or other suitable materials or a combination of the above materials, but the present disclosure is not limited thereto.

[0046] The transistor T1 is, for example, disposed on the substrate SB. In the present embodiment, the transistor T1 includes a gate G, a gate dielectric layer GI, a semiconductor layer SE, a source S, and a drain D.

[0047] The gate G is, for example, disposed on the substrate SB. In some embodiments, the material of the gate G may include molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), hafnium (Hf), nickel (Ni), chromium (Cr), cobalt (Co), zirconium (Zr), tungsten (W), aluminum (Al), copper (Cu), silver (Ag), other suitable metals, or alloys or combinations of the above materials, but the present disclosure is not limited thereto.

[0048] The gate dielectric layer GI is, for example, disposed on the gate G, and may, for example, cover the gate G. In some embodiments, the material of the gate dielectric layer GI may include an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material (e.g., a polyimide resin, an epoxy resin, or an acrylic resin), or a combination thereof, but the present disclosure is not limited thereto. In the present embodiment, the material of the gate dielectric layer GI includes a silicon nitride-based material, and the silicon nitride-based material may include SiN, SiON, SiCN, SiOCN, or a combination thereof. In some embodiments, the gate dielectric layer GI may include a single-layer structure or a multi-layer structure, and the present disclosure is not limited thereto. However, when the gate dielectric layer GI includes a multi-layer structure, the portion (layer) of the gate dielectric layer GI in contact with the semiconductor layer SE includes a silicon nitride-based material. By making the gate dielectric layer GI include a silicon nitride-based material and making the portion of the gate dielectric layer GI in contact with the semiconductor layer SE include a silicon nitride-based material, the radiation hardness of the transistor T1 can be improved, which will be further described in subsequent experimental examples.

[0049] The semiconductor layer SE is, for example, disposed on the gate dielectric layer GI, and at least partially overlaps with the gate G in, for example, the normal direction n of the substrate SB. In the present embodiment, the material of the semiconductor layer SE includes a metal oxide, and the metal oxide may include indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZTO), or an organic semiconductor including a polycyclic aromatic compound, or a combination thereof, but the present disclosure is not limited thereto. In other embodiments, the material of the semiconductor layer SE includes silicon, which may include low temperature polysilicon (LTPS) or amorphous silicon (a-Si), but the present disclosure is not limited thereto. For example, the material of the semiconductor layer SE may include but is not limited to amorphous silicon, polycrystalline silicon, germanium, compound semiconductors (such as gallium nitride, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (such as SiGe alloy, GaAsP alloy, AlInAs alloy, AlGaAs alloy, GaInAs alloy, GaInP alloy, GaInAsP alloy) or combinations of the foregoing.

[0050] In some embodiments, the semiconductor layer SE includes a first region SE_R1 and a second region SE_R2. The first region SE_R1 of the semiconductor layer SE, for example, at least partially overlaps with the gate G in the normal direction n of the substrate SB. In the present embodiment, the first region SE_R1 of the semiconductor layer SE overlaps with the gate G in the normal direction n of the substrate SB to serve as a channel region of the transistor T1. The second region SE_R2 of the semiconductor layer SE, for example, extends from the first region SE_R1 to the edge SE_E of the semiconductor layer SE. In detail, the semiconductor layer SE may include, for example, one first region SE_R1 and two second regions SE_R2, wherein the two second regions SE_R2 may be respectively a second region SE_R21 and a second region SE_R22, and the second region SE_R21 and the second region SE_R22 respectively extend from opposite ends of the first region SE_R1 to two edges SE_E of the semiconductor layer SE, but the present disclosure is not limited thereto.

[0051] In the present embodiment, the second region SE_R2 of the semiconductor layer SE further includes dopants relative to the first region SE_R1. Specifically, the second region SE_R2 of the semiconductor layer SE may include, for example, additional dopants relative to the first region SE_R1, wherein the dopants include, for example, B, Ar, P, F, or a combination thereof. By making the second region SE_R2 of the semiconductor layer SE include the additional dopants relative to the first region SE_R1, the oxygen vacancy in the second region SE_R2 of the semiconductor layer SE may be increased due to the introduction of the dopants. The generation of oxygen vacancy means that the valence electrons from the metal originally attracted by the oxygen ions will be released and become free electrons. Based on this, when the oxygen vacancy increases, the free electrons in the second region SE_R2 of the semiconductor layer SE will also increase, resulting in a decrease in the impedance of the second region SE_R2 of the semiconductor layer SE, so that the impedance value of the second region SE_R2 of the semiconductor layer SE may be lower than the impedance value of the first region SE_R1.

[0052] The source electrode S and the drain electrode D are, for example, disposed on the semiconductor layer SE and are, for example, separated from each other. In the present embodiment, the source electrode S and the drain electrode D are in direct contact with the semiconductor layer SE and are electrically connected thereto, but the present disclosure is not limited thereto. The material included in the source electrode S and the drain electrode D may be, for example, the same or similar to the material included in the gate electrode G, and will not be described in detail herein.

[0053] In some embodiments, at least one of the source S and the drain D does not overlap with the gate G in the normal direction n of the substrate SB. In this embodiment, the source S and the drain D do not overlap with the gate G in the normal direction n of the substrate SB. In some embodiments, the distance D between the drain D and the gate G in the first direction d1 is DGThe first direction d1 is perpendicular to the normal direction n of the substrate SB. By making the drain electrode D not overlap the gate electrode G, the parasitic capacitance generated between the drain electrode D and the gate electrode G can be reduced, so that the transistor T1 can have a relatively small gate / drain capacitance (gate-drain capacitance; Cgd) and have a relatively good electrical performance. Furthermore, the load of the data line DL electrically connected to the drain electrode D can also be reduced.

[0054] In addition, in the present embodiment, the source S and the drain D are electrically connected to the second region SE_R2 of the semiconductor layer SE. Specifically, the source S and the drain D are electrically connected to the second region SE_R21 and the second region SE_R22 located on both sides of the first region SE_R1, for example. By electrically connecting the source S and the drain D to the second region SE_R2 with relatively low impedance, the ability of the gate G to control the first region SE_R1 (channel region) of the semiconductor layer SE can be increased when at least one of the source S and the drain D does not overlap with the gate G in the normal direction n of the substrate SB, so that the transistor T1 can have relatively good electrical performance.

[0055] Based on the above introduction to the components of the transistor T1, it can be seen that the transistor T1 of this embodiment is a bottom-gate transistor, and is an inverted-staggered bottom-gate transistor. As mentioned above, the transistor T1 of this embodiment can have a relatively small gate / drain capacitance and a relatively good radiation resistance, and the reasons are not repeated here.

[0056] The photosensitive element PS is, for example, disposed on the substrate SB and coupled to the transistor T1. In the present embodiment, the photosensitive element PS does not overlap with the transistor T1 in the normal direction of the substrate SB, but the present disclosure is not limited thereto. The photosensitive element PS may, for example, include a lower electrode BE, an upper electrode TE, and a semiconductor PD, wherein the semiconductor PD is, for example, disposed between the lower electrode BE and the upper electrode TE in the normal direction n of the substrate SB. The photosensitive element PS may, for example, be coupled to the source S of the transistor T1 through the lower electrode BE, and may, for example, be coupled to the bias line BL to be introduced later through the upper electrode TE. In some embodiments, the material of the lower electrode BE and the upper electrode TE may, for example, include a transparent conductive material, which may be, for example, indium tin oxide (ITO), but the present disclosure is not limited thereto. The material of the semiconductor PD may, for example, include amorphous silicon, but the present disclosure is not limited thereto. In other embodiments, the semiconductor PD may include a single crystal material or a polycrystalline material. In some embodiments, the semiconductor PD includes a first layer (not shown), an intrinsic layer (not shown) and a second layer (not shown), and the first layer, the intrinsic layer and the second layer are stacked in this order in the normal direction n of the substrate SB, but the present disclosure is not limited to this.

[0057] In some embodiments, the semiconductor PD of the photosensitive element PS can receive light and generate carriers (e.g., electrons and / or holes), and when the transistor T1 is not turned on, the carriers are stored in the photosensitive element PS. After the transistor T1 is turned on, the carriers stored in the photosensitive element PS can be transmitted to a processing circuit (not shown) via, for example, a lower electrode BE and a data line DL (read line) coupled to the transistor T1 and to be described later, thereby achieving the purpose of light sensing.

[0058] In this embodiment, when the light sensing device 10a is used for light sensing, the threshold voltage shift of the transistor T1 in the radiation resistance of the light sensing device 10a is 0-8V, which will be further described in the subsequent experimental examples. In some embodiments, the threshold voltage shift of the transistor T1 in the radiation resistance of the light sensing device 10a may be 0-6V. In other embodiments, the threshold voltage shift of the transistor T1 in the radiation resistance of the light sensing device 10a may be 0-4V.

[0059] In some embodiments, the light sensing device 10 a further includes an insulating layer PV1 .

[0060] The insulating layer PV1 is, for example, disposed between the transistor T1 and the photosensitive element PS. In the present embodiment, the insulating layer PV1 partially covers the source S of the transistor T1. Specifically, the insulating layer PV1 has an opening BE_OP exposing a portion of the source S, wherein the lower electrode BE of the photosensitive element PS is disposed on the insulating layer PV1 and can be electrically connected to the source S of the transistor T1 through the opening BE_OP, but the present disclosure is not limited thereto. The material of the insulating layer PV1 can include, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material (e.g., polyimide resin, epoxy resin, or acrylic resin), or a combination thereof, but the present disclosure is not limited thereto.

[0061] In some embodiments, the light sensing device 10 a further includes scan lines SL, data lines DL, and bias lines BL.

[0062] The scan line SL is, for example, disposed on the substrate SB and coupled to the gate G of the transistor T1, wherein the scan line SL can be, for example, used to provide a scan signal to the corresponding transistor T1 to turn it on. In some embodiments, the scan line SL extends in the first direction d1, but the present disclosure is not limited thereto. In the present embodiment, the scan line SL and the gate G can be formed by the same conductor layer. Therefore, the material of the scan line SL can be, for example, the same as the material of the gate G, which will not be described in detail herein.

[0063] The data line DL is, for example, disposed on the substrate SB and coupled to the drain D of the transistor T1, wherein the signal (carrier) generated by the photosensitive element PS can be transmitted to the data line DL via the drain D, and the data line DL can transmit the signal (carrier) to a processing circuit (not shown). In some embodiments, the data line DL extends in a second direction d2, wherein the second direction d2 can be perpendicular to the first direction d1, but the present disclosure is not limited thereto.

[0064] In this embodiment, the data line DL and the source electrode S and the drain electrode D belong to the same layer, but the present disclosure is not limited thereto. In other embodiments, the data line DL and the bottom electrode BE of the photosensitive element PS belong to the same layer. In still other embodiments, the data line DL and the bias line BL to be described later belong to the same layer. In still other embodiments, the data line DL and (1) the source electrode S and the drain electrode D, (2) the bottom electrode BE of the photosensitive element PS, and (3) the bias line BL belong to different layers.

[0065] In some embodiments, the data line DL may be farther from the gate G of the transistor T1 relative to the drain D in the normal direction n of the substrate SB. By increasing the distance between the data line DL and the gate G, the parasitic capacitance of the data line DL may be reduced, thereby reducing the load of the data line DL.

[0066] The bias line BL is, for example, disposed on the substrate SB and coupled to the photosensitive element PS, wherein the bias line BL can be used to apply a voltage level to the photosensitive element PS. In some embodiments, the bias line BL extends toward the second direction d2, but the disclosure is not limited thereto.

[0067] In some embodiments, the light sensing device 10 a further includes an insulating layer PV2 , a planar layer PL1 , an insulating layer PV3 , and a planar layer PL2 .

[0068] The insulating layer PV2 is, for example, disposed between the bias line BL and the photosensitive element PS. In the present embodiment, the insulating layer PV2 partially covers the upper electrode TE of the photosensitive element PS. In detail, the insulating layer PV2 has an opening PV2_OP exposing a portion of the upper electrode TE. The material of the insulating layer PV2 may include, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material (e.g., polyimide resin, epoxy resin, or acrylic resin), or a combination thereof, but the present disclosure is not limited thereto.

[0069] The planar layer PL1 is, for example, disposed between the bias line BL and the insulating layer PV2. In the present embodiment, the planar layer PL1 also partially covers the upper electrode TE of the photosensitive element PS. Specifically, the planar layer PL1 also has an opening PL1_OP exposing a portion of the upper electrode TE, that is, the opening PL1_OP of the planar layer PL1 can be connected with the opening PV2_OP of the insulating layer PV2 to form an opening TE_OP to expose a portion of the upper electrode TE together, wherein the bias line BL is disposed on the planar layer PL and can be electrically connected to the upper electrode TE of the photosensitive element PS through the opening TE_OP, but the present disclosure is not limited thereto. The material of the planar layer PL1 can be, for example, an organic material, such as: a polyimide resin, an epoxy resin, or an acrylic resin, or a combination thereof, but the present disclosure is not limited thereto.

[0070] The insulating layer PV3 is, for example, disposed on the bias line BL. In the present embodiment, the insulating layer PV3 covers the bias line BL, but the present disclosure is not limited thereto. In addition, in the present embodiment, the insulating layer PV3 may cover the photosensitive element PS and may be used to protect the photosensitive element PS. The material of the insulating layer PV3 may, for example, include an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material (e.g., polyimide resin, epoxy resin, or acrylic resin), or a combination thereof, but the present disclosure is not limited thereto.

[0071] The flat layer PL2 is, for example, disposed on the insulating layer PV3. In the present embodiment, the flat layer PL2 covers the insulating layer PV3, but the present disclosure is not limited thereto. The material of the flat layer PL2 may, for example, include an organic material (e.g., a polyimide resin, an epoxy resin, or an acrylic resin), but the present disclosure is not limited thereto. In some embodiments, the flat layer PL2 may have flatness so that subsequent components may be stably formed on the flat layer PL2. For example, a scintillator (not shown) may be disposed on the flat layer PL2 later, but the present disclosure is not limited thereto.

[0072] In addition, in some other embodiments, the light sensing device 10a may further include an insulating layer (not shown) disposed between the source S and the drain D and the semiconductor layer SE. The insulating layer may have openings exposing portions of the second region SE_R21 and the second region SE_R22, and the source S and the drain D may be electrically connected to the second region SE_R21 and the second region SE_R22 through the openings.

[0073] Figure 2A is a partial top view of a light sensing device according to a second embodiment of the present disclosure, and Figure 2B Based on Figure 2A A schematic cross-sectional view of an embodiment of the invention is shown along the section line A2-A2'. It should be noted that: Figure 2A as well as Figure 2BThe embodiments can be used separately Figure 1A as well as Figure 1B The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0074] Please also refer to Figure 2A as well as Figure 2B The main difference between the light sensing device 10b of this embodiment and the aforementioned light sensing device 10a is that the photosensitive element PS' at least partially overlaps with the transistor T1 in the normal direction n of the substrate SB.

[0075] In detail, in the present embodiment, the light sensing device 10b further includes a planar layer PL3. The planar layer PL3 is, for example, disposed between the light sensing element PS' and the transistor T1. In the present embodiment, the planar layer PL3 partially covers the source S of the transistor T1. In detail, the planar layer PL3 has an opening PL3_OP exposing a portion of the source S, wherein the opening PL3_OP of the planar layer PL3 can be connected with the opening PV1_OP of the insulating layer PV1 to form an opening BE_OP' to expose a portion of the source S together, and the lower electrode BE of the light sensing element PS' is disposed on the planar layer PL3 and can be electrically connected to the source S of the transistor T1 through the opening BE_OP', but the present disclosure is not limited thereto. The material of the planar layer PL3 can be the same as or similar to the material of the planar layer PL1, and will not be described in detail herein. In this embodiment, by making the photosensitive element PS' at least partially overlap with the transistor T1 in the normal direction n of the substrate SB, the surface area of ​​the photosensitive element PS' in the normal direction n of the substrate SB can be increased to have a relatively high fill factor (FF), thereby improving the photoelectric conversion efficiency of the photosensitive element PS'.

[0076] Figure 3A is a partial top view of a light sensing device according to a third embodiment of the present disclosure, and Figure 3B Based on Figure 3A A schematic cross-sectional view of an embodiment of the invention is shown along the section line A3-A3'. It should be noted that: Figure 3A as well as Figure 3B The embodiments can be used separately Figure 1A as well as Figure 1B The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0077] Please also refer to Figure 3A as well as Figure 3BThe main difference between the light sensing device 10c of this embodiment and the aforementioned light sensing device 10a is that the source S′ in the transistor T2 of the transistor device TD2 at least partially overlaps with the gate G in the normal direction n of the substrate SB.

[0078] In this embodiment, the source S' extends further along the first direction d1 than the source S in the above embodiment, so that the source S' may have an overlapping portion SG with the gate G in the normal direction n of the substrate SB. In some embodiments, the width W of the portion SG overlapping the source S' and the gate G in the first direction d1 (the direction in which the extra portion of the source S' extends relative to the source S) is SG By making the source S' overlap at least partially with the gate G in the normal direction n of the substrate SB, the distance between the source S' and the drain D in the first direction d1 can be relatively shortened, so that the path of the drain current in the transistor T2 can be relatively reduced, thereby improving the electrical performance of the transistor T2.

[0079] Figure 4A is a partial top view of a light sensing device according to a fourth embodiment of the present disclosure, and Figure 4B Based on Figure 4A A schematic cross-sectional view of an embodiment of the invention is shown along the section line A4-A4'. Figure 4A as well as Figure 4B The embodiments can be used in their own way Figure 2A as well as Figure 2B and Figure 3A as well as Figure 3B The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0080] Please also refer to Figure 4A as well as Figure 4B The main difference between the light sensing device 10d of this embodiment and the aforementioned light sensing device 10c is that the photosensitive element PS' at least partially overlaps with the transistor T1 in the normal direction n of the substrate SB.

[0081] Specifically, in the present embodiment, the light sensing device 10d further includes a planar layer PL3, wherein the introduction of the planar layer PL3 can refer to the technical content of the light sensing device 10b, and will not be repeated here. In the present embodiment, by making the light sensing element PS' overlap at least partially with the transistor T2 in the normal direction n of the substrate SB, the surface area of ​​the light sensing element PS' in the normal direction n of the substrate SB can be increased and have a relatively high fill factor (FF), thereby improving the photoelectric conversion efficiency of the light sensing element PS'.

[0082] Figure 5A is a partial top view of a transistor according to an embodiment of the present disclosure, and Figure 5B This is a partial top view of a transistor according to another embodiment of the present disclosure. It should be noted that: Figure 5A as well as Figure 5B The embodiments can be used separately Figure 1A The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0083] Please refer to Figure 5A In this embodiment, the width W of the drain D in the transistor T1 in the second direction d2 is D may be smaller than the width W of the semiconductor layer SE in the second direction d2 SE In addition, in this embodiment, the width W of the drain electrode S in the transistor T1 in the second direction d2 is S It may also be smaller than the width W of the semiconductor layer SE in the second direction d2. SE ; however, the present disclosure is not limited thereto.

[0084] Please refer to Figure 5B In this embodiment, the width W of the drain D' in the transistor T1' in the second direction d2 is D’ may be greater than the width W of the semiconductor layer SE in the second direction d2 SE’ In addition, in this embodiment, the width W of the drain S" in the transistor T1 in the second direction d2 is S” It may also be greater than the width W of the semiconductor layer SE in the second direction d2. SE’ ; however, the present disclosure is not limited thereto.

[0085] It is worth mentioning that Figure 5A as well as Figure 5B The illustrated size relationship between the drain D (or drain D′) and the source S (or source S″) and the semiconductor layer SE can also be applied to the above-mentioned light sensing element 10b, light sensing element 10c and light sensing element 10d, and will not be repeated here.

[0086] Fig. 6A FIG. 1 is a flow chart of a method for manufacturing a light sensing device according to an embodiment of the present disclosure. It is worth noting that: Fig. 6A The light sensing device described herein is taken as the above-mentioned light sensing device 10 a as an example, but it should be noted that the present disclosure is not limited thereto.

[0087] Please refer to Fig. 6A , the manufacturing method of the optical sensing device 10a of this embodiment includes the following steps.

[0088] Step (1): A gate G, a gate dielectric layer GI and a semiconductor layer SEa are sequentially formed on a substrate SB, wherein the gate dielectric layer GI covers the gate G, and the semiconductor layer SEa at least partially overlaps with the gate G in the normal direction n of the substrate SB. The materials included in the substrate SB can refer to the aforementioned embodiments and will not be described in detail here. The method for forming the gate G can, for example, include the following steps. First, a gate material layer (not shown) is formed on the substrate SB using physical vapor deposition or metal chemical vapor deposition or other suitable processes, and then the gate material layer is patterned to form the gate G, but the present disclosure is not limited thereto. The materials included in the gate G and its structure can refer to the aforementioned embodiments and will not be described in detail here. The method for forming the gate dielectric layer GI can, for example, be formed on the substrate SB using chemical vapor deposition or other suitable processes, but the present disclosure is not limited thereto. The materials included in the gate dielectric layer GI and its structure can refer to the aforementioned embodiments and will not be described in detail here.

[0089] The method for forming the semiconductor layer SEa may, for example, include the following steps. First, a semiconductor material layer (not shown) is formed on the substrate SB by sputtering or other suitable processes, and then the semiconductor material layer is patterned to form the semiconductor layer SEa, but the present disclosure is not limited thereto. The materials and structures included in the semiconductor layer SEa can refer to the semiconductor layer SE of the aforementioned embodiment, and will not be described in detail here. In the present embodiment, the material of the semiconductor layer SEa includes indium gallium zinc oxide (IGZO).

[0090] Step (2): performing ion implantation on the semiconductor layer SEa using the photoresist PR to form the semiconductor layer SE including the first region SE_R1 and the second region SE_R2.

[0091] In detail, a photoresist PR may be provided to cover a portion of the semiconductor layer SEa, and then an ion implantation device (not shown) may be used to ionize the dopant, and the ionized dopant may be implanted into the semiconductor layer SEa using an electric field and / or a magnetic field, wherein the area covered by the photoresist PR is approximately the first region SE_R1 of the semiconductor layer SE, and the area not covered by the photoresist PR is approximately the second region SE_R2 of the semiconductor layer SE. The material of the dopant used in the ion implantation method may refer to the aforementioned embodiment, and will not be described in detail herein. In addition, after the ion implantation method is performed, the photoresist PR may be removed.

[0092] Step (3): forming a source S and a drain D in the gate dielectric layer GI to form a transistor T1, wherein the source S and the drain D are electrically connected to the second region SE_R2 of the semiconductor layer SE, and the source S and the drain D do not overlap with the gate G in the normal direction n of the substrate SB.

[0093] In detail, a source and drain material layer (not shown) may be formed on the gate dielectric layer GI by physical vapor deposition or metal chemical vapor deposition or other suitable processes, and then the source and drain material layers are patterned to form a source S and a drain D, respectively, but the present disclosure is not limited thereto. The materials and structures of the source S and the drain D may refer to the aforementioned embodiments, and will not be described in detail herein. In the present embodiment, the source S and the drain D are, for example, respectively electrically connected to the second region SE_R21 and the second region SE_R22 located on both sides of the first region SE_R1.

[0094] In the present embodiment, the transistor T1 may be formed by a back channel etch (BCE) process, that is, an etching stop layer is not formed on the semiconductor layer SE during the process of forming the source S and the drain D, but the present disclosure is not limited thereto.

[0095] It is worth noting that if step (2) is performed after step (3), there will be parts in the second region SE_R2 of the semiconductor layer SE that are covered by the source S and the drain D and cannot be implanted with dopants. These parts will be in contact with the source S and the drain D respectively. When the transistor is turned on, the current will tend to flow through the current path with low impedance, so that the current path flowing from the drain D to the semiconductor layer SE will be densely present in the upper half of the part that is not implanted with dopants. This is called the current crowding effect (CCE). The above-mentioned current crowding effect causes uneven distribution of current density, which makes the transistor prone to loss.

[0096] Based on this, in this embodiment, by performing step (2) first and then performing step (3), the possibility of the transistor T1 generating a current crowding effect can be reduced.

[0097] Furthermore, in the present embodiment, by forming the semiconductor layer SE first and then forming the source electrode S and the drain electrode D, the possibility of disconnection of the semiconductor layer SE can be reduced.

[0098] Step (4): forming a photosensitive element PS on the transistor T1 to form a light sensing device 10a, wherein the photosensitive element PS is coupled to the transistor T1, and the photosensitive element PS does not overlap with the transistor T1 in the normal direction n of the substrate SB.

[0099] The photosensitive element PS may be formed by, for example, sequentially forming a bottom electrode BE, a semiconductor PD, and an upper electrode TE. The photosensitive element PS may be formed by an existing photosensitive element manufacturing method, which will not be described in detail herein.

[0100] In addition, before forming the photosensitive element PS on the transistor T1, an insulating layer PV1 may be formed on the transistor T1. The method for forming the insulating layer PV1 may be, for example, to form it on the transistor T1 using a chemical vapor deposition method or other suitable processes, but the present disclosure is not limited thereto. The materials and structures included in the insulating layer PV1 may refer to the aforementioned embodiments, and will not be described in detail herein. In the present embodiment, the insulating layer PV1 has an opening BE_OP that exposes a portion of the source S, wherein the photosensitive element PS may be electrically connected to the transistor T1 through the opening BE_OP, but the present disclosure is not limited thereto.

[0101] In addition, after forming the photosensitive element PS on the transistor T1, an insulating layer PV2, a planar layer PL1, a bias line BL, an insulating layer PV3, and a planar layer PL2 may be sequentially formed on the photosensitive element PS. The insulating layer PV2, the planar layer PL1, the insulating layer PV3, and the planar layer PL2 may be formed by, for example, chemical vapor deposition or other suitable processes, and the bias line BL may be formed by physical vapor deposition or metal chemical vapor deposition or other suitable processes, but the present disclosure is not limited thereto. In the present embodiment, the openings PL1_OP and PV2_OP of the planar layer PL1 and the insulating layer PV2 are connected to form an opening TE_OP to expose a portion of the upper electrode TE, wherein the bias line BL is disposed so as to be electrically connected to the photosensitive element PS through the opening TE_OP, but the present disclosure is not limited thereto.

[0102] Figure 6B FIG. 1 is a flow chart of a method for manufacturing a light sensing device according to another embodiment of the present disclosure. It should be noted that: Figure 6B The embodiments can be used Fig. 6A The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0103] Please refer to Figure 6B The main difference between the manufacturing method of the optical sensing device 10a of the present embodiment and the aforementioned manufacturing method of the optical sensing device 10a is that in the step (2)' of forming the semiconductor layer SE, the first region SE_R1 and the second region SE_R2 of the semiconductor layer SE are formed by chemical vapor deposition.

[0104] Specifically, after performing step (1), step (2)' is performed. In step (2)', an insulating layer PV0 may be first formed to cover a portion of the semiconductor layer SEa. Thereafter, a chemical vapor deposition method is performed using, for example, silane as a reaction gas to form an insulating layer PV1a' on the semiconductor layer SEa, wherein the area not covered by the insulating layer PV0 may be doped with elements in the reaction gas (e.g., hydrogen in silane) to form the second region SE_R2 of the semiconductor layer SE, and the area covered by the insulating layer PV0 is the first region SE_R1 of the semiconductor layer SE. Based on this, the process for forming the first region SE_R1 and the second region SE_R2 of the semiconductor layer SE in step (2)' can be regarded as a self-aligned process.

[0105] Afterwards, step (3) and step (4) are performed in sequence. It is worth noting that before performing step (3), the insulating layer PV1a' is first patterned to form the insulating layer PV1a that exposes a portion of the second region SE_R21 and the second region SE_R22 of the semiconductor layer SE, so that the source S and the drain D formed in step (3) can be electrically connected to the second region SE_R21 and the second region SE_R22, respectively. In addition, the insulating layer PV0 and the insulating layer PV1a can be used as part of the insulating layer PV1 later, but the present disclosure is not limited thereto.

[0106] Fig. 7A A partial cross-sectional schematic diagram showing a method for manufacturing a light sensing device in which photoresists of different heights are applied according to an embodiment of the present invention. Figure 7B for Fig. 7A A graph showing the relationship between the concentration distribution of the dopant in the semiconductor layer of an embodiment of the present invention, Figure 7C for Fig. 7A A graph showing the relationship between the concentration distribution of the dopant in the semiconductor layer of another embodiment of the present invention and Fig.7D for Fig. 7A A relationship curve diagram of the dopant concentration distribution of the semiconductor layer in another embodiment of the present invention.

[0107] Please refer to Fig. 7A , which shows Fig. 6A Various situations when the photoresist PR is formed on the semiconductor layer SEa, including a first photoresist PR1, a second photoresist PR2 and a third photoresist PR3, and the first photoresist PR1, the second photoresist PR2 and the third photoresist PR3 have different heights.

[0108] For details, please refer to Figure 7B, the first photoresist PR1, the second photoresist PR2 and the third photoresist PR3 have substantially the same width W in the first direction d1 perpendicular to the normal direction n of the substrate SB. In contrast, the first photoresist PR1, the second photoresist PR2 and the third photoresist PR3 each have different heights H1, H2 and H3 in the normal direction n of the substrate SB, wherein the height H1 is smaller than the height H2, and the height H2 is smaller than the height H3. Therefore, when the first photoresist PR1, the second photoresist PR2 and the third photoresist PR3 are used for ion implantation, the concentration distribution of the dopants implanted in the semiconductor layer SE will be different. Figure 7B In the illustrated embodiment, it can be seen that in the semiconductor layer SE formed by using the third photoresist PR3 having a relatively high height H3, it can have a relatively long current path EP3, because the third photoresist PR3 can shield more dopants implanted from above in the ion implantation method compared to the first photoresist PR1 and the second photoresist PR2, so that the first region SE_R1 of the semiconductor layer SE formed by using the third photoresist PR3 will have a relatively large width in the first direction d1. In contrast, the first region SE_R1 of the semiconductor layer SE formed by using the first photoresist PR1 has a relatively small width in the first direction d1, and the second region SE_R1 of the semiconductor layer SE formed by using the second photoresist PR2 can have a moderate width in the first direction d1.

[0109] Please refer to Figure 7C as well as Fig.7D , each showing a case where a photoresist PR is offset when formed on the semiconductor layer SEa, wherein Figure 7C shows the photoresistance PR relative to Figure 7B The photoresist PR in the embodiment is offset along the first direction d1, and Fig.7D shows the photoresistance PR relative to Figure 7B The photoresist PR in the image is offset in a direction opposite to the first direction d1. Figure 7C as well as Fig.7D The embodiments can be used Figure 7B The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0110] Fig. 8A A partial cross-sectional schematic diagram showing a method for manufacturing a light sensing device in which photoresists of different widths are applied according to an embodiment of the present invention. Figure 8B for Fig. 8A A graph showing the relationship between the concentration distribution of the dopant in the semiconductor layer of an embodiment of the present invention, Figure 8C for Fig. 8A A graph showing the relationship between the concentration distribution of the dopant in the semiconductor layer of another embodiment of the present invention and Fig.8D for Fig. 8AA relationship curve diagram of the dopant concentration distribution of the semiconductor layer in another embodiment of the present invention.

[0111] Please refer to Fig. 8A , which shows Fig. 6A Various situations in which the photoresist PR is formed on the semiconductor layer SEa include a first photoresist PR1', a second photoresist PR2' and a third photoresist PR3', and the first photoresist PR1', the second photoresist PR2' and the third photoresist PR3' have different widths.

[0112] For details, please refer to Figure 8B , the first photoresist PR1', the second photoresist PR2' and the third photoresist PR3' have substantially the same height H in the normal direction n of the substrate SB. In contrast, the first photoresist PR1', the second photoresist PR2' and the third photoresist PR3' each have different widths W1, W2 and W3 in the first direction d1 perpendicular to the normal direction n of the substrate SB, wherein the width W1 is smaller than the width W2, and the width W2 is smaller than the width W3. Therefore, when the first photoresist PR1', the second photoresist PR2' and the third photoresist PR3' are used for ion implantation, the concentration distribution of the dopants implanted in the semiconductor layer SE will be different. Figure 8B In the illustrated embodiment, it can be seen that in the semiconductor layer SE formed by using the third photoresist PR3' having a relatively large width W3, it can have a relatively long current path EP3', because the third photoresist PR3' can shield more dopants implanted from above in the ion implantation method compared to the first photoresist PR1' and the second photoresist PR2', so that the first region SE_R1 of the semiconductor layer SE formed by using the third photoresist PR3' will have a relatively large width in the first direction d1. In contrast, the first region SE_R1 of the semiconductor layer SE formed by using the first photoresist PR1' has a relatively small width in the first direction d1, and the first region SE_R1 of the semiconductor layer SE formed by using the second photoresist PR2' can have a moderate width in the first direction d1.

[0113] Please refer to Figure 8C as well as Fig.8D , each showing a case where a photoresist PR is offset when formed on the semiconductor layer SEa, wherein Figure 8C shows the photoresistance PR relative to Figure 8B The photoresist PR in the embodiment is offset along the first direction d1, and Fig.8D shows the photoresistance PR relative to Figure 8B The photoresist PR in the image is offset in a direction opposite to the first direction d1. Figure 8C as well as Fig.8D The embodiments can be used Figure 8BThe component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0114] Experimental example

[0115] The present disclosure will be described below by means of experimental examples, but these experimental examples are only for illustration purposes and are not intended to limit the scope of the present disclosure.

[0116] Fig.9A is a characteristic curve diagram of drain current-gate voltage (Id-Vg) of the transistor in the light sensing device of the first embodiment of the present disclosure, and Fig. 9B is a characteristic curve diagram of drain current-gate voltage of the transistor in the light sensing device of Comparative Example 1.

[0117] The light sensing device used in Example 1 is Figure 1A as well as Figure 1B In the illustrated optical sensing device 10a, the gate insulating layer GI comprises a single silicon nitride layer, and the gate insulating layer GI contacts the semiconductor layer SE. The remaining components of the optical sensing device 10a can refer to the above embodiments, and will not be described in detail herein.

[0118] The optical sensing device used in Comparative Example 1 is substantially the same as the optical sensing device 10a used in Example 1, except that the optical sensing device of Comparative Example 1 further includes a silicon oxide layer, wherein the silicon oxide layer is disposed between the gate insulating layer GI and the semiconductor layer SE and is in contact with the semiconductor layer SE. In addition, the optical sensing device 10a of Example 1 and the optical sensing device of Comparative Example 1 are both used to sense an 80 kV X-ray source.

[0119] [Example 1]

[0120] In the first embodiment, the transistor T1 absorbs 2000 Gray (Gy) of radiation energy, and the threshold voltage shift of the transistor T1 in the radiation resistance capability of the light sensing device 10 a is approximately between 4V and 6V.

[0121] [Comparative Example 1]

[0122] In Comparative Example 1, the transistor absorbs 150 grays of radiation energy, and the threshold voltage shift of the transistor in the radiation resistance capability of the light sensing device is approximately between 15V and 20V.

[0123] Based on the above, since the portion of the gate insulating layer GI where the transistor T1 in the optical sensing device 10a of Example 1 contacts the semiconductor layer SE is a silicon nitride layer with a relatively small energy gap, it has better radiation resistance than the transistor in the optical sensing device of Comparative Example 1.

[0124] In summary, in a transistor device (photosensing device) provided in an embodiment of the present disclosure, the drain does not overlap with the gate in the normal direction of the substrate, which can reduce the parasitic capacitance generated between the drain and the gate, so that the transistor can have a relatively small gate / drain capacitance and have relatively good electrical performance. Furthermore, it can also reduce the load of the data line electrically connected to the drain.

[0125] In a transistor device (photosensing device) provided in another embodiment of the present disclosure, the portion of the gate dielectric layer in contact with the semiconductor layer includes a silicon nitride-based material, which has a smaller energy gap than the silicon oxide layer, thereby enabling the transistor in the transistor device (photosensing device) to have relatively good radiation resistance.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A transistor device, characterized in that: include: substrate; as well as A transistor is disposed on the substrate and includes: Gate; A gate dielectric layer, disposed on the gate; a semiconductor layer disposed on the gate dielectric layer and comprising a first region and a second region, wherein the first region at least partially overlaps with the gate in a normal direction of the substrate, and the second region extends from the first region to an edge of the semiconductor layer, and the second region further comprises dopants relative to the first region; and A source electrode and a drain electrode are disposed on the semiconductor layer and electrically connected to the second region of the semiconductor layer, wherein at least one of the source electrode and the drain electrode does not overlap with the gate electrode in the normal direction of the substrate. 2 . The transistor device according to claim 1 , wherein the source and the drain do not overlap with the gate in the normal direction of the substrate. The transistor device according to claim 1 , wherein a material of the semiconductor layer comprises a metal oxide. 4 . The transistor device of claim 1 , wherein the dopant comprises B, Ar, P, F, or a combination thereof. The transistor device of claim 1 , wherein an impedance of the second region is smaller than an impedance of the first region.

6. The transistor device according to claim 1, further comprising: A scan line, disposed on the substrate and coupled to the gate of the transistor; as well as The data line is disposed on the substrate and coupled to the drain of the transistor. 7 . The transistor device according to claim 6 , wherein the source of the transistor at least partially overlaps the gate in the normal direction of the substrate.

8. The transistor device according to claim 7, wherein the distance between the drain and the gate in a specific direction is greater than 0.5 microns, the width of the overlapping portion of the source and the gate in the specific direction is less than 4 microns, and the specific direction is perpendicular to the normal direction of the substrate. 9 . The transistor device according to claim 6 , wherein the data line and the drain of the transistor belong to different layers, and the data line is away from the gate of the transistor relative to the drain in the normal direction of the substrate.

10. A light sensing device, characterized in that: include: substrate; A transistor is disposed on the substrate and includes: Gate; a gate dielectric layer disposed on the gate; and A semiconductor layer, disposed on the gate dielectric layer, wherein a portion of the gate dielectric layer in contact with the semiconductor layer comprises a silicon nitride-based material; A source electrode and a drain electrode are disposed on the semiconductor layer; and A light sensing element is disposed on the substrate and coupled to the transistor. The threshold voltage shift of the transistor in the radiation resistance capability of the light sensing device is 0-8V. 11 . The light sensing device according to claim 10 , wherein the silicon nitride-based material comprises SiN, SiON, SiCN, SiOCN or a combination thereof. 12 . The light sensing device according to claim 10 , wherein the gate dielectric layer comprises a multi-layer structure.

13. The light sensing device according to claim 10, wherein the semiconductor layer comprises a first region and a second region, the first region at least partially overlaps with the gate in a normal direction of the substrate, the second region extends to the first region to an edge of the semiconductor layer, and the second region further comprises dopants relative to the first region. 14 . The light sensing device according to claim 13 , wherein the source and the drain are electrically connected to the second region of the semiconductor layer, and at least one of the source and the drain does not overlap with the gate in a normal direction of the substrate.

15. The light sensing device according to claim 10, further comprising: A scan line, disposed on the substrate and coupled to the gate of the transistor; A data line, disposed on the substrate and coupled to the drain of the transistor; as well as The bias line is disposed on the substrate and coupled to the light sensing element. 16 . The light sensing device according to claim 10 , wherein the light sensing element at least partially overlaps with the transistor in a normal direction of the substrate.

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