Method for processing cft device with non-conformal gate dielectric
By forming a fin structure and a gate dielectric layer with a non-uniform layer thickness during the CFET manufacturing process, the problem of gate oxide layer wrapping and protection is solved, and effective protection and performance improvement of CFET performance is achieved.
Patent Information
- Application Number
- CN202411401532.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-24
- Filing Date
- 2024-10-09
- Publication Date
- 2025-04-25
AI Technical Summary
During the manufacturing process of complementary field effect transistor (CFET), it is difficult to effectively wrap the nanosheet stack when depositing the gate oxide layer, and subsequent manufacturing steps may destroy the gate oxide and the underlying nanosheet stack, resulting in a degradation of performance.
A fin structure with a non-uniform layer thickness is formed on the substrate, and a thicker gate dielectric layer is formed around the fin structure on the top surface and a thinner gate dielectric layer on the side to protect the fin structure and reduce damage in subsequent manufacturing steps.
By increasing the thickness of the gate dielectric layer on the top surface, the fin structure is effectively protected, NSH erosion is reduced, and the stability of CFET performance is ensured, while thinning the gate dielectric layer on the sides for subsequent processing steps.
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Figure CN119894078A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a method for processing a complementary field effect transistor (CFET) device. Background Art
[0002] In CFET, different transistor structures, in particular NMOS and PMOS transistors, can be stacked on top of each other. For example, compared to a nanosheet device, the nanosheet device includes NMOS and PMOS transistors arranged side by side with spacing between them. The stacking of transistor structures enables the effective channel width to be increased.
[0003] A key step in CFET fabrication is the deposition of a gate oxide layer, which is typically deposited around a stack of nanosheets (NSHs) containing the NMOS and PMOS channels. However, fabricating this gate oxide to wrap around the NSH stack can be challenging.
[0004] In addition, subsequent manufacturing steps (e.g., full gate etching steps) may damage the gate oxide and the underlying NSH stack, which can degrade CFET performance. Such damage to the NSH stack is sometimes referred to as "NSH erosion." NSH erosion generally increases when the gate oxide layer above the NSH stack is relatively thin, because the thin gate oxide provides less protection to the underlying NSH stack. Summary of the invention
[0005] Therefore, it is an object to provide an improved method for processing CFET devices. In particular, the above-mentioned disadvantages should be avoided.
[0006] This object is achieved by the embodiments provided in the attached independent claim. Advantageous implementations of the embodiments of the invention are further defined in the dependent claims.
[0007] A first aspect of the present disclosure provides a method for processing a complementary field effect transistor (CFET) device. The method comprises the following steps: forming at least one fin structure on a substrate, wherein the at least one fin structure comprises a horizontal top surface and two vertically oriented side surfaces between the top surface and the substrate, and wherein the at least one fin structure comprises a first layer stack and a second layer stack above the first layer stack; and forming a gate dielectric layer having a non-uniform layer thickness around the at least one fin structure; wherein the layer thickness of the gate dielectric layer arranged on the top surface of the at least one fin structure is greater than the layer thickness of the gate dielectric layer arranged on the side surfaces of the at least one fin structure.
[0008] This provides the advantage that the fin structure can be efficiently protected from damage during subsequent manufacturing steps. This is because of the increased layer thickness of the gate dielectric on the top surface of the fin structure, where subsequent manufacturing steps (e.g., full gate etching) cause most damage. In particular, so-called NSH corrosion of layers within the fin structure can be reduced.
[0009] The thicker gate dielectric layer on the top surface can serve as a protection layer for the fin structure, while the layer thickness of the gate dielectric layer on the side of the fin structure can be reduced to a level that allows access to the space between two adjacent fin structures and / or further processing steps (e.g., a gate oxide breakthrough step) to be performed in the space.
[0010] The top surface of the fin structure may be an area on the fin structure that wraps around the tip of the fin structure, wherein most or all of the top surface faces away from the substrate. For example, the top surface of the fin structure is tapered (ie, not completely flat). The vertical side surface may be a surface of a sidewall of the fin structure.
[0011] The gate dielectric layer may be a gate oxide (Gox) layer.
[0012] Herein, processing a CFET device may refer to fabricating or manufacturing a CFET device.
[0013] In one embodiment, a layer thickness of the gate dielectric layer arranged on the top surface of the at least one fin structure is 1.5 to 3 times greater than a layer thickness of the gate dielectric layer arranged on the side surfaces of the at least one fin structure.
[0014] This achieves the advantage that the gate dielectric layer above the fin structure can be used as an additional protection layer to protect NSH corrosion.
[0015] In one embodiment, the gate dielectric layer is a silicon dioxide (SiO 2 ) layer.
[0016] In one embodiment, the gate dielectric layer is deposited on the at least one fin structure by a layer deposition technique such as plasma enhanced atomic layer deposition (PEALD) or pulsed chemical vapor deposition (CVD).
[0017] In one embodiment, a gate dielectric layer is thereby formed on a top surface of the at least one fin structure, the gate dielectric layer having a different film quality than on a side surface of the at least one fin structure.
[0018] Here, different film quality may refer to different (e.g., higher) film density and / or dielectric stoichiometry and composition of the gate dielectric layer at the top surface of the fin structure compared to the side surface. This may result in higher film stability (e.g., chemical stability) of the gate dielectric layer on the top surface compared to the gate dielectric layer on the side surface.
[0019] Specifically, non-conformal / non-uniform deposition of the gate dielectric layer can be achieved by a single deposition step, for example in contrast to conformal / uniform deposition with additional plasma treatment. For example, during the same deposition process, the dielectric layer can be deposited on the top surface of the fin structure at a higher deposition rate than on the sides.
[0020] In one embodiment, after deposition, the layer thickness of the gate dielectric layer surrounding the at least one fin structure is reduced by an etching step.
[0021] The etching step may create and / or enhance a layer thickness difference between the gate dielectric layer on the top surface and the side surfaces of the fin structure. For example, the etching step may be a wet etching with a hydrofluoric acid (HF) solution.
[0022] In one embodiment, the etching step has a higher etching rate on the gate dielectric layer disposed on the side of the at least one fin structure than on the gate dielectric layer disposed on the top surface of the at least one fin structure.
[0023] This may be due to the higher film quality and / or stability of the gate dielectric layer on the top surface compared to the gate dielectric layer on the side of the fin structure.
[0024] Thus, step coverage control with wet post-processing can result in thickness modulation of the gate dielectric layer around the 3D topography of the fin structure and / or non-conformal deposition for compact pitch fin structures, such as for CFET FEOL integration. Here, non-conformal deposition can refer to loading the fin structure with a thickness difference between the top surface (thicker gate dielectric) and the sidewalls (thinner gate dielectric).
[0025] In an embodiment, the method further comprises the step of selectively adapting, in particular densifying, a gate dielectric layer arranged on a top surface of the at least one fin structure.
[0026] In this way, the film quality and / or stability of the gate dielectric layer on the top surface may be further enhanced.
[0027] In one embodiment, the step of selectively adapting the gate dielectric layer is performed immediately after the deposition of the gate dielectric layer or directly before the full gate etching step.
[0028] In an embodiment, the selective adaptation of the gate dielectric layer is performed by any of the following techniques: plasma treatment, UV treatment or annealing.
[0029] In one embodiment, arrays of two or more fin structures are generated simultaneously.
[0030] In one embodiment, the method further comprises the step of forming at least one gate structure on or around the at least one fin structure.
[0031] The gate structure may be a fin-shaped structure arranged perpendicular to the fin structure. The gate structure may be a dummy gate structure. The dummy gate structure may be replaced by a replacement metal gate structure in a later step.
[0032] In an embodiment, the first layer stack includes at least one channel layer of a first transistor structure of a CFET device, and the second layer stack includes at least one channel layer of a second transistor structure of the CFET device.
[0033] The first (or bottom) transistor structure may be arranged in a first level (or layer) of the CFET device and the second (or top) transistor structure may be arranged in a second level (or layer) of the CFET device, wherein the second level is arranged above the first level. This may result in a stacked transistor structure of the CFET device. The CFET device may further include transistor structures or other elements that may be directly above or below the first and second transistor structures, respectively.
[0034] For example, the first transistor structure and the second transistor structure may form a CFET cell.A CFET device may include one or more CFET cells or portions thereof.
[0035] It is worth noting that in the present disclosure, the terms "below" and "above", "bottom" and "top" or similar terms should be interpreted mutually. Specifically, these terms describe the opposite sides of the CFET device or the opposite sides of any element of the CFET device. These terms can describe the relationship of the elements of the CFET device (e.g., transistor structures, signal wiring, power rails, etc.) along the stacking direction of each level (or each layer) of the CFET device. The stacking direction can therefore be aligned with the arrangement of two levels (or even more than two levels) of the CFET device. That is, two or more levels (or layers) arranged above each other are arranged one by one along a certain direction (stacking direction).
[0036] The transistor structure in the present disclosure may be or may include a transistor, such as a field effect transistor (FET), or may be or may include a more complex semiconductor-based structure that functions similarly to a transistor. For example, the semiconductor-based structure may be a nanosheet structure, a fin structure, or a fork-sheet structure, for example, provided with a gate that partially wraps around or completely wraps around a channel portion. The latter may be, for example, a gate-around structure.
[0037] The transistor structure of the CFET device of the first aspect can be an NMOS and a PMOS transistor structure. For example, the first transistor structure can be an NMOS transistor structure and the second transistor structure can be a PMOS transistor structure, or vice versa.
[0038] In one embodiment, the method further comprises the following steps: forming a first source and / or drain structure electrically contacting a first layer stack of at least one fin structure; and forming a second source and / or drain structure electrically contacting a second layer stack of the at least one fin structure.
[0039] For example, the source and / or drain structures are formed by an epitaxial growth process.
[0040] A second aspect of the present disclosure provides a CFET device, which can be obtained by the method according to the first aspect of the present disclosure.
[0041] This CFET device produced by the method of the first aspect of the present disclosure shows a clear “fingerprint” of the method. For example, an electron microscope image of a cross section of the CFET device can reveal different layer thicknesses of the gate dielectric layer on the top and side surfaces of the fin structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] The above aspects and implementations are explained in the following description of embodiments with respect to the accompanying drawings:
[0043] Figure 1 AD show the steps of a method for processing a CFET device according to an embodiment.
[0044] Figure 2 AB show steps of a method for processing a CFET device according to an embodiment.
[0045] Figure 3 AB show steps of a method for processing a CFET device according to an embodiment. DETAILED DESCRIPTION
[0046] Figure 1 AD show the steps of a method for processing a CFET device according to an embodiment. Figure 1 AD thus shows a cross-sectional view of the xz plane (as shown in a Cartesian coordinate system) perpendicular to the channel direction (y direction) of the CFET device.
[0047] exist Figure 1 In the examples shown in AD, two structures with the same basic elements are processed side by side. The two structures may form different CFET devices or different CFET units or components of a single CFET unit. The CFET device may be a unit of a CFET unit, where a unit means that the CFET device may be repeated one or more times in the CFET unit. Specifically, equivalent elements of the two structures (and other structures not shown) may be formed simultaneously. In the following, processing steps that may be equivalent for the two structures are generally described with reference to only one (or at least one) of the structures.
[0048] exist Figure 1 In a first step shown in A, the method includes forming at least one fin structure 23 on the substrate 14 , wherein the at least one fin structure includes a horizontal top surface and two vertically oriented side surfaces between the top surface and the substrate 14 .
[0049] The at least one fin structure 23 includes a first layer stack 23 a and a second layer stack 23 b above the first layer stack 23 a .
[0050] The first layer stack 23a may include at least one channel 11a of a first transistor structure of a CFET device, and the second layer stack 23b may include at least one channel 12a of a second transistor structure of a CFET device. For example, the first transistor structure is a bottom transistor structure of a CFET device, and the second transistor structure is a top transistor structure of a CFET device. The bottom transistor structure may be NMOS, and the top transistor structure may be PMOS, or vice versa.
[0051] The first and second layer stacks 23a, 23b may be arranged directly on top of each other. Each layer stack 23a, 23b may include a plurality of alternating layers, the plurality of alternating layers including at least one channel layer (e.g., Si layer) and at least one dielectric layer. For example, each layer stack 23a, 23b may include alternating Si and SiGe layers. The top layer of the fin structure 23 may be a Si3N4 layer. A dielectric isolation layer stack (e.g., an intermediate dielectric isolation MDI) may be arranged between the first and second layer stacks 23a, 23b. For example, an isolation layer may include a SiGe layer (with a high Ge percentage), which is initially a part of the Si / SiGe layer stack 23a, 23b and is converted into a dielectric in a subsequent step. However, the dielectric isolation layer stack may also be a part of the first or second layer stack 23a, 23b, such as in the case of an embedded MDI.
[0052] The fin structure 23 may be formed on the substrate 14 by active nanosheet patterning, for example, by patterning of a nanosheet stack on the substrate 14. The nanosheet stack may include a layer stack 23a, 23b and a dielectric isolation layer stack.
[0053] like Figure 1 As shown in FIG. 1B and FIG. 1C , the method further includes forming a gate dielectric layer 41 having a non-uniform layer thickness around the at least one fin structure 23. Thus, the layer thickness of the gate dielectric layer 41 arranged on the top surface of the at least one fin structure 23 is greater than the layer thickness of the gate dielectric layer arranged on the side surface of the at least one fin structure 23.
[0054] The gate dielectric layer 41 may be a gate oxide layer, such as a silicon dioxide (SiO 2 ) layer.
[0055] The gate dielectric layer 41 may be Figure 1 In a first step shown in B, the gate dielectric layer 41 is deposited around the fin structure 23. For example, the gate dielectric layer 41 may thus be deposited by a layer deposition technique such as plasma enhanced atomic layer deposition (PEALD) or pulsed chemical vapor deposition (CVD).
[0056] Subsequently, the layer thickness of the gate dielectric layer 41 may be reduced by an etching step, such as Figure 1 As shown in FIG. C. As a result, the gate dielectric layer 41 on the side of the fin structure 23 can be etched at a higher etching rate than the gate dielectric layer 41 on the top surface of the fin structure 23 (the etching rate is higher than that of the gate dielectric layer 41 on the top surface of the fin structure 23). Figure 1 C). In this way, a gate dielectric layer 41 having a non-conformal (ie, non-uniform) layer thickness surrounding the fin structure 23 may be generated, wherein the layer thickness on the top surface of the fin structure 23 is greater than the layer thickness on the side surfaces.
[0057] For example, the layer thickness of the gate dielectric layer 41 arranged on the top surface of the at least one fin structure 23 is 1.5 to 3 times greater than the layer thickness of the gate dielectric layer 41 arranged on the side surfaces of the at least one fin structure 23 .
[0058] Such a non-conformal layer thickness of the gate dielectric 41 can be advantageous in different integration schemes and modules. For example, a thicker dielectric layer 41 on the top surface of the fin structure 23 can be used as a protective layer during subsequent processing steps. In this way, for example, the so-called NSH erosion effect can be reduced. In addition, the reduced layer thickness on the side of the fin structure 23 can provide more space for downstream integration applications between adjacent fins, especially when using high aspect ratio fin structures 23 with close spacing between lines.
[0059] The gate dielectric layer 41 may be directly deposited as a non-conformal layer, ie having a higher layer thickness on the top surface of the fin structure 23 than on the side surfaces of the fin structure 23. This non-uniformity can then be corrected by an etching step ( Figure 1 C) to further enhance.
[0060] Alternatively, the gate dielectric layer 41 may be deposited as a uniform (conformal) layer with a (mostly) uniform layer thickness and the non-uniformities may be eliminated by an etching step ( Figure 1 C) to be generated.
[0061] The etching step may be a wet etching with hydrofluoric acid (HF). Thus, the concentration of HF and / or the etching time may be adjusted to achieve a target layer thickness on the top and side surfaces.
[0062] For example, in the deposition ( Figure 1During the deposition of the at least one fin structure 23, a gate dielectric layer 41 having a different film quality than that on the side of the at least one fin structure is formed on the top surface of the at least one fin structure 23. Thus, the different film quality may refer to a different (higher) film density and / or dielectric stoichiometry (and composition) at the top surface of the fin structure 23 compared to the side. Specifically, the gate dielectric layer 41 on the top surface can be deposited with a higher film stability than the gate dielectric layer 41 on the side.
[0063] This improved film quality (eg, density, stability) of the gate dielectric layer 41 on the top surface may result in the portion of the gate dielectric layer 41 being removed during the etching step ( Figure 1 C) during etching compared to the gate dielectric layer 41 disposed on the side. In other words, due to the higher film quality of the dielectric layer 41 on the top surface, less material is removed during etching in this area. In contrast, the gate dielectric layer 41 disposed on the side of the fin structure 23 can be etched at a higher etching rate (i.e., more material is removed) due to its lower film stability.
[0064] In addition, the concentration of the etchant and / or the etching time can be adapted to achieve the target layer thickness on the top surface and the side surfaces. In one example, the etching rate of the gate dielectric layer 41 with the HF solution can be 2-10 nm / min on the top surface and 3-30 nm / min on the side surfaces (depending on the HF concentration). The resulting gate dielectric layer can have a thickness greater than 5 nm on the top surface and a thickness less than 4 nm on the side surfaces.
[0065] Thus, by utilizing a conformal or non-conformal gate dielectric film 41 deposited, for example, by PEALD and a suitable wet treatment (e.g. with HF), the thickness of the gate dielectric 41 may be adjusted at the sidewalls and top of the fin structure 23. This adjustment may be supported by different film qualities on the top and side surfaces of the fin structure 23 that may be obtained in the as-deposited state.
[0066] The gate dielectric layer 41 may also be formed on the substrate 14 in the region between two adjacent fin structures 23. The layer thickness of the gate dielectric layer 41 on the substrate 14 may also be greater than the layer thickness on the corresponding side of the fin structure 23. The extent of this effect may depend on the pitch and aspect ratio of the fin structure 23.
[0067] like Figure 1 As shown in FIG. 2 , the method may further include: forming at least one gate structure 32 on or around at least one fin structure 23 . The gate structure 32 may be a dummy gate structure that is replaced by a replacement metal gate in a later step. The gate structure 32 may be formed on a gate dielectric layer 41 .
[0068] In addition, if Figure 1As shown in FIG. 4 , the method may include: forming a first source and / or drain structure 11 b electrically contacting a first layer stack 23 a of at least one fin structure 23 ; and forming a second source and / or drain structure 12 b electrically contacting a second layer stack 23 b of the at least one fin structure 23 .
[0069] Specifically, the source or drain structure 11b, 12b (also referred to as: source or drain terminal 11b, 12b) can be arranged to electrically contact the channel(s) 11a, 12a of the first layer stack 23a or the second layer stack 23b, respectively. For example, the source or drain structure 11b, 12b can be formed by an epitaxial growth process on or around the channel(s) 11a, 12a.
[0070] Before forming the source or drain structures 11 b , 12 b , the fin structure 23 may be partially removed to expose the channels 11 a , 12 a .
[0071] The source or drain terminals 11b, 12b are Figure 1 Indicated by the dashed box in D, these terminals are generally arranged offset relative to the gate structure 32 in the channel direction (y direction) (i.e., at Figure 1 D in front of and / or behind the gate structure 32).
[0072] In this method, Figure 1 In other steps shown in AD, a contact structure electrically contacting the first and / or second source or drain terminals 11b, 12b may be formed. For example, the source or drain terminals 11b, 12b may be contacted from the side by the contact structure. The source or drain terminals of the transistors of adjacent CFETs may be connected by a signal wiring structure (e.g., a side wiring structure).
[0073] In addition, power rails (e.g., VDD and VSS power rails) may be formed to contact the first and second transistor structures, respectively. In addition, a set of signal routing for the CFET device may be formed in a metal layer above the transistor structure and may be connected to the first and second transistor structures.
[0074] Figure 1The method shown in AD allows for increased step coverage control and the formation of a non-conformal gate dielectric layer for high aspect ratio (AR) CFET applications (e.g., a CFET with a high aspect ratio fin structure 23). Having a thicker dielectric film on the top surface of the fin structure 23 compared to the sidewalls is advantageous in CFET applications. For example, a thicker gate dielectric layer 41 at the top surface of the fin structure 23 is advantageous for achieving full gate etching, particularly to avoid NSH erosion. At the same time, a thinner gate dielectric layer 41 on the sidewalls of the fin structure 23 can be better used for gate oxide breakthrough steps, such as to touch the sacrificial SiGe layer of the layer stack (s) 23a, 23b, and thus for its removal, such as for intermediate dielectric isolation (MDI) filling. A gate dielectric layer 41 that is too thick on the sidewalls of the fin structure 23 may further lead to harmful shallow trench isolation (STI) attacks, resulting in the STI being removed.
[0075] Figure 2 AB shows a further optional step of the method for manufacturing a CFET device. This step is a selective adaptation of the gate dielectric layer 41 arranged on the top surface of at least one fin structure 23 .
[0076] This step may be performed after forming the gate dielectric layer 41 (for example, directly before Figure 1 After deposition of the layer shown in B) is performed.
[0077] Figure 2 The left figure in A shows a cross-sectional view of the fin structure 23 in the yz plane (along the fin extension direction / channel direction). Figure 2 The right figure of A shows a cross-sectional view of the fin structure 23 in the xz plane (perpendicular to the fin extension direction / channel direction) after the gate dielectric layer is deposited. Thus, the inner first layer stack 23a and the second layer stack 23b can be seen.
[0078] The substrate 14 between the fin structures 23 may be covered by a shallow trench isolation (STI) layer 42 .
[0079] The gate dielectric layer 41 is adapted by Figure 2 The arrow in the figure of B indicates. For example, the adaptation may be a densification of layer 41. The adaptation (eg densification) is "selective" meaning that only a portion of gate dielectric layer 41, ie the portion arranged on the top surface of fin structure 23, is processed.
[0080] This adaptation can further enhance the stability of the gate dielectric layer 41 on the top surface of the fin structure 23. Therefore, the gate dielectric layer 41 on the top surface can be more robust during subsequent manufacturing steps. For example, NSH erosion during a full gate etch (FGE) soft landing attack can be further reduced.
[0081] The partial removal of the dummy gate material at the FGE can be accomplished by patterning the gate material, including: (1) depositing and patterning a hard mask layer over the dummy gate using a single or multiple patterning technique, and (2) subsequently etching the dummy gate layer, for example, using a dry (plasma) etch (e.g., using the dummy gate hard mask as an etch mask). When the dummy material is etched down to the bottom of the fin, the top surface of the gate oxide is also eroded so that the risk of attack on the underlying channel nanosheet is avoided by the thicker (and adapted) top of the gate oxide (gate dielectric layer 41). In a later step, the remaining gate oxide directly below the dummy gate structure can be completely removed and replaced by the final gate dielectric (e.g., replaced by HfO2 during the replacement metal gate step).
[0082] The selective adaptation of the gate dielectric layer 41 may be performed using one or more of the following techniques: plasma treatment, UV treatment, or annealing of the gate dielectric layer 41 .
[0083] Figure 3 AB further illustrates a cross-sectional view of the fin structure 23 during a later stage of the manufacturing process, namely after the formation of the dummy gate structure 32 .
[0084] thus, Figure 3 B shows that the selective adaptation of the gate dielectric layer 41 is performed after the dummy gate formation but before the full gate etch. The processing (eg, densification) of the gate dielectric layer 41 on the top surface of the fin structure 23 is indicated by arrows in the right figure.
[0085] The (dummy) gate structure 32 may be formed of aSi (amorphous silicon). The aSi material may include silicon nitride (Si3N4) and silicon oxide (SiO x )layer.
[0086] In the claims and the description of the present disclosure, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single element may fulfill the functions of several entities or items recited in the claims. The fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to an advantageous embodiment.
Claims
1. A method for processing a complementary field effect transistor (CFET) device, comprising the following steps: forming at least one fin structure on a substrate, wherein the at least one fin structure comprises a horizontal top surface and two vertically oriented side surfaces between the top surface and the substrate, and wherein the at least one fin structure comprises a first layer stack and a second layer stack above the first layer stack; as well as forming a gate dielectric layer having a non-uniform layer thickness around the at least one fin structure; The gate dielectric layer disposed on the top surface of the at least one fin structure has a layer thickness greater than a layer thickness of the gate dielectric layer disposed on the side surfaces of the at least one fin structure.
2. The method according to claim 1, The gate dielectric layer disposed on the top surface of the at least one fin structure has a layer thickness that is 1.5 to 3 times greater than a layer thickness of the gate dielectric layer disposed on the side surfaces of the at least one fin structure.
3. The method according to claim 1, The gate dielectric layer is a silicon dioxide SiO2 layer.
4. The method according to claim 1, The gate dielectric layer is deposited on the at least one fin structure by a layer deposition technique such as plasma enhanced atomic layer deposition (PEALD) or pulsed chemical vapor deposition (CVD).
5. The method according to claim 4, Wherein a gate dielectric layer is thereby formed on the top surface of the at least one fin structure, the gate dielectric layer having a different film quality than on the side surfaces of the at least one fin structure.
6. The method according to claim 4, in, After deposition, the layer thickness of the gate dielectric layer surrounding the at least one fin structure is reduced by an etching step.
7. The method according to claim 6, Wherein the etching step has a higher etching rate on the gate dielectric layer disposed on the side surface of the at least one fin structure than on the gate dielectric layer disposed on the top surface of the at least one fin structure.
8. The method of claim 1, further comprising the steps of: A gate dielectric layer arranged on the top surface of the at least one fin structure is selectively adapted, in particular densified.
9. The method according to claim 8, The step of selectively adapting the gate dielectric layer is performed immediately after the deposition of the gate dielectric layer or directly before the full gate etching step.
10. The method according to claim 8, The selective adaptation of the gate dielectric layer is performed by any one of the following techniques: plasma treatment, UV treatment or annealing.
11. The method of claim 1, further comprising the steps of: At least one gate structure is formed on or around the at least one fin structure.
12. The method of claim 1, The first layer stack includes at least one channel layer of a first transistor structure of the CFET device, and the second layer stack includes at least one channel layer of a second transistor structure of the CFET device.
13. The method of claim 12, further comprising the steps of: forming a first source and / or drain structure in electrical contact with the first layer stack of the at least one fin structure; as well as A second source and / or drain structure is formed in electrical contact with the second layer stack of the at least one fin structure.
14. A complementary field effect transistor (CFET) device obtainable by a method according to any one of the preceding claims.