Internal node jumpers for memory bit cells

Abstract

Memory bit cells with internal node jumpers are described. In an example, an integrated circuit structure includes memory bit cells on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction being orthogonal to the second direction. First, second, and third interconnect lines are over the first and second gate lines. The first, second, and third interconnect lines are parallel along a second direction of the substrate. The first, second, and third interconnect lines have a second pitch along the first direction, wherein the second pitch is less than the first pitch. One of the first, second, and third interconnect lines is an internal node jumper for the memory bit cell.

Description

Technical Field

[0001] This application is a divisional application of Application No.: 201780091023.X Invention Name: Internal Node Jumper for Memory Bit Cell Embodiments of the present disclosure are in the field of integrated circuit structures, and in particular in the field of memory bit cells with internal node jumpers. Background Art

[0002] Over the past several decades, the scaling of features in integrated circuits has been the driving force behind the evolving semiconductor industry. Scaling to smaller and smaller features enables an increased density of functional units on the limited real estate of a semiconductor chip.

[0003] For example, shrinking the size of transistors allows an increased number of memories or logic devices to be incorporated on a chip, thereby being suitable for manufacturing products with increased capacity. However, the drive for increasingly more capacity is not without problems. The necessity for optimizing the performance of each device becomes increasingly significant. In the manufacture of integrated circuit devices, as device sizes continue to shrink, multi-gate transistors such as tri-gate transistors have become more common. In conventional processes, tri-gate transistors are generally manufactured on bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-yield bulk silicon substrate infrastructure. However, scaling multi-gate transistors is not without consequences. As the size of these basic building blocks of microelectronic circuits shrinks and as the absolute number of basic building blocks manufactured in a given area increases, the constraints on the semiconductor processes used to manufacture these building blocks have become overwhelming.

[0004] Variability in conventional and prior art manufacturing processes may limit the possibility of further extending them into the 10 nm or sub-10 nm range, for example. Therefore, manufacturing the functional components required for future technology nodes may require the introduction of new methodologies or integration of new technologies in or in place of current manufacturing processes. New layouts may be introduced to accommodate or enable such future technology nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A first view of a conventional cell layout for a memory cell is illustrated.

[0006] Figure 2 A first view of a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure is illustrated.

[0007] Figure 3 A second view of a conventional cell layout for a memory cell is illustrated.

[0008] Figure 4 Illustrated is a second view of a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure.

[0009] Figure 5 A third view of a conventional cell layout for a memory cell is illustrated.

[0010] Figure 6 A third view of a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure is illustrated.

[0011] Fig. 7A and 7B A bit cell layout and a schematic diagram for a six-transistor (6T) static random access memory (SRAM) according to an embodiment of the present disclosure are illustrated, respectively.

[0012] Fig. 8A Illustrated is a cross-sectional view of a non-planar semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 8B The embodiment according to the present disclosure is illustrated along Fig. 8A A plan view of the semiconductor device taken along the a-a' axis.

[0014] Fig. 9 A computing device according to one implementation of an embodiment of the present disclosure is illustrated.

[0015] Fig.10 is an inserter that implements one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] A memory bit cell with an internal node jumper is described. In the following description, numerous specific details, such as specific layouts and material systems, are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features, such as single or dual mosaic processing, are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. In addition, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, and then, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be interpreted as implying that the operations are necessarily order-dependent. In particular, the operations do not need to be performed in the order presented.

[0017] Certain terms may also be used in the following description for reference purposes only, and thus the certain terms are not intended to be limiting. For example, terms such as "upper", "lower", "above", "below", "bottom", and "top" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and / or position of parts of a component within an arbitrary but consistent reference frame made clear by reference to the text and associated drawings describing the component in question. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0018] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0019] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using wiring on the wafer, such as one or more metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in BEOL.

[0020] The embodiments described below may be applicable to FEOL processes and structures, BEOL processes and structures, or both FEOL and BEOL processes and structures. In particular, although exemplary processing schemes may be described using FEOL processing scenarios, such methods may also be applicable to BEOL processing. Likewise, although exemplary processing schemes may be described using BEOL processing scenarios, such methods may also be applicable to FEOL processing.

[0021] One or more of the embodiments described herein relate to memory bit cells with internal node jumpers. Specific embodiments may include techniques for achieving efficient layout of memory bit cells with advanced self-aligned process techniques. Embodiments may relate to technology nodes of 10 nanometers or less. Embodiments may provide the ability to develop memory bit cells with improved performance within the same footprint by utilizing contacts over active gates (COAG) and / or aggressive metal 1 (M1) pitch scaling. Embodiments may include or relate to a bit cell layout that enables higher performance bit cells in the same or smaller footprint relative to previous technology nodes.

[0022] According to an embodiment of the present disclosure, a higher metal layer (e.g., Metal 1 or M1) jumper is implemented to connect internal nodes instead of using a traditional gate-trench contact-gate contact (polysilicon-tcn-polycon) connection. In an embodiment, a contact over active gate (COAG) integration scheme combined with a Metal 1 jumper for connecting internal nodes reduces or completely eliminates the need to grow a footprint for a higher performance bit cell. That is, an improved transistor ratio can be achieved. In an embodiment, such a scheme enables aggressive scaling to provide improved cost per transistor for, for example, a 10 nanometer (10nm) technology node. The internal node M1 jumper can be implemented in SRAM, RF, and dual-port bit cells in 10nm technology to produce a very compact layout.

[0023] As a comparative example, Figure 1 A first view of a conventional cell layout for a memory cell is illustrated.

[0024] refer to Figure 1 , an exemplary 14 nanometer (14 nm) layout 100 includes a bit cell 102. The bit cell 102 includes a gate or polysilicon line 104 and a metal 1 (M1) line 106. In the example shown, the polysilicon line 104 has a 1x pitch and the M1 line 106 has a 1x pitch. In a specific example, the polysilicon line 104 has a 70 nm pitch and the M1 line 106 has a 70 nm pitch.

[0025] and Figure 1 In contrast, Figure 2 A first view of a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure is illustrated.

[0026] refer to Figure 2, an exemplary 10 nanometer (10 nm) layout 200 includes a bit cell 202. The bit cell 202 includes a gate or polysilicon line 204 and a metal 1 (M1) line 206. In the example shown, the polysilicon line 204 has a 1x pitch and the M1 line 206 has a 0.67x pitch. The result is an overlapping line 205, which includes an M1 line directly above the polysilicon line. In a specific example, the polysilicon line 204 has a 54 nm pitch and the M1 line 206 has a 36 nm pitch.

[0027] Compared to layout 100, in layout 200, the M1 pitch is smaller than the gate pitch, and an extra line (205) is freed up for every three lines (e.g., for every two polysilicon lines, there are three M1 lines). The "freed up" M1 lines are referred to herein as internal node jumpers. Internal node jumpers can be used for gate-to-gate (polysilicon-to-polysilicon) interconnects or for trench contact-to-trench contact interconnects. In an embodiment, the contact to the polysilicon is achieved by a contact over active gate (COAG) arrangement, thereby achieving the fabrication of internal node jumpers.

[0028] More generally refer to Figure 2 In an embodiment, an integrated circuit structure includes a memory bit cell 202 on a substrate. The memory bit cell 202 includes first and second gate lines 204 that are parallel along a second direction 2 of the substrate. The first and second gate lines 202 have a first pitch along a first direction (1) of the substrate, and the first direction (1) is orthogonal to the second direction (2). First, second, and third interconnect lines 206 are above the first and second gate lines 204. The first, second, and third interconnect lines 206 are parallel along the second direction (2) of the substrate. The first, second, and third interconnect lines 206 have a second pitch along the first direction, wherein the second pitch is less than the first pitch. In an embodiment, one of the first, second, and third interconnect lines 206 is an internal node jumper for the memory bit cell 202.

[0029] As applicable throughout the present disclosure, the gate line 204 can be referred to as being located on a track to form a grid structure. The interconnect line 206 can also be referred to as being located on a track to form a grid structure. In an embodiment, the term "grid" for the gate line or interconnect line is used herein to refer to a tight pitch grid structure. In one such embodiment, the tight pitch is not directly achievable by conventional photolithography. For example, a pattern based on conventional photolithography can be formed first, but the pitch can be halved by patterning using a spacer mask, as known in the art. Even further, the original pitch can be divided into four equal parts by patterning a second round of spacer masks. Therefore, the grid-like pattern described herein can have gate lines or interconnect lines that are spaced at a constant pitch and have a constant width. The pattern can be manufactured by halving the pitch or quartering the pitch or other pitch division schemes.

[0030] As a comparative example, Figure 3 A second view of a conventional cell layout 300 for a memory cell is illustrated.

[0031] refer to Figure 3 , the 14nm bit cell 102 is shown with N diffusion 302 (e.g., P-type doped active region, such as a boron doped diffusion region of the underlying substrate) and P diffusion 304 (e.g., N-type doped active region, such as a phosphorus and / or arsenic doped diffusion region of the underlying substrate), with the M1 line removed for clarity. The layout 300 of the bit cell 102 includes a gate or polysilicon line 104, a trench contact 306, a gate contact 308 (specific to the 14nm node), and a contact via 310.

[0032] and Figure 3 In contrast, Figure 4 Illustrated is a second view of a cell layout 400 for a memory cell with internal node jumpers according to an embodiment of the present disclosure.

[0033] refer to Figure 4 , the 10nm bit cell 202 is shown with N diffusion 402 (e.g., P-type doped active region, such as a boron doped diffusion region of the underlying substrate) and P diffusion 404 (e.g., N-type doped active region, such as a phosphorus and / or arsenic doped diffusion region of the underlying substrate), with the M1 line removed for clarity. The layout 400 of the bit cell 202 includes the gate or polysilicon line 204, the trench contact 406, the gate via 408 (specific to the 10nm node), and the trench contact via 310.

[0034] In the comparative layouts 300 and 400, according to an embodiment of the present disclosure, in the 14nm layout, the internal nodes are connected only through the gate contacts (GCN). Due to the polysilicon to GCN space constraints, an enhanced performance layout cannot be created in the same footprint. In the 10nm layout, the design allows the contact (VCG) to land on the gate to eliminate the need for the polysilicon contact. In one embodiment, the arrangement enables the connection of internal nodes by using M1, thereby allowing the active area density (e.g., increased number of fins) to be added within the 14nm footprint. In the 10nm layout, when using the COAG architecture, the spacing between the diffusion regions can be made smaller because they are not limited by the trench contact to gate contact spacing. In an embodiment, Figure 3 The layout 300 is referred to as a 112 (1 fin pull-up, 1 fin pass gate, 2 fin pull-down) arrangement. In contrast, Figure 4 The layout 400 is referred to as a 122 (1 fin pull-up, 2 fin pass gate, 2 fin pull-down) arrangement, which in a particular embodiment is in conjunction with Figure 3 The 122 arrangement is within the same footprint as the 112 arrangement. In an embodiment, the 122 arrangement provides improved performance compared to the 112 arrangement.

[0035] As a comparative example, Figure 5 A third view of a conventional cell layout 500 for a memory cell is illustrated.

[0036] refer to Figure 5 , the 14 nm bit cell 102 is shown with a metal 0 (M0) line 502 with the polysilicon line removed for clarity. Also shown are a metal 1 (M1) line 106, a contact via 310, and a via 0 structure 504.

[0037] and Figure 5 In contrast, Figure 6 A third view of a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure is illustrated.

[0038] refer to Figure 6 , the 10 nm bit cell 202 is shown with a metal 0 (M0) line 602, where the polysilicon line is removed for clarity. Also shown are a metal 1 (M1) line 206, a gate via 408, a trench contact via 410, and a via 0 structure 604. Figure 5 and 6 In accordance with an embodiment of the present invention, for a 14 nm layout, the internal nodes are connected only through a gate contact (GCN), whereas for a 10 nm layout, one of the internal nodes is connected by using an M1 jumper.

[0039] Common reference Figure 2, 4 6, according to an embodiment of the present disclosure, an integrated circuit structure includes a memory bit cell 202 on a substrate. The memory bit cell 202 includes a first (top 402), a second (top 404), a third (bottom 404), and a fourth (bottom 402) active region that are parallel along a first direction (1) of the substrate. A first (left side 204) and a second (right side 204) gate line are above the first, second, third, and fourth active regions 402 / 404. The first and second gate lines 204 are parallel along a second direction (2) of the substrate, and the second direction (2) is orthogonal to the first direction (1). A first (far left side 206), a second (near left side 206), and a third (near right side 206) interconnect line are above the first and second gate lines 204. The first, second, and third interconnect lines 206 are parallel along the second direction (2) of the substrate.

[0040] In an embodiment, the first (far left 206) and second (near left 206) interconnect lines are electrically connected to the first and second gate lines 204 at locations where the first and second gate lines 204 are located above one or more of the first, second, third, and fourth active regions 402 / 404 (e.g., at so-called "active gate" locations). In an embodiment, the first (far left 206) and second (near left 206) interconnect lines are electrically connected to the first and second gate lines 204 through a plurality of intervening interconnect lines 604 vertically between the first and second interconnect lines 206 and the first and second gate lines 204. The plurality of intervening interconnect lines 604 are parallel along a second direction (1) of the substrate.

[0041] In an embodiment, the third interconnect line (near right side 206) electrically couples a pair of gate electrodes of the memory bit cell 202 together, the pair of gate electrodes being included in the first and second gate lines 204. In another embodiment, the third interconnect line (near right side 206) electrically couples a pair of trench contacts of the memory bit cell 202 together, the pair of trench contacts being included in the plurality of trench contact lines 406. In an embodiment, the third interconnect line (near right side 206) is an internal node jumper.

[0042] In an embodiment, the first active region (top 402) is a P-type doped active region (e.g., to provide N diffusions for NMOS devices), the second active region (top 404) is an N-type doped active region (e.g., to provide P diffusions for PMOS devices), the third active region (bottom 404) is an N-type doped active region (e.g., to provide P diffusions for PMOS devices), and the fourth active region (bottom 402) is an N-type doped active region (e.g., to provide N diffusions for NMOS devices). In an embodiment, the first, second, third, and fourth active regions 402 / 404 are silicon fins. In an embodiment, the memory bit cell 202 includes a pull-up transistor based on a single silicon fin, a pass-gate transistor based on two silicon fins, and a pull-down transistor based on two silicon fins.

[0043] In an embodiment, the first and second gate lines 204 alternate with individual trench contact lines of a plurality of trench contact lines 406 parallel along a second direction (2) of the substrate. The plurality of trench contact lines 406 include trench contacts for the memory bit cells 202. The first and second gate lines 204 include gate electrodes for the memory bit cells 202.

[0044] In an embodiment, the first and second gate lines 204 have a first pitch along the first direction (1). The first, second, and third interconnect lines 206 have a second pitch along the first direction (2). In one such embodiment, the second pitch is less than the first pitch. In a specific such embodiment, the first pitch is in the range of 50 nanometers to 60 nanometers, and the second pitch is in the range of 30 nanometers to 40 nanometers. In a specific such embodiment, the first pitch is 54 nanometers and the second pitch is 36 nanometers.

[0045] The embodiments described herein can be implemented to provide an increased number of fins within a relatively similar bit cell footprint as a previous technology node, thereby enhancing the performance of a smaller technology node memory bit cell relative to the performance of previous generations. As an example, Fig. 7A and 7B A bit cell layout and a schematic diagram for a six-transistor (6T) static random access memory (SRAM) according to an embodiment of the present disclosure are illustrated, respectively.

[0046] refer to Fig. 7A and 7B, the bit cell layout 702 includes gate lines 704 (which may also be referred to as polysilicon lines) that are parallel along direction (2). Trench contact lines 706 alternate with the gate lines 704. The gate lines 704 and the trench contact lines 706 are above NMOS diffusion regions 708 (e.g., P-type doped active regions, such as boron-doped diffusion regions of the underlying substrate) and PMOS diffusion regions 710 (e.g., N-type doped active regions, such as phosphorus and / or arsenic-doped diffusion regions of the underlying substrate), which are parallel along direction (1). In an embodiment, the two NMOS diffusion regions 708 each include two silicon fins. The two PMOS diffusion regions 710 each include one silicon fin.

[0047] Reference again Fig. 7A and 7B , NMOS pass gate transistor 712, NMOS pull-down transistor 714, and PMOS pull-up transistor 716 are formed by gate line 704 and NMOS diffusion region 708 and PMOS diffusion region 710. Also depicted are word line (WL) 718, internal nodes 720 and 726, bit line (BL) 722, bit line bar (BLB) 724, SRAM VCC 728, and VSS 730.

[0048] In an embodiment, contacts to the first and second gate lines 704 of the bitcell layout 702 are made to active gate locations of the first and second gate lines 704. In an embodiment, the 6T SRAM bitcell 704 includes internal node jumpers, such as described above.

[0049] In an embodiment, the layout described herein is compatible with a unified plug and mask pattern, including a unified fin trimming mask. The layout may be compatible with non-EUV processes. In addition, the layout may only require the use of an intermediate fin trimming mask. Compared to conventional layouts, the embodiments described herein may achieve increased density in terms of area. Embodiments may be implemented to provide a layout efficient memory implementation with advanced self-aligned process technology. Advantages may be achieved in terms of die area and / or memory performance. Circuit technology may be uniquely implemented through such a layout approach.

[0050] One or more embodiments described herein relate to the integration of semiconductor devices, such as metal oxide semiconductor (MOS) device integration. As an example, Fig. 8A Illustrated is a cross-sectional view of a non-planar semiconductor device according to an embodiment of the present disclosure. Figure 8B The embodiment according to the present disclosure is illustrated along Fig. 8A A plan view of the semiconductor device taken along the a-a' axis.

[0051] refer to Fig. 8A, semiconductor structure or device 800 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 804 and a sub-fin region 805) formed by a substrate 802 and within an isolation region 806. A gate line 808 is disposed over the protruding portion 804 of the non-planar active region and over a portion of the isolation region 806. As shown, the gate line 808 includes a gate electrode 850 / 899 and a gate dielectric layer 852. In one embodiment, the gate line 808 may also include a dielectric cap layer 854. Also seen from this perspective are a gate contact 814 and an overlying gate contact via 816, along with an overlying metal interconnect 860, all of which are disposed in an interlayer dielectric stack or layer 870.

[0052] from Fig. 8A It is also seen from the perspective that in one embodiment, the gate contact 814 is disposed above the isolation region 806, but not above the non-planar active region. However, the arrangement of the semiconductor structure or device 800 places the gate contact above the isolation region. Such an arrangement may be viewed as an inefficient use of layout space in certain applications for certain technology nodes, or may be restrictive for cell design. In another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active region to provide a contact over active gate (COAG) architecture.

[0053] It is to be appreciated that, for ease of illustration, the gate line 808 is shown as being above three protruding fin portions 804, but is not limited to such. For example, the gate line may be formed on 1, 2, 4 or even more protruding fin portions instead. As applicable throughout the present disclosure, the protruding fin portion 804 may be referred to as forming a grid structure. In an embodiment, the term "grid" for the protruding fin portion 804 is used herein to refer to a tight pitch grid structure. In one such embodiment, the tight pitch is not directly achievable by conventional lithography. For example, a pattern based on conventional lithography may be formed first, but the pitch may be halved by patterning using a spacer mask, as known in the art. Even further, the original pitch may be divided into four equal parts by patterning a second round of spacer masks. Therefore, the grid-like pattern described herein may have protruding fin portions 804 spaced at a constant pitch and having a constant width. The pattern may be manufactured by halving the pitch or by quartering the pitch or by other pitch division methods.

[0054] refer to Figure 8B, the gate line 808 is shown as being disposed above the protruding fin portion 804. From this perspective, the source and drain regions 804A and 804B of the protruding fin portion 804 can be seen. In one embodiment, the source or drain region 804A and 804B is a doped portion of the original material of the protruding fin portion 804. In another embodiment, the material of the protruding fin portion 804 is removed and replaced with another semiconductor material, for example by epitaxial deposition. In either case, the source and drain regions 804A and 804B can extend below the height of the dielectric layer 806, i.e., into the sub-fin region 805.

[0055] In an embodiment, the semiconductor structure or device 800 is a non-planar device, such as, but not limited to, a fin-type FET or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region is composed of or formed in a three-dimensional body. In one such embodiment, the gate electrode and gate electrode material of the gate line 808 surround at least the top surface and a pair of sidewalls of the three-dimensional body.

[0056] The substrate 802 may be composed of a semiconductor material that can undergo a manufacturing process and in which charge can migrate. In an embodiment, the substrate 802 is a bulk substrate composed of a crystalline silicon, silicon / germanium or germanium layer, which is doped with charge carriers such as but not limited to phosphorus, arsenic, antimony, boron, gallium or a combination thereof to form an active region 804. In one embodiment, the concentration of silicon atoms in the bulk substrate 802 is greater than 97%. In another embodiment, the bulk substrate 802 is composed of an epitaxial layer grown on top of a different crystalline substrate, such as a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate. The bulk substrate 802 may alternatively be composed of a III-V group material. In an embodiment, the bulk substrate 802 is composed of a III-V material, such as but not limited to gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, bulk substrate 802 is composed of III-V materials and the charge carrier dopant impurity atoms are those such as, but not limited to, magnesium, beryllium, zinc, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0057] The isolation region 806 may be composed of a material suitable for ultimately electrically isolating or contributing to isolating a portion of the permanent gate structure from the underlying bulk substrate or isolating an active region formed within the underlying bulk substrate, such as an isolation fin active region. For example, in one embodiment, the isolation region 806 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0058] In an embodiment, the gate dielectric layer 852 is composed of a high-K material. For example, in one embodiment, the gate dielectric layer 752 is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer may include a layer of native oxide formed by the top layers of the substrate 802. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion, the lower portion being composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 852 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride.

[0059] In an embodiment, the layer 850 of the gate electrode 850 / 899 is composed of a non-work function setting conductive fill material formed over the work function setting layer 899. In a specific embodiment, the transistor 800 is an N-type (NMOS) transistor, and the work function setting layer 899 is an N-type work function. In another specific embodiment, the transistor 800 is a P-type (PMOS) transistor, and the work function setting layer 899 has a P-type work function.

[0060] In one such embodiment, the conductive fill material 850 includes a material such as, but not limited to, tungsten (W), aluminum (Al), or copper (Cu). In one embodiment, one or more conductive barrier layers (such as titanium nitride or tantalum nitride) are between layers 850 and 899 of the gate electrode. In some implementations, the gate electrode may include a "U" shaped structure, the "U" shaped structure including a bottom portion substantially parallel to the substrate surface and two sidewall portions substantially orthogonal to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include a sidewall portion that is substantially orthogonal to the top surface of the substrate. In other implementations of the present disclosure, the gate electrode may include a combination of a U-shaped structure and a planar, non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers, the one or more U-shaped metal layers being formed on top of one or more planar non-U-shaped layers.

[0061] In an embodiment, the dielectric cap layer 854 and / or the dielectric spacer associated with the gate electrode stack may be composed of a material suitable for ultimately electrically isolating the permanent gate structure from an adjacent or overlying conductive contact, such as a self-aligned contact, or contributing to its isolation. For example, in one embodiment, the dielectric cap layer 854 and / or the dielectric spacer are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0062] The gate contact 814, the overlying gate contact via 816 and / or the overlying metal interconnect 860 may be composed of a conductive material. In an embodiment, one or more of the contact, interconnect or via is composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy, such as a metal-metal alloy, or a metal-semiconductor alloy (e.g., such as a silicide material). In a specific embodiment, one or more of the gate contact 814, the overlying gate contact via 816 or the overlying metal interconnect 860 includes a barrier layer and a conductive filling material. In one such embodiment, the barrier layer is composed of titanium and / or titanium nitride or tantalum and / or tantalum nitride. In an embodiment, the conductive filling material is composed of a conductive material, such as but not limited to Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or its alloy. Generally, as used throughout the present disclosure, interconnects are sometimes also referred to in the art as traces, wires, lines, metal lines, or simply interconnects.

[0063] In an embodiment, the interlayer dielectric stack or layer 870 consists of or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO2)), doped silicon oxides, fluorinated silicon oxides, carbon-doped silicon oxides, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0064] In an embodiment (although not shown), providing structure 800 involves the formation of a contact pattern that is substantially perfectly aligned with an existing gate pattern, while eliminating the use of a lithography step with an extremely tight alignment budget. In one such embodiment, the method enables the use of an inherently highly selective wet etch (e.g., relative to a conventionally implemented dry or plasma etch) to generate a contact opening. In an embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the method enables the elimination of the need for a lithography operation that is otherwise critical for generating a contact pattern as used in conventional methods. In an embodiment, the trench contact grid is not patterned separately, but is instead formed between multiple (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0065] In addition, the gate stack structure 808 can be manufactured by a replacement gate process. In such a scheme, the virtual gate material, such as polysilicon or silicon nitride pillar material, can be removed and replaced by a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, as opposed to that completed from an earlier process. In an embodiment, the virtual gate is removed by a dry etching or wet etching process. In one embodiment, the virtual gate is composed of polysilicon or amorphous silicon and is removed by a dry etching process including the use of SF6. In another embodiment, the virtual gate is composed of polysilicon or amorphous silicon and is removed by a wet etching process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the virtual gate is composed of silicon nitride and is removed by a wet etching including aqueous phosphoric acid.

[0066] In an embodiment, one or more methods described herein essentially contemplate dummy and replacement gate processes that combine dummy and replacement contact processes to achieve structure 800. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, annealing of at least a portion of the permanent gate structure is performed at a temperature greater than approximately 600 degrees Celsius, such as after forming the gate dielectric layer. The annealing is performed prior to forming the permanent contact.

[0067] In an embodiment, before (e.g., in addition to) forming a gate contact structure (such as a via) over an active portion of the gate and in the same layer as the trench contact via, one or more embodiments of the present disclosure include first using a gate-aligned trench contact process. Such a process can be implemented to form a trench contact structure for semiconductor structure manufacturing, such as for integrated circuit manufacturing. In an embodiment, the trench contact pattern is formed to align with an existing gate pattern. In contrast, conventional methods typically involve an additional lithography process with close alignment of the lithographic contact pattern with the existing gate pattern, combined with selective contact etching. For example, a conventional process may include patterning of multiple (gate) grids, separate patterning of contact features.

[0068] In a particular embodiment, each of the trench contacts comprises a barrier layer and a conductive fill material. In one such embodiment, the barrier layer is composed of titanium and / or titanium nitride or tantalum and / or tantalum nitride. In an embodiment, the conductive fill material is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof.

[0069] It is to be appreciated that not all aspects of the above process need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, a dummy gate need not have been formed before a gate contact is made over the active portion of the gate stack. The above gate stack may actually be a permanent gate stack as initially formed. Moreover, the processes described herein may be used to manufacture one or more semiconductor devices. The semiconductor device may be a transistor or a similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Moreover, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, an independently accessed dual-gate device, or a FIN-FET. One or more embodiments may be particularly useful for manufacturing semiconductor devices at a technology node of 10 nanometers (10nm) or less.

[0070] In an embodiment, as also used throughout this description, lithography operations are performed by using 193nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, and / or electron beam direct write (EBDW) lithography, etc. Positive photoresist or negative photoresist can be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific such embodiment, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating type layer is a silicon ARC layer.

[0071] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., desktop computers, laptop computers, servers), cellular phones, personal electronic devices, and the like. Integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, and the like through one or more buses. Each of the processors, memories, and chipsets can potentially be manufactured by using the methods disclosed herein. In addition, integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., desktop computers, laptop computers, servers), cellular phones, personal electronic devices, and the like. Integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, and the like through one or more buses. Each of the processors, memories, and chipsets can potentially be manufactured by using the methods disclosed herein.

[0072] Fig. 9 A computing device 900 according to one implementation of the present disclosure is illustrated. The computing device 900 houses a board 902. The board 902 may include a number of components, including, but not limited to, a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some implementations, the at least one communication chip 906 is also physically and electrically coupled to the board 902. In other implementations, the communication chip 906 is part of the processor 904.

[0073] Depending on its application, the computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard drives, compact disks (CDs), digital versatile disks (DVDs)), etc.).

[0074] The communication chip 906 enables wireless communication for transferring data to and from the computing device 900. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., which can transmit data through non-solid media using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, although in some embodiments they may not. The communication chip 906 can implement any of a plurality of wireless standards or protocols including but not limited to the following: Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. The computing device 900 may include a plurality of communication chips 906. For example, the first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0075] The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some implementations of the present disclosure, the integrated circuit die of the processor includes a memory bit cell layout with internal node jumpers according to implementations of embodiments of the present disclosure, the internal node jumpers being provided, for example, by a metal line pattern having a tighter pitch than an underlying gate line pattern. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that may be stored in registers and / or memory.

[0076] The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. According to another implementation of an embodiment of the present disclosure, the integrated circuit die of the communication chip includes a memory bit cell layout according to an implementation of an embodiment of the present disclosure with internal node jumpers, such as provided by a metal line pattern having a tighter pitch than the underlying gate line pattern.

[0077] In further implementations, another component housed within the computing device 900 may include an integrated circuit die comprising a memory bit cell layout according to an implementation of an embodiment of the present disclosure having internal node jumpers, such as provided by a metal line pattern having a tighter pitch than an underlying gate line pattern.

[0078] In various implementations, computing device 900 may be a laptop, netbook, notebook, ultrabook, smart phone, tablet device, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other implementations, computing device 900 may be any other electronic device that processes data.

[0079] Fig.10 An insert 1000 including one or more embodiments of the present disclosure is illustrated. The insert 1000 is an intermediate substrate for bridging a first substrate 1002 to a second substrate 1004. The first substrate 1002 may be, for example, an integrated circuit die. The second substrate 1004 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of the insert 1000 is to spread connections to a wider pitch, or to reroute connections to different connections. For example, the insert 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006, which may then be coupled to a second substrate 1004. In some embodiments, the first and second substrates 1002 / 1004 are attached to opposite sides of the insert 1000. In other embodiments, the first and second substrates 1002 / 1004 are attached to the same side of the insert 1000. And in further embodiments, three or more substrates are interconnected by the insert 1000.

[0080] The insert 1000 may be formed of epoxy, fiberglass reinforced epoxy, ceramic material, or polymer material, such as polyimide. In other implementations, the insert may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0081] The insert may include metal interconnects 1008 and through-holes 1010, including but not limited to through silicon vias (TSVs) 1012. The insert 1000 may further include embedded devices 1014, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the insert 1000. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be used in the manufacture of the insert 1000. In one such embodiment, one or more of the components of the insert 1000 include a memory bit cell layout with an internal node jumper, such as provided by a metal line pattern having a tighter pitch than the underlying gate line pattern.

[0082] Thus, embodiments described herein include memory bit cells having internal node jumpers.

[0083] The above description of the illustrated implementations of the embodiments of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Although specific implementations and examples of the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as will be recognized by those skilled in the relevant art.

[0084] In view of the above detailed description, these modifications may be made to the present disclosure. The terms used in the appended claims should not be interpreted as limiting the present disclosure to the specific implementations disclosed in the specification and claims. On the contrary, the scope of the present disclosure will be determined entirely by the appended claims, which will be interpreted according to the established principles of claim interpretation.

[0085] Example embodiment 1: An integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first, second, third and fourth active regions that are parallel along a first direction of the substrate. First and second gate lines are above the first, second, third and fourth active regions, and the first and second gate lines are parallel along a second direction of the substrate, and the second direction is orthogonal to the first direction. First, second and third interconnect lines are above the first and second gate lines, and the first, second and third interconnect lines are parallel along the second direction of the substrate. The first and second interconnect lines are electrically connected to the first and second gate lines at the positions of the first and second gate lines located above one or more of the first, second, third and fourth active regions. The third interconnect line electrically couples a pair of gate electrodes of the memory bit cell together, or electrically couples a pair of trench contacts of the memory bit cell together.

[0086] Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein the third interconnect line electrically couples the pair of gate electrodes of the memory bit cell together.

[0087] Example Embodiment 3: The integrated circuit structure of Example Embodiment 1, wherein the third interconnect line electrically couples the pair of trench contacts of the memory bit cell together.

[0088] Example embodiment 4: The integrated circuit structure described in Example embodiment 1, 2 or 3, wherein the first active region is a P-type doped active region, the second active region is an N-type doped active region, the third active region is an N-type doped active region, and the fourth active region is an N-type doped active region.

[0089] Example Embodiment 5: The integrated circuit structure of Example Embodiment 1, 2, 3 or 4, wherein the first, second, third and fourth active regions are in silicon fins.

[0090] Example Embodiment 6: The integrated circuit structure of Example Embodiment 1, 2, 3, 4 or 5, wherein the memory bit cell includes a pull-up transistor based on a single silicon fin, a pass-gate transistor based on two silicon fins, and a pull-down transistor based on two silicon fins.

[0091] Example embodiment 7: The integrated circuit structure described in example embodiments 1, 2, 3, 4, 5 or 6, wherein the first and second gate lines alternate with individual trench contact lines from a plurality of trench contact lines parallel to a second direction of the substrate, wherein the plurality of trench contact lines include the pair of trench contacts of the memory bit cell.

[0092] Example embodiment 8: The integrated circuit structure described in example embodiments 1, 2, 3, 4, 5, 6 or 7, wherein the first and second gate lines have a first pitch along the first direction, the first, second and third interconnect lines have a second pitch along the first direction, and wherein the second pitch is smaller than the first pitch.

[0093] Example Embodiment 9: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, 5, 6, 7 or 8, wherein the first pitch is in the range of 50 nanometers to 60 nanometers, and wherein the second pitch is in the range of 30 nanometers to 40 nanometers.

[0094] Example embodiment 10: An integrated circuit structure as described in example embodiments 1, 2, 3, 4, 5, 6, 7, 8 or 9, wherein the first and second interconnect lines are electrically connected to the first and second gate lines through a plurality of intermediate interconnect lines between the first and second interconnect lines and the first and second gate lines, and wherein the plurality of intermediate interconnect lines are parallel along a first direction of the substrate.

[0095] Example embodiment 11: An integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines that are parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, and the first direction is orthogonal to the second direction. First, second, and third interconnect lines are above the first and second gate lines. The first, second, and third interconnect lines are parallel along the second direction of the substrate. The first, second, and third interconnect lines have a second pitch along the first direction, wherein the second pitch is less than the first pitch. One of the first, second, and third interconnect lines is an internal node jumper for the memory bit cell.

[0096] Example Embodiment 12: The integrated circuit structure of Example Embodiment 11, wherein the internal node jumper electrically couples together a pair of gate electrodes of the memory bit cell.

[0097] Example Embodiment 13: The integrated circuit structure of Example Embodiment 11, wherein the internal node jumper electrically couples together a pair of trench contacts of a memory bit cell.

[0098] Example Embodiment 14: The integrated circuit structure of Example Embodiment 11, 12 or 13, wherein the first and second gate lines alternate with individual trench contact lines of a plurality of trench contact lines parallel to the second direction of the substrate.

[0099] Example Embodiment 15: The integrated circuit structure of Example Embodiment 11, 12, 13, or 14, wherein the first pitch is in a range of 50 nanometers to 60 nanometers, and wherein the second pitch is in a range of 30 nanometers to 40 nanometers.

[0100] Example embodiment 16: An integrated circuit structure includes a substrate. A six-transistor (6T) static random access memory (SRAM) bit cell is on the substrate. The 6T SRAM bit cell includes first, second, third, and fourth active regions parallel along a first direction of the substrate. The first active region includes two silicon fins, the second active region includes one silicon fin, the third active region includes one silicon fin, and the fourth active region includes two silicon fins. First and second gate lines are above the first and second active regions. The first and second gate lines are parallel along a second direction of the substrate, the second direction being orthogonal to the first direction.

[0101] Example Embodiment 17: The integrated circuit structure of Example Embodiment 16, wherein the first and fourth active regions are P-type doped active regions, and the second and third active regions are N-type doped active regions.

[0102] Example Embodiment 18: The integrated circuit structure of Example Embodiment 16 or 17, wherein individual ones of the first and second gate lines are spaced apart from each other by trench contact lines parallel to each other along the second direction of the substrate.

[0103] Example Embodiment 19: The integrated circuit structure of Example Embodiment 16, 17 or 18, wherein contacts to the first and second gate lines are made to active gate locations of the first and second gate lines.

[0104] Example Embodiment 20: The integrated circuit structure of Example Embodiment 16, 17, 18 or 19, wherein the 6T SRAM bit cell includes an internal node jumper.

Claims

1. An integrated circuit structure, comprising: a fin along a first direction; a first metal line, a second metal line, and a third metal line along a second direction, the second direction being orthogonal to the first direction, wherein the first metal line, the second metal line, and the third metal line are within a footprint vertically above the fin; a first gate line and a second gate line along a second direction, the first gate line and the second gate line being vertically above the fin and below the first metal line, the second metal line, and the third metal line, wherein the first gate line and the second gate line, but no additional gate lines, are within a footprint of the first metal line, the second metal line, and the third metal line, and wherein a pitch of the first gate line and the second gate line is greater than a pitch of the first metal line, the second metal line, and the third metal line; as well as A fourth metal line along the first direction is vertically above the first gate line and the second gate line and vertically below the first metal line, the second metal line and the third metal line. 2 . The integrated circuit structure according to claim 1 , wherein there is no other metal line between the fourth metal line and the first and second gate lines in a vertical direction. 3 . The integrated circuit structure according to claim 1 , wherein there are no other metal lines between the fourth metal line and the first, second, and third metal lines in a vertical direction.

4. The integrated circuit structure according to claim 1, wherein there are no other metal lines in the vertical direction between the fourth metal line and the first and second gate lines, and wherein there are no other metal lines in the vertical direction between the fourth metal line and the first, second, and third metal lines. 5 . The integrated circuit structure of claim 1 , wherein one of the first metal line, the second metal line, or the third metal line is vertically above and aligned with one of the first gate electrode or the second gate electrode.

6. The integrated circuit structure according to claim 1, further comprising: A gate contact couples the fourth metal line to one of the first gate electrode or the second gate electrode located vertically above the fin. 7 . The integrated circuit structure of claim 1 , wherein the first gate line and the second gate line are on top of the fin and along a pair of sidewalls of the fin.

8. An integrated circuit structure comprising: a fin along a first direction; a first metal line, a second metal line, and a third metal line vertically above the fin along a second direction, the second direction being orthogonal to the first direction; a first gate line and a second gate line along a second direction, the first gate line and the second gate line being vertically above the fin and below the first metal line, the second metal line, and the third metal line, wherein a distance along the first direction from an outermost wall of the first gate line to an outermost wall of the second gate line is less than a distance along the first direction from an outermost wall of the first metal line to an outermost wall of the third metal line, and wherein a pitch of the first gate line and the second gate line is greater than a pitch of the first metal line, the second metal line, and the third metal line; as well as A fourth metal line along the first direction is vertically above the first gate line and the second gate line and vertically below the first metal line, the second metal line and the third metal line. 9 . The integrated circuit structure according to claim 8 , wherein there is no other metal line between the fourth metal line and the first and second gate lines in a vertical direction. 10 . The integrated circuit structure according to claim 8 , wherein there are no other metal lines between the fourth metal line and the first, second, and third metal lines in a vertical direction.

11. The integrated circuit structure according to claim 8, wherein there are no other metal lines in a vertical direction between the fourth metal line and the first and second gate lines, and wherein there are no other metal lines in a vertical direction between the fourth metal line and the first, second, and third metal lines.

12. The integrated circuit structure of claim 8, wherein one of the first metal line, the second metal line, or the third metal line is vertically above and aligned with one of the first gate electrode or the second gate electrode.

13. The integrated circuit structure of claim 8, further comprising: A gate contact couples the fourth metal line to one of the first gate electrode or the second gate electrode located vertically above the fin.

14. The integrated circuit structure of claim 8, wherein the first gate line and the second gate line are on top of the fin and along a pair of sidewalls of the fin.

15. An integrated circuit structure comprising: a three-dimensional body along a first direction; a first metal line, a second metal line, and a third metal line along a second direction, the second direction being orthogonal to the first direction, wherein the first metal line, the second metal line, and the third metal line are within a footprint vertically above the three-dimensional body; a first gate line and a second gate line along a second direction, the first gate line and the second gate line being vertically above the three-dimensional body and below the first metal line, the second metal line, and the third metal line, wherein the first gate line and the second gate line surround at least a top portion and a pair of sidewalls of the three-dimensional body, wherein the first gate line and the second gate line but no additional gate lines are within the coverage of the first metal line, the second metal line, and the third metal line, and wherein a pitch of the first gate line and the second gate line is greater than a pitch of the first metal line, the second metal line, and the third metal line; as well as A fourth metal line along the first direction is vertically above the first gate line and the second gate line and vertically below the first metal line, the second metal line and the third metal line. 16 . The integrated circuit structure according to claim 15 , wherein there is no other metal line between the fourth metal line and the first and second gate lines in a vertical direction. 17 . The integrated circuit structure according to claim 15 , wherein there are no other metal lines between the fourth metal line and the first, second, and third metal lines in a vertical direction.

18. The integrated circuit structure according to claim 15, wherein there are no other metal lines in a vertical direction between the fourth metal line and the first and second gate lines, and wherein there are no other metal lines in a vertical direction between the fourth metal line and the first, second, and third metal lines.

19. The integrated circuit structure of claim 15, wherein one of the first metal line, the second metal line, or the third metal line is vertically above and aligned with one of the first gate electrode or the second gate electrode.

20. The integrated circuit structure of claim 15, further comprising: A gate contact couples the fourth metal line to one of the first gate electrode or the second gate electrode located vertically above the three-dimensional body.

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