Array substrate, preparation method thereof and display device

Abstract

The invention provides an array substrate, a preparation method thereof and a display device. The array substrate is used for the display panel and comprises a substrate and a plurality of transistors arranged on the substrate. The transistor comprises a grid electrode arranged on one side of a substrate; the grid electrode insulating layer is arranged on the grid electrode and covers the grid electrode; the semiconductor layer is arranged on the gate insulating layer; the source electrode and the drain electrode are arranged on the semiconductor layer; the first heating electrode is embedded in the gate insulating layer; and / or the second heating electrode is arranged on the semiconductor layer and is insulated from the source electrode and the drain electrode. The transistors on the array substrate can realize a self-heating function, and the adaptability of the display panel in a low-temperature environment is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display device. Background Art

[0002] With the continuous improvement of display technology, users have increasingly stringent requirements on the quality of display panels. One of them is that the display panel must be able to adapt to the needs of multiple scenarios. As the mainstream amorphous silicon (α-Si / a-Si) display panel, when the display panel is in a low temperature environment, the semiconductor devices are prone to problems such as insufficient on-state current and insufficient charging rate, which causes the display panel to be prone to problems such as abnormal images when used in a low temperature environment, which severely limits the usage scenarios and reduces the product competitiveness.

[0003] At present, in order to solve the above technical problems, the existing technology increases the IC design to perform reverse temperature compensation on a-Si semiconductor devices in low temperature environments, but such a solution greatly increases the preparation cost of the product. For display devices with backlights, the a-Si semiconductor devices on the display panel can be indirectly heated by adjusting the brightness of the backlight to increase the on-state current of the semiconductor devices at low temperatures. However, this method will cause the off-state current of the semiconductor device in a normal temperature environment to increase synchronously, affecting the use of the panel in normal temperature scenarios. At the same time, due to the increase in the backlight brightness, the photogenerated carriers of the semiconductor device increase, which increases the device light leakage, and the display panel is prone to afterimage problems. Moreover, this solution is not applicable to panels without backlight. Summary of the invention

[0004] The present application provides an array substrate and a preparation method thereof and a display device, aiming to solve the problem in the prior art that in a low temperature environment, the semiconductor devices of the display panel are prone to insufficient on-state current and insufficient charging rate, resulting in abnormal images.

[0005] In order to solve the above technical problems, the first technical solution provided by the present application is: to provide an array substrate. The array substrate is used for a display panel, including a substrate and a plurality of transistors arranged on the substrate; the transistors include:

[0006] A gate is disposed on one side of the substrate;

[0007] A gate insulating layer is disposed on the gate and covers the gate;

[0008] A semiconductor layer is disposed on the gate insulating layer;

[0009] A source electrode is disposed on the semiconductor layer;

[0010] A drain electrode is disposed on the semiconductor layer;

[0011] Among them, transistors also include:

[0012] A first heating electrode, the first heating electrode is buried in the gate insulating layer; and / or,

[0013] The second heating electrode is arranged on the semiconductor layer and is insulated from the source electrode and the drain electrode.

[0014] In some embodiments, the transistor further comprises a first heating electrode;

[0015] The gate insulating layer includes a first gate insulating layer and a second gate insulating layer stacked in layers; the first heating electrode is arranged between the first gate insulating layer and the second gate insulating layer; wherein the thickness of the first gate insulating layer is The thickness of the second gate insulating layer is

[0016] The thickness of the first heating electrode is

[0017] In some embodiments, the transistor further includes a second heating electrode and an insulating layer;

[0018] The second heating electrode is disposed on the semiconductor layer and has at least two hollow portions to expose at least two portions of the semiconductor layer;

[0019] An insulating layer is arranged on the second heating electrode, covering the second heating electrode, and an electrode via is also opened on the insulating layer. The electrode via is located in the hollow part, and the insulating layer is filled between the hole wall of the electrode via and the side wall of the hollow part; the source and the drain are respectively in contact with the semiconductor layer through the corresponding electrode vias.

[0020] In some embodiments, the transistor further includes a passivation layer and a third heating electrode;

[0021] The passivation layer is arranged on the source and the drain, and covers the source and the drain; the third heating electrode is arranged on the passivation layer, and the orthographic projection of the third heating electrode on the semiconductor layer covers the channel region; wherein the region of the semiconductor layer corresponding to the region between the source and the drain is the channel region.

[0022] In some embodiments, the array substrate further includes a heating layer, which is disposed on a side of the substrate away from the transistor, and an orthographic projection of the heating layer on the substrate covers an orthographic projection of the transistor on the substrate.

[0023] In order to solve the above technical problems, the second technical solution provided by the present application is to provide a method for preparing an array substrate. The preparation method comprises:

[0024] Providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to form a gate;

[0025] Depositing a gate insulating layer on the substrate so that the gate insulating layer covers the gate;

[0026] An active layer and a semiconductor doping layer are sequentially deposited on the gate insulating layer, and photolithography is performed to form a semiconductor layer;

[0027] Depositing a second metal layer on the semiconductor doping layer, and patterning the second metal layer to form a source electrode and a drain electrode;

[0028] The step of depositing a gate insulating layer on the substrate so that the gate insulating layer covers the gate specifically includes:

[0029] Depositing a first gate insulating layer on the substrate so that the first gate insulating layer covers the gate;

[0030] Depositing a first heat-conducting layer on the first gate insulating layer, and patterning the first heat-conducting layer to form a first heating electrode;

[0031] Depositing a first sub-gate insulating layer, a second sub-gate insulating layer and a third sub-gate insulating layer in sequence at different deposition rates on the first heating electrode to form a second gate insulating layer;

[0032] And / or, before the step of depositing a second metal layer on the semiconductor doped layer and patterning the second metal layer to form a source electrode and a drain electrode, the method further includes:

[0033] Depositing a second heat-conducting layer on the semiconductor layer, and patterning the second heat-conducting layer to form a second heating electrode;

[0034] An insulating layer is deposited on the second heating electrode and patterned to form an electrode via hole, wherein the electrode via hole exposes a portion of the semiconductor doping layer; wherein the second heating electrode is insulated from the source electrode and the drain electrode.

[0035] In some embodiments, an active layer and a semiconductor doping layer are sequentially deposited on the gate insulating layer, and a photolithography process is performed to form a semiconductor layer, and the step includes:

[0036] A first active layer is formed by depositing on the gate insulating layer at a first deposition rate; the thickness of the first active layer is

[0037] A second active layer is formed by depositing on the first active layer at a second deposition rate; the thickness of the second active layer is The first deposition rate is lower than the second deposition rate; the materials of the first active layer and the second active layer are amorphous silicon;

[0038] A first doped amorphous silicon layer, a second doped amorphous silicon layer, a third doped amorphous silicon layer and a fourth doped amorphous silicon layer with different doping concentrations are sequentially deposited on the second active layer; the doping concentrations of the first doped amorphous silicon layer to the fourth doped amorphous silicon layer are increased sequentially, and the total thickness of the first doped amorphous silicon layer to the fourth doped amorphous silicon layer is

[0039] The active layer and the semiconductor doping layer are subjected to photolithography processing to form a channel region, wherein the channel region penetrates the semiconductor doping layer and partially penetrates to the active layer.

[0040] In some embodiments, the preparation method further comprises:

[0041] Depositing a passivation layer on the source electrode and the drain electrode so that the passivation layer covers the source electrode and the drain electrode;

[0042] A third heat-conducting layer is deposited on the passivation layer, and the third heat-conducting layer is patterned to form a third heating electrode, so that the orthographic projection of the third heating electrode on the semiconductor layer covers the channel region of the semiconductor layer; the thickness of the third heating electrode is

[0043] In some embodiments, the array substrate is used for an electrophoretic display panel, and the preparation method further includes:

[0044] A fourth heat-conducting layer is deposited on a side of the substrate away from the gate to form a heating layer, so that the orthographic projection of the heating layer on the substrate covers the orthographic projection of the semiconductor layer on the substrate.

[0045] In order to solve the above technical problems, the third technical solution provided by the present application is to provide a display device. The display device includes:

[0046] A display panel, the display panel comprising an array substrate provided by the above technical solution;

[0047] The control circuit board is electrically connected to the display panel and is used to control the display panel to display corresponding images.

[0048] Beneficial effects of the present application: Different from the prior art, the present application provides an array substrate and a method for preparing the same, and a display device. The array substrate is used for a display panel to drive each sub-pixel to emit light. The array substrate includes a substrate and a plurality of transistors arranged on the substrate. Among them, the transistor includes a gate, a gate insulating layer, a semiconductor layer, a source electrode and a drain electrode, and can be used as a semiconductor driving device required in a gate driving unit and a pixel driving circuit. In the embodiment of the present application, by making the transistor further include a first heating electrode and / or a second heating electrode, the first heating electrode is buried in the gate insulating layer, and / or the second heating electrode is arranged on the semiconductor layer, the semiconductor layer can be heated by the first heating electrode and / or the second heating electrode in a low temperature environment, thereby realizing self-heating of the transistor, so as to increase the on-state current of the transistor in a low temperature environment, reduce the situation of insufficient charging rate, reduce the problem of afterimage on the display panel, and improve the "cold resistance" of the display panel, so as to better adapt to the low temperature environment. Moreover, by integrating the first heating electrode and / or the second heating electrode into the transistor, the distance between the heating electrode and the semiconductor layer in the transistor is smaller, which can further improve the heating effect. Furthermore, through the above-mentioned configuration, the startup and operation of the display panel in a low temperature environment can be solved without adding a driver IC, thereby saving the manufacturing cost of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0050] Figure 1 is an IV characteristic curve diagram of a transistor at different temperatures provided by an embodiment of the prior art;

[0051] Figure 2 is a schematic diagram of a planar structure of an array substrate provided in one embodiment of the present application;

[0052] Figure 3 yes Figure 2 A schematic cross-sectional structure diagram of the first embodiment provided along the AA direction;

[0053] Figure 4 yes Figure 2 A schematic cross-sectional structure diagram of the second embodiment provided along the AA direction;

[0054] Figure 5 yes Figure 2 A schematic cross-sectional structure diagram of the third embodiment provided along the AA direction;

[0055] Figure 6 yes Figure 2 A schematic cross-sectional structure diagram of the fourth embodiment provided along the AA direction;

[0056] Figure 7 yes Figure 2 A schematic cross-sectional structure diagram of the fifth embodiment provided along the AA direction;

[0057] Figure 8 yes Figure 2 A schematic cross-sectional structure diagram of the sixth embodiment provided along the AA direction;

[0058] Fig. 9 yes Figure 2 A schematic cross-sectional structure diagram of the seventh embodiment provided along the AA direction;

[0059] Fig.10 is a schematic flow chart of a method for preparing an array substrate provided in the first embodiment of the present application;

[0060] Fig.11 yes Fig.10 A schematic diagram of a preparation method provided in one embodiment of step S20;

[0061] Fig.12 It is a schematic flow chart of the steps of manufacturing the second heating electrode provided in one embodiment of the present application;

[0062] Fig.13 is a schematic flow chart of a method for preparing a semiconductor layer provided in one embodiment of the present application;

[0063] Fig.14 is a schematic flow chart of a method for preparing a third heating electrode provided in one embodiment of the present application;

[0064] Fig.15 It is a schematic flow chart of a method for preparing a heating layer provided in one embodiment of the present application;

[0065] Fig.16 It is a schematic diagram of the structure of a display device provided in one embodiment of the present application.

[0066] Reference numerals:

[0067] 1000, display panel; 100, array substrate; 101, display driving module; 1011, scan line; 1012, data line; 1013, pixel driving unit; 1014, common electrode; 1015, pixel electrode; 102, gate driving module; 1021, gate driving unit; 10, substrate; 21, gate; 22, gate insulating layer; 221, first gate insulating layer; 222, second gate insulating layer; 2221, first sub-gate insulating layer; 2222, second sub-gate insulating layer; 2223, third sub-gate insulating layer; 23, semiconductor layer; 231, active layer; 2311, first active layer; 2312, second active layer; 232, ohmic contact layer; 233, channel region; 241, source electrode; 242, drain electrode; 25, first heating electrode; 26, second heating electrode; 261, hollow portion; 27, insulating layer; 271, electrode via hole; 28, passivation layer; 29, third heating electrode; 30, second passivation layer; 40, heating layer; 200, opposing substrate; 300, liquid crystal layer; 400, electrophoretic medium layer; 500, control circuit board; TFT, transistor; X, first direction; Y, second direction. DETAILED DESCRIPTION

[0068] The scheme of the embodiment of the present application is described in detail below in conjunction with the drawings of the specification.

[0069] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0070] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0071] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0072] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0073] See also Figure 1 , Figure 1 It is a graph of IV characteristic curves of transistors at different temperatures provided by an embodiment of the prior art. At present, the a-Si type display panel has a plurality of a-Si type thin film transistors integrated on its array substrate. The current-voltage (IV) output characteristic curve of this type of transistor is shown in the figure. It can be seen that the IV output characteristics of a-Si type thin film transistors are different under different temperature environments. It can be seen from the figure that the lower the temperature, the lower the on-state current of the transistor, which makes it easy for the transistor to have insufficient charging rate when the driving substrate is driving. Therefore, when the display panel is used in a low temperature environment, problems such as abnormal screen are very likely to occur, which seriously limits the use scenarios of the display panel and reduces the competitiveness of the display panel.

[0074] In order to solve the above technical problems, the design of the driver IC is usually increased to compensate the temperature of the transistors on the array substrate in a low temperature environment, but such a setting will greatly increase the preparation cost of the product. For display devices with backlight components, the brightness of the backlight component can also be increased to indirectly heat the transistors, so that the carriers on the deep energy level and in the trap of the transistor are excited by energy, so that the carrier concentration accumulated in the channel is increased, thereby increasing the on-state current of the transistor. Although the on-state current can be increased by this method, the off-state current of the transistor on the array substrate at room temperature will be increased, thereby affecting the use of the display panel at room temperature; at the same time, due to the increase in the backlight brightness, the photogenerated carriers of the transistor will also increase, which will increase the light leakage of the transistor device, and the display panel is prone to field line afterimages. Moreover, for display devices without backlight components, such as electrophoretic display panels such as electronic paper readers, this method is not applicable because there is no backlight component, and the temperature compensation of the transistor by adding a driver IC will increase the product cost.

[0075] An embodiment of the present application provides an array substrate for a display panel. By optimizing the structure of transistor devices on the array substrate, the display panel can be self-heated in a low temperature environment without adding a driver IC, so as to increase the on-state current of the transistor device at low temperatures and improve the charging rate of the transistor, so that the display panel can adapt to harsh usage environments and improve the "cold resistance" of the display panel.

[0076] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0077] See also Figure 2-5 , Figure 2 is a schematic diagram of a planar structure of an array substrate provided in an embodiment of the present application, Figure 3 yes Figure 2 The cross-sectional structure diagram of the first embodiment provided by AA direction, Figure 4 yes Figure 2 A schematic cross-sectional structure diagram of the second embodiment provided along the AA direction, Figure 5 yes Figure 2 A schematic cross-sectional structure diagram of the third embodiment provided along the AA direction.

[0078] In an embodiment of the present application, an array substrate 100 is provided. The array substrate 100 can be used for a display panel 1000 (see Fig.16 ), which can be specifically used for a display panel 1000 driven by an electric field, such as a liquid crystal panel or an electrophoretic panel. The array substrate 100 includes a substrate 10 and a plurality of transistors TFT disposed on the substrate 10. Figure 2As shown, the array substrate 100 includes a display driving module 101 and a gate driving module 102. The display driving module 101 includes a plurality of scanning lines 1011, data lines 1012 and pixel driving units 1013 distributed in an array.

[0079] The scan line 1011 extends along a first direction X for transmitting a scan signal. The data line 1012 extends along a second direction Y for transmitting a data signal. The first direction X intersects with the second direction Y, and the scan line 1011 and the data line 1012 are staggered to define a plurality of pixel regions. The pixel driving unit 1013 is located in the pixel region and corresponds to the pixel region one by one.

[0080] The pixel driving unit 1013 includes a transistor TFT, a common electrode 1014 and a pixel electrode 1015. Among them, the gate electrode 21 of the transistor TFT is electrically connected to the corresponding scan line 1011 for receiving a scan signal; the source electrode 241 of the transistor TFT is electrically connected to the corresponding data line 1012 to receive a data signal; the drain electrode 242 of the transistor TFT is electrically connected to the pixel electrode 1015 to transmit the driving voltage generated by the transistor TFT to the pixel electrode 1015 to realize image display. The common electrode 1014 is used to form a storage capacitor to maintain the driving voltage of the pixel electrode 1015 during the display stage. In some embodiments, the common electrode 1014 can be used as one plate of the storage capacitor, and the pixel electrode 1015 can also be used as the other plate of the storage capacitor to form a storage capacitor. Specifically, the orthographic projection of the common electrode 1014 on the substrate 10 surrounds the orthographic projection of the pixel electrode 1015 on the substrate 10, and the common electrodes 1014 between adjacent pixel driving units 1013 are electrically connected to each other, thereby achieving full-surface connection of the common electrode 1014, so that the common voltage is more evenly distributed on the common electrode 1014.

[0081] The gate driving module 102 is electrically connected to the display driving module 101. The gate driving module 102 includes a plurality of cascaded gate driving units 1021, each gate driving unit 1021 is electrically connected to a corresponding scan line 1011 in the display driving module 101, and is used to provide a scan signal to the corresponding scan line 1011. Specifically, the gate driving unit 1021 includes a gate 21 driving circuit composed of transistors TFT.

[0082] In the embodiment of the present application, the transistor TFT in the pixel driving unit 1013 and the transistor TFT in the gate driving unit 1021 are both amorphous silicon (a-Si) thin film transistors TFT, and their structures may be the same or similar, and the same technical effects may be achieved. In the embodiments below, the transistor TFT in the pixel driving unit 1013 is taken as an example for introduction.

[0083] like Figure 3-5As shown, the transistor TFT includes a gate 21, a gate insulating layer 22, a semiconductor layer 23, a source 241, a drain 242, a first heating electrode 25 and / or a second heating electrode 26. The gate 21 is arranged on one side of the substrate 10; the gate insulating layer 22 is arranged on the gate 21 and covers the gate 21; the semiconductor layer 23 is arranged on the gate insulating layer 22. The first heating electrode 25, the first heating electrode 25 is buried in the gate insulating layer 22; and / or the second heating electrode 26, the second heating electrode 26 is arranged on the semiconductor layer 23, and is insulated from the source 241 and the drain 242.

[0084] In the embodiment of the present application, by making the transistor TFT further include the first heating electrode 25 and / or the second heating electrode 26, the first heating electrode 25 is buried in the gate insulating layer 22, and / or the second heating electrode 26 is arranged on the semiconductor layer 23, the semiconductor layer 23 can be heated by the first heating electrode 25 and / or the second heating electrode 26 in a low temperature environment, thereby realizing the self-heating of the transistor TFT, so as to improve the on-state current of the transistor TFT in a low temperature environment, reduce the situation of insufficient charging rate, reduce the problem of the display panel 1000 being prone to residual image, improve the "cold resistance" of the display panel 1000, and better adapt to the low temperature environment. Moreover, by making the first heating electrode 25 and / or the second heating electrode 26 integrated in the transistor TFT, the distance between the heating electrode and the semiconductor layer 23 in the transistor TFT is smaller, which can further improve the heating effect. Further, through the above-mentioned setting method, the startup and operation of the display panel 1000 in a low temperature environment can be solved without adding a driver IC, saving the preparation cost of the display panel 1000.

[0085] like Figure 3 As shown, in this embodiment, a first heating electrode 25 is provided in the transistor TFT. Specifically, the gate insulating layer 22 includes a first gate insulating layer 221 and a second gate insulating layer 222 which are stacked; the first heating electrode 25 is provided between the first gate insulating layer 221 and the second gate insulating layer 222; wherein the thickness of the first gate insulating layer 221 is The thickness of the second gate insulating layer 222 is The thickness of the first heating electrode 25 is

[0086]

[0087] Specifically, the material of the gate 21 of the transistor TFT is a metal material, which may include aluminum (Al), molybdenum (Mo), titanium (Ti), copper (Cu) or a combination thereof. The thickness of the gate 21 is For example, The specific thickness can be set according to the actual production process accuracy and the characteristic requirements of the transistor TFT, and there is no specific limitation on this.

[0088] The first gate insulating layer 221 can be prepared by chemical vapor deposition (CVD). The material of the first gate 21 can be an inorganic insulating material such as silicon nitride (SiNx), which is used to isolate the gate 21 from the first heating electrode 25 to prevent the gate 21 from shorting the heating electrode. The thickness of the first gate insulating layer 221 is For example The specific thickness can be set according to the characteristics of the transistor TFT, the insulation requirements, the anti-interference requirements, etc., and there is no specific limitation on this.

[0089] The first heating electrode 25 is disposed on the surface of the first insulating layer 27 away from the gate 21, and can be prepared by CVD deposition or patterning processes such as photolithography. The material of the first heating electrode 25 can be aluminum (Al), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), nanosilver, graphene and other heat-generating materials. The thickness of the first heating electrode 25 is For example The specific thickness can be set according to actual needs, and there is no specific restriction on this. When the display panel 1000 is used in a low temperature environment, a heating signal can be provided to the first heating electrode 25 through the control circuit board 500 of the display panel 1000, so that the first heating electrode 25 generates heat, thereby heating the semiconductor layer 23 and realizing the self-heating of the transistor TFT. Specifically, the heating temperature of the first heating electrode 25 is 40 to 60°C, for example, 40°C, 42°C, 44°C, 46°C, 48°C, 50°C, 52°C, 54°C, 56°C, 58°C, 60°C, which can be set according to the actual ambient temperature and the performance of the transistor TFT to meet the display requirements, so that the display panel 1000 can be more adaptable to the low temperature use environment.

[0090] The second gate insulating layer 222 is disposed on a side surface of the first heating electrode 25 away from the first gate insulating layer 221. The second gate insulating layer 222 can be prepared by a CVD deposition process. The material of the second gate insulating layer 222 can be an inorganic insulating material such as silicon nitride (SiNx). The thickness of the second gate insulating layer 222 is For example The specific thickness can be set according to actual needs and there is no specific limitation on this.

[0091] In some embodiments, the second gate insulating layer 222 includes a first sub-gate insulating layer 2221, a second sub-gate insulating layer 2222, and a third sub-gate insulating layer 2223 sequentially stacked on the first heating electrode 25. During preparation, a CVD deposition process can be used for layered preparation, and the first sub-gate insulating layer 2221 is sequentially prepared at a high deposition rate, the second sub-gate insulating layer 2222 is prepared at a medium deposition rate, and the third sub-gate insulating layer 2223 is prepared at a low deposition rate, that is, the deposition rate from the first sub-gate insulating layer 2221 to the third sub-gate insulating layer 2223 is gradually reduced. It can be understood that the first sub-gate insulating layer 2221 away from the semiconductor layer 23 is formed at a high speed, and the third sub-gate insulating layer 2223 close to the semiconductor layer 23 is formed at a low speed, so as to improve the interface characteristics of the gate insulating layer 22, reduce interface defects, and reduce the occurrence of leakage problems. During preparation, the surface of the third sub-gate insulating layer 2223 can also be subjected to hydrogen (H 2 ) treatment, the power can be 7~8KW to further optimize the film quality.

[0092] like Figure 4 As shown, in this embodiment, a second heating electrode 26 is provided in the transistor TFT. Specifically, the transistor TFT further includes a second heating electrode 26 and an insulating layer 27. The second heating electrode 26 is provided on the semiconductor layer 23, and has at least two hollow portions 261 to expose at least two parts of the semiconductor layer 23. The insulating layer 27 is provided on the second heating electrode 26, covering the second heating electrode 26, and an electrode via 271 is also provided on the insulating layer 27, the electrode via 271 is located in the hollow portion 261, and the hole wall of the electrode via 271 and the side wall of the hollow portion 261 are filled with the insulating layer 27; the source electrode 241 and the drain electrode 242 are in contact with the semiconductor layer 23 through the corresponding electrode vias 271, respectively.

[0093] Specifically, the semiconductor layer 23 includes an active layer 231 and an ohmic contact layer 232. The semiconductor layer 23 can be manufactured by a CVD deposition process, specifically, SiH4 gas can be used to deposit the active layer 231, and PH3 and SiH4 gases can be used to deposit the ohmic contact layer 232.

[0094] In some embodiments, the active layer 231 may include a first active layer 2311 and a second active layer 2312 sequentially stacked on the gate insulating layer 22. During preparation, a CVD deposition process may be used for layered preparation, and the first active layer 2311 is deposited at a first deposition rate, and the second active layer 2312 is deposited at a second deposition rate, and the first deposition rate is less than the second deposition rate. That is, the first active layer 2311 close to the gate insulating layer 22 is formed at a low rate to improve the film quality and increase the electron mobility; the second active layer 2312 far from the gate insulating layer 22 is formed at a high rate to improve the production cycle. Among them, the thickness of the first active layer 2311 is For example The thickness of the second active layer 2312 is For example Among them, under the condition of meeting the film quality requirements and electron mobility, the thickness of the first active layer 2311 is set as small as possible, and the second active layer 2312 is set thicker, so as to improve the production cycle while ensuring the quality of the active layer 231.

[0095] The ohmic contact layer 232 is disposed on the active layer 231 and includes at least two doped layers with different doping concentrations. In some embodiments, the ohmic contact layer 232 may include a first doped amorphous silicon layer, a second doped amorphous silicon layer, a third doped amorphous silicon layer and a fourth doped amorphous silicon layer sequentially stacked on the active layer 231. The doping concentrations of the first doped amorphous silicon layer, the second doped amorphous silicon layer, the third doped amorphous silicon layer and the fourth doped amorphous silicon layer increase in a gradient. Based on the average doping concentration of the second doped amorphous silicon layer and the third doped amorphous silicon layer, the doping concentration of the first doped amorphous silicon layer is (-70%) to 50%, the doping concentration of the second doped amorphous silicon layer is (-40%) to (-25%), the doping concentration of the third doped amorphous silicon layer is 25% to 35%, and the doping concentration of the fourth doped amorphous silicon layer is 50% to 70%. During the deposition preparation, the power in the process is 5000 to 6000 W, the total deposition time is 24 to 32 s, and the total film thickness is

[0096] The second heating electrode 26 is disposed on the side of the semiconductor layer 23 away from the gate insulating layer 22, and is made using the same preparation process as the first heating electrode 25. The material of the second heating electrode 26 can be aluminum (Al), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), nanosilver, graphene and other heat-generating materials. The thickness of the second heating electrode 26 is For example The specific thickness can be set according to actual needs and there is no specific limitation on this.

[0097] The second heating electrode 26 has at least two hollow portions 261 to expose at least part of the ohmic contact layer 232 so that the source and drain electrodes 242 can be in contact with the ohmic contact layer 232. The insulating layer 27 is disposed on a surface of the second heating electrode 26 away from the gate insulating layer 22 and covers the second heating electrode 26. An electrode via 271 is also provided on the insulating layer 27 at the position of the hollow portion 261, so that the electrode via 271 is set in the hollow portion 261 to expose the ohmic contact layer 232, so as to facilitate the contact and connection between the source and drain electrodes 242 and the ohmic contact layer 232; and the insulating layer 27 is filled between the hole wall of the electrode via 271 and the side wall of the hollow portion 261, and the source electrode 241 and the drain electrode 242 are respectively insulated from the second heating electrode 26 by the corresponding electrode via 271, so as to prevent the source electrode 241 and the drain electrode 242 from being short-circuited through the second heating electrode 26.

[0098] In this embodiment, when the display panel 1000 is used in a low temperature environment, a heating signal can be provided to the second heating electrode 26 through the control circuit board 500 of the display panel 1000, so that the second heating electrode 26 generates heat, thereby heating the semiconductor layer 23 and realizing the self-heating of the transistor TFT. Specifically, the heating temperature of the second heating electrode 26 is 40 to 60°C, such as 40°C, 42°C, 44°C, 46°C, 48°C, 50°C, 52°C, 54°C, 56°C, 58°C, 60°C, and can be set according to the actual ambient temperature and the performance of the transistor TFT to meet the display requirements, so that the display panel 1000 can be more adapted to the low temperature use environment. Moreover, the second heating electrode 26 is arranged on the semiconductor layer 23, and the distance to the semiconductor layer 23 is closer, which can further improve the heating effect.

[0099] like Figure 5 As shown, in this embodiment, a first heating electrode 25 and a second heating electrode 26 are provided in the transistor TFT. Specifically, the structure and function of the first heating electrode 25 and the second heating electrode 26 are the same or similar to those of the first heating electrode 25 and the second heating electrode 26 in the above embodiment, and the same technical effect can be achieved. For details, please refer to the above description. In this embodiment, by providing the first heating electrode 25 and the second heating electrode 26 in the transistor TFT, the semiconductor layer 23 is located between the first heating electrode 25 and the second heating electrode 26, so that in a low temperature environment, the first heating electrode 25 and the second heating electrode 26 can heat the semiconductor layer 23 from both sides at the same time or from one side according to the specific ambient temperature, thereby further improving the heating effect.

[0100] See also Figure 6-8 , Figure 6 yes Figure 2 A schematic cross-sectional structure diagram of the fourth embodiment provided along the AA direction, Figure 7 yes Figure 2 A schematic cross-sectional structure diagram of the fifth embodiment provided along the AA direction, Figure 8 yes Figure 2 A schematic diagram of a cross-sectional structure of the sixth embodiment provided in the AA direction. In some embodiments, further, the transistor TFT further includes a passivation layer 28 and a third heating electrode 29. The passivation layer 28 is disposed on the source electrode 241 and the drain electrode 242, and covers the source electrode 241 and the drain electrode 242; the third heating electrode 29 is disposed on the passivation layer 28, and the orthographic projection of the third heating electrode 29 on the semiconductor layer 23 covers the channel region 233; wherein the region between the source electrode 241 and the drain electrode 242 corresponds to the region of the portion of the semiconductor layer 23 is the channel region 233.

[0101] Specifically, the passivation layer 28 is disposed on the surface of the source electrode 241 and the drain electrode 242 away from the gate insulating layer 22, and covers the source electrode 241 and the drain electrode 242 to protect the source electrode 241 and the drain electrode 242 from the intrusion of water, oxygen and other harmful substances. The material of the passivation layer 28 can be silicon oxide (SiO 2 ), silicon nitride (SiNx), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ) or polyimide (PI) and other materials. At the same time, the passivation layer 28 is also used to isolate the third heating electrode 29 from the source electrode 241 and the drain electrode 242, so that the third heating electrode 29, the source electrode 241 and the drain electrode 242 are insulated from each other to prevent short circuit.

[0102] The third heating electrode 29 is disposed on a surface of the passivation layer 28 away from the gate insulating layer 22, and the orthographic projection of the third heating electrode 29 on the semiconductor layer 23 covers the channel region 233. The third heating electrode 29 is manufactured by the same manufacturing process as the first heating electrode 25 and / or the second heating electrode 26. The material of the third heating electrode 29 can be aluminum (Al), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), nano silver, graphene and other heat-generating materials.

[0103] In order to reduce the risk of disconnection of the pixel electrode 1015 disposed above, the thickness of the third heating electrode 29 is For example It can be set according to actual needs. It can be understood that the second passivation layer 30 is provided on the side of the third heating electrode 29 away from the gate 21 driving substrate, and the pixel electrode 1015 is provided on the side of the second passivation layer 30 away from the substrate 10. In order to reduce the risk of disconnection of the pixel electrode 1015, the side of the second passivation layer 30 away from the substrate 10 should be as flat as possible. Therefore, the thickness of the third heating electrode 29 should be reduced and controlled at In between, while auxiliary heating is performed, the risk of disconnection of the pixel electrode 1015 is reduced.

[0104] Specifically, Figure 6 As shown, in this embodiment, a first heating electrode 25 and a third heating electrode 29 are provided in the transistor TFT, and the first heating electrode 25 and the third heating electrode 29 can heat the semiconductor layer 23 from opposite sides of the semiconductor layer 23, which can not only improve the heating rate, but also have a heat preservation effect, so as to reduce the heating power consumption, improve the heating effect, and further improve the "cold resistance" of the display panel 1000 in a low temperature environment; and it is also possible to select the first heating electrode 25 or the third heating electrode 29 to heat the semiconductor layer 23 from one side according to the specific ambient temperature, so as to improve the flexibility of the heating function.

[0105] like Figure 7 As shown, in this embodiment, the second heating electrode 26 and the third heating electrode 29 are provided in the transistor TFT. In a low temperature environment, when the heating effect of the second heating electrode 26 does not meet the requirements of the on-state current and the charging rate of the transistor TFT, the semiconductor layer 23 can be further heated by the third heating electrode 29 to further increase the heating temperature. Alternatively, when the second heating electrode 26 is heated, the heating temperature of the third heating electrode 29 can be lower than that of the second heating electrode 26, and the temperature of the second heating electrode 26 is maintained at a lower power to achieve a heat preservation effect, thereby further improving the heating effect.

[0106] like Figure 8 As shown, in this embodiment, a first heating electrode 25, a second heating electrode 26 and a third heating electrode 29 are provided in the transistor TFT, and the heating method of the first heating electrode 25, the second heating electrode 26 and the third heating electrode 29 may be the same or similar to that in the above embodiment, so as to further improve the heating effect and enhance the "cold resistance" of the display panel 1000 in a low temperature environment.

[0107] See also Fig. 9 , Fig. 9 yes Figure 2In some embodiments, the array substrate 100 further includes a heating layer 40, which is disposed on a side of the substrate 10 away from the transistor TFT, and the orthographic projection of the heating layer 40 on the substrate 10 covers the orthographic projection of the transistor TFT on the substrate 10.

[0108] The material of the heating layer 40 can be the same as the material of the first heating electrode 25 mentioned above. The material and thickness of the heating layer 40 can be set according to the actual heating requirements and light transmission requirements, and there is no specific limitation on this. When the material of the heating layer 40 is a transparent material, the substrate 10 can be covered on the entire surface; alternatively, the heating layer 40 can also be only provided in the routing area and device area of ​​the array substrate 100, avoiding the pixel opening area, so as to reduce the influence on the backlight transmission. In some applications, for electronic reading products, such as electrophoretic panels, the problems caused by low temperature to the transistor TFT will be more obvious due to the lack of backlight. By providing a heating layer 40, the transistor TFT can be further heated, and at the same time, the first heating electrode 25, the second heating electrode 26 and / or the third heating electrode 29 in the transistor TFT can be used together to further enhance the "cold resistance effect" of the display panel 1000, and further ensure the display effect in a low temperature environment.

[0109] Specifically, the array substrate 100 can be manufactured by using the manufacturing method provided in the following implementation mode. Please refer to the following introduction for details.

[0110] See also Figure 10-12 , Fig.10 is a schematic flow chart of a method for preparing an array substrate 100 provided in one embodiment of the present application. Fig.11 yes Fig.10 A schematic diagram of a preparation method provided in one embodiment of step S20, Fig.12 1 is a schematic flow chart of the steps of manufacturing the second heating electrode provided in one embodiment of the present application. In one embodiment of the present application, a method for manufacturing an array substrate 100 is provided, comprising:

[0111] S10: providing a substrate 10, depositing a first metal layer on the substrate 10, and patterning the first metal layer to form a gate 21;

[0112] S20: depositing a gate insulating layer 22 on the substrate 10 so that the gate insulating layer 22 covers the gate 21;

[0113] S30: depositing an active layer 231 and a semiconductor doping layer on the gate insulating layer 22 in sequence, and performing photolithography to form a semiconductor layer 23;

[0114] S40 : depositing a second metal layer on the semiconductor doping layer, and patterning the second metal layer to form a source electrode 241 and a drain electrode 242 .

[0115] The preparation method further includes the steps of making the first heating electrode 25 and / or the steps of making the second heating electrode 26 involved in the above embodiments.

[0116] like Fig.12 As shown, the manufacturing step S22 of the first heating electrode 25 is arranged in the step S20, and the step S20 specifically includes:

[0117] S21: depositing a first gate insulating layer 221 on the substrate 10 so that the first gate insulating layer 221 covers the gate 21;

[0118] S22: depositing a first heat-conducting layer on the first gate insulating layer 221 and patterning the first heat-conducting layer to form a first heating electrode 25;

[0119] S23 : depositing a first sub-gate insulating layer 2221 , a second sub-gate insulating layer 2222 and a third sub-gate insulating layer 2223 in sequence on the first heating electrode 25 at different deposition rates to form a second gate insulating layer 222 .

[0120] In step S23, when preparing the second gate insulating layer 222, a CVD deposition process can be used for layered preparation, and the first sub-gate insulating layer 2221 is prepared at a high deposition rate, the second sub-gate insulating layer 2222 is prepared at a medium deposition rate, and the third sub-gate insulating layer 2223 is prepared at a low deposition rate, that is, the deposition rates of the first sub-gate insulating layer 2221 to the third sub-gate insulating layer 2223 are gradually reduced. It can be understood that the first sub-gate insulating layer 2221 away from the semiconductor layer 23 is formed at a high speed, and the third sub-gate insulating layer 2223 close to the semiconductor layer 23 is formed at a low speed, so as to improve the interface characteristics of the gate insulating layer 22, reduce interface defects, and reduce the occurrence of leakage problems. During preparation, the surface of the third sub-gate insulating layer 2223 can also be subjected to hydrogen (H 2 ) treatment, the power can be 7~8KW to further optimize the film quality.

[0121] like Fig.12 As shown, the manufacturing step S50 of the second heating electrode 26 is arranged after the step S30 and before the step S40, and specifically includes:

[0122] S51: depositing a second heat-conducting layer on the semiconductor layer 23, and patterning the second heat-conducting layer to form a second heating electrode 26;

[0123] S52: depositing an insulating layer 27 on the second heating electrode 26 and performing patterning to form an electrode via 271 , wherein the electrode via 271 exposes a portion of the semiconductor doping layer; wherein the second heating electrode 26 is insulated from the source electrode 241 and the drain electrode 242 .

[0124] In the above-mentioned embodiment, in the process flow of preparing the transistor TFT, the first heating electrode 25 is formed in the step of manufacturing the gate insulating layer 22, and / or the process of manufacturing the second heating electrode 26 is added between the process of manufacturing the semiconductor layer 23 and the process of manufacturing the source and drain 242 to form the second heating electrode 26, so that the transistor TFT on the array substrate 100 can realize a self-heating function through its own first heating electrode 25 and / or second heating electrode 26, so as to improve the on-state current and charging rate of the transistor TFT in a low temperature environment without adding a driver IC, thereby improving the low-temperature start-up and operation capabilities of the display panel 1000 and reducing the risk of image abnormality in a low temperature environment.

[0125] Specifically, the structures of the gate 21, the gate insulating layer 22, the semiconductor layer 23, the source 241, the drain 242, the first heating electrode 25 and the second heating electrode 26 and the manufacturing process adopted are the same as those in the above embodiment, and can achieve the same technical effects. For details, please refer to the introduction of the above embodiment, which will not be repeated here.

[0126] See also Fig.13 , Fig.13 2 is a flow chart of a method for preparing a semiconductor layer provided in one embodiment of the present application. In this embodiment, the steps of preparing the semiconductor layer 23 specifically include:

[0127] S31: forming a first active layer 2311 by deposition on the gate insulating layer 22 at a first deposition rate; the thickness of the first active layer 2311 is

[0128] S32: forming a second active layer 2312 by deposition on the first active layer 2311 at a second deposition rate; the thickness of the second active layer 2312 is The first deposition rate is lower than the second deposition rate; the materials of the first active layer 2311 and the second active layer 2312 are amorphous silicon;

[0129] S33: a first doped amorphous silicon layer, a second doped amorphous silicon layer, a third doped amorphous silicon layer and a fourth doped amorphous silicon layer with different doping concentrations are sequentially deposited on the second active layer 2312; the doping concentrations of the first doped amorphous silicon layer to the fourth doped amorphous silicon layer are increased sequentially, and the total thickness of the first doped amorphous silicon layer to the fourth doped amorphous silicon layer is

[0130] S34 : performing photolithography processing on the active layer 231 and the semiconductor doping layer to form a channel region 233 , wherein the channel region 233 penetrates the semiconductor doping layer and partially penetrates the active layer 231 .

[0131] In this embodiment, through step S31 and step S32, the active layer 231 is layered and prepared by a CVD deposition process, and the first active layer 2311 is formed by deposition at a first deposition rate, and the second active layer 2312 is formed by deposition at a second deposition rate, and the first deposition rate is less than the second deposition rate. That is, the first active layer 2311 close to the gate insulating layer 22 is formed at a low rate to improve the film quality and increase the electron mobility; the second active layer 2312 away from the gate insulating layer 22 is formed at a high rate to improve the production cycle. Wherein, under the condition of meeting the film quality requirements and the electron mobility, the thickness of the first active layer 2311 is set as small as possible, and the second active layer 2312 is set thicker, so as to improve the production cycle while ensuring the quality of the active layer 231.

[0132] Through step S33 and step S34, an ohmic contact layer 232 with a multilayer structure having a gradient doping concentration is prepared. Specifically, based on the average doping concentration of the second doped amorphous silicon layer and the third doped amorphous silicon layer, the doping concentration of the first doped amorphous silicon layer is (-70%) to 50%, the doping concentration of the second doped amorphous silicon layer is (-40%) to (-25%), the doping concentration of the third doped amorphous silicon layer is 25% to 35%, and the doping concentration of the fourth doped amorphous silicon layer is 50% to 70%. During the deposition preparation, the process power is 5000 to 6000 W, the total deposition time is 24 to 32 s, and the total film thickness is

[0133] Of course, in other embodiments, the ohmic contact layer 232 can also be set to two or three doping layers with different doping concentrations, or to five doping layers with different doping concentrations. The number of doping layers and specific doping concentrations can be set according to actual needs, and no specific limitation is made to this.

[0134] See also Fig.14 , Fig.14 : is a schematic flow chart of a method for preparing a third heating electrode provided in an embodiment of the present application. In some embodiments, the preparation method further includes a step S60 of making the third heating electrode 29, and the step S60 specifically includes:

[0135] S61: depositing a passivation layer 28 on the source electrode 241 and the drain electrode 242 so that the passivation layer 28 covers the source electrode 241 and the drain electrode 242;

[0136] S62: depositing a third heat-conducting layer on the passivation layer 28, and patterning the third heat-conducting layer to form a third heating electrode 29, so that the orthographic projection of the third heating electrode 29 on the semiconductor layer 23 covers the channel region 233 of the semiconductor layer 23; the thickness of the third heating electrode 29 is

[0138] In this embodiment, the third heating electrode 29 is manufactured by the same preparation process as the first heating electrode 25 and / or the second heating electrode 26. Specifically, the materials and structures of the passivation layer 28 and the third heating electrode 29 are the same or similar to those of the passivation layer 28 and the third heating electrode 29 involved in the above embodiment, and the same technical effects can be achieved. For details, please refer to the above description. In this embodiment, by adding the process of the third heating electrode 29 to the preparation process of the transistor TFT, the self-heating effect of the transistor TFT can be further improved, so as to further improve the "drought resistance" of the display panel 1000 in a low temperature environment.

[0139] See also Fig.15 , Fig.15 1 is a flow chart of a method for preparing a heating layer provided in an embodiment of the present application. In some embodiments, the array substrate 100 is used for an electrophoretic display panel 1000, and the method for preparing the array substrate 100 further includes a step S70 of making a heating layer 40, and the step S70 specifically includes: depositing a fourth heat-conducting layer on a side of the substrate 10 away from the gate 21 to form a heating layer 40, so that the orthographic projection of the heating layer 40 on the substrate 10 covers the orthographic projection of the semiconductor layer 23 on the substrate 10.

[0140] Among them, the material of the heating layer 40 is the same as that of the first heating electrode 25, and can be manufactured by the same preparation process as the first heating electrode 25. In the array substrate 100 manufactured by this embodiment, the heating layer 40 is formed on the surface of the side of the substrate 10 away from the transistor TFT. Since the electrophoretic display panel 1000 has no backlight support, the problem caused by low temperature to the transistor TFT will be more obvious. Through further heating of the heating layer 40, the first heating electrode 25, the second heating electrode 26 and / or the third heating electrode 29 in the transistor TFT can be used together to further enhance the "cold resistance effect" of the display panel 1000 and further ensure the display effect in a low temperature environment. Moreover, since the electrophoretic display panel 1000 does not require a backlight assembly, adding a heating layer 40 will not cause a problem of transmittance to the display panel 1000.

[0141] See also Fig.16 , Fig.16 1 is a schematic diagram of a display device according to an embodiment of the present application. In this embodiment, a display device is provided, and the display device includes a display panel 1000 and a control circuit board 500 .

[0142] The display panel 1000 includes the array substrate 100 provided in the above embodiment. The display panel 1000 may be a liquid crystal panel or an electrophoretic panel. In one embodiment, the display panel 1000 is a liquid crystal panel, and the display panel 1000 includes an array substrate 100, an opposing substrate 200, and a liquid crystal layer 300 sealed between the array substrate 100 and the opposing substrate 200. In another embodiment, the display panel 1000 is an electrophoretic panel, and the display panel 1000 includes an array substrate 100, an opposing substrate 200, and an electrophoretic medium layer 400 sealed between the array substrate 100 and the opposing substrate 200, and the electrophoretic medium layer 400 includes an electrophoretic liquid and charged display particles dispersed in the electrophoretic liquid.

[0143] The control circuit board 500 is electrically connected to the display panel 1000 to control the display panel 1000 to display a corresponding image. At the same time, the control circuit board 500 is also used to provide a heating signal to the heating electrode in the transistor TFT to control the heating temperature of the transistor TFT according to the ambient temperature to adapt to the low temperature use environment.

[0144] The display device provided in this embodiment can realize the self-heating function of the transistor TFT device according to the ambient temperature without adding a driver IC, so as to increase the on-state current of the transistor TFT at low temperature and improve the charging rate of the transistor TFT, thereby improving the low-temperature start-up and operation capabilities of the display panel 1000 and reducing the risk of image abnormalities at low temperatures.

[0145] The above are only implementation methods of the present application, and are not intended to limit the patent protection scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An array substrate for a display panel, comprising a substrate and a plurality of transistors disposed on the substrate; the transistors comprising: A gate, disposed on one side of the substrate; A gate insulating layer, disposed on the gate and covering the gate; A semiconductor layer, disposed on the gate insulating layer; A source electrode is disposed on the semiconductor layer; A drain electrode is disposed on the semiconductor layer; Characterized in that the transistor further comprises: A first heating electrode, wherein the first heating electrode is buried in the gate insulating layer; and / or, The second heating electrode is disposed on the semiconductor layer and is insulated from the source electrode and the drain electrode.

2. The array substrate according to claim 1, characterized in that: The transistor further includes the first heating electrode; The gate insulating layer includes a first gate insulating layer and a second gate insulating layer stacked in layers; the first heating electrode is arranged between the first gate insulating layer and the second gate insulating layer; wherein the thickness of the first gate insulating layer is The thickness of the second gate insulating layer is The thickness of the first heating electrode is 3. The array substrate according to claim 1, characterized in that: The transistor further includes the second heating electrode and an insulating layer; The second heating electrode is disposed on the semiconductor layer and has at least two hollow portions to expose at least two portions of the semiconductor layer; The insulating layer is arranged on the second heating electrode and covers the second heating electrode. An electrode via is also opened on the insulating layer. The electrode via is located in the hollow portion, and the insulating layer is filled between the hole wall of the electrode via and the side wall of the hollow portion. The source electrode and the drain electrode are respectively in contact with the semiconductor layer through the corresponding electrode vias.

4. The array substrate according to claim 1, characterized in that: The transistor further comprises a passivation layer and a third heating electrode; The passivation layer is arranged on the source electrode and the drain electrode, and covers the source electrode and the drain electrode; the third heating electrode is arranged on the passivation layer, and the orthographic projection of the third heating electrode on the semiconductor layer covers the channel region; wherein the region of the semiconductor layer corresponding to the region between the source electrode and the drain electrode is the channel region.

5. The array substrate according to claim 1, characterized in that: The array substrate further includes a heating layer, which is disposed on a side of the substrate away from the transistor, and an orthographic projection of the heating layer on the substrate covers an orthographic projection of the transistor on the substrate.

6. A method for preparing an array substrate, comprising: Providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to form a gate; Depositing a gate insulating layer on the substrate so that the gate insulating layer covers the gate; Depositing an active layer and a semiconductor doping layer on the gate insulating layer in sequence, and performing photolithography to form a semiconductor layer; Depositing a second metal layer on the semiconductor doping layer, and patterning the second metal layer to form a source electrode and a drain electrode; The method is characterized in that the step of depositing a gate insulating layer on the substrate so that the gate insulating layer covers the gate specifically comprises: Depositing a first gate insulating layer on the substrate so that the first gate insulating layer covers the gate; Depositing a first heat-conducting layer on the first gate insulating layer, and patterning the first heat-conducting layer to form a first heating electrode; Depositing a first sub-gate insulating layer, a second sub-gate insulating layer and a third sub-gate insulating layer in sequence at different deposition rates on the first heating electrode to form a second gate insulating layer; And / or, before the step of depositing a second metal layer on the semiconductor doping layer and patterning the second metal layer to form a source electrode and a drain electrode, the method further includes: Depositing a second heat-conducting layer on the semiconductor layer, and patterning the second heat-conducting layer to form a second heating electrode; An insulating layer is deposited on the second heating electrode and patterned to form an electrode via hole, wherein the electrode via hole exposes a portion of the semiconductor doping layer; wherein the second heating electrode is insulated from the source electrode and the drain electrode.

7. The preparation method according to claim 6, characterized in that: The steps of sequentially depositing an active layer and a semiconductor doping layer on the gate insulating layer and performing photolithography to form a semiconductor layer include: A first active layer is formed by depositing on the gate insulating layer at a first deposition rate; the thickness of the first active layer is A second active layer is formed by depositing on the first active layer at a second deposition rate; the thickness of the second active layer is The first deposition rate is lower than the second deposition rate; the material of the first active layer and the second active layer is amorphous silicon; A first doped amorphous silicon layer, a second doped amorphous silicon layer, a third doped amorphous silicon layer and a fourth doped amorphous silicon layer with different doping concentrations are sequentially deposited on the second active layer; the doping concentrations of the first doped amorphous silicon layer to the fourth doped amorphous silicon layer are increased sequentially, and the total thickness of the first doped amorphous silicon layer to the fourth doped amorphous silicon layer is The active layer and the semiconductor doping layer are subjected to photolithography processing to form a channel region, wherein the channel region penetrates the semiconductor doping layer and partially penetrates to the active layer.

8. The preparation method according to claim 6, characterized in that: The preparation method further comprises: Depositing a passivation layer on the source electrode and the drain electrode so that the passivation layer covers the source electrode and the drain electrode; A third heat-conducting layer is deposited on the passivation layer, and the third heat-conducting layer is patterned to form a third heating electrode, so that the orthographic projection of the third heating electrode on the semiconductor layer covers the channel region of the semiconductor layer; the thickness of the third heating electrode is 9. The preparation method according to claim 6, characterized in that: The array substrate is used for an electrophoretic display panel, and the preparation method further includes: A fourth heat-conducting layer is deposited on a side of the substrate away from the gate to form a heating layer, so that the orthographic projection of the heating layer on the substrate covers the orthographic projection of the semiconductor layer on the substrate.

10. A display device, characterized in that: include: A display panel, the display panel comprising an array substrate as claimed in any one of claims 1 to 5; A control circuit board is electrically connected to the display panel and is used to control the display panel to display a corresponding image.

Images