Display panel and display device

Abstract

The invention provides a display panel and a display device. An active layer of a first initialization transistor of a first pixel circuit is connected with an active layer of a second initialization transistor of a second pixel circuit through a first connecting line, so that the active layers of the initialization transistors in different areas are connected together; therefore, after an initialization signal is accessed to one initialization transistor, the initialization signal can be transmitted to the other initialization transistor through the first connecting line, so that the problem that the difference of the initialization signals accessed to the initialization transistors in different areas is large due to the fact that the initialization signal is transmitted only through a signal line with voltage drop is avoided; and the uniformity of the initialization signals accessed by the initialization transistors in different areas of the display panel is high.

Description

[0001] This application is a divisional application with the application date of September 14, 2021, application number 202111075596.8, and invention name “Display panel and display device”. Technical Field

[0002] The present invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Art

[0003] The border area of ​​the existing display device includes a peripheral driving circuit for providing a driving signal to the pixel unit in the display area. In the display device, a plurality of pixel units are arranged in the display area, and each pixel unit includes a pixel circuit. Each pixel circuit is electrically connected to the peripheral driving circuit in the border area, and the peripheral driving circuit provides a scanning control signal and a light-emitting control signal to the pixel circuit, so as to control the pixel circuit to provide a driving current for the light-emitting element.

[0004] The pixel circuit also includes an initialization transistor. When initializing the pixel circuit, an initialization signal needs to be applied to the initialization transistor, and the initialization transistor selectively transmits the initialization signal to a preset node in the pixel circuit. Therefore, a separate signal line needs to be set in the display device to apply the initialization signal to the initialization transistor; the initialization signal in the existing display device is generally provided by an integrated chip (IC). Considering the voltage drop on the signal line, the initialization signal is inconsistent near the IC end and far from the IC end. Summary of the invention

[0005] In view of this, the present invention provides a display panel and a display device, which effectively solve the technical problems existing in the prior art and ensure that the initialization signals connected to the initialization transistors in different areas of the display panel are highly uniform.

[0006] To achieve the above purpose, the technical solution provided by the present invention is as follows:

[0007] A display panel, comprising:

[0008] Pixel circuit and light emitting element;

[0009] The pixel circuit includes a driving transistor and an initialization transistor, wherein the initialization transistor is used to provide an initialization signal for a preset node, and the preset node is the gate of the driving transistor or the anode of the light-emitting element;

[0010] The pixel circuit includes an oxide semiconductor transistor and a silicon transistor, wherein an active layer of the oxide semiconductor transistor includes an oxide semiconductor, and an active layer of the silicon transistor includes silicon;

[0011] The pixel circuit includes a first pixel circuit and a second pixel circuit, the first pixel circuit includes a first initialization transistor, the second pixel circuit includes a second initialization transistor, the active layer of the first initialization transistor is connected to the active layer of the second initialization transistor through a first connecting line, and at least a portion of the first connecting line is located in the same layer as the active layer of the oxide semiconductor transistor.

[0012] Correspondingly, the present invention also provides a display device, comprising the above-mentioned display panel.

[0013] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0014] The present invention provides a display panel and a display device, wherein an active layer of a first initialization transistor of a first pixel circuit is connected to an active layer of a second initialization transistor of a second pixel circuit via a first connecting line, so as to connect the active layers of initialization transistors in different regions together, and then after an initialization signal is connected to one of the initialization transistors, the initialization signal can be transmitted to another initialization transistor via the first connecting line, thereby avoiding the problem of large differences in initialization signals connected to initialization transistors in different regions caused by transmitting the initialization signal only via a signal line with a voltage drop, and ensuring high uniformity of initialization signals connected to initialization transistors in different regions of the display panel.

[0015] At the same time, by connecting the active layer of the first initialization transistor and the active layer of the second initialization transistor through the first connecting line, the number of signal lines for transmitting the initialization signal can be appropriately reduced, which is conducive to reducing the line density of the display panel, thereby achieving the purpose of improving the resolution. In addition, when the signal line for transmitting the initialization signal is broken, the initialization signal can also be transmitted to the connected initialization transistor through the first connecting line, thereby improving the flexibility and reliability of the line.

[0016] Moreover, at least a partial area of ​​the first connecting line provided by the present invention is located in the same layer as the active layer of the oxide semiconductor transistor. By adjusting the conductivity of the first connecting line, the first connecting line can be used as a wiring to connect the two active layers, thereby eliminating the need to separately prepare a conductive film for making the first connecting line, thereby reducing the process flow of preparing the display panel and avoiding increasing the wiring layout burden of other conductive film layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0018] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0019] Figure 2 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0020] Figure 3 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0021] Figure 4 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0022] Figure 5 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0023] Figure 6 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0024] Figure 7 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0025] Figure 8 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0026] Fig. 9 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0027] Fig.10 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0028] Fig.11 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0029] Fig.12 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0030] Fig.13 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0031] Fig.14A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0032] Fig.15 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0033] Fig.16 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0034] Fig.17 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0035] Fig.18 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0036] Fig.19 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0037] Fig. 20 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0038] Fig.21 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0039] Fig. 22 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] As described in the background technology, the pixel circuit also includes an initialization transistor. When initializing the pixel circuit, an initialization signal needs to be applied to the initialization transistor, and the initialization transistor selectively transmits the initialization signal to a preset node in the pixel circuit. Therefore, a separate signal line needs to be set in the display device to apply the initialization signal to the initialization transistor; the initialization signal in the existing display device is generally provided by an integrated chip (IC). Considering the voltage drop on the signal line, the initialization signal is inconsistent near the IC end and far from the IC end.

[0042] Based on this, the embodiments of the present invention provide a display panel and a display device, which effectively solve the technical problems existing in the prior art and ensure that the initialization signals connected to the initialization transistors in different areas of the display panel are highly uniform.

[0043] To achieve the above purpose, the technical solution provided by the embodiment of the present invention is as follows, specifically combined with Figures 1 to 22 The technical solution provided by the embodiment of the present invention is described in detail.

[0044] Combination Figures 1 to 4 As shown, Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, Figure 2 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Figure 3 A schematic diagram of a pixel circuit according to an embodiment of the present invention is provided. Figure 4 A schematic diagram of another pixel circuit provided by an embodiment of the present invention, wherein a display panel includes:

[0045] The display area AA and the frame area NA surrounding the display area AA include a pixel circuit 10 and a light emitting element 20 in the display area AA.

[0046] The pixel circuit 10 includes a driving transistor T0 and an initialization transistor Tx. The initialization transistor Tx is used to provide an initialization signal for a preset node Q. The preset node Q is the gate of the driving transistor T0 (eg, Figure 3 ) or the anode of the light emitting element 20 (as shown Figure 4 shown).

[0047] The pixel circuit 10 includes an oxide semiconductor transistor IGZO and a silicon transistor SiTFT, wherein the active layer of the oxide semiconductor transistor IGZO includes an oxide semiconductor, and the active layer of the silicon transistor SiTFT includes silicon. The display panel includes a substrate 100; a silicon semiconductor layer 211 located on the substrate 100, wherein the silicon semiconductor layer 211 includes an active layer of the silicon transistor SiTFT; a first insulating layer 212 located on the side of the silicon semiconductor layer 211 away from the substrate 100; a first gate metal layer 213 located on the side of the first insulating layer 212 away from the substrate 100, wherein the first gate metal layer 213 includes a gate of the silicon transistor SiTFT; a second insulating layer 214 located on the side of the first gate metal layer 213 away from the substrate 100; a capacitor metal layer 215 located on the side of the second insulating layer 214 away from the substrate 100, wherein the capacitor metal layer 215 includes one plate of a storage capacitor C, and the other plate of the storage capacitor C can be prepared by the first gate metal layer 213 or other conductive layers; a capacitor metal layer 215 located on the side of the capacitor metal layer 215 away from the substrate A third insulating layer 216 on one side of the base substrate 100; an oxide semiconductor layer 217 located on the side of the third insulating layer 216 away from the base substrate 100, the oxide semiconductor layer 217 including an active layer of an oxide semiconductor transistor IGZO; a fourth insulating layer 218 located on the side of the oxide semiconductor layer 217 away from the base substrate 100; a second gate metal layer 219 located on the side of the fourth insulating layer 218 away from the base substrate 100, the second gate metal layer 219 including a gate of the oxide semiconductor transistor IGZO; a fifth insulating layer 220 located on the side of the second gate metal layer 219 away from the base substrate 100; a source-drain metal layer 221 located on the side of the fifth insulating layer 220 away from the base substrate 100, the source-drain metal layer 221 including a source and a drain of the oxide semiconductor transistor IGZO and a silicon transistor SiTFT.

[0048] The pixel circuit 10 includes a first pixel circuit 11 and a second pixel circuit 12, the first pixel circuit 11 includes a first initialization transistor, the second pixel circuit 12 includes a second initialization transistor, the active layer of the first initialization transistor is connected to the active layer of the second initialization transistor through a first connecting line 30, and at least a partial area of ​​the first connecting line 30 is located on the same layer as the active layer of the oxide semiconductor transistor.

[0049] It can be understood that the active layer of the first initialization transistor of the first pixel circuit provided in the embodiment of the present invention is connected to the active layer of the second initialization transistor of the second pixel circuit through a first connecting line to connect the active layers of the initialization transistors in different regions together, and then after one of the initialization transistors is connected to the initialization signal, the initialization signal can be transmitted to the other initialization transistor through the first connecting line, thereby avoiding the problem of large differences in the initialization signals connected to the initialization transistors in different regions caused by transmitting the initialization signal only through a signal line with a voltage drop, thereby ensuring the high uniformity of the initialization signals connected to the initialization transistors in different regions of the display panel.

[0050] At the same time, by connecting the active layer of the first initialization transistor and the active layer of the second initialization transistor through the first connecting line, the number of signal lines for transmitting the initialization signal can be appropriately reduced, which is conducive to reducing the line density of the display panel, thereby achieving the purpose of improving the resolution. In addition, when the signal line for transmitting the initialization signal is broken, the initialization signal can also be transmitted to the connected initialization transistor through the first connecting line, thereby improving the flexibility and reliability of the line.

[0051] Moreover, at least a partial region of the first connecting line provided in the embodiment of the present invention is located in the same layer as the active layer of the oxide semiconductor transistor. By adjusting the conductivity of the first connecting line, the first connecting line can be used as a wiring to connect the two active layers, thereby eliminating the need to separately prepare a conductive film for making the first connecting line, thereby reducing the process flow of preparing the display panel and avoiding increasing the wiring layout burden of other conductive film layers.

[0052] like Figure 3 or Figure 4As shown, the pixel circuit 10 provided in the embodiment of the present invention includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a driving transistor T0, an initialization transistor Mx and a holding capacitor C, wherein the driving transistor T0 is used to provide a driving current for the light-emitting element 20; and the initialization transistor Mx is used to initialize and reset the pixel circuit 10. Among them, the first electrode of the first transistor T1 is connected to the data signal Vdata, the second electrode of the first transistor T1 is connected to the first electrode of the driving transistor T0, and the gate of the first transistor T1 is connected to the first scanning signal K1. The first electrode of the second transistor T2 is connected to the second electrode of the driving transistor T0, the second electrode of the second transistor T2 is connected to the gate of the driving transistor T0, and the gate of the second transistor T2 is connected to the second scanning signal K2. The gates of the third transistor T3 and the fourth transistor T4 are connected to the light-emitting control signal EM, the first electrode of the third transistor T3 is connected to the first power signal PVDD, the second electrode of the third transistor T3 is connected to the source of the driving transistor T0, the first electrode of the fourth transistor T4 is connected to the drain of the driving transistor T0, the second electrode of the fourth transistor T4 is connected to one end of the light-emitting element 20, and the other end of the light-emitting element 20 is connected to the second power signal PVEE; wherein the light-emitting control signal EM is a pulse signal, the light-emitting control signal EM controls the third transistor T3 and the fourth transistor T4 to be turned on when the pulse is valid, and the light-emitting element 20 is in the light-emitting stage; and the light-emitting control signal EM controls the third transistor T3 and the fourth transistor T4 to be turned off when the pulse is invalid, and the light-emitting element 20 is in the non-light-emitting stage. And a holding capacitor C for maintaining the node potential, the first end of the holding capacitor C is connected to the first power signal PVDD, and the second end of the holding capacitor C is connected to the gate of the driving transistor T0.

[0053] like Figure 3As shown, the gate of the initialization transistor Tx provided in the embodiment of the present invention is connected to the initialization control signal Kx, the first electrode of the initialization transistor Tx is connected to the initialization signal Vref, the second electrode of the initialization transistor Tx is electrically connected to the gate of the driving transistor T0, wherein the preset node Q is the gate of the driving transistor T0. The working process of the pixel circuit 10 includes an initialization stage, a data writing stage and a light-emitting stage; in the initialization stage, the initialization transistor Tx transmits the initialization signal Vref to the gate of the driving transistor T0 to initialize and reset the driving transistor T0, and the first transistor T1 to the fourth transistor T4 are in the cut-off state; then in the data writing stage, the first transistor T1 and the second transistor T2 are turned on, the first transistor T1 transmits the data signal Vdata to the first electrode of the driving transistor T0, the second transistor T2 connects the gate of the driving transistor T0 with the second electrode, and the initialization transistor Tx, the third transistor T3 and the fourth transistor T4 are in the cut-off state; finally, in the light-emitting stage, the third transistor T3 and the fourth transistor T4 are turned on, the path of the driving current generated by the driving transistor T0 to the light-emitting element 20 is turned on, and the light-emitting element 20 is driven to emit light, wherein the light-emitting element 20 can be a light-emitting diode.

[0054] like Figure 4 As shown, the gate of the initialization transistor Tx provided in the embodiment of the present invention is connected to the initialization control signal Kx, the first electrode of the initialization transistor Tx is connected to the initialization signal Vref, and the second electrode of the initialization transistor Tx is electrically connected to the anode of the light-emitting element 20, wherein the preset node Q is the anode of the light-emitting element 20. The working process of the pixel circuit 10 includes an initialization stage, a data writing stage and a light-emitting stage; in the initialization stage, the initialization transistor Tx transmits the initialization signal Vref to the anode of the light-emitting element 20 to initialize and reset the pixel circuit 10, and the first transistor T1 to the fourth transistor T4 are in the cut-off state; then in the data writing stage, the first transistor T1 and the second transistor T2 are turned on, the first transistor T1 transmits the data signal Vdata to the first electrode of the driving transistor T0, the second transistor T2 connects the gate of the driving transistor T0 to the second electrode, and the initialization transistor Tx, the third transistor T3 and the fourth transistor T4 are in the cut-off state; finally, in the light-emitting stage, the third transistor T3 and the fourth transistor T4 are turned on, the path of the driving current generated by the driving transistor T0 to the light-emitting element 20 is turned on, and the light-emitting element 20 is driven to emit light, wherein the light-emitting element 20 can be a light-emitting diode.

[0055] It should be noted that the pixel circuit provided by the present invention is not limited to Figure 2 and Figure 3 The two types shown can also be other circuit structures, which need to be specifically selected according to actual applications.

[0056] In one embodiment of the present invention, the initialization transistor provided by the present invention may be an oxide semiconductor transistor. Optionally, both the first connection line and the active layer of the initialization transistor include an oxide semiconductor; and the conductivity of the first connection line is greater than the conductivity of the channel region of the active layer of the initialization transistor. Figure 5 As shown, the first initialization transistor Mx1 and the second initialization transistor Mx2 provided in the embodiment of the present invention are both oxide semiconductor transistors, wherein the active layer of the first initialization transistor Mx1 and the active layer of the second initialization transistor Mx2 are connected through the first connection line 30, and the first connection line 30 and the active layer of the oxide semiconductor transistor are located in the same layer. In addition, when preparing the first connection line 30, its conductivity is regulated so that the conductivity of the first connection line 30 is greater than the conductivity of the channel region of the active layer of the initialization transistor, thereby ensuring that the signal transmission performance of the first connection line 30 is high.

[0057] like Figure 6 As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the first pixel circuit 11 and the second pixel circuit 12 provided by the embodiment of the present invention are arranged along the first direction X, and the first connecting line 30 extends from the active layer Mx10 of the first initialization transistor along the first direction X to the active layer Mx20 of the second initialization transistor. The pixel circuit provided by the embodiment of the present invention can be arranged in an array of multiple rows and multiple columns, wherein the first direction X can be the extension direction of the pixel circuit row (that is, the arrangement direction of multiple pixel circuit columns), and then when one of the first pixel circuit 11 and the second pixel circuit 12 receives the initialization signal, the other pixel circuit also receives the initialization signal, thereby reducing the number of signal lines. Furthermore, when the active layers of the initialization transistors of all pixel circuits in the same row are connected together, when one of them receives the initialization signal, all pixel circuits in the row receive the initialization signal, further reducing the number of signal lines.

[0058] Alternatively, the first direction provided in the embodiment of the present invention may also be the extending direction of the pixel circuit column. Figure 7As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the first pixel circuit 11 and the second pixel circuit 12 are arranged along the first direction X, and the first connecting line 30 extends from the active layer Mx10 of the first initialization transistor along the first direction X to the active layer Mx20 of the second initialization transistor. The pixel circuit provided by the embodiment of the present invention can be arranged in an array of multiple rows and multiple columns, wherein the first direction X can be the extension direction of the pixel circuit column (that is, the arrangement direction of multiple pixel circuit rows), and then when one of the first pixel circuit 11 and the second pixel circuit 12 receives the initialization signal, the other pixel circuit also receives the initialization signal, thereby reducing the number of signal lines. Furthermore, when the active layers of the initialization transistors of all pixel circuits in the same column are connected together, when one of them receives the initialization signal, all pixel circuits in the column receive the initialization signal, further reducing the number of signal lines.

[0059] Alternatively, the first direction provided in the embodiment of the present invention may also be an oblique direction. Figure 8 As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the first pixel circuit 11 and the second pixel circuit 12 are arranged along the first direction X, and the first connecting line 30 extends from the active layer Mx10 of the first initialization transistor along the first direction X to the active layer Mx20 of the second initialization transistor. The pixel circuit provided by the embodiment of the present invention can be arranged in an array of multiple rows and multiple columns, wherein the first direction X can be an oblique direction intersecting with the row direction or the column direction and having an angle less than 90 degrees, and then when one of the first pixel circuit 11 and the second pixel circuit 12 receives an initialization signal, the other pixel circuit also receives the initialization signal, thereby reducing the number of signal lines. Further, when the active layers of the initialization transistors of all pixel circuits in the first direction X are connected together, when one of them receives an initialization signal, all the connected pixel circuits receive the initialization signal, further reducing the number of signal lines.

[0060] like Fig. 9 , which is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, wherein the display panel includes a first signal line 41, the first signal line 41 extends along the first direction X, and the first signal line 41 provides a control signal or an input signal for the pixel circuit 10; wherein the first signal line 41 does not overlap with the first connecting line 30. Thus, parasitic capacitance between the first signal line 41 and the first connecting line 30 can be avoided, ensuring high signal transmission stability between the first signal line 41 and the first connecting line 30.

[0061] It should be noted that the first signal line provided in the embodiment of the present invention can transmit a control signal generated by a driving circuit of the display panel, such as Figure 2 and 3 The pixel circuit 10 is connected to a first control signal K1, a second control signal K2, an initialization control signal Kx, a light emitting control signal EM, etc., or the first signal line can transmit an input signal, such as Figure 2 and 3 The pixel circuit 10 is shown as being connected to a power signal, an initialization signal Vref, a data signal Vdata, and the like.

[0062] In one embodiment of the present invention, the display panel provided by the present invention can not only connect the active layers of the initialization transistors of the pixel circuits in the same direction, but also connect the active layers of the initialization transistors of the pixel circuits in different directions. Fig.10 As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the first pixel circuit 11 and the second pixel circuit 12 provided by the embodiment of the present invention are arranged along the first direction X, and the first connection line 30 extends from the active layer Mx10 of the first initialization transistor to the active layer Mx20 of the second initialization transistor along the first direction X. And, the pixel circuit also includes a third pixel circuit 13, and the third pixel circuit 13 includes a third initialization transistor, and the first pixel circuit 11 and the third pixel circuit 13 are arranged along the second direction Y, and the first direction X intersects with the second direction Y; wherein the active layer Mx10 of the first initialization transistor is connected to the active layer Mx30 of the third initialization transistor through a second connection line 32 extending along the second direction Y, and at least a part of the second connection line 32 is located in the same layer as the active layer of the initialization transistor.

[0063] Optionally, the pixel circuits provided in the embodiment of the present invention may be arranged in a multi-row*multi-column array, wherein the first direction X may be the extension direction of the pixel circuit row (i.e., the arrangement direction of the plurality of pixel circuit columns), and the second direction Y may be the extension direction of the pixel circuit column, and then when one of the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 receives an initialization signal, the other two pixel circuits also receive the initialization signal, thereby reducing the number of signal lines set. Furthermore, when the active layers of the initialization transistors of all pixel circuits are connected together, when one of them receives an initialization signal, all pixel circuits receive the initialization signal, so as to transmit the initialization signal to the pixel circuits of the entire display panel, further reducing the number of signal lines set.

[0064] like Fig.11As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the display panel provided by the embodiment of the present invention includes an integrated chip IC, the integrated chip IC is located at a side frame of the display area AA of the display panel arranged along the second direction Y, and the integrated chip IC provides the initialization signal for the pixel circuit 10; wherein the width of the second connection line 32 is greater than the width of the first connection line 30. Since the extension direction of the second connection line 32 is the same as the second direction Y, the second connection line 32 is a line including a near IC end and a far IC end. Further, the embodiment of the present invention makes the width of the second connection line 32 greater than the width of the first connection line 30, which can ensure that the impedance of the second connection line 32 is small, so as to reduce the voltage drop on the second connection line 32 and ensure that the consistency of the signal transmitted on the second connection line 32 is high. At the same time, by narrowing the line width of the first connection line 30, the area occupied by the line can be reduced, and the resolution of the display panel can be ensured to be high.

[0065] like Fig.12 As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the display panel provided by the embodiment of the present invention includes a second signal line 42, the second signal line 42 extends along the second direction Y, and the second signal line 42 provides a control signal or an input signal for the pixel circuit 10; wherein the second connecting line 32 and the second signal line 42 do not overlap. Furthermore, it is possible to avoid the generation of parasitic capacitance between the second signal line 42 and the second connecting line 32, and ensure that the signal transmission stability of the second signal line 42 and the second connecting line 32 is high. The signals transmitted by the first signal line and the second signal line provided by the embodiment of the present invention can be specifically selected according to the actual application, and the present invention does not make any specific restrictions on this.

[0066] like Fig.13As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the first pixel circuit 11 and the second pixel circuit 12 provided by the embodiment of the present invention are arranged along the first direction X, at least a part of the area of ​​the first connection line 30 is a curve or a fold line, and the first connection line 30 includes a first sub-connection line segment 301, and the first sub-connection line 301 extends along the first direction X; wherein the display panel includes a signal line 43 that provides a control signal or an input signal to the pixel circuit 10 and extends along the first direction X, and there is no overlap between the first sub-connection line 301 and the signal line 43. In the display panel provided by the embodiment of the present invention, the first connection line 30 can be set to a fold line or a curve shape, so as to optimize the overlapping area between the first connection line 30 and the signal line 43 to be smaller, such as making the first sub-connection line 301 and the signal line 43 extend in the same direction, and overlapping another line segment with the signal line 43 in a cross manner, so as to ensure that the overlapping area between the first connection line 30 and the signal line 43 is small, and to ensure that the parasitic capacitance generated between the two is small.

[0067] like Fig.14 , which is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the first pixel circuit 11 and the second pixel circuit 12 provided by the embodiment of the present invention are arranged along a first direction X, and the display panel further comprises an initialization signal line 44 extending along the first direction X, for providing the initialization signal to the initialization transistor; wherein the initialization signal line 44 at least partially overlaps with the first connection line 30. The initialization signal line 44 and the first connection line 30 provided by the embodiment of the present invention are both used to transmit the initialization signal, and overlapping the two is equivalent to connecting a line transmitting the same signal in parallel to the initialization signal line, which can save the panel space, and can also reduce the voltage drop on the initialization signal line 44, thereby ensuring the high stability of the transmission signal.

[0068] Or Fig.15As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the first pixel circuit 11 and the second pixel circuit 12 provided by the embodiment of the present invention are arranged along the first direction X, and the first connecting line 30 extends along the first direction X; wherein the display panel further includes an initialization signal line 44 extending along the second direction Y, which is used to provide an initialization signal for the initialization transistor, and the first direction X and the second direction Y intersect. The pixel circuit provided by the embodiment of the present invention can be arranged in an array of multiple rows and multiple columns, wherein the first direction X can be the extension direction of the pixel circuit row (that is, the arrangement direction of multiple pixel circuit columns), and the second direction Y can be the extension direction of the pixel circuit column. Among them, the active layer of the initialization transistor in the pixel circuit 10 in the first direction X provided by the embodiment of the present invention is connected through the first connecting line 30, and the initialization transistor in the pixel circuit 10 in the second direction Y is connected to the initialization signal line 44, and then the active layers of all the initialization transistors are formed into a connectivity grid through the first connecting line 30 and the initialization signal line 44. When the initialization signal line 44 provides the initialization signal, the initialization signal is transmitted in both the first direction X and the second direction Y, thereby improving the consistency of receiving the initialization signal at various locations of the display panel.

[0069] In one embodiment of the present invention, Figure 3 As shown, the preset node Q provided by the present invention is the gate of the driving transistor; wherein the driving transistor T0 is a PMOS transistor, and there is no overlap between the first connecting line 30 and the active layer of the silicon transistor SiTFT in the pixel circuit 10; specifically, the silicon transistor SiTFT is generally a PMOS transistor, and when the driving transistor T0 is a PMOS transistor, the initialization signal is a low-level signal and is initialized. At this time, a low-level signal is transmitted on the first connecting line 30. If it overlaps with the active layer of the PMOS silicon transistor SiTFT, it will cause the PMOS silicon transistor SiTFT, which was originally in the cut-off state, to be turned on, affecting the normal operation of the circuit.

[0070] Alternatively, the driving transistor T0 is an NMOS transistor, and there is no overlap between the first connecting line 30 and the active layer of the oxide semiconductor transistor IGZO in the pixel circuit 10; specifically, the oxide semiconductor transistor IGZO is generally an NMOS transistor. When the driving transistor T0 is an NMOS transistor, the initialization signal is a high-level signal and it is initialized. At this time, a high-level signal is transmitted on the first connecting line 30. If it overlaps with the active layer of the NMOS oxide semiconductor transistor IGZO, it will cause the NMOS oxide semiconductor transistor IGZO, which was originally in the cut-off state, to be turned on, affecting the normal operation of the circuit.

[0071] In one embodiment of the present invention, Figure 4 As shown, the preset node Q provided in the embodiment of the present invention is the anode of the light emitting element 20; the first connecting line 30 does not overlap with the active layer of the silicon transistor SiTFT in the pixel circuit 10. Specifically, the initialization signal for the anode of the light emitting element 20 is a low-level signal. At this time, the low-level signal transmitted on the first connecting line 30, if it overlaps with the active layer of the PMOS-type silicon transistor SiTFT, will cause the PMOS-type silicon transistor SiTFT, which is originally in the off state, to be turned on, affecting the normal operation of the circuit.

[0072] like Fig.16 As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, in the active layer of the initialization transistor provided by the embodiment of the present invention, its connection position is fixed. The portion 311 where the active layer Mx10 of the first initialization transistor and the active layer Mx20 of the second initialization transistor are connected to the first connection line 30 extends along a third direction S, and the remaining portion 312 of the first connection line 30 extends along a fourth direction Z, and the third direction S intersects with the fourth direction Z. Furthermore, it can avoid the situation where the first connection line 30 covers the active layer when the first connection line 30 and the active layer extend in the same direction, avoid the generation of additional parasitic capacitance, and facilitate the connection between the active layer and the first connection line 30.

[0073] like Fig.17 As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the pixel circuit 10 includes a pixel circuit group 101 repeatedly arranged along a fifth direction H, and the pixel circuit group 101 includes the first pixel circuit 11 and the second pixel circuit 12 arranged adjacent to each other; along the fifth direction H, the spacing d1 between the active layers of the initialization transistors between two adjacent pixel circuit groups 101 is greater than the spacing d2 between the active layers of the initialization transistors in the first pixel circuit 11 and the second pixel circuit 12 in the pixel circuit group 101; wherein the active layers of the initialization transistors of the pixel circuits of two adjacent pixel circuit groups 101 are not connected through the first connecting line 30.

[0074] like Fig.18As shown, it is a structural schematic diagram of another display panel provided in an embodiment of the present invention, wherein the display panel provided in an embodiment of the present invention includes a first voltage signal line and a data signal line, the first voltage signal line is used to provide a first voltage signal PVDD for the pixel circuit 10, and the data signal line is used to provide a data signal Vdata for the pixel circuit; wherein the first connecting line 30 extends in the same direction as the first voltage signal line and the data signal line, and there is no overlap between the first connecting line 30 and the first voltage signal line and the data signal line.

[0075] It can be understood that the first connection line provided in the embodiment of the present invention has no overlapping arrangement with the first voltage signal line and the data signal line, thereby avoiding the formation of parasitic capacitance between the first connection line and the first voltage signal line and the data signal line, thereby ensuring the stability of signal transmission of each line.

[0076] Alternatively, in one embodiment of the present invention, the overlapping area S1 between the first connection line and the first voltage signal line provided by the present invention is greater than the overlapping area S2 between the first connection line and the data signal line, and S2 ≥ 0. The signal PVDD transmitted by the first voltage signal line is a fixed potential signal and is relatively stable, while the signal Vdata transmitted by the data signal line is variable. The parasitic capacitance generated by the overlap between the first connection line and the data signal line will cause interference, affect the stability of the signal Vdata transmitted by the data signal line and determining the magnitude of the driving current, and therefore the overlapping area between the first connection line and the first voltage signal line is designed to be greater than the overlapping area between the first connection line and the data signal line.

[0077] like Fig.19 , which is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, wherein the first connecting line 30 provided by the embodiment of the present invention includes a first sub-segment 313 and a second sub-segment 314, wherein the first sub-segment 313 is directly connected to the active layer Mx10 of the first initialization transistor, and the first sub-segment 313 also includes a portion connected to the active layer Mx20 of the second initialization transistor, and the second sub-segment 314 is located on the side of the first sub-segment 313 away from the active layer Mx10 of the first initialization transistor; wherein the width of the second sub-segment 314 is greater than the width of the first sub-segment 313. Furthermore, by setting the width of the second sub-segment 314 to be greater than the width of the first sub-segment 313, the impedance of the first connecting line 30 can be reduced, and the area of ​​the pixel circuit 10 can be avoided to be increased additionally.

[0078] like Fig. 20As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the pixel circuit provided by the embodiment of the present invention further includes a first conductive layer 50, and the first conductive layer 50 is located on the side of the active layer of the silicon transistor SiTFT facing the substrate 100 of the display panel; wherein the first connecting line 30 is connected to the first conductive layer 50. In the display panel provided by the embodiment of the present invention, the first conductive layer 50 is arranged below the active layer of the silicon transistor SiTFT, and a fixed signal can be applied to the first conductive layer 50, which is beneficial to improve the stability of the silicon transistor SiTFT. Therefore, the embodiment of the present invention connects the first connecting line 30 with the first conductive layer 50 to transmit the initialization signal of the fixed potential to the first conductive layer 50, avoiding the separate arrangement of the wiring for transmitting the signal to the first conductive layer 50; in particular, when the wiring for transmitting the signal is a metal wiring, it will affect the transmittance of the display panel.

[0079] like Fig.21 As shown, it is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, wherein the display panel provided by an embodiment of the present invention includes a first display area AA1 and a second display area AA2, and the second display area AA2 is correspondingly provided with an imaging element or a light-sensitive fingerprint recognition element; wherein the first pixel circuit 11 and the second pixel circuit 12 are located in the second display area AA2. The display panel provided by an embodiment of the present invention includes an under-screen camera area or an under-screen fingerprint recognition area. Since this area is required to have a large transmittance, it is necessary to reduce some wiring. For this, a transparent first connecting line can be provided to replace the existing signal line for transmitting the initialization signal to increase the transmittance of this area.

[0080] like Fig.21 As shown, the first display area AA1 includes an initialization signal line 44 for providing an initialization signal to the initialization transistor, the initialization signal line 44 is connected to the active layer Mx10 of the first initialization transistor, and the active layer Mx10 of the first initialization transistor is connected to the active layer Mx20 of the second initialization transistor through the first connection line 30.

[0081] Correspondingly, an embodiment of the present invention further provides a display device, comprising the display panel provided by any one of the above embodiments.

[0082] like Fig. 22 , which is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, wherein the display device 1000 provided in an embodiment of the present invention may be a mobile terminal device.

[0083] In other embodiments of the present invention, the display device provided by the present invention may also be an electronic display device such as a mobile phone, a computer, a vehicle-mounted terminal, etc., and the present invention does not make any specific limitation on this.

[0084] An embodiment of the present invention provides a display panel and a display device, wherein an active layer of a first initialization transistor of a first pixel circuit is connected to an active layer of a second initialization transistor of a second pixel circuit via a first connecting line, so as to connect the active layers of initialization transistors in different regions together, and then after one of the initialization transistors is connected to an initialization signal, the initialization signal can be transmitted to another initialization transistor via the first connecting line, thereby avoiding the problem of large differences in initialization signals connected to initialization transistors in different regions caused by transmitting the initialization signal only through a signal line with a voltage drop, thereby ensuring high uniformity of initialization signals connected to initialization transistors in different regions of the display panel.

[0085] At the same time, by connecting the active layer of the first initialization transistor and the active layer of the second initialization transistor through the first connecting line, the number of signal lines for transmitting the initialization signal can be appropriately reduced, which is conducive to reducing the line density of the display panel, thereby achieving the purpose of improving the resolution. In addition, when the signal line for transmitting the initialization signal is broken, the initialization signal can also be transmitted to the connected initialization transistor through the first connecting line, thereby improving the flexibility and reliability of the line.

[0086] Moreover, at least a partial region of the first connecting line provided in the embodiment of the present invention is located in the same layer as the active layer of the oxide semiconductor transistor. By adjusting the conductivity of the first connecting line, the first connecting line can be used as a wiring to connect the two active layers, thereby eliminating the need to separately prepare a conductive film for making the first connecting line, thereby reducing the process flow of preparing the display panel and avoiding increasing the wiring layout burden of other conductive film layers.

[0087] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: Pixel circuit and light emitting element; The pixel circuit includes a driving transistor and an initialization transistor, wherein a first electrode of the initialization transistor is connected to an initialization signal, and a second electrode of the initialization transistor is connected to a preset node, and the preset node is the gate of the driving transistor or the anode of the light-emitting element; The pixel circuit includes an oxide semiconductor transistor and a silicon transistor, wherein an active layer of the oxide semiconductor transistor includes an oxide semiconductor, and an active layer of the silicon transistor includes silicon; The pixel circuit includes a first pixel circuit and a second pixel circuit, the first pixel circuit includes a first initialization transistor, the second pixel circuit includes a second initialization transistor, an active layer of the first initialization transistor is connected to an active layer of the second initialization transistor via a first connection line, and at least a portion of the first connection line is located in the same layer as the active layer of the oxide semiconductor transistor; The pixel circuit includes a pixel circuit group repeatedly arranged along a fifth direction, and the pixel circuit group includes the first pixel circuit and the second pixel circuit that are adjacently arranged; A spacing between active layers of initialization transistors between two adjacent pixel circuit groups is greater than a spacing between active layers of initialization transistors in the first pixel circuit and the second pixel circuit in the pixel circuit group.

2. The display panel according to claim 1, characterized in that: The first connection line and the active layer of the initialization transistor both include oxide semiconductor.

3. The display panel according to claim 2, characterized in that: The conductivity of the first connection line is greater than the conductivity of the channel region of the active layer of the initialization transistor.

4. The display panel according to claim 1, characterized in that: The active layers of the initialization transistors of all pixel circuits in the same row are connected.

5. The display panel according to claim 1, characterized in that: The first pixel circuit and the second pixel circuit are arranged along a first direction, and the first connection line extends from the active layer of the first initialization transistor to the active layer of the second initialization transistor along the first direction.

6. The display panel according to claim 5, characterized in that: The display panel includes a first signal line, the first signal line extends along the first direction, and the first signal line provides a control signal or an input signal for the pixel circuit; wherein, There is no overlap between the first signal line and the first connection line.

7. The display panel according to claim 5, characterized in that: The pixel circuit further includes a third pixel circuit, the third pixel circuit includes a third initialization transistor, the first pixel circuit and the third pixel circuit are arranged along a second direction, and the first direction intersects with the second direction; wherein, The active layer of the first initialization transistor is connected to the active layer of the third initialization transistor through a second connection line extending along the second direction, and at least a portion of the second connection line is located in the same layer as the active layer of the initialization transistor.

8. The display panel according to claim 7, characterized in that: The display panel includes an integrated chip, the integrated chip is located on a side frame of the display area of ​​the display panel arranged along the second direction, and the integrated chip provides the initialization signal for the pixel circuit; wherein, The width of the second connection line is greater than the width of the first connection line.

9. The display panel according to claim 7, characterized in that: The display panel includes a second signal line, the second signal line extends along the second direction, and the second signal line provides a control signal or an input signal for the pixel circuit; wherein, The second connecting line and the second signal line do not overlap each other.

10. The display panel according to claim 1, characterized in that: The first pixel circuit and the second pixel circuit are arranged along a first direction, at least a portion of the first connection line is a curve or a fold line, the first connection line includes a first sub-connection line, and the first sub-connection line segment extends along the first direction; wherein, The display panel includes a signal line that provides a control signal or an input signal to the pixel circuit and extends along the first direction, and there is no overlap between the first sub-connection line and the signal line.

11. The display panel according to claim 1, characterized in that: The first pixel circuit and the second pixel circuit are arranged along a first direction, and the display panel further comprises an initialization signal line extending along the first direction, for providing the initialization signal to the initialization transistor; wherein, The initialization signal line at least partially overlaps with the first connection line.

12. The display panel according to claim 1, characterized in that: The first pixel circuit and the second pixel circuit are arranged along a first direction, and the first connecting line extends along the first direction; wherein, The display panel further includes an initialization signal line extending along a second direction for providing an initialization signal to the initialization transistor, and the first direction and the second direction intersect.

13. The display panel according to claim 1, characterized in that: The preset node is the gate of the driving transistor; The driving transistor is a PMOS transistor, and there is no overlap between the first connecting line and the active layer of the silicon transistor in the pixel circuit, or the driving transistor is an NMOS transistor, and there is no overlap between the first connecting line and the active layer of the oxide semiconductor transistor in the pixel circuit.

14. The display panel according to claim 1, characterized in that: The preset node is the anode of the light emitting element; The first connecting line has no overlap with an active layer of a silicon transistor in the pixel circuit.

15. The display panel according to claim 1, characterized in that: The display panel includes a first voltage signal line and a data signal line, wherein the first voltage signal line is used to provide a first voltage signal to the pixel circuit, and the data signal line is used to provide a data signal to the pixel circuit; wherein The first connecting line extends in the same direction as the first voltage signal line and the data signal line, and there is no overlap between the first connecting line and the first voltage signal line and the data signal line, or an overlapping area S1 between the first connecting line and the first voltage signal line is greater than an overlapping area S2 between the first connecting line and the data signal line, and S2≥0.

16. The display panel according to claim 1, characterized in that: The first connecting line includes a first sub-line segment and a second sub-line segment, the first sub-line segment is directly connected to the active layer of the first initialization transistor, and the second sub-line segment is located on a side of the first sub-line segment away from the active layer of the first initialization transistor; wherein, The width of the second sub-line segment is greater than the width of the first sub-line segment.

17. The display panel according to claim 1, characterized in that: The pixel circuit further includes a first conductive layer, which is located on a side of the active layer of the silicon transistor facing the substrate of the display panel; wherein, The first connecting line and the first conductive layer are connected to each other.

18. The display panel according to claim 1, characterized in that: The display panel includes a first display area and a second display area, and the second display area is correspondingly provided with an imaging element or a light-sensitive fingerprint recognition element; wherein, The first pixel circuit and the second pixel circuit are located in the second display area.

19. The display panel according to claim 18, characterized in that: The first display area includes an initialization signal line for providing an initialization signal to the initialization transistor, the initialization signal line is connected to an active layer of the first initialization transistor, and the active layer of the first initialization transistor is connected to an active layer of the second initialization transistor through the first connection line.

20. The display panel according to claim 1, characterized in that: The active layers of the initialization transistors of the pixel circuits of two adjacent pixel circuit groups are not connected through the first connection line.

21. The display panel according to claim 1, characterized in that: The preset node of the first pixel circuit and the preset node of the second pixel circuit are gates of corresponding driving transistors; and / or, the preset node of the first pixel circuit and the preset node of the second pixel circuit are anodes of corresponding light-emitting elements.

22. A display device, characterized in that: A display panel comprising any one of claims 1-21.

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