Back contact solar cell, preparation method thereof and cell module

Abstract

The invention relates to the technical field of solar cells, and provides a back contact solar cell and a preparation method thereof, and a cell assembly, the back contact solar cell enables the edge of the front surface of a silicon wafer to form a mask layer with a certain width through the process of debugging the mask layer on the back surface, and the thickness of the mask layer is gradually reduced from the edge of the silicon wafer to the inside. According to the special winding plating design, 70%-90% of the area in the middle of the front face of the silicon wafer can form a large pyramid suede, and 10%-30% of the area of the edge of the silicon wafer can form a small pyramid suede, so that the edge of the large-size silicon wafer is the small pyramid suede, the edge is kept in a thick silicon wafer state, and the pyramid is subjected to smooth treatment; and the fragment rate in the manufacturing process can be reduced, and the production yield can be improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and in particular relates to a back-contact solar cell and a preparation method thereof, and a cell assembly. Background Art

[0002] When preparing existing back-contact solar cells, a large pyramid velvet surface is formed on the edge of the silicon wafer, and the sharp channels on its surface are prone to form crack initiation sites, which will cause a certain probability of fragmentation. Especially for large-sized silicon wafers, the use of existing back-contact technology is likely to cause the silicon wafer to deform more, thereby increasing the breakage rate during the production process and reducing the yield.

[0003] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0004] The purpose of the present invention is to provide a back-contact solar cell and a preparation method thereof, and a cell assembly, so as to solve the technical problem that large-size silicon wafers are easily broken and result in poor yield.

[0005] In order to achieve the above objectives, in a first aspect, the present invention provides a back-contact solar cell, comprising: A silicon wafer having a front side and a back side; the front side of the silicon wafer includes a plating-around area and a texturing area, the plating-around area is located at the edge of the silicon wafer, and the texturing area is surrounded by the plating-around area; the thickness of the plating-around area gradually decreases from the edge of the silicon wafer toward the texturing area, and the plating-around area is cleaned by texturing to form a first texturing surface, and the texturing area is cleaned by texturing to form a second texturing surface, and the convexity of the first texturing surface is less than that of the second texturing surface; A first semiconductor layer is arranged on the back side of the silicon wafer, the first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer sequentially formed on the back side of the silicon wafer; the first semiconductor layer is separated by a plurality of second semiconductor opening regions, the second semiconductor opening regions and the surface of the first semiconductor layer around the second semiconductor opening regions are covered with the second semiconductor layer; a first semiconductor opening region is provided between adjacent second semiconductor opening regions, the first semiconductor opening region separates the second semiconductor layer; A passivation layer and an anti-reflection layer, wherein the passivation layer and the anti-reflection layer are sequentially arranged on the front side of the silicon wafer; wherein a first surface structure is formed on the surface of the passivation layer and the anti-reflection layer covering the coating area, and a second surface structure is formed on the surface of the passivation layer and the anti-reflection layer covering the texturing area, and the protrusion amplitude of the first surface structure is smaller than the protrusion amplitude of the second surface structure.

[0006] Optionally, the first textured surface includes a plurality of first pyramid structures, and the second textured surface includes a plurality of second pyramid structures; the height of the first pyramid structure is smaller than the height of the second pyramid structure.

[0007] Optionally, the structure height of the first pyramid is 0.3 μm to 0.6 μm, and the height of the second pyramid structure is 2 μm to 3 μm.

[0008] Optionally, the ratio of the width of the plating area to the width of the texturing area is (10%~30%): (70%~90%).

[0009] Optionally, the thickness of the plating-around area gradually decreases from the edge of the silicon wafer toward the texturing area, and the inclination angle of the plating-around area on the front side of the silicon wafer is 0.018°~0.0238°.

[0010] Optionally, the first semiconductor layer includes a tunneling silicon oxide layer and an N-type doped polysilicon layer, the tunneling silicon oxide layer has a thickness of 1-2 nm, and the N-type doped polysilicon layer has a thickness of 80-140 nm.

[0011] Optionally, a width of the first semiconductor opening region is 400 μm to 600 μm, and a width of the second semiconductor opening region is 200 μm to 300 μm.

[0012] In a second aspect, the present invention provides a method for preparing a back-contact solar cell, which is used to prepare the back-contact solar cell as described in the first aspect, comprising: S1. Provide a double-sided polished silicon wafer; S2, forming a first semiconductor layer and a first mask layer on the back side of the silicon wafer, and forming a second mask layer in the plating area on the front side of the silicon wafer; the thickness of the second mask layer gradually decreases from the edge of the front side of the silicon wafer to the texturing area; S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region; S4, texturing and cleaning the front and back opening areas of the silicon wafer; The first texturing surface is formed in the plating area on the front side of the silicon wafer by texturing cleaning, and the texturing area in the middle of the silicon wafer forms a second texturing surface; during the entire texturing time, the reaction time ratio of the plating area and the texturing area of ​​the silicon wafer in the texturing liquid is 1:(3-5); S5, forming a second semiconductor layer on the back side of the silicon wafer; the second semiconductor layer is a combination of an intrinsic amorphous silicon layer and a P-type doped amorphous / microcrystalline silicon layer; S6, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer; S7, etching an opening on the back side of the silicon wafer for the second time to form a first semiconductor opening region; S8, depositing a transparent conductive film layer on the back side of the silicon wafer; S9, etching an opening on the back side of the silicon wafer for the third time to form an insulating groove; S10, forming metal electrodes at the first semiconductor opening and the second semiconductor opening on the back side of the silicon wafer respectively.

[0013] Optionally, in step S2, the first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer, the first mask layer and the second mask layer are both carbon-doped silicon nitride layers, the deposition temperature is 250°C~400°C, the mass flow rate of silane is 1000sccm~2000sccm, the mass flow rate of ammonia is 300sccm~1000sccm, the mass flow rate of nitrogen is 2000sccm~50000sccm, the mass flow rate of methane is 1000sccm~2000sccm, the pressure is 200Pa~400Pa, the power density of the power supply is 1.25kW / m2~3.75kW / m2, and the deposition time is 200s~500s.

[0014] Optionally, in step S2, the thickness of the first mask layer is 70nm~120nm; the thickness of the second mask layer decreases from 10nm~20nm to 0~5nm from the edge of the silicon wafer toward the texturing area, and the width of the second mask layer is 1cm~2cm.

[0015] Optionally, in step S4, it includes: The texturing liquid is a mixture of potassium hydroxide or sodium hydroxide, a texturing additive and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1% to 5%, and the mass percentage of the texturing additive is 0.5% to 1%. The texturing time is 10 to 60 minutes, and the texturing temperature is 70°C to 85°C.

[0016] Optionally, in step S4, it also includes: During the texturing cleaning process, the first mask layer on the back of the silicon wafer is also removed through the final cleaning solution. The solution used to remove the first mask layer is HF solution. The mass percentage of HF acid in the HF solution is 0.5%~5%, the mass percentage of hydrogen peroxide is 3%~10%, and the mass percentage of deionized water is 95%~99.5%. The processing temperature is 20℃~30℃, and the removal time is 60s~300s.

[0017] Optionally, in step S5, it includes: The second semiconductor layer is formed by plate-type CVD, the thickness of the intrinsic amorphous silicon layer is 4-8 nm, the thickness of the P-type doped amorphous / microcrystalline silicon layer is 6-12 nm, and the deposition temperature of the second semiconductor layer is 150-250° C.

[0018] Optionally, in step S6, it includes: The passivation layer is a combination of a silicon oxide layer and an aluminum oxide layer, and the aluminum oxide layer is formed by an atomic layer deposition method. The conditions of the atomic layer deposition method include: a process temperature between 150°C and 180°C, reaction gases are trimethylaluminum and ozone, and in the first stage, the flow rate of trimethylaluminum introduced is 2000sccm to 5000sccm, the reaction time is 20s to 40s, and then nitrogen is used to purge the chamber and pipelines; then the second stage is carried out, and the flow rate of ozone introduced in the second stage is 3000sccm to 6000sccm, the ozone introduction time is 15 to 30s, and then nitrogen is used to purge the chamber and pipelines; the first stage and the second stage are carried out in sequence as a cycle reaction, and a total of 30 to 80 cycle reactions are carried out.

[0019] In a third aspect, the present invention provides a battery assembly, comprising: a back-contact solar cell as described in the first aspect.

[0020] The embodiments of the present invention have at least the following beneficial effects: The present invention adopts the above technical scheme and adjusts the process of the back mask layer so that the front edge of the silicon wafer is also coated to form a mask layer of a certain width, and the thickness of the film layer gradually decreases from the edge of the silicon wafer to the inside. This special coating design can form a large pyramid velvet surface on 70% to 90% of the area in the middle of the front side of the silicon wafer and a small pyramid velvet surface on 10% to 30% of the area at the edge of the silicon wafer, thereby making the edge of the large-size silicon wafer a small pyramid velvet surface and the edge remains in a thicker silicon wafer state and the pyramid is rounded, which is beneficial to reducing the breakage rate in the manufacturing process and improving the production yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of the structure of a back-contact solar cell provided by an embodiment of the present invention; Figure 2 A flow chart of a method for preparing a back-contact solar cell provided by an embodiment of the present invention; Figure 3 A process structure diagram corresponding to step S3 in a method for preparing a back-contact solar cell provided in an embodiment of the present invention; Figure 4A process structure diagram corresponding to step S4 in a method for preparing a back-contact solar cell provided in an embodiment of the present invention; Figure 5 A process structure diagram after steps S5 to S10 in a back-contact solar cell preparation method provided by an embodiment of the present invention; Figure 6 An electron microscope image of a first pyramid structure of a back-contact solar cell provided by an embodiment of the present invention; Figure 7 An electron microscope image of the second pyramid structure of a back-contact solar cell provided in an embodiment of the present invention.

[0023] In the figure: 1-silicon wafer; 2-tunneling silicon oxide layer; 3-N-type doped polysilicon layer; 4.1-first mask layer; 4.2-second mask layer; 5-intrinsic amorphous silicon layer; 6-P-type doped amorphous / microcrystalline silicon layer; 7-passivation layer; 7.1-silicon oxide layer; 7.2-aluminum oxide layer; 8-anti-reflection layer; 9-transparent conductive film layer; 10-metal electrode. DETAILED DESCRIPTION

[0024] The technical solution of the present application will be described clearly and completely below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0025] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.

[0026] Those skilled in the art will appreciate that, unless otherwise stated, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0027] The first aspect, such as Figure 1As shown, an embodiment of the present invention provides a back-contact solar cell based on the preparation method of the above embodiment, comprising: A silicon wafer 1 having a front side and a back side; the front side of the silicon wafer 1 includes a coating zone and a texturing zone, the coating zone is located at the edge of the silicon wafer 1, and the texturing zone is surrounded by the coating zone. Optionally, the ratio of the width of the coating zone to the width of the texturing zone is (10%~30%): (70%~90%). For example: the side length of the silicon wafer 1 is 182mm, the width of the coating zone is 10mm, and the width of the texturing zone is 162mm.

[0028] The thickness of the plating-around region gradually decreases from the edge of the silicon wafer 1 toward the texturing region. Optionally, the inclination angle of the plating-around region on the front side of the silicon wafer 1 is 0.018° to 0.0238°.

[0029] The plating area is cleaned by texturing to form a first texturing surface, and the texturing area is cleaned by texturing to form a second texturing surface. The protrusion of the first texturing surface is smaller than that of the second texturing surface.

[0030] The first textured surface includes a plurality of first pyramid structures, and the second textured surface includes a plurality of second pyramid structures; the height of the first pyramid structure is less than the height of the second pyramid structure. Among them, the first pyramid structure formed on the front of the silicon wafer 1 is a large pyramid velvet structure, which is beneficial to reduce the reflection of sunlight, improve the incidence rate and utilization rate of sunlight, and improve the current density of the battery. The second pyramid structure at the edge of the silicon wafer 1 is a small pyramid velvet structure, and the edge maintains a thicker silicon wafer 1 state and the pyramid is rounded, which is beneficial to reduce the breakage rate of the silicon wafer 1 and maintain a certain reflectivity in the manufacturing process, and achieves the effect of taking into account both optics and process yield.

[0031] Optionally, the height of the first pyramid structure is 0.3 μm to 0.6 μm, and the height of the second pyramid structure is 2 μm to 3 μm.

[0032] A first semiconductor layer is arranged on the back side of the silicon wafer 1, and the first semiconductor layer includes a tunneling silicon oxide layer 2 and an N-type doped polysilicon layer 3 sequentially formed on the back side of the silicon wafer 1; the first semiconductor layer is separated by a plurality of second semiconductor opening regions, and the second semiconductor opening regions and the surface of the first semiconductor layer around the second semiconductor opening regions are covered with the second semiconductor layer; a first semiconductor opening region is provided between adjacent second semiconductor opening regions, and the first semiconductor opening region separates the second semiconductor layer. The passivation layer 7 and the anti-reflection layer 8 are sequentially arranged on the front side of the silicon wafer 1; wherein, the surfaces of the passivation layer 7 and the anti-reflection layer 8 covering the bypass plating area form a first surface structure with a smaller protrusion amplitude, and the surfaces of the passivation layer 7 and the anti-reflection layer 8 covering the texturing area form a second surface structure with a larger protrusion amplitude.

[0033] The embodiment of the present invention forms a winding plating structure with a certain width on the front side of the silicon wafer 1 and the thickness gradually decreases from the edge of the silicon wafer 1 to the inside. In the subsequent masking and texturing process, 70% to 90% of the area in the middle of the front side of the silicon wafer 1 can form a large pyramid velvet surface, while 10% to 30% of the area at the edge of the silicon wafer 1 can form a small pyramid velvet surface. The edge of the large-sized silicon wafer 1 is a small pyramid velvet surface, the edge remains in a state of a thicker silicon wafer 1, and the pyramid is rounded, which is beneficial to reducing the breakage rate in the manufacturing process and improving the production yield.

[0034] Optionally, the first semiconductor layer includes a tunneling silicon oxide layer 2 and an N-type doped polysilicon layer 3, the tunneling silicon oxide layer 2 has a thickness of 1 nm to 2 nm, and the N-type doped polysilicon layer 3 has a thickness of 80 nm to 140 nm.

[0035] Optionally, a width of the first semiconductor opening region is 400 μm to 600 μm, and a width of the second semiconductor opening region is 200 μm to 300 μm.

[0036] Optionally, the passivation layer 7 is a stacked structure of a silicon oxide layer 7.1 and an aluminum oxide layer 7.2, the silicon oxide layer 7.1 has a thickness of 1 nm to 2 nm, and the aluminum oxide layer 7.2 has a thickness of 3 nm to 4 nm.

[0037] Optionally, the anti-reflection layer 8 is a stacked structure of a silicon nitride layer and a silicon oxide layer 7.1, the thickness of the silicon nitride layer is 50nm-100nm, and the thickness of the silicon oxide layer 7.1 is 80nm-150nm.

[0038] The second aspect, such as Figure 2 As shown, an embodiment of the present invention provides a method for preparing a back-contact solar cell, which is used to prepare the back-contact solar cell in the above embodiment, and the preparation method comprises the following steps: S1. Provide a double-sided polished silicon wafer 1.

[0039] Specifically, the silicon wafer 1 has a front side and a back side, which are realized by polishing the front side and the back side of the silicon wafer 1; wherein the front side refers to the light-receiving surface of the silicon wafer 1, and the back side is the opposite back side of the light-receiving surface. In the embodiment of the present invention, the side close to the silicon wafer 1 is usually considered as the inside, and the side far from the silicon wafer 1 is considered as the outside. Optionally, the silicon wafer 1 is an N-type single crystal silicon wafer 1, for example: a Czochralski single crystal silicon wafer 1 or a cast single crystal silicon wafer 1.

[0040] S2, forming a first semiconductor layer and a first mask layer 4.1 on the back side of the silicon wafer 1, and forming a second mask layer 4.2 in the plating area on the front side of the silicon wafer 1; the thickness of the second mask layer 4.2 gradually decreases from the edge of the front side of the silicon wafer 1 to the texturing area.

[0041] Optionally, the first semiconductor layer comprises a tunneling silicon oxide layer 2 and an N-type doped polysilicon layer 3, the thickness of the tunneling silicon oxide layer 2 is 1-2 nm, and the thickness of the N-type doped polysilicon layer 3 is 80-140 nm. The tunneling silicon oxide layer 2 and the N-type doped polysilicon layer 3 are both formed by sequentially depositing and high-temperature annealing in a tubular polysilicon deposition furnace, and the deposition temperature is 400-500°C. When depositing the tunnel oxide layer, the mass flow rate of nitrous oxide is 8000~1200sccm, the pressure is 100~200pa, the power is 3~20KW, and the time is 20~100 seconds; when depositing the N-type doped polysilicon layer 3, the mass flow rate of silane is 1000~3000sccm, the mass flow rate of phosphine (2% PH3 and 98% H2) is 1000~2500sccm, the mass flow rate of hydrogen is 7000~9000sccm, the pressure is 100~300pa, the power is 5~20KW, and the time is 800~1300 seconds.

[0042] The first mask layer 4.1 and the second mask layer 4.2 are both carbon-doped silicon nitride layers, which are deposited using a plate-type PECVD device. The deposition temperature is 250~400°C, the mass flow rate of silane is 1000~2000sccm, the mass flow rate of ammonia is 300~1000sccm, the mass flow rate of nitrogen is 2000~50000sccm, the mass flow rate of methane is 1000~2000sccm, and the pressure is 200~400pa, which is 100%~200% higher than that of the existing process. The power density of the power supply is 1.25kw / m2~3.75kw / m2, which is 15%~40% higher than that of the existing process. The time is 200~500 seconds. By increasing the gas pressure of the deposited film layer and matching the appropriate power, the back side of the silicon wafer 1 can be uniformly coated while the front edge can be fully coated.

[0043] Optionally, the thickness of the first mask layer 4.1 is 70-120 nm, the thickness H of the second mask layer 4.2 gradually decreases from the edge of the silicon wafer 1 to the inside, and the thickness decreases from 10-20 nm to 0-5 nm, and the width W4 of the front-side carbon-doped silicon nitride film layer is 1-2 cm. Figure 1 As shown, the corresponding silicon wafer 1 has a size of 18.2 cm×18.2 cm or 21 cm×21 cm or larger.

[0044] In this embodiment, the first mask layer 4.1 and the second mask layer 4.2 are both prepared by carbon-doping silicon nitride, which is beneficial to improve the density of the film layer under low-temperature deposition conditions, improve the etching effect of strong alkali, and avoid damage to the underlying polycrystalline layer during the texturing process.

[0045] S3, etching an opening on the back side of the silicon wafer 1 for the first time to form a second semiconductor opening region.

[0046] Alternatively, if Figure 3 As shown, the first etching opening can be performed by laser or mask etching, as long as the second semiconductor opening area can be formed; wherein the laser can be an ultraviolet or green laser with a pulse width less than 10ns, and the width of the formed second semiconductor opening area is 400~600um.

[0047] S4, texturing and cleaning the front and back opening areas of the silicon wafer 1.

[0048] Alternatively, if Figure 4 As shown, the opening areas on the front and back sides of the silicon wafer 1 are textured and cleaned, and the texture liquid is a mixture of potassium hydroxide or sodium hydroxide, a texture additive and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1%~5%, and the mass percentage of the texture additive is 0.5%~1%. The texture time is 10~60 minutes, and the texture temperature is 70℃~85℃.

[0049] The edge of the silicon wafer 1 is blocked by the mask layer, so that in the early stage of the reaction, the middle and edge of the silicon wafer 1 have a relatively different reaction speed in the texturing solution; as the reaction proceeds, the mask layer around the edge is etched and consumed in the texturing solution, and the texturing reaction starts at the edge of the silicon wafer 1. Therefore, after the reaction is completed, a first texturing surface with a smaller size is formed in the coating area on the front side of the silicon wafer 1, and a second texturing surface with a larger size is formed in the texturing area in the middle of the silicon wafer 1. The height of the second texturing surface (the second pyramid structure) is 2~3um (the electron microscope image of the middle pyramid is as shown in FIG. Figure 7 As shown in the figure), the height of the first textured surface (first pyramid structure) is 0.3~0.6um (the electron microscope image of the first textured surface is as shown in the figure). Figure 6 As shown); during the entire texturing time, the reaction time ratio of the plating area and the texturing area of ​​the silicon wafer 1 in the texturing liquid is 1: (3~5).

[0050] During the texturing cleaning process, the first mask layer 4.1 on the back of the silicon wafer 1 is also removed by the final cleaning solution. The solution used to remove the first mask layer 4.1 is an acid solution such as HF, with a mass percentage of 0.5%~5% for HF acid and a mass percentage of 3%~10% for hydrogen peroxide; a mass percentage of 95%~99.5% for deionized water, a processing temperature of 20℃~30℃, and a removal time of 60~300s.

[0051] In this embodiment, by adding a certain amount of hydrogen peroxide into the cleaning tank, it is beneficial to make the pyramid velvet surface smoother, reduce the formation of sharp concave corners on the edges, further reduce the probability of fragmentation, and improve the yield.

[0052] S5 , forming a second semiconductor layer on the back side of the silicon wafer 1 ; the second semiconductor layer is a combination of an intrinsic amorphous silicon layer 5 and a P-type doped amorphous / microcrystalline silicon layer 6 .

[0053] Alternatively, if Figure 5 As shown, the second semiconductor layer is formed by plate CVD, the thickness of the intrinsic amorphous silicon layer 5 is 4-8 nm, the thickness of the P-type doped amorphous silicon layer or the P-type microcrystalline silicon layer is 6-12 nm, and the deposition temperature of the second semiconductor layer is 150-250°C.

[0054] S6. Form a passivation layer 7 and an anti-reflection layer 8 on the front side of the silicon wafer 1.

[0055] Optionally, continue to Figure 5 , the passivation layer 7 is a combination of a silicon oxide layer 7.1 and an aluminum oxide layer 7.2, the thickness of the silicon oxide layer 7.1 is 1-2 nm, and the thickness of the aluminum oxide layer 7.2 is 3-4 nm. The aluminum oxide is formed by an atomic layer deposition method, and the conditions of the atomic layer deposition method include: the process temperature is between 150 180°C, the reaction gases are trimethylaluminum and ozone, the flow rate of trimethylaluminum in the first stage is 2000sccm-5000sccm, the reaction time is 20-40s, and then the chamber and pipeline are purged with nitrogen; then the second stage is carried out, the flow rate of ozone in the second stage is 3000sccm-6000sccm, the ozone time is 15-30s, and then the chamber and pipeline are purged with nitrogen; the first stage and the second stage are carried out in sequence as a cycle reaction, and a total of 30-80 cycle reactions are carried out.

[0056] The anti-reflection layer 8 may be one or a combination of silicon nitride and silicon oxide layer 7.1, preferably a combination of silicon nitride and silicon oxide. The thickness of the silicon nitride layer is 50-100 nm, and the thickness of the silicon oxide layer 7.1 is 80-150 nm.

[0057] S7, etching an opening on the back side of the silicon wafer 1 for the second time to form a first semiconductor opening region.

[0058] Optionally, the second etching opening is performed by laser, the laser may be ultraviolet or green laser, the pulse width is less than 10ns, and the width of the formed first semiconductor opening region is 200-300um.

[0059] S8. Depositing a transparent conductive film layer 9 on the back side of the silicon wafer 1.

[0060] Optionally, a transparent conductive film is deposited on the back of the silicon wafer 1 by physical vapor deposition (PVD) or activated plasma deposition (RPD), the thickness of the transparent conductive film is 40-80 nm, and the material of the transparent conductive film can be an indium oxide-based film doped with tin / tungsten / titanium / zinc or an aluminum / boron-doped zinc oxide-based film.

[0061] S9, etching an opening on the back side of the silicon wafer 1 for the third time to form an insulating groove.

[0062] Optionally, an opening is etched on the back of the silicon wafer 1 by mask etching or laser to form an insulating groove W3 between the first semiconductor and the second semiconductor. The width of the insulating groove W3 is 20-100 μm. After etching, the resistance between the first semiconductor and the second semiconductor is greater than 1 KΩ.

[0063] S10 , forming metal electrodes 10 at the first semiconductor opening and the second semiconductor opening on the back side of the silicon wafer 1 , respectively.

[0064] Optionally, the metal electrode 10 is formed on the surface of the first semiconductor opening region W1 and the second semiconductor opening region W2 on the back side of the silicon wafer 1 by using screen printing technology.

[0065] In a third aspect, an embodiment of the present invention further provides a battery assembly, comprising: a back-contact solar cell as described in the above embodiment.

[0066] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0067] Example 1 The present embodiment provides a back-contact solar cell, comprising: a silicon wafer 1 having a front side and a back side; the front side of the silicon wafer 1 comprises a wrap-around area and a texturing area, the wrap-around area is located at the edge of the silicon wafer 1, the texturing area is surrounded by the wrap-around area, the ratio of the width of the wrap-around area to the width of the texturing area is 12%:88%, the thickness of the wrap-around area gradually decreases from the edge of the silicon wafer 1 toward the texturing area, and the inclination angle of the wrap-around area on the front side of the silicon wafer 1 is 0.021°.

[0068] The first textured surface is formed after the plating area is textured and cleaned, and the second textured surface is formed after the textured area is textured and cleaned, and the convexity of the first textured surface is less than that of the second textured surface. Specifically, the first textured surface includes a plurality of first pyramid structures, and the second textured surface includes a plurality of second pyramid structures; the height of the first pyramid structure is less than the height of the second pyramid structure.

[0069] The height of the first pyramid structure is 0.5 μm, and the height of the second pyramid structure is 2.5 μm.

[0070] A first semiconductor layer is arranged on the back side of the silicon wafer 1, and the first semiconductor layer includes a tunneling silicon oxide layer 2 and an N-type doped polysilicon layer 3 sequentially formed on the back side of the silicon wafer 1; the first semiconductor layer is separated by a plurality of second semiconductor opening regions, and the second semiconductor opening regions and the surface of the first semiconductor layer around the second semiconductor opening regions are covered with the second semiconductor layer; a first semiconductor opening region is provided between adjacent second semiconductor opening regions, and the first semiconductor opening region separates the second semiconductor layer. The passivation layer 7 and the anti-reflection layer 8 are sequentially arranged on the front side of the silicon wafer 1; wherein, the surfaces of the passivation layer 7 and the anti-reflection layer 8 covering the bypass plating area form a first surface structure with a smaller protrusion amplitude, and the surfaces of the passivation layer 7 and the anti-reflection layer 8 covering the texturing area form a second surface structure with a larger protrusion amplitude.

[0071] Embodiment 1 of the present invention further provides a method for preparing a back-contact solar cell, which is used to prepare the back-contact solar cell shown in the embodiment, and the preparation method comprises: S1, providing a double-sided polished silicon wafer 1; S2, forming a first semiconductor layer and a first mask layer 4.1 on the back side of the silicon wafer 1, and forming a second mask layer 4.2 in the bypass plating area on the front side of the silicon wafer 1; the thickness of the second mask layer 4.2 gradually decreases from the edge of the front side of the silicon wafer 1 to the texturing area, and the thickness decreases from 15nm to 2nm, and the ratio of the width of the bypass plating area to the width of the texturing area is 12%:88%; S3, etching an opening on the back side of the silicon wafer 1 for the first time to form a second semiconductor opening region; S4, texturing and cleaning the front and back opening areas of the silicon wafer 1; Through texturing cleaning, a smaller velvet effect is formed in the plating area on the front side of the silicon wafer 1, and a larger velvet effect is formed in the texturing area in the middle of the silicon wafer 1; during the entire texturing time, the reaction time ratio of the plating area and the texturing area of ​​the silicon wafer 1 in the texturing liquid is 1:4.5; S5, forming a second semiconductor layer on the back side of the silicon wafer 1; the second semiconductor layer is a combination of an intrinsic amorphous silicon layer 5 and a P-type doped amorphous / microcrystalline silicon layer 6; S6, forming a passivation layer 7 and an anti-reflection layer 8 on the front side of the silicon wafer 1; S7, etching an opening on the back side of the silicon wafer 1 for the second time to form a first semiconductor opening region; S8, depositing a transparent conductive film layer 9 on the back side of the silicon wafer 1; S9, etching an opening on the back side of the silicon wafer 1 for the third time to form an insulating groove; S10 , forming metal electrodes 10 at the first semiconductor opening and the second semiconductor opening on the back side of the silicon wafer 1 , respectively.

[0072] Example 2 Referring to the back contact solar cell of Example 1, the difference is that the ratio of the width of the coating zone to the width of the texturing zone is 25%:75%.

[0073] Example 3 Referring to the back contact solar cell of Example 1, the difference is that the thickness of the plating-around area gradually decreases from the edge of the silicon wafer 1 toward the texturing area, and the inclination angle of the plating-around area on the front side of the silicon wafer 1 is 0.018°.

[0074] Example 4 Referring to the back contact solar cell of Example 1, the difference is that the height of the first pyramid structure is 0.6 μm, and the height of the second pyramid structure is 2 μm.

[0075] Example 5 Referring to the method for preparing a back-contact solar cell of Example 1, the difference is that in step S2, the thickness of the second mask layer 4.2 gradually decreases from the edge of the front side of the silicon wafer 1 toward the texturing area, and the thickness decreases from 10 nm to 2 nm.

[0076] Example 6 Referring to the method for preparing a back-contact solar cell of Example 1, the difference is that in step S2, the reaction time ratio of the plating area and the texturing area of ​​the silicon wafer 1 in the texturing liquid is 1:3.

[0077] Comparative Example 1 Refer to the back contact solar cell of Example 1, except that no wrap-around plating area is provided.

[0078] Comparative Example 2 Referring to the back contact solar cell of Example 1, the difference is that a wrap-around plating area is provided, but the wrap-around plating area and the texturing area are in the same plane, and the wrap-around plating area has no inclination angle.

[0079] Comparative Example 3 Referring to the method for preparing a back-contact solar cell of Example 1, the difference is that the ratio of the width of the coating zone to the width of the texturing zone is 2%:95%.

[0080] Comparative Example 4 Referring to the back contact solar cell of Example 1, the difference is that the thickness of the plating-around area gradually decreases from the edge of the silicon wafer 1 toward the texturing area, and the inclination angle of the plating-around area on the front side of the silicon wafer 1 is 0.005°.

[0081] Comparative Example 5 Referring to the method for preparing a back-contact solar cell of Example 2, the difference is that in step S2, the thickness of the second mask layer 4.2 gradually decreases from the edge of the front side of the silicon wafer 1 toward the texturing area, and the thickness decreases from 5nm to 0nm.

[0082] Comparative Example 6 Referring to the method for preparing a back-contact solar cell of Example 1, the difference is that in step S2, the reaction time ratio of the plating area and the texturing area of ​​the silicon wafer 1 in the texturing liquid is 1:1.2.

[0083] Test Case The performance of the back-contact solar cells obtained in the above-mentioned embodiments and comparative examples was tested, and the specific test results are shown in Table 1.

[0084] Table 1 Test results of different embodiments and comparative examples

[0085] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present invention can significantly reduce the fragmentation rate, ensure the high performance of the battery, and facilitate the promotion of production. Furthermore, according to Example 1 and Examples 2 to 6, it can be seen that the preferred scheme of the present invention can improve the conversion efficiency and is more conducive to reducing the fragmentation rate.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A back contact solar cell, characterized in that: include: A silicon wafer having a front side and a back side; the front side of the silicon wafer includes a plating-around area and a texturing area, the plating-around area is located at the edge of the silicon wafer, and the texturing area is surrounded by the plating-around area; the thickness of the plating-around area gradually decreases from the edge of the silicon wafer toward the texturing area, and the plating-around area is cleaned by texturing to form a first texturing surface, and the texturing area is cleaned by texturing to form a second texturing surface, and the convexity of the first texturing surface is less than that of the second texturing surface; A first semiconductor layer is arranged on the back side of the silicon wafer, the first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer sequentially formed on the back side of the silicon wafer; the first semiconductor layer is separated by a plurality of second semiconductor opening regions, the second semiconductor opening regions and the surface of the first semiconductor layer around the second semiconductor opening regions are covered with the second semiconductor layer; a first semiconductor opening region is provided between adjacent second semiconductor opening regions, the first semiconductor opening region separates the second semiconductor layer; A passivation layer and an anti-reflection layer, wherein the passivation layer and the anti-reflection layer are sequentially arranged on the front side of the silicon wafer; wherein a first surface structure is formed on the surface of the passivation layer and the anti-reflection layer covering the coating area, and a second surface structure is formed on the surface of the passivation layer and the anti-reflection layer covering the texturing area, and the protrusion amplitude of the first surface structure is smaller than the protrusion amplitude of the second surface structure.

2. The back contact solar cell according to claim 1, characterized in that: The first textured surface includes a plurality of first pyramid structures, and the second textured surface includes a plurality of second pyramid structures; the height of the first pyramid structure is smaller than the height of the second pyramid structure.

3. The back contact solar cell according to claim 2, characterized in that: The structure height of the first pyramid is 0.3 μm to 0.6 μm, and the height of the second pyramid structure is 2 μm to 3 μm.

4. The back contact solar cell according to claim 1, characterized in that: The ratio of the width of the plating area to the width of the texturing area is (10%~30%): (70%~90%).

5. The back contact solar cell according to claim 1, characterized in that: The thickness of the plating-around area gradually decreases from the edge of the silicon wafer toward the texturing area, and the inclination angle of the plating-around area on the front side of the silicon wafer is 0.018° to 0.0238°.

6. The back contact solar cell according to claim 1, characterized in that: The first semiconductor layer includes a tunneling silicon oxide layer and an N-type doped polysilicon layer. The thickness of the tunneling silicon oxide layer is 1-2 nm, and the thickness of the N-type doped polysilicon layer is 80-140 nm.

7. The back contact solar cell according to claim 1, characterized in that: The width of the first semiconductor opening region is 400 μm to 600 μm, and the width of the second semiconductor opening region is 200 μm to 300 μm.

8. A method for preparing a back-contact solar cell, for preparing the back-contact solar cell according to any one of claims 1 to 7, characterized in that: include: S1. Provide a double-sided polished silicon wafer; S2, forming a first semiconductor layer and a first mask layer on the back side of the silicon wafer, and forming a second mask layer in the plating area on the front side of the silicon wafer; the thickness of the second mask layer gradually decreases from the edge of the front side of the silicon wafer to the texturing area; S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region; S4, texturing and cleaning the front and back opening areas of the silicon wafer; The first texturing surface is formed in the plating area on the front side of the silicon wafer by texturing cleaning, and the texturing area in the middle of the silicon wafer forms the second texturing surface; during the entire texturing time, the reaction time ratio of the plating area and the texturing area of ​​the silicon wafer in the texturing liquid is 1:(3-5); S5, forming a second semiconductor layer on the back side of the silicon wafer; the second semiconductor layer is a combination of an intrinsic amorphous silicon layer and a P-type doped amorphous / microcrystalline silicon layer; S6, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer; S7, etching an opening on the back side of the silicon wafer for the second time to form a first semiconductor opening region; S8, depositing a transparent conductive film layer on the back side of the silicon wafer; S9, etching an opening on the back side of the silicon wafer for the third time to form an insulating groove; S10, forming metal electrodes at the first semiconductor opening and the second semiconductor opening on the back side of the silicon wafer respectively.

9. The method for preparing a back-contact solar cell according to claim 8, characterized in that: In step S2, The first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer, the first mask layer and the second mask layer are both carbon-doped silicon nitride layers, the deposition temperature is 250°C~400°C, the mass flow rate of silane is 1000sccm~2000sccm, the mass flow rate of ammonia is 300sccm~1000sccm, the mass flow rate of nitrogen is 2000sccm~50000sccm, the mass flow rate of methane is 1000sccm~2000sccm, the pressure is 200Pa~400Pa, the power density of the power supply is 1.25kW / m2~3.75kW / m2, and the deposition time is 200s~500s.

10. The method for preparing a back contact solar cell according to claim 8, characterized in that: In step S2, the thickness of the first mask layer is 70nm~120nm; the thickness of the second mask layer decreases from 10nm~20nm to 0~5nm from the edge of the silicon wafer to the texturing area, and the width of the second mask layer is 1cm~2cm.

11. The method for preparing a back-contact solar cell according to claim 8, characterized in that: In step S4, it includes: The texturing liquid is a mixture of potassium hydroxide or sodium hydroxide, a texturing additive and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1% to 5%, the mass percentage of the texturing additive is 0.5% to 1%, the texturing time is 10 to 60 minutes, and the texturing temperature is 70°C to 85°C.

12. The method for preparing a back contact solar cell according to claim 8, characterized in that: In step S4, it also includes: During the texturing cleaning process, the first mask layer on the back of the silicon wafer is also removed through the final cleaning solution. The solution used to remove the first mask layer is HF solution. The mass percentage of HF acid in the HF solution is 0.5%~5%, the mass percentage of hydrogen peroxide is 3%~10%, and the mass percentage of deionized water is 95%~99.5%. The processing temperature is 20℃~30℃, and the removal time is 60s~300s.

13. The method for preparing a back contact solar cell according to claim 8, characterized in that: In step S5, it includes: The second semiconductor layer is formed by plate-type CVD, the thickness of the intrinsic amorphous silicon layer is 4-8 nm, the thickness of the P-type doped amorphous / microcrystalline silicon layer is 6-12 nm, and the deposition temperature of the second semiconductor layer is 150-250° C.

14. The method for preparing a back-contact solar cell according to claim 8, characterized in that: In step S6, it includes: The passivation layer is a combination of a silicon oxide layer and an aluminum oxide layer, and the aluminum oxide layer is formed by an atomic layer deposition method. The conditions of the atomic layer deposition method include: a process temperature between 150°C and 180°C, reaction gases are trimethylaluminum and ozone, and in the first stage, the flow rate of trimethylaluminum introduced is 2000sccm to 5000sccm, the reaction time is 20s to 40s, and then nitrogen is used to purge the chamber and pipelines; then the second stage is carried out, and the flow rate of ozone introduced in the second stage is 3000sccm to 6000sccm, the ozone introduction time is 15 to 30s, and then nitrogen is used to purge the chamber and pipelines; the first stage and the second stage are carried out in sequence as a cycle reaction, and a total of 30 to 80 cycle reactions are carried out.

15. A battery assembly, characterized in that: include: A back-contact solar cell as claimed in any one of claims 1 to 7.

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