High-reliability LED chip, preparation method thereof and display screen

Abstract

The invention relates to the technical field of light emitting diode manufacturing, in particular to a high-reliability LED chip, a preparation method thereof and a display screen. The preparation method comprises the steps of providing an epitaxial wafer; forming a conductive step and etching a groove; forming a first passivation layer and a second passivation layer; patterning the second passivation layer to enable the second passivation layer to cover the side wall of the etching groove, extend a first preset distance L1 along the bottom wall of the conductive step, and extend a second preset distance L2 along the bottom wall of the etching groove; forming a third passivation layer; and opening holes and forming a first electrode and a second electrode. Wherein the deposition rate of the third passivation layer and the deposition rate of the first passivation layer are the same and are smaller than the deposition rate of the second passivation layer. L1 > = 1.5 [mu] m, and L2 > = 1.5 [mu] m; according to the invention, the reliability of the LED chip can be improved.

Description

Technical Field

[0001] The invention relates to the technical field of light emitting diode manufacturing, and in particular to a high-reliability LED chip and a preparation method thereof, and a display screen. Background Art

[0002] In recent years, the market for display screens based on red, green and blue LED chips has expanded rapidly, and the demand is strong. Such LED chips used in display screens need to be used outdoors in different regions and environments, which places high demands on their high temperature resistance. Furthermore, as LED chips used in display screens are gradually miniaturized, more and more LED chips are integrated into a single display screen device, and the heat generated is also increasing, which in turn places higher demands on the high temperature resistance of a single LED chip.

[0003] The high temperature and high humidity resistance of LED chips mainly depends on the insulating protective film on its surface, which is generally Al2O3 film, SiN x Film, SiO2 film or a combination of at least two of them. For the most widely used SiO2 film, it is generally prepared by PECVD. In order to optimize the high temperature and high humidity resistance of the SiO2 film, it is often required to have a higher density. Therefore, a lower deposition rate is generally used for deposition to increase the crystal size, crystal quality, and film density. At the same time, a high film density also means that the film is more transparent and has a high light extraction efficiency. However, when the grain size of the SiO2 film is large, it is difficult to form a good combination with the etched side wall, that is, there will be a gap between the two, which causes moisture to enter the LED chip from the gap during high temperature and high humidity use, causing the chip to fail. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a high-reliability LED chip and a preparation method thereof, which has strong high temperature and high humidity resistance and high reliability.

[0005] In order to solve the above technical problems, the present invention provides a method for preparing a high-reliability LED chip, which comprises the following steps: (1) Providing an epitaxial wafer; wherein the epitaxial wafer comprises a substrate and a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the substrate; (2) removing the second semiconductor layer, the active layer and the first semiconductor layer in a preset area on the epitaxial wafer to form a conductive step; the angle between the side wall of the conductive step and the surface of the epitaxial wafer is α1; (3) removing the conductive step in a predetermined area on the epitaxial wafer obtained in step (2) to form an etched groove; the angle between the sidewall of the etched groove and the surface of the epitaxial wafer is α2, α2>α1; (4) depositing a first passivation layer on the epitaxial wafer obtained in step (3) at a first deposition rate; (5) depositing a second passivation layer on the first passivation layer at a second deposition rate; the second deposition rate is greater than the first deposition rate; (6) patterning the second passivation layer so that the second passivation layer covers the sidewalls of the etching groove and extends a first preset distance L1 along the bottom wall of the conductive step and a second preset distance L2 along the bottom wall of the etching groove, to obtain an intermediate; wherein L1 ≥ 1.5 μm, L2 ≥ 1.5 μm; (7) depositing a third passivation layer on the intermediate body at a first deposition rate, wherein the third passivation layer covers the first passivation layer and the second passivation layer; and the thickness of the third passivation layer is greater than the thickness of the first passivation layer; (8) forming a first electrode hole on the conductive step that penetrates the third passivation layer and the second passivation layer, and forming a second electrode hole on the second semiconductor layer that penetrates the third passivation layer and the second passivation layer; (9) A first electrode and a second electrode are formed, wherein the first electrode is electrically connected to the first semiconductor layer through the first electrode hole, and the second electrode is electrically connected to the second semiconductor layer through the second electrode hole.

[0006] As an improvement of the above technical solution, the first passivation layer, the second passivation layer, and the third passivation layer are all SiO2 layers, and are all deposited by PECVD method; and / or The first deposition rate is 1.5-2.5 Å / s; the second deposition rate is 3-5 Å / s.

[0007] As an improvement of the above technical solution, the deposition temperature of the second passivation layer is lower than the deposition temperature of the first passivation layer; The flow ratio of SiH4 to N2O during the deposition of the second passivation layer is greater than the flow ratio of SiH4 to N2O during the deposition of the first passivation layer; The RF power during the deposition of the second passivation layer is less than the RF power during the deposition of the first passivation layer.

[0008] As an improvement of the above technical solution, the process conditions for depositing the first passivation layer include: RF power of 80~100W, SiH4 flow rate of 60~100sccm, N2O flow rate of 1800~2000sccm, and temperature of 270~300℃.

[0009] As an improvement of the above technical solution, the process conditions for depositing the second passivation layer include: RF power of 60~80W, SiH4 flow rate of 120~200sccm, N2O flow rate of 1000~1800sccm, and temperature of 80~120℃.

[0010] As an improvement of the above technical solution, the process conditions for depositing the third passivation layer include: RF power of 80~100W, SiH4 flow rate of 60~100sccm, N2O flow rate of 1800~2000sccm, and temperature of 270~300℃.

[0011] As an improvement of the above technical solution, the thickness of the second passivation layer is greater than the sum of the thickness of the first passivation layer and the thickness of the third passivation layer.

[0012] As an improvement of the above technical solution, the first electrode and the second electrode each include a Cr layer, an Al layer, a first Ti layer, a first Pt layer, a second Ti layer, a second Pt layer and an Au layer stacked in sequence; The thickness of the Cr layer is 30~50Å, the thickness of the Al layer is 1200~2000Å, the thickness of the first Ti layer is 1000~2000Å, the thickness of the first Pt layer is 1000~2000Å, the thickness of the second Ti layer is 1000~2000Å, the thickness of the second Pt layer is 1000~2000Å, and the thickness of the Au layer is 15000~20000Å.

[0013] Correspondingly, the present invention also discloses a high-reliability LED chip, which is prepared by the above-mentioned method for preparing the high-reliability LED chip.

[0014] Correspondingly, the present invention also discloses a display screen, which includes the above-mentioned high-reliability LED chip.

[0015] The implementation of the present invention has the following beneficial effects: In the method for preparing a high-reliability LED chip in one embodiment of the present invention, a first passivation layer deposited at a low deposition rate, a second passivation layer deposited at a high deposition rate, and a third passivation layer deposited at a low deposition rate are sequentially arranged on the sidewalls of the etching grooves at a large inclination angle, and the two sides of the second passivation layer are respectively extended along the bottom wall of the conductive step and the bottom wall of the etching groove by a preset distance, which greatly optimizes the connection between the first passivation layer and the sidewall of the etching groove, effectively prevents the first passivation layer from separating from the sidewall of the etching groove under high temperature and high humidity conditions, and improves the reliability of the LED chip. At the same time, the sidewalls of the conductive step at a small inclination angle are sequentially covered with the first passivation layer and the third passivation layer, which can play a good passivation role and ensure sufficient transparency, thereby improving the light extraction efficiency of the LED chip and the luminous efficiency of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of the structure of the epitaxial wafer after step S3 in one embodiment of the present invention; Figure 2 is a schematic diagram of the structure of the epitaxial wafer after step S4 in one embodiment of the present invention; Figure 3 is a schematic structural diagram of the intermediate obtained after step S6 in one embodiment of the present invention; Figure 4 is a schematic diagram of the structure of the intermediate after step S7 in one embodiment of the present invention; Figure 5 is a schematic structural diagram of a high-reliability LED chip obtained after step S9 in one embodiment of the present invention; In the figure, 1 is an epitaxial wafer, 11 is a substrate, 12 is a first semiconductor layer, 13 is an active layer, 14 is a second semiconductor layer, 15 is a conductive step, 151 is a side wall of the conductive step, 16 is an etching groove, 161 is a side wall of the etching groove, 2 is a transparent conductive layer, 3 is a first passivation layer, 4 is a second passivation layer, 41 is a first electrode hole, 42 is a second electrode hole, 5 is a third passivation layer, 6 is a first electrode, and 7 is a second electrode. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0018] In the description of the present application, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0019] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0020] The present invention discloses a method for preparing a high-reliability LED chip, which comprises the following steps: S1: Provide epitaxial wafers; The epitaxial wafer 1 includes a substrate 11 and an epitaxial layer. The epitaxial layer includes a first semiconductor layer 12, an active layer 13 and a second semiconductor layer 14 stacked on the substrate 11 in sequence. The substrate 11 is a sapphire substrate, a silicon substrate or a SiC substrate, but is not limited thereto. The first semiconductor layer 12 may be an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but is not limited thereto. The active layer 13 may be an InGaN-GaN type MQW layer, an InGaN-AlGaN type MQW layer or an AlGaN-AlGaN type MQW layer, but is not limited thereto. The second semiconductor layer 14 may be a P-type GaN layer, a P-type AlGaN layer, or a P-type GaAs layer, but is not limited thereto.

[0021] Preferably, in an embodiment of the present invention, the epitaxial layer may further include one or more of a buffer layer, an intrinsic semiconductor layer, a stress buffer layer, an electron blocking layer, and an ohmic contact layer commonly used in the art, but is not limited thereto.

[0022] S2: removing the second semiconductor layer, the active layer and the first semiconductor layer in a preset area on the epitaxial wafer to form a conductive step; Specifically, a mask (photoresist layer, SiO2 layer, etc.) can be first formed on the epitaxial wafer 1 obtained in step S1, and then the second semiconductor layer 14, the active layer 13 and part of the first semiconductor layer 12 in a preset area are removed by wet etching or dry etching to form a conductive step 15, but not limited to this.

[0023] Preferably, in some embodiments, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S1, and after being exposed, developed and patterned, the second semiconductor layer 14, the active layer 13 and part of the first semiconductor layer 12 are etched away using an inductively coupled plasma etching process (ICP) to obtain a conductive step 15.

[0024] Specifically, see Figure 1 The angle between the side wall 151 of the conductive step and the surface of the epitaxial wafer 1 is α1, and the value range of α1 is 20°~50°. The inclination angle of the side wall 151 of the conductive step in the present invention is small, which is convenient for the first passivation layer 3 and the third passivation layer 5 formed at a low deposition rate to form a good combination thereon, thereby achieving saturation of the side wall dangling bonds, reducing leakage channels and non-radiative recombination centers, and improving the luminous efficiency and reliability of the LED chip. It should be noted that the inclination angle of the side wall 151 of the conventional conductive step reaches 60°~90°.

[0025] Preferably, in some embodiments, step S2 comprises: S21: etching the epitaxial wafer obtained in step S1 to form a conductive step; S22: forming a transparent conductive layer on the epitaxial wafer obtained in step S21; The transparent conductive layer 2 may be a common ITO layer, IZO layer, AZO layer, ATO layer or FTO layer in the art, but is not limited thereto. Preferably, the transparent conductive layer 2 is an ITO layer. The thickness of the transparent conductive layer 2 is 5 to 150 nm, preferably 50 to 150 nm.

[0026] The transparent conductive layer 2 can be formed by a process such as magnetron sputtering, electron beam evaporation, etc., but is not limited thereto. Preferably, in one embodiment, after the transparent conductive layer 2 is formed, it is annealed at a temperature of 500° C. to 600° C. for a time of 3 min to 10 min. Through annealing, its light transmittance can be optimized, and its ohmic contact with the second semiconductor layer 14 can be optimized.

[0027] S23: etching and removing the transparent conductive layer in the preset area, and retaining the transparent conductive layer on the second semiconductor layer; Specifically, a mask (photoresist layer, SiO2 layer, etc.) can be first formed on the epitaxial wafer 1 obtained in step S22, and then the transparent conductive layer 2 in a preset area is removed by wet etching or dry etching, leaving only the transparent conductive layer 2 on the second semiconductor layer 14, but not limited thereto.

[0028] Preferably, in some implementations, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S22, and after being exposed, developed and patterned, a corrosive solution is used to corrode and remove the transparent conductive layer 2 in a preset area, and then the photoresist layer is removed.

[0029] S3: removing the conductive step in a preset area on the epitaxial wafer obtained in step S2 to form an etching groove; Specifically, a mask (photoresist layer, SiO2 layer, etc.) may be first formed on the epitaxial wafer 1 obtained in step S2, and then the conductive step 15 in the preset area may be removed by wet etching or dry etching to form an etching groove 16 exposing the substrate 11, but the present invention is not limited thereto.

[0030] Preferably, in some implementations, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S2 , and after being exposed, developed and patterned, the conductive step 15 is etched by an ICP process to form an etched groove 16 .

[0031] Specifically, the angle between the side wall 161 of the etched groove and the surface of the epitaxial wafer 1 is α2, α2>α1. Specifically, the value range of α2 is 70°~90°. The inclination angle of the side wall 161 of the etched groove in the present invention is relatively large, which can reduce the occupation of the light-emitting area of ​​the LED chip and improve the light-emitting efficiency. At the same time, by subsequently covering the side wall 16 of the etched groove with the second passivation layer 4, the side wall 161 of the etched groove can also be effectively passivated to ensure that the LED chip has better reliability.

[0032] S4: depositing a first passivation layer on the epitaxial wafer obtained in step S3 at a first deposition rate; Among them, see Figure 2 The first passivation layer 3 can be made of SiO2, Al2O3, SiN x 、SiO x N y The thickness of the first passivation layer 3 is 200-1500Å, exemplarily 300Å, 400Å, 600Å, 800Å, 1100Å or 1400Å, but not limited thereto. Preferably, it is 300-1000Å.

[0033] The first passivation layer 3 may be deposited by PECVD, ALD or MOCVD, but is not limited thereto.

[0034] Preferably, in some embodiments, the first passivation layer 3 is a SiO2 layer, which is deposited by PECVD. The deposition process conditions include: RF power of 80-100W, SiH4 flow rate of 60-100sccm, N2O flow rate of 1800-2000sccm, and temperature of 270-300°C. Based on the process conditions, the deposition rate of the first passivation layer 3 can be controlled to 1.5-2.5Å / s, thereby effectively improving the compactness and light transmittance of the first passivation layer 3, and improving the passivation effect on the sidewall 151 of the conductive step and other positions.

[0035] S5: depositing a second passivation layer on the first passivation layer at a second deposition rate; The second passivation layer 4 can be made of SiO2, Al2O3, SiN x 、SiO x N y The thickness of the second passivation layer 4 is 800-3500Å, exemplarily 900Å, 1400Å, 1900Å, 2300Å, 2700Å or 3100Å, but not limited thereto. Preferably, it is 1000-2000Å.

[0036] Among them, the second passivation layer 4 can be deposited by PECVD, ALD or MOCVD, but is not limited thereto. The second deposition rate is greater than the first deposition rate to form a looser second passivation layer 4 on the first passivation layer 3, which will introduce tensile stress, prompting the first passivation layer 3 to better combine with the side wall 161 of the etching groove with a larger inclination angle, thereby improving the ability to withstand high temperature and humidity, and improving the reliability of the LED chip. It should be noted that the first passivation layer 3 deposited at a lower deposition rate is mainly composed of compressive stress, which drives the first passivation layer 3 to detach from the surface of the epitaxial wafer 1, especially from the surface of the side wall 161 of the etching groove with a larger inclination angle, and the introduction of the second passivation layer 4 with a higher deposition rate introduces tensile stress, which can effectively balance the compressive stress, thereby making the first passivation layer 3 more closely adhere to the side wall 161 of the etching groove, thereby improving the reliability of the LED chip.

[0037] Preferably, in some embodiments, the second passivation layer 4 is a SiO2 layer, which is deposited by a PECVD method. The deposition temperature of the second passivation layer 4 is lower than the deposition temperature of the first passivation layer 3, which can reduce the breakage and decomposition of Si-H bonds and increase tensile stress. The flow ratio of SiH4 to N2O during the deposition of the second passivation layer 4 is greater than the flow ratio of SiH4 to N2O during the deposition of the first passivation layer 3, so as to weaken the densification of the SiO2 network, inhibit the formation of large grains, and promote the formation of Si-H bonds, thereby increasing tensile stress. The RF power during the deposition of the second passivation layer 4 is lower than the RF power during the deposition of the first passivation layer 3.

[0038] More specifically, the process conditions for depositing the second passivation layer 4 include: RF power of 80-100 W, SiH4 flow rate of 60-100 sccm, N2O flow rate of 1800-2000 sccm, and temperature of 270-300° C. Based on the process conditions, the deposition rate of the second passivation layer 4 can be controlled to be 3-5 Å / s, thereby effectively improving the adhesion of the first passivation layer 3 to the sidewall 161 of the etched groove, thereby improving the reliability of the LED chip.

[0039] S6: patterning the second passivation layer to obtain an intermediate; Specifically, in some embodiments, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S5, and after exposing and developing the photoresist layer to pattern, the second passivation layer 4 in the preset area is etched away using an inductively coupled plasma etching process (ICP). Figure 3, after removal, the second passivation layer 4 covers the side wall 161 of the etching groove, and its top extends along the bottom wall of the conductive step 15 by a first preset distance L1, and its bottom extends along the bottom wall of the etching groove 16 by a second preset distance L2, L1≥1.5μm, L2≥1.5μm. Through the second passivation layer 4 of this structure, the combination of the first passivation layer 3 and the side wall 161 of the etching groove can be greatly optimized to improve reliability. It should be noted that the inclination angle of the side wall 151 of the conductive step in the traditional LED chip is not much different from the inclination angle of the side wall 161 of the etching groove, both of which are 60°~90°. In the present invention, the angles of the two are quite different. One adopts the side wall 151 of the conductive step with a small inclination angle, which strengthens the connection with the first passivation layer 3, so there is no need to set a loose and porous second passivation layer 4 on it, so as to avoid the second passivation layer 4 reducing the light extraction efficiency. In the other, the side wall 161 of the etching groove with a large inclination angle is adopted, and the second passivation layer 4 is set thereon. This not only expands the light-emitting area, but also ensures the reliability of the LED chip.

[0040] More specifically, L1 is 1.5 to 2.5 μm, and L2 is 1.8 to 3 μm.

[0041] Preferably, in some embodiments, the thickness of the second passivation layer 4 is greater than the sum of the thickness of the first passivation layer 3 and the thickness of the third passivation layer 5. Based on this embodiment, the reliability of the LED chip can be further improved.

[0042] S7: depositing a third passivation layer on the intermediate obtained in step S6 at the first deposition rate; Among them, see Figure 4 The third passivation layer 5 can be made of SiO2, Al2O3, SiN x 、SiO x N y One or more of, but not limited to.

[0043] The thickness of the third passivation layer 5 is greater than that of the first passivation layer 3. Specifically, the thickness of the third passivation layer 5 is 300-1500Å, exemplarily 300Å, 400Å, 600Å, 800Å, 1100Å or 1400Å, but not limited thereto, preferably 500-1200Å.

[0044] The third passivation layer 5 may be deposited by PECVD, ALD or MOCVD, but is not limited thereto.

[0045] Preferably, in some embodiments, the third passivation layer 5 is a SiO2 layer, which is deposited by PECVD. The deposition process conditions include: RF power of 80-100W, SiH4 flow rate of 60-100sccm, N2O flow rate of 1800-2000sccm, and temperature of 270-300°C. Based on the process conditions, the deposition rate of the third passivation layer 5 can be controlled to 1.5-2.5Å / s, thereby effectively improving the compactness and light transmittance of the third passivation layer 5, improving the passivation effect, and improving the reliability of the LED chip.

[0046] S8: forming a first electrode hole penetrating the third passivation layer and the second passivation layer on the conductive step, and forming a second electrode hole penetrating the third passivation layer and the second passivation layer on the second semiconductor layer; Specifically, in some embodiments, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S5, and after being exposed, developed and patterned, the first passivation layer 3 and the second passivation layer 4 in the preset area are etched away by an inductively coupled plasma etching process (ICP) to form a first electrode hole 41 and a second electrode hole 42. The bottom of the first electrode hole 41 exposes the first semiconductor layer 12, and the bottom of the second electrode hole 42 exposes the second semiconductor layer 14 or the transparent conductive layer 2.

[0047] S9: forming a first electrode and a second electrode; Specifically, the first electrode and the second electrode may be formed by PVD or evaporation process, but not limited thereto. The first electrode and the second electrode may be formed simultaneously or in steps, but not limited thereto. Figure 5 The first electrode 6 is electrically connected to the first semiconductor layer 12 through the first electrode hole 41 , and the second electrode 7 is electrically connected to the second semiconductor layer 14 through the second electrode hole 42 .

[0048] Specifically, the first electrode 6 and the second electrode 7 are made of one or more of Al, Cr, Ti, Ni, Pt, and Au, but are not limited thereto. Preferably, in some embodiments, the first electrode 6 and the second electrode 7 each include a Cr layer, an Al layer, a first Ti layer, a first Pt layer, a second Ti layer, a second Pt layer, and an Au layer stacked in sequence; the thickness of the Cr layer is 30-50Å, the thickness of the Al layer is 1200-2000Å, the thickness of the first Ti layer is 1000-2000Å, the thickness of the first Pt layer is 1000-2000Å, the thickness of the second Ti layer is 1000-2000Å, the thickness of the second Pt layer is 1000-2000Å, and the thickness of the Au layer is 15000-20000Å.

[0049] In summary, in the preparation method of the high-reliability LED chip in this embodiment, the side wall 161 of the etching groove with a large inclination angle sequentially covers the first passivation layer 3 deposited at a low deposition rate, the second passivation layer 4 deposited at a high deposition rate, and the third passivation layer 5 deposited at a low deposition rate, and the two sides of the second passivation layer 4 extend along the bottom wall of the conductive step and the bottom wall of the etching groove for a preset distance, which greatly optimizes the connection between the first passivation layer 3 and the side wall 161 of the etching groove, effectively preventing it from separating from the side wall of the etching groove under high temperature and high humidity conditions, and improving the reliability of the LED chip. At the same time, the side wall 151 of the conductive step with a small inclination angle sequentially covers the first passivation layer 3 and the third passivation layer 5, which can play a good passivation role and ensure sufficient transparency, thereby improving the light extraction efficiency of the LED chip and the luminous efficiency of the LED chip.

[0050] Specifically, based on the technical solution in this embodiment, the high temperature and high humidity aging failure time can reach more than 2000 hours, and up to 3250 hours. However, the traditional LED chip (the inclination angle of the side wall of the conductive step and the side wall of the etching groove are both 75°, and only the first passivation layer 3 and the third passivation layer 5 are formed) can only reach about 680 hours. Specifically, the aging process is as follows: the prepared LED chip is aged at high temperature and high humidity, and the LED chip is tested for reverse current every 24 hours. The test reverse voltage is 10V. When the reverse current value is less than 0.5μA, the LED chip is considered to have failed. Among them, the aging temperature is 85°C and the aging humidity is 90%RH.

[0051] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0052] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a high-reliability LED chip, characterized in that: The following steps are involved: (1) Providing an epitaxial wafer; wherein the epitaxial wafer comprises a substrate and a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the substrate; (2) removing the second semiconductor layer, the active layer and the first semiconductor layer in a preset area on the epitaxial wafer to form a conductive step; the angle between the side wall of the conductive step and the surface of the epitaxial wafer is α1; (3) removing the conductive step in a predetermined area on the epitaxial wafer obtained in step (2) to form an etched groove; the angle between the sidewall of the etched groove and the surface of the epitaxial wafer is α2, α2>α1; (4) depositing a first passivation layer on the epitaxial wafer obtained in step (3) at a first deposition rate; (5) depositing a second passivation layer on the first passivation layer at a second deposition rate; the second deposition rate is greater than the first deposition rate; (6) patterning the second passivation layer so that the second passivation layer covers the sidewalls of the etching groove and extends a first preset distance L1 along the bottom wall of the conductive step and a second preset distance L2 along the bottom wall of the etching groove, to obtain an intermediate; wherein L1 ≥ 1.5 μm, L2 ≥ 1.5 μm; (7) depositing a third passivation layer on the intermediate body at a first deposition rate, wherein the third passivation layer covers the first passivation layer and the second passivation layer; and the thickness of the third passivation layer is greater than the thickness of the first passivation layer; (8) forming a first electrode hole on the conductive step that penetrates the third passivation layer and the second passivation layer, and forming a second electrode hole on the second semiconductor layer that penetrates the third passivation layer and the second passivation layer; (9) A first electrode and a second electrode are formed, wherein the first electrode is electrically connected to the first semiconductor layer through the first electrode hole, and the second electrode is electrically connected to the second semiconductor layer through the second electrode hole.

2. The method for preparing a high-reliability LED chip according to claim 1, characterized in that: The first passivation layer, the second passivation layer, and the third passivation layer are all SiO2 layers, and are deposited by PECVD method; and / or The first deposition rate is 1.5-2.5 Å / s; the second deposition rate is 3-5 Å / s.

3. The method for preparing a high-reliability LED chip according to claim 2, characterized in that: The deposition temperature of the second passivation layer is lower than the deposition temperature of the first passivation layer; The flow ratio of SiH4 to N2O during the deposition of the second passivation layer is greater than the flow ratio of SiH4 to N2O during the deposition of the first passivation layer; The RF power during the deposition of the second passivation layer is less than the RF power during the deposition of the first passivation layer.

4. The method for preparing a high-reliability LED chip according to claim 2, characterized in that: The process conditions for depositing the first passivation layer include: RF power of 80-100 W, SiH4 flow rate of 60-100 sccm, N2O flow rate of 1800-2000 sccm, and temperature of 270-300°C.

5. The method for preparing a high-reliability LED chip according to claim 4, characterized in that: The process conditions for depositing the second passivation layer include: RF power of 60-80 W, SiH4 flow rate of 120-200 sccm, N2O flow rate of 1000-1800 sccm, and temperature of 80-120°C.

6. The method for preparing a high-reliability LED chip according to claim 5, characterized in that: The process conditions for depositing the third passivation layer include: RF power of 80-100 W, SiH4 flow rate of 60-100 sccm, N2O flow rate of 1800-2000 sccm, and temperature of 270-300°C.

7. The method for preparing a high-reliability LED chip according to claim 1, characterized in that: The thickness of the second passivation layer is greater than the sum of the thickness of the first passivation layer and the thickness of the third passivation layer.

8. The method for preparing a high-reliability LED chip according to claim 1, characterized in that: The first electrode and the second electrode each include a Cr layer, an Al layer, a first Ti layer, a first Pt layer, a second Ti layer, a second Pt layer and an Au layer stacked in sequence; The thickness of the Cr layer is 30~50Å, the thickness of the Al layer is 1200~2000Å, the thickness of the first Ti layer is 1000~2000Å, the thickness of the first Pt layer is 1000~2000Å, the thickness of the second Ti layer is 1000~2000Å, the thickness of the second Pt layer is 1000~2000Å, and the thickness of the Au layer is 15000~20000Å.

9. A high reliability LED chip, characterized in that: The LED chip is prepared by the method for preparing a high-reliability LED chip as described in any one of claims 1 to 8.

10. A display screen, characterized in that: Comprising the high-reliability LED chip as claimed in claim 9.

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