Display panel

Abstract

A display panel includes: a substrate having an opening area, a display area, and an intermediate area between the opening area and the display area; a plurality of display elements in the display area; an encapsulation layer covering the plurality of display elements and extending from the display area to the intermediate area; a planarization layer in the intermediate region and overlapping a portion of the encapsulation layer; a crack sensing portion on the planarization layer and extending around a portion of the opening region; and a capping layer covering a first end of the planarization layer on the encapsulation layer and electrically connected to the crack sensing portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0142351 filed in the Korean Intellectual Property Office on October 23, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display panel. Background Art

[0004] Recently, the applications of display devices have been diversified. In addition, display devices are manufactured to be thinner and lighter, thereby allowing for a wider range of uses.

[0005] As the area occupied by the display region in the display device has been expanded, various functions incorporated into or linked to the display device have been added to the display device. As a way of adding various functions to the display device while expanding the area of ​​the display region, the display device includes a display panel having an opening in the display region. Summary of the invention

[0006] In a display panel having an opening in a display area, problems such as cracks or film peeling may occur in components arranged around the opening.

[0007] An embodiment of the present disclosure includes a display panel having an opening in a display area, around which components may be arranged. However, this embodiment is merely an example, and the scope of the present disclosure is not limited thereto.

[0008] Additional aspects and features of the disclosure will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the described embodiments.

[0009] According to an embodiment of the present invention, a display panel includes: a substrate having an opening area, a display area, and an intermediate area between the opening area and the display area; a plurality of display elements in the display area; an encapsulation layer covering the plurality of display elements and extending from the display area to the intermediate area; a planarization layer in the intermediate area and overlapping with a portion of the encapsulation layer; a crack sensing portion on the planarization layer and extending around a portion of the opening area; and a covering layer covering a first end of the planarization layer and electrically connected to the crack sensing portion, the first end of the planarization layer being on the encapsulation layer.

[0010] In an embodiment, the crack sensing portion may include: a first connection line and a second connection line each extending to the outside of the middle region; and a crack sensing pattern electrically connecting the first connection line to the second connection line and adjacent to the opening region.

[0011] In an embodiment, the first connection line and the crack sensing pattern may be in a first conductive layer, and the second connection line may include a first sub connection line in the first conductive layer and a second sub connection line in a second conductive layer different from the first conductive layer.

[0012] In an embodiment, the cover layer may be in the second conductive layer.

[0013] In an embodiment, the second sub connection line may be provided integrally with the cover layer.

[0014] In an embodiment, the crack sensing pattern may have a ring shape with one side opened.

[0015] In an embodiment, the crack sensing pattern may include a first portion having a ring shape with one side open, a second portion connecting one end of the first portion to the first connection line, and a third portion connecting the other end of the first portion to the second connection line.

[0016] In an embodiment, the cover layer may have a closed loop shape when viewed in a direction perpendicular to the substrate.

[0017] In an embodiment, the display panel may further include a groove, the groove may be in the middle region and may extend around the opening region, and the planarization layer may cover the groove.

[0018] In an embodiment, the groove may have an undercut shape.

[0019] According to an embodiment of the present invention, a display panel includes: a substrate having an opening area, a display area, and an intermediate area between the opening area and the display area; a plurality of display elements in the display area; an encapsulation layer covering the plurality of display elements and extending from the display area to the intermediate area; an input sensing layer on the encapsulation layer; a planarization layer in the intermediate area and overlapping with a portion of the encapsulation layer; a crack sensing portion on the planarization layer and extending around a portion of the opening area; and a covering layer covering a first end of the planarization layer and electrically connected to the crack sensing portion, the first end of the planarization layer being on the encapsulation layer.

[0020] In an embodiment, the input sensing layer may include a first conductive layer, a second conductive layer, and an insulating layer between the first conductive layer and the second conductive layer, and the cover layer may include the same material as the first conductive layer.

[0021] In an embodiment, the crack sensing portion may include a first connection line and a second connection line each extending to the outside of the middle region, and the crack sensing pattern electrically connects the first connection line to the second connection line and is adjacent to the opening region.

[0022] In an embodiment, each of the first connection line and the crack sensing pattern may include the same material as the second conductive layer, and the second connection line may include a first sub-connection line and a second sub-connection line, the first sub-connection line and the second conductive layer include the same material, and the second sub-connection line and the first conductive layer include the same material.

[0023] In an embodiment, the cover layer may be provided integrally with the second sub connection line.

[0024] In an embodiment, when viewed in a direction perpendicular to the substrate, a portion of the first connection line and a portion of the second connection line may overlap the cover layer.

[0025] In an embodiment, the crack sensing pattern may have a ring shape with one side opened.

[0026] In an embodiment, the crack sensing pattern may include a first portion having a ring shape with one side open, a second portion connecting one end of the first portion to the first connection line, and a third portion connecting the other end of the first portion to the second connection line.

[0027] In an embodiment, the cover layer may have a closed loop shape when viewed in a direction perpendicular to the substrate.

[0028] In an embodiment, the display panel may further include a groove, the groove may be in the middle region and may extend around the opening region, and the planarization layer may cover the groove.

[0029] Other aspects and features besides those described above will become apparent from the accompanying drawings, claims and detailed description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a schematic perspective view of an electronic device according to an embodiment;

[0032] Figure 2 is a schematic cross-sectional view of an electronic device according to an embodiment;

[0033] Figure 3 is a schematic plan view of a display panel according to an embodiment;

[0034] Figure 4 is an equivalent circuit diagram of a pixel included in a display panel according to an embodiment;

[0035] Figure 5 is a schematic plan view of a portion of a display panel according to an embodiment;

[0036] Figure 6 is a schematic plan view of a portion of a display panel according to an embodiment;

[0037] Figure 7 is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0038] Figure 8 is a schematic plan view of an input sensing layer of a display panel according to an embodiment;

[0039] Fig. 9 is a schematic plan view of a portion of an input sensing layer of a display panel according to an embodiment;

[0040] Fig. 10A and Fig. 10B is a schematic plan view of a first conductive layer and a second conductive layer of an input sensing layer according to an embodiment;

[0041] Fig. 10C is a schematic cross-sectional view of an input sensing layer according to an embodiment;

[0042] Fig.11 is a schematic cross-sectional view of a display panel according to an embodiment;

[0043] Fig.12 is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0044] Fig.13 is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0045] Fig.14A and Fig. 14B is a schematic plan view of a portion of a display panel according to an embodiment;

[0046] Fig.15A is a schematic plan view of a portion of a display panel according to an embodiment; and

[0047] Fig. 15B and Fig. 15C is a schematic cross-sectional view of a portion of a display panel according to an embodiment. DETAILED DESCRIPTION

[0048] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings. The described embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to describe aspects and features of the present specification.

[0049] Various modifications may be made to the described embodiments, and embodiments will be shown in the drawings and described in the detailed description. By referring to the following detailed description in conjunction with the drawings, aspects and features of the presented embodiments and methods of implementing them will become more apparent. However, the described embodiments may be implemented in various forms, and the present disclosure is not limited to the embodiments presented below.

[0050] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings and in the description with reference to the accompanying drawings. The same or corresponding elements are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0051] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element may be directly on, directly connected to, or directly coupled to the other element or layer, or there may also be one or more intervening elements or layers. When an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For example, when a first element is described as being "coupled to" or "connected to" a second element, the first element may be directly coupled or connected to the second element, or the first element may be indirectly coupled or connected to the second element via one or more intervening elements.

[0052] In the accompanying drawings, for the clarity of explanation, the sizes of various elements, layers, etc. may be exaggerated. The same reference numerals represent the same elements. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. In addition, when describing the embodiments of the present disclosure, the use of "may" relates to "one or more embodiments of the present disclosure". When expressions such as "at least one / kind / person in ... " and "any one / kind / person in ... " are after a column of elements, the entire column of elements is modified instead of the individual elements in the column. For example, the expression "at least one / kind / person in a, b, and c" represents only a, only b, only c, a and b, a and c, b and c, a, b, and c, all or their variants. As used herein, the term "use (use, using and used)" can be considered to be synonymous with the term "utilize (utilize, utilizing and utilized)" respectively. As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree, and are intended to account for the inherent variation in measurements or calculations that those skilled in the art would recognize.

[0053] It will be understood that, although the terms first, second, third, etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teaching of the exemplary embodiment, the first element, first component, first region, first layer or first part discussed below can be named as the second element, second component, second region, second layer or second part.

[0054] For ease of description, spatially relative terms such as "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device is flipped in the accompanying drawings, an element described as "below" or "below" other elements or features will then be oriented "above" or "on" the other elements or features. Therefore, the term "below" can include both above and below orientations. In addition, the device can be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0055] The terms used herein are for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, "one" and "one / kind / person" are also intended to include plural forms. It will also be understood that the terms "include", "comprise", "have" and / or "have" illustrate the existence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0056] In this specification, the x direction, y direction, and z direction are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x direction, y direction, and z direction may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0057] In this specification, when a specific embodiment can be implemented differently, a specific process sequence can be performed in a different order from the described sequence. For example, two processes described in succession can be performed substantially simultaneously, or in a reverse order from the described sequence.

[0058] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the elements in the drawings may be arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0059] Figure 1 is a schematic perspective view of an electronic device according to an embodiment.

[0060] Reference Figure 1 , the electronic device 1 is a display device that displays moving images and / or still images, and can be used as a display screen for various products (such as televisions, laptop computers, monitors, billboards, or Internet of Things (IoT) devices) and portable electronic devices (such as mobile phones, smart phones, tablet personal computers (tablet PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, or ultra-mobile PCs (UMPCs)). In addition, according to an embodiment, the electronic device 1 can be used in wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). In addition, the electronic device 1 according to an embodiment can be used as a display for an instrument panel of a vehicle, a central information display (CID) arranged on a central instrument panel or dashboard of a vehicle, an interior mirror display instead of a side mirror of a vehicle, or a display arranged at the rear side of a front seat as an entertainment device for a rear seat of a vehicle. Figure 1 An embodiment in which the electronic device 1 is used as a smartphone is shown as an example.

[0061] The electronic device 1 may have a rectangular shape in a plan view. Figure 1 As shown in , the electronic device 1 may have a rectangular shape having a short side in a first direction (e.g., x direction) and a long side in a second direction (e.g., y direction). The corner where the short side in the first direction and the long side in the second direction meet may be rounded with a curvature, or may be formed to have a right angle. The planar shape of the electronic device 1 is not limited to a rectangle, and the electronic device 1 may have other polygonal shapes, an elliptical shape, or an irregular shape.

[0062] The electronic device 1 may have an opening area (e.g., an open area) OA and a display area DA surrounding at least a portion of the opening area OA (e.g., at least partially surrounding the opening area OA or at least partially extending around the periphery of the opening area OA in a plan view). The electronic device 1 may have an intermediate area MA arranged between the opening area OA and the display area DA and an outer area PA outside the display area DA (e.g., surrounding the display area DA (e.g., extending around the periphery of the display area DA in a plan view or surrounding the display area DA in a plan view)). In a plan view, the intermediate area MA may have a closed loop shape that completely surrounds the opening area OA.

[0063] The opening area OA may be arranged inside the display area DA. Figure 1 As shown in , the opening area OA may be arranged in the upper center of the display area DA. In another embodiment, the opening area OA may be arranged in various areas; for example, the opening area OA may be arranged on the upper left side of the display area DA or on the upper right side of the display area DA. Figure 1 An embodiment in which one opening area OA is arranged is shown, but in some embodiments, a plurality of opening areas OA may be provided.

[0064] Figure 2 is a schematic cross-sectional view of an electronic device according to an embodiment. Figure 2 It is along Figure 1 Schematic cross-sectional view of the electronic device 1 taken along line II'.

[0065] Reference Figure 2 , the electronic device 1 may include a display panel 10, a cover window 60 disposed above the display panel 10, and an assembly 70 disposed in (or below) an opening area OA in the display panel 10. The display panel 10 and the assembly 70 may be accommodated in a housing HS.

[0066] The display panel 10 may include an image generation layer 20 , an input sensing layer 40 , and an optical function layer 50 .

[0067] The image generation layer 20 may include a display element (e.g., a light emitting element) configured to emit light to display an image. The display element may include a light emitting diode, for example, an organic light emitting diode including an organic light emitting layer. In some embodiments, the light emitting diode may be an inorganic light emitting diode including an inorganic material. The inorganic light emitting diode may include a PN junction diode including an inorganic semiconductor-based material. When a voltage is applied to the PN junction diode in the forward direction, holes and electrons are injected, and the energy generated by the recombination of holes and electrons is converted into light energy, thereby emitting light of a specific color. The width of the inorganic light emitting diode may be in the range of several microns to several hundred microns or several nanometers to several hundred nanometers. In some embodiments, the image generation layer 20 may include a quantum dot light emitting diode. For example, the emission layer of the image generation layer 20 may include an organic material, an inorganic material, a quantum dot, an organic material and a quantum dot, or an inorganic material and a quantum dot.

[0068] The input sensing layer 40 may obtain coordinate information according to an external input (e.g., a touch event). The input sensing layer 40 may include a sensing electrode (e.g., a touch electrode) and a trace connected to the sensing electrode. The input sensing layer 40 may be disposed on the image generation layer 20. The input sensing layer 40 may sense an external input by using a mutual capacitance method or / and a self capacitance method.

[0069] The input sensing layer 40 may be directly formed on the image generating layer 20, or may be separately formed and then bonded to the image generating layer 20 through an adhesive layer such as an optically transparent adhesive layer. For example, the input sensing layer 40 may be formed after a process of forming the image generating layer 20 is performed, and in such an embodiment, an adhesive layer may not be disposed between the input sensing layer 40 and the image generating layer 20 (or the adhesive layer may be omitted). Figure 2 An embodiment is shown in which the input sensing layer 40 is disposed between the image generating layer 20 and the optical functional layer 50 , and in some embodiments, the input sensing layer 40 may be disposed on the optical functional layer 50 .

[0070] The optical function layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (e.g., external light) incident on the display panel 10 from the outside via the cover window 60. The anti-reflection layer may include a retarder and a polarizer. In some embodiments, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged in consideration of the color of the light emitted from each of the light emitting diodes.

[0071] In order to increase the transmittance of the opening area OA, the display panel 10 may include a panel hole 10H (e.g., an opening) passing through some layers of the display panel 10. The panel hole 10H may include a first hole 20H, a second hole 40H, and a third hole 50H that penetrate (or extend through) the image generation layer 20, the input sensing layer 40, and the optical function layer 50, respectively. The first hole 20H in the image generation layer 20, the second hole 40H in the input sensing layer 40, and the third hole 50H in the optical function layer 50 may overlap with each other (e.g., may be aligned with each other in the thickness direction of the display panel 10) to form the panel hole 10H in the display panel 10.

[0072] The cover window 60 may be disposed over the display panel 10. The cover window 60 may be bonded to the display panel 10 via an adhesive layer, such as an optically transparent adhesive layer OCA disposed between the cover window 60 and the display panel 10. The cover window 60 may cover the first hole 20H in the image generation layer 20, the second hole 40H in the input sensing layer 40, and the third hole 50H in the optical function layer 50.

[0073] The cover window 60 may include a glass material or a plastic material. The glass material may include ultra-thin glass. The plastic material may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0074] The opening area OA may be a type of component area (eg, a sensor area, a camera area, a speaker area, etc.) in which the components 70 for providing various functions to the electronic device 1 are arranged.

[0075] The component 70 may include an electronic component. For example, the component 70 may be an electronic component that uses (e.g., senses) light or sound. For example, the electronic component may include a sensor that uses light (such as an infrared sensor), a camera that captures an image by receiving light, a sensor that outputs and senses light or sound to measure distance or recognize fingerprints, etc., a small lamp that outputs light, or a speaker that outputs sound. The electronic component that uses light can use light in various wavelength bands, such as visible light, infrared light, ultraviolet light, etc. The opening area OA corresponds to an area through which light or / and sound that is output from the component 70 to the outside or travels from the outside to the electronic component can pass.

[0076] Figure 3 is a schematic plan view of a display panel according to an embodiment.

[0077] Reference Figure 3 , the display panel 10 may have an opening area OA, a display area DA, a middle area MA, and an outer area PA.

[0078] The display panel 10 may include a plurality of pixels P arranged in a display area DA, and the display panel 10 may display an image by using light emitted from each of the pixels P. Each of the pixels P may emit red light, green light, or blue light by using a display element such as a light emitting diode. The display element of each of the pixels P may be electrically connected to a scan line SL and a data line DL.

[0079] A scan driver 2100 that provides a scan signal to each of the pixels P, a data driver 2200 that provides a data signal to each of the pixels P, and a first main power line and a second main power line configured to provide a first power voltage and a second power voltage, respectively, may be arranged in the external area PA. The scan driver 2100 may be arranged on both sides, with the display area DA between the two sides. In such an embodiment, the pixel P arranged on the left side of the opening area OA may be connected to the scan driver 2100 arranged on the left side, and the pixel P arranged on the right side of the opening area OA may be connected to the scan driver 2100 arranged on the right side. In some embodiments, the scan driver 2100 may be arranged only on one side of the external area PA.

[0080] The middle area MA may surround the opening area OA (e.g., may extend around the periphery of the opening area OA). The middle area MA is an area in which display elements (such as light-emitting diodes that emit light) are not arranged, and traces may pass through the middle area MA, and the traces are configured to provide signals to pixels P disposed around the opening area OA. For example, the data line DL and / or the scan line SL pass through the display area DA, and portions of the data line DL and / or the scan line SL may bypass the middle area MA along the edge of the panel hole formed in the opening area OA. Figure 3 In the embodiment shown in , the data lines DL cross the display area DA in the second direction (e.g., the y direction), and some of the data lines DL bypass the middle area MA to partially surround the opening area OA. The scan lines SL cross the display area DA in the first direction (e.g., the x direction), and may be spaced apart from each other with the opening area OA interposed therebetween. In an embodiment, the scan lines SL may be connected to each other via a connection line that bypasses the middle area MA to partially surround the opening area OA.

[0081] Figure 3 The data driver 2200 is shown to be arranged adjacent to one side of the substrate 100, but according to some embodiments, the data driver 2200 may be provided on a printed circuit board electrically connected to a pad arranged on one side of the display panel 10. The printed circuit board may be flexible, and a portion of the printed circuit board may be bent to be provided under the rear surface of the substrate 100.

[0082] Figure 4 is a schematic equivalent circuit diagram of one pixel included in a display panel according to an embodiment.

[0083] Reference Figure 4 , one pixel P may include a pixel circuit PC and an organic light emitting diode OLED as a display element connected to the pixel circuit PC.

[0084] The pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. Each of the pixels P may emit, for example, red light, green light, blue light, or white light via an organic light emitting diode OLED.

[0085] The first transistor T1 as a driving thin film transistor is connected to the driving voltage line PL and the storage capacitor Cst, and may be configured to control a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to a voltage stored in the storage capacitor Cst.

[0086] The second transistor T2 as a switching thin film transistor is connected to the scan line SL and the data line DL, and can be configured to transmit a data voltage input from the data line DL to the first transistor T1 according to a switching voltage input from the scan line SL. The storage capacitor Cst is connected to the second transistor T2 and the driving voltage line PL, and can store a voltage corresponding to a difference between a voltage received from the second transistor T2 and a first power voltage ELVDD supplied to the driving voltage line PL.

[0087] The organic light emitting diode OLED may emit light with a certain brightness according to the driving current. An opposite electrode (eg, a cathode) of the organic light emitting diode OLED may receive a second power voltage ELVSS.

[0088] Figure 4 An embodiment in which the pixel circuit PC includes two thin film transistors and one storage capacitor is shown, but the present disclosure is not limited thereto. The number of thin film transistors and the number of storage capacitors may vary according to the design of the pixel circuit PC. For example, in addition to two thin film transistors, the pixel circuit PC may also include at least four thin film transistors.

[0089] Figure 5 and Figure 6 is a schematic plan view of a portion of a display panel according to an embodiment. Figure 5 The traces (eg, data lines DL and signal lines SL) adjacent to the opening area OA are schematically shown. Figure 6 The trench G arranged in the middle area MA is schematically shown.

[0090] Reference Figure 5 and Figure 6 , the middle area MA may be arranged between the opening area OA and the display area DA. A plurality of pixels P may be arranged in the display area DA. Figure 3 ), the pixels P adjacent to the opening area OA may be spaced apart from each other with the opening area OA interposed therebetween. For example, in a plan view, the pixels P may be spaced apart from each other above and below the opening area OA, or may be spaced apart from each other on the left and right sides of the opening area OA.

[0091] Among the traces supplying signals to the pixels P, traces (e.g., data lines DL and signal lines SL) adjacent to the opening area OA may bypass the opening area OA. Among the data lines DL passing through the display area DA, some data lines DL adjacent to the opening area OA may extend in the second direction (e.g., y direction) to provide data signals to the pixels P disposed above and below the opening area OA, and may bypass the middle area MA along the edge of the opening area OA. Among the scan lines SL, some scan lines SL passing through the display area DA may extend in the first direction (e.g., x direction) to provide scan signals to the pixels P disposed on the left and right of the opening area OA, and may bypass the middle area MA along the edge of the opening area OA.

[0092] One or more grooves G may be arranged in the middle area MA. In this regard, Figure 6 An embodiment is shown in which three grooves G are arranged spaced apart from each other in the middle area MA. The groove G may have a shape concave in the thickness direction (eg, z direction) by removing a portion from one or more layers.

[0093] When viewed in a direction perpendicular to the substrate 100, the grooves G may each have a closed loop shape surrounding (eg, extending around) the opening area OA. For example, the plurality of grooves G may have concentric circle shapes that share the opening area OA and the center C but have different diameters.

[0094] The groove G may be arranged closer to the opening area OA than the bypassing portions of the data lines DL and the scan lines SL bypassing the opening area OA. For example, when viewed in a direction perpendicular to the substrate 100, the bypassing portions of the data lines DL and the scan lines SL may be arranged closer to the display area DA than the groove G.

[0095] In some embodiments, the display panel may include one or more spacers in the middle area MA instead of the groove G. The one or more spacers each have a shape protruding from the peripheral area in the thickness direction (e.g., z direction), and may each have a tip protruding in a direction parallel to the substrate 100. When viewed in a direction perpendicular to the substrate 100, the one or more spacers may each have a closed loop shape surrounding the opening area OA.

[0096] The groove G or one or more partitions may cut off or separate an organic material layer such as an intermediate layer, thereby reducing or blocking a path through which moisture or the like may penetrate from a panel hole arranged in the opening area OA to a display element.

[0097] Figure 7 is a schematic cross-sectional view of a portion of a display panel according to an embodiment. Figure 7 It is along Figure 6 Schematic diagram of a cross-section of the display panel taken along line II-II'.

[0098] Reference Figure 7 , a pixel circuit PC and an organic light emitting diode OLED as a display element electrically connected to the pixel circuit PC may be arranged in the display area DA. The pixel circuit PC may be disposed on the substrate 100, and the organic light emitting diode OLED may be disposed on the pixel circuit PC. The pixel circuit PC may include a thin film transistor TFT disposed on the substrate 100 and a storage capacitor Cst.

[0099] The substrate 100 may include a polymer resin or a glass material. The substrate 100 may be formed into a multi-layer structure. For example, the substrate 100 may include a base layer and a barrier layer.

[0100] The base layer may include a polymer resin, which may include polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, and the like.

[0101] The barrier layer prevents penetration of foreign substances, and may be a single layer or a multilayer structure each including an inorganic insulating material such as silicon nitride, silicon nitride oxide, and silicon oxide.

[0102] The buffer layer 201 may be formed on the substrate 100 to prevent impurities from penetrating into the semiconductor layer Act of the thin film transistor TFT. The buffer layer 201 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and may be a single layer or a multilayer structure each including an inorganic insulating material.

[0103] The pixel circuit PC may be disposed on the buffer layer 201. The pixel circuit PC may include a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0104] Figure 7 The thin film transistor TFT shown in FIG. Figure 4 In the illustrated embodiment, a top-gate transistor is shown in which the gate electrode GE is disposed on the semiconductor layer Act and the gate insulating layer 203 is interposed between the gate electrode GE and the semiconductor layer Act, but according to some embodiments, the thin film transistor TFT may be a bottom-gate transistor.

[0105] The semiconductor layer Act may include polycrystalline silicon. In another embodiment, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, or an organic semiconductor. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed into a multilayer structure or a single layer each including the above materials.

[0106] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The gate insulating layer 203 may be a single layer or a multilayer structure each including the above materials.

[0107] Each of the source electrode SE and the drain electrode DE may include a material having excellent electrical conductivity. Each of the source electrode SE and the drain electrode DE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed into a multilayer structure or a single layer each including the above materials. In an embodiment, each of the source electrode SE and the drain electrode DE may include a multilayer structure of Ti / Al / Ti. In an embodiment, at least one of the source electrode SE and the drain electrode DE may be omitted, and the impurity region of the semiconductor layer Act may be used as a source or a drain.

[0108] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 that overlap each other, with the first interlayer insulating layer 205 interposed between the lower electrode CE1 and the upper electrode CE2. The storage capacitor Cst may overlap with the thin film transistor TFT. In this regard, Figure 7 An embodiment in which the gate electrode GE of the thin film transistor TFT and the lower electrode CE1 of the storage capacitor Cst are integrally formed is shown. In some embodiments, the storage capacitor Cst may not overlap with the thin film transistor TFT. The upper electrode CE2 of the storage capacitor Cst may be covered by the second interlayer insulating layer 207. The upper electrode CE2 of the storage capacitor Cst may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer structure or a single layer each including the above materials.

[0109] Each of the first interlayer insulating layer 205 and the second interlayer insulating layer 207 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. Each of the first interlayer insulating layer 205 and the second interlayer insulating layer 207 may be a single layer or multilayer structure each including the above materials.

[0110] The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst may be covered by the planarization insulating layer 209. The planarization insulating layer 209 may include an organic insulating material, such as a general polymer (such as polystyrene (PS)), polymethyl methacrylate (PMMA), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and a blend thereof. In an embodiment, the planarization insulating layer 209 may include polyimide. In another embodiment, the planarization insulating layer 209 may include an inorganic insulating material, or may include an inorganic insulating material and an organic insulating material. The planarization insulating layer 209 may have a substantially flat upper surface.

[0111] The organic light emitting diode OLED may be disposed on the planarization insulating layer 209. The organic light emitting diode OLED may include a pixel electrode 221, an opposite electrode 223, and an intermediate layer 222 disposed between the pixel electrode 221 and the opposite electrode 223.

[0112] The pixel electrode 221 may be formed on the planarization insulating layer 209. The pixel electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 221 may include a reflective film containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. In some embodiments, the pixel electrode 221 may also include a reflective film containing ITO, IZO, ZnO or indium oxide (e.g., In) above or / and below the reflective film. 2 O 3 ) layer.

[0113] The pixel defining film 211 may be formed on the pixel electrode 221. The pixel defining film 211 may have an opening that exposes the upper surface of the pixel electrode 221 but covers the edge of the pixel electrode 221. The pixel defining film 211 may include an organic insulating material. In another embodiment, the pixel defining film 211 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. In another embodiment, the pixel defining film 211 may include an organic insulating material and an inorganic insulating material.

[0114] The pixel defining film 211 may be black. The pixel defining film 211 may include a light blocking material. The light blocking material may include a resin or a slurry including a black dye (such as carbon black), a carbon nanotube, a metal particle (such as nickel (Ni), aluminum (Al), molybdenum (Mo) and alloys thereof), a metal oxide particle (e.g., chromium oxide) or a metal nitride particle (e.g., chromium nitride). When the pixel defining film 211 includes a light blocking material, the reflection of external light by the metal structure disposed under the pixel defining film 211 may be reduced.

[0115] The intermediate layer 222 includes an emission layer. The intermediate layer 222 may include a first functional layer disposed below the emission layer and / or a second functional layer disposed above the emission layer. The emission layer may include a polymer or a low molecular weight organic material that emits light of a specific color.

[0116] The first functional layer may be a single layer or a multilayer structure. For example, when the first functional layer includes a polymer material, the first functional layer may include poly (3,4) -ethylene - dihydroxythiophene or polyaniline as a hole transport layer having a single layer structure. When the first functional layer includes a low molecular weight material, the first functional layer may include a hole injection layer and a hole transport layer.

[0117] The second functional layer may be a single layer or a multilayer structure. The second functional layer may include an electron transport layer and / or an electron injection layer. In some embodiments, the second functional layer may be omitted.

[0118] The emission layer of the intermediate layer 222 may be arranged in each pixel in the display area DA. For example, the emission layer may be patterned to correspond to the pixel electrode 221. The first functional layer and / or the second functional layer of the intermediate layer 222 may be formed in common across a plurality of organic light emitting diodes OLED. The first functional layer and / or the second functional layer of the intermediate layer 222 may be arranged not only in the display area DA but also in the intermediate area MA.

[0119] The relative electrode 223 may be disposed on the intermediate layer 222. The relative electrode 223 may include a conductive material having a low work function. For example, the relative electrode 223 may include a (semi) transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. In another embodiment, the relative electrode 223 may also include a (semi) transparent layer including ITO, IZO, ZnO, or indium oxide (e.g., In) on the (semi) transparent layer including the above materials. 2 O 3) layer. The opposing electrode 223 may be commonly formed across a plurality of organic light emitting diodes OLED. The opposing electrode 223 may be arranged not only in the display area DA but also in the middle area MA.

[0120] The capping layer 230 may be disposed on the opposite electrode 223. For example, the capping layer 230 may include lithium fluoride (LiF) and may be formed by a thermal deposition method. According to the principle of constructive interference, the capping layer 230 may improve the luminous efficiency of the organic light emitting diode OLED. The capping layer 230 may be an organic capping layer including an organic material, an inorganic capping layer including an inorganic material, or a composite capping layer including an organic material and an inorganic material. In some embodiments, the capping layer 230 may be omitted.

[0121] The spacer 213 may be formed on the pixel defining film 211. The spacer 213 may include an organic insulating material such as polyimide. In another embodiment, the spacer 213 may include an inorganic insulating material such as silicon nitride or silicon oxide, or may include an organic insulating material and an inorganic insulating material.

[0122] The spacer 213 may include a material different from that of the pixel defining film 211. In another embodiment, the spacer 213 may include the same material as that of the pixel defining film 211, and in such an embodiment, the pixel defining film 211 and the spacer 213 may be formed together in a mask process using a half-tone mask, etc. In an embodiment, each of the pixel defining film 211 and the spacer 213 may include polyimide.

[0123] The organic light emitting diode OLED may be covered by an encapsulation layer 300. The encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Figure 7 An embodiment is shown in which the encapsulation layer 300 includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 disposed between the first and second inorganic encapsulation layers 310 and 330. In some embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and their stacking order may vary.

[0124] Each of the first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide (ZnO x , which can be ZnO or ZnO 2 ), at least one inorganic material among silicon oxide, silicon nitride, and silicon oxynitride. Each of the first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 may be a single layer or a multilayer structure each including the above materials.

[0125] The organic encapsulation layer 320 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide, and polyethylene. In an embodiment, the organic encapsulation layer 320 may include acrylate.

[0126] The input sensing layer 40 may be disposed on the display panel 10. For example, Figure 7 An embodiment is shown in which the input sensing layer 40 is directly formed on the display panel 10 and contacts the encapsulation layer 300 .

[0127] Figure 8 is a schematic plan view of an input sensing layer of a display panel according to an embodiment, and Fig. 9 is a schematic plan view of a portion of an input sensing layer of a display panel according to an embodiment. Figure 8 The crack sensing portion 900 and the crack sensing lines CNL1 and CNL2 arranged in the same layer as the input sensing layer 40 are schematically shown, and Fig. 9 It can be corresponding to Figure 8 Magnified view of part III.

[0128] Reference Figure 8 and Fig. 9 , the display panel 10 may include an input sensing layer 40. The input sensing layer 40 may include a first sensing electrode SP1, a second sensing electrode SP2, first, second, and third input sensing lines TSL1, TSL2, and TSL3, and first, second, and third input sensing pads TPD1, ​​TPD2, and TPD3.

[0129] The first sensing electrodes SP1 and the second sensing electrodes SP2 may be arranged in the display area DA. The first sensing electrodes SP1 may be connected to each other in a first direction (e.g., an x ​​direction), and the second sensing electrodes SP2 may be connected to each other in a second direction (e.g., a y direction). The first sensing electrodes SP1 adjacent to each other in the first direction may be electrically connected to each other via the first connection electrode CP1, and the second sensing electrodes SP2 adjacent to each other in the second direction may be electrically connected to each other via the second connection electrode CP2.

[0130] The first and second sensing electrodes SP1 and SP2 may be arranged apart from each other and the first and second connection electrodes CP1 and CP2 may overlap each other when viewed in a direction perpendicular to the substrate 100. The first and second connection electrodes CP1 and CP2 may perpendicularly cross each other.

[0131] One end of the first sensing electrode SP1 connected to each other in the first direction (e.g., the x direction) may be connected to the second input sensing pad TPD2 via the second input sensing line TSL2. One end of the second sensing electrode SP2 connected to each other in the second direction (e.g., the y direction) may be connected to the first input sensing pad TPD1 via the first input sensing line TSL1, and the other end may be connected to the third input sensing pad TPD3 via the third input sensing line TSL3. The first input sensing pad TPD1, ​​the second input sensing pad TPD2, and the third input sensing pad TPD3 may be electrically connected to the pads provided on the printed circuit board, and thus an electrical signal may be sent to the input sensing control unit. In some embodiments, the first input sensing line TSL1 and the first input sensing pad TPD1 are omitted, and therefore, only one end of the second sensing electrode SP2 may be connected to the third input sensing pad TPD3.

[0132] The second input sensing pad TPD2 may be arranged separately from the first input sensing pad TPD1 and the third input sensing pad TPD3. For example, the second input sensing pad TPD2 may be arranged on the left side of the display panel 10, and the first input sensing pad TPD1 and the third input sensing pad TPD3 may be arranged on the right side of the display panel 10. The data driver pad that electrically connects the data driver to the data line may be arranged between the second input sensing pad TPD2 and the first input sensing pad TPD1. An embodiment in which the second input sensing line TSL2 and the second input sensing pad TPD2 are arranged on the left side of the display panel 10 and the third input sensing line TSL3, the first input sensing pad TPD1 and the third input sensing pad TPD3 are arranged on the right side of the display panel 10 is shown. However, the positions of the first input sensing line TSL1, the second input sensing line TSL2 and the third input sensing line TSL3 and the first input sensing pad TPD1, ​​the second input sensing pad TPD2 and the third input sensing pad TPD3 may be changed.

[0133] The input sensing layer 40 may sense an external input by using a mutual capacitance method and / or a self-capacitance method. For example, the input sensing layer 40 may be driven using a mutual capacitance method during a first interval (e.g., a first time period), and the input sensing layer 40 may be driven using a self-capacitance method during a second interval (e.g., a second time period) to calculate the coordinates of the external input. When the input sensing layer 40 is driven by using a mutual capacitance method, a driving signal may be applied to the first sensing electrode SP1 via the second input sensing line TSL2, and a sensing signal may be sent from the second sensing electrode SP2 to the input sensing control unit via the first input sensing line TSL1 and the third input sensing line TSL3.

[0134] like Figure 8As shown in FIG. 9 , the display panel 10 may include a crack sensing portion 900 , first and second crack sensing lines CNL1 and CNL2 , and first, second, third, and fourth crack sensing pads PD1 , PD2 , PD3 , and PD4 .

[0135] The crack sensing portion 900 may include a crack sensing pattern 930 disposed in the middle area MA to be adjacent to the opening area OA, a first connection line 910 configured to connect one end of the crack sensing pattern 930 to the first crack sensing line CNL1, and a second connection line 920 configured to connect the other end of the crack sensing pattern 930 to the second crack sensing line CNL2. The crack sensing pattern 930 may connect the first connection line 910 to the second connection line 920 by bypassing the opening area OA, and may have a ring shape with one side (or a portion) opened.

[0136] Figure 8 An embodiment in which the crack sensing pattern 930 has a ring shape opening toward the upper side of the display panel 10 is shown. In such an embodiment, the first connection line 910 and the second connection line 920 extend in the second direction (e.g., the y direction), but the present disclosure is not limited thereto. Depending on the position of the opening area OA and the arrangement of the surrounding components, the crack sensing pattern 930 may have a ring shape opening toward the left or right side thereof. In such an embodiment, the first connection line 910 and the second connection line 920 may extend in the first direction (e.g., the x direction).

[0137] The first crack sensing line CNL1 may be connected to the first crack sensing pad PD1 and the fourth crack sensing pad PD4, and the second crack sensing line CNL2 may be connected to the second crack sensing pad PD2 and the third crack sensing pad PD3. In an embodiment, the first crack sensing line CNL1 and the second crack sensing line CNL2 may be arranged outside the second input sensing line TSL2 and the third input sensing line TSL3.

[0138] Each of the first crack sensing pad PD1 and the third crack sensing pad PD3 may be an input terminal, and each of the second crack sensing pad PD2 and the fourth crack sensing pad PD4 may be an output terminal. For example, an electrical signal input to the first crack sensing pad PD1 may be output to the second crack sensing pad PD2 via the first crack sensing line CNL1, the crack sensing portion 900, and the second crack sensing line CNL2. An electrical signal input to the third crack sensing pad PD3 may be output to the fourth crack sensing pad PD4 via the second crack sensing line CNL2, the crack sensing portion 900, and the first crack sensing line CNL1.

[0139] When the crack sensing pattern 930 is damaged, the electrical signals output to the second and fourth crack sensing pads PD2 and PD4 may be less than a reference value or may have a value of zero (0). Therefore, it may be determined whether a crack occurs in a region adjacent to the opening region OA.

[0140] Fig. 10A and Fig. 10B is a schematic plan view of a first conductive layer and a second conductive layer of an input sensing layer according to an embodiment, and Fig. 10C is a schematic cross-sectional view of an input sensing layer according to an embodiment. Fig. 10A and Fig. 10B Each corresponds to Figure 8 Part III, and Fig. 10C It is along Fig. 9 FIG. 4 is a schematic cross-sectional view of the input sensing layer 40 taken along line IV-IV′ in FIG.

[0141] Reference Fig. 10A and Fig. 10B , the first sensing electrode SP1 and the second sensing electrode SP2 may be disposed in the same layer. Fig. 10A The first conductive layer 410 shown in FIG. 4 may include a first connection electrode CP1, and Fig. 10B The second conductive layer 420 shown in FIG. 4 may include a first sensing electrode SP1 , a second sensing electrode SP2 , and a second connection electrode CP2 .

[0142] The second sensing electrodes SP2 adjacent to each other in the second direction (e.g., the y direction) may be electrically connected to each other through the second connection electrode CP2 provided in the same layer as the second sensing electrodes SP2. The second sensing electrodes SP2 connected to each other in the second direction (e.g., the y direction) and the second connection electrode CP2 connecting the second sensing electrodes SP2 to each other may be integrally provided.

[0143] The first sensing electrodes SP1 adjacent to each other in the first direction (e.g., the x direction) may be electrically connected to each other through the first connection electrode CP1 disposed in a different layer from the first sensing electrode SP1. In some embodiments, the first sensing electrode SP1, the second sensing electrode SP2, and the first connection electrode CP1 may be disposed in the same layer, and the second connection electrode CP2 may be disposed in a different layer from the first sensing electrode SP1 and the second sensing electrode SP2.

[0144] Reference Fig. 10C, the intermediate insulating layer 403 may be disposed between the first conductive layer 410 and the second conductive layer 420. The first sensing electrode SP1 disposed in the second conductive layer 420 may be connected to the first connection electrode CP1 disposed in the first conductive layer 410 via a contact hole (e.g., contact opening) CNT in the intermediate insulating layer 403. The second conductive layer 420 may be covered by the upper insulating layer 405, and the lower insulating layer 401 may be disposed under the first conductive layer 410.

[0145] In an embodiment, the first sensing electrode SP1 and the first connection electrode CP1 may be arranged in the first conductive layer 410, and the second sensing electrode SP2 and the second connection electrode CP2 may be arranged in the second conductive layer 420. In such an embodiment, the intermediate insulating layer 403 may not include a separate contact hole, and the first sensing electrode SP1 and the second sensing electrode SP2 may be electrically insulated from the intermediate insulating layer 403 between the first sensing electrode SP1 and the second sensing electrode SP2.

[0146] Each of the first conductive layer 410 and the second conductive layer 420 may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), and alloys thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide, indium zinc oxide, zinc oxide, or indium tin zinc oxide. In addition, the transparent conductive layer may include a conductive polymer (such as PEDOT), a metal nanowire, a carbon nanotube, graphene, etc.

[0147] Each of the lower insulating layer 401 , the intermediate insulating layer 403 , and the upper insulating layer 405 may be an organic insulating layer or an inorganic insulating layer. In some embodiments, the lower insulating layer 401 may be omitted, and the first conductive layer 410 may be directly disposed on the encapsulation layer 300 .

[0148] In an embodiment, each of the first sensing electrode SP1, the second sensing electrode SP2, the first connection electrode CP1, and the second connection electrode CP2 may have a mesh structure including a plurality of holes (eg, a plurality of openings) The plurality of holes may be arranged to overlap with the emission region of the display element.

[0149] Fig.11 is a schematic cross-sectional view of a display panel according to an embodiment, Fig.12 is a schematic cross-sectional view of a portion of a display panel according to an embodiment, and Fig.13 is a schematic cross-sectional view of a portion of a display panel according to an embodiment. Fig.11 It is along Figure 6 A schematic cross-sectional view of the display panel taken along the line V-V' in FIG. Fig.12 yes Fig.11A schematic cross-sectional view of a portion VI of a display panel shown in FIG. 1 , and Fig.13 yes Fig.11 Schematic cross-sectional view of portion VII of the display panel shown in FIG.

[0150] Reference Fig.11 The display panel 10 may have an opening area OA in which the panel hole 10H is arranged, a display area DA, and an intermediate area MA arranged between the opening area OA and the display area DA. The pixel circuit PC on the substrate 100 and the organic light emitting diode OLED electrically connected to the pixel circuit PC may be arranged in the display area DA.

[0151] The substrate 100 may be a multilayer structure. For example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104 sequentially stacked on each other. Each of the first base layer 101 and the second base layer 103 may include a polymer resin. Each of the first barrier layer 102 and the second barrier layer 104 prevents penetration of foreign matter and may be a single layer or multilayer structure each including an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide.

[0152] The buffer layer 201 may be disposed on the substrate 100, and the pixel circuit PC may be disposed on the buffer layer 201. The pixel circuit PC may include a thin film transistor and a storage capacitor. A planarization insulating layer 209 may be disposed on the pixel circuit PC, and the organic light emitting diode OLED may be disposed on the planarization insulating layer 209. The organic light emitting diode OLED may include a pixel electrode 221, an opposing electrode 223, and an intermediate layer 222 disposed between the pixel electrode 221 and the opposing electrode 223. The organic light emitting diode OLED may be covered by an encapsulation layer 300.

[0153] The middle area MA may include a first sub middle area SMA1 relatively adjacent to the display area DA and a second sub middle area SMA2 relatively adjacent to the opening area OA.

[0154] The first sub middle area SMA1 may be an area where traces (eg, data lines DL and signal lines SL) pass. Fig.11 The data lines DL and the scan lines SL shown in may each correspond to a bypass portion bypassing the opening area OA. For example, the first sub-middle area SMA1 may be a line area or a bypass area through which the data lines DL and the scan lines SL pass.

[0155] The data lines DL may be arranged alternately with an insulating layer interposed therebetween. When the data lines DL adjacent to each other are disposed above and below the insulating layer (eg, the second interlayer insulating layer 207), the gap (eg, spacing) between the adjacent data lines DL may be reduced, and the width of the middle area MA may be reduced.

[0156] Fig.11 An embodiment is shown in which the scan line SL is arranged between the gate insulating layer 203 and the first interlayer insulating layer 205, and the data line DL is arranged between the first interlayer insulating layer 205 and the second interlayer insulating layer 207 and between the second interlayer insulating layer 207 and the planarizing insulating layer 209, but the present disclosure is not limited thereto. In some embodiments, the data line DL may be arranged between the second interlayer insulating layer 207 and the planarizing insulating layer 209, and the scan line SL may be arranged between the first interlayer insulating layer 205 and the second interlayer insulating layer 207.

[0157] The shielding layer 80 may be disposed on the data line DL or / and the scan line SL located in the first sub-middle area SMA1. The shielding layer 80 may be arranged to overlap the data line DL or / and the scan line SL, thereby preventing the data line DL or / and the scan line SL from being visible to the user. In an embodiment, the shielding layer 80 may include metal.

[0158] One or more grooves G (see Figure 6 ) or a partition may be arranged in the second sub-middle area SMA2. Fig.11 An embodiment of a display panel having four grooves G in the second sub-middle area SMA2 is shown, but the number of grooves G may vary.

[0159] Each of the grooves G may be formed in a multilayer film including a first layer and a second layer, the first layer and the second layer including materials different from each other. Fig.12 An embodiment in which the groove G is formed in a sub-layer provided on the substrate 100 is shown.

[0160] Reference Fig.11 and Fig.12 , the groove G may be formed by removing a portion of the second barrier layer 104 and a portion of the second base layer 103. The hole (e.g., opening) H1 defined in the second barrier layer 104 and the recess R1 defined in the second base layer 103 may be spatially connected to form the groove G. The second base layer 103 may correspond to a first layer of the multilayer film, and the second barrier layer 104 may correspond to a second layer of the multilayer film.

[0161] In the process of forming the groove G, a portion of the buffer layer 201 on the second barrier layer 104 may be removed together with the second barrier layer 104 to define the hole H1. Although the buffer layer 201 and the second barrier layer 104 are described as separate components, the buffer layer 201 on the substrate 100 may be a sublayer of the second barrier layer 104 having a multi-layer structure.

[0162] The portion of the groove G that penetrates (or extends through) the second barrier layer 104 (e.g., the width of the hole H1) may be smaller than the portion of the groove G that passes through the second base layer 103 (e.g., the width of the recess R1). The width (or diameter) W2 of the hole H1 may be smaller than the width (or diameter) W1 of the recess R1, and the groove G may have an undercut shape.

[0163] Therefore, the side surface of the second barrier layer 104 defining the hole H1 may protrude further toward the center of the groove G than the side surface of the second base layer 103 defining the recess R1. The portion of the second barrier layer 104 protruding toward the center of the groove G may form a pair of protrusions (e.g., a pair of tips) PT. The length l of each of the pair of tips PT may be less than about 2.0 μm. In an embodiment, the length l may be in the range of about 1.0 μm to about 1.8 μm.

[0164] The groove G may be formed before the process of forming the intermediate layer 222. The emission layer of the intermediate layer 222 may be arranged in each pixel corresponding to the pixel electrode 221, and a portion 222' of the intermediate layer 222 may extend from the display area DA to the intermediate area MA. For example, the first functional layer 222a and / or the second functional layer 222c may be arranged in the intermediate area MA.

[0165] The portion 222 ′ of the intermediate layer 222 extending to the middle area MA may be separated or cut off by the groove G. Similarly, the opposite electrode 223 and the capping layer 230 may also be separated or cut off by the groove G.

[0166] Fig.11 and Fig.12 An embodiment in which the bottom surface of the groove G is disposed on a virtual plane between the lower surface and the upper surface of the second base layer 103 is shown, but in some embodiments, the bottom surface of the groove G may be coplanar with the lower surface of the second base layer 103. For example, in the etching process for forming the groove G, the depth dp of the recess R1 may be substantially the same as the thickness t of the second base layer 103, and in such an embodiment, the bottom surface of the groove G may be coplanar with the lower surface of the second base layer 103 (for example, may be disposed on the upper surface of the first barrier layer 102). When the depth dp of the recess R1 is the same as the thickness t of the second base layer 103, the recess R1 may be understood as a hole penetrating (or extending through) the second base layer 103.

[0167] like Fig.11 As shown in , the encapsulation layer 300 covering the display element in the display area DA may extend to cover the middle area MA. For example, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may extend from the display area DA to the middle area MA. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be formed by chemical vapor deposition (CVD) or the like, and may have a relatively good step coverage range than the middle layer 222 or the relative electrode 223. Therefore, each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be formed continuously without being cut off by the groove G (for example, each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may extend continuously throughout the groove G). The first inorganic encapsulation layer 310 may cover the inner surface of the groove G. The first inorganic encapsulation layer 310 may be in direct contact with the lower surface of the tip PT protruding from the recess R1 to form an inorganic contact portion where the inorganic materials are in contact with each other. The inorganic contact portion may block or reduce the path for moisture, etc. to penetrate from the boundary of the panel hole 10H.

[0168] like Fig.11 As shown in , the organic encapsulation layer 320 may cover the display area DA, but the end 320E of the organic encapsulation layer 320 may be arranged on one side of the first partition wall 510, and the first partition wall 510 is arranged in the middle area MA. The organic encapsulation layer 320 may be formed by applying and curing a monomer, and the flow of the monomer may be controlled by the first partition wall 510 (e.g., may be blocked by the first partition wall 510). The organic encapsulation layer 320 (e.g., the end 320E of the organic encapsulation layer 320) is arranged spaced apart from the opening area OA, thereby preventing moisture or the like infiltrated from the boundary of the panel hole 10H from traveling through the organic encapsulation layer 320 to the organic light emitting diode OLED of the display area DA.

[0169] The first partition wall 510 may include a plurality of layers. For example, Fig.11 An embodiment is shown in which the first partition wall 510 has a stacked structure including a plurality of layers including a layer having the same material as the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 and a layer having the same material as the planarizing insulating layer 209 and the pixel defining film 211. In some embodiments, some layers of the first partition wall 510 may be omitted, or additional layers may be added.

[0170] The planarization layer 720 may be arranged in the middle area MA. The planarization layer 720 may include an organic insulating material. The planarization layer 720 may include a polymer material. For example, the planarization layer 720 may include a silicon resin, an acrylic resin, an epoxy resin, polyimide, and polyethylene. The polymer material may be transparent.

[0171] The planarization layer 720 may cover at least one groove G disposed in the middle area MA. The planarization layer 720 may cover at least one area in the middle area MA that is not covered by the organic encapsulation layer 320, and thus may improve the display panel 10 around the opening area OA (see Figure 2 ) flatness. Therefore, it is possible to prevent or mitigate the flatness of the input sensing layer 40 (see, for example Figure 2 ) and / or an optically functional layer 50 (see e.g. Figure 2 ). A portion of the planarization layer 720 may overlap the organic encapsulation layer 320. One end of the planarization layer 720 (e.g., a first end 720E1 adjacent to the display area DA) may be disposed above the organic encapsulation layer 320. For example, the first end 720E1 of the planarization layer 720 may be disposed closer to the display area DA than the end 320E of the organic encapsulation layer 320.

[0172] The first insulating layer 710 may be disposed directly below the planarization layer 720. The planarization layer 720 may be in direct contact with the upper surface of the first insulating layer 710. The first insulating layer 710 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The first insulating layer 710 may be in direct contact with the encapsulation layer 300. For example, the first insulating layer 710 may be in direct contact with the upper surface of the second inorganic encapsulation layer 330. The first insulating layer 710 may include the same material as the material of the second inorganic encapsulation layer 330, or may include a material different from the material of the second inorganic encapsulation layer 330. When the first insulating layer 710 includes the same material as the material of the second inorganic encapsulation layer 330 (e.g., silicon nitride), the specific composition ratio (e.g., the content ratio of silicon and nitrogen, etc.) may be different, and an interface may be formed between the first insulating layer 710 and the second inorganic encapsulation layer 330.

[0173] The second insulating layer 740 may be disposed on the planarization layer 720, for example, directly on the planarization layer 720. The second insulating layer 740 may include an inorganic insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The first insulating layer 710 and the second insulating layer 740 may include the same or different materials. The thickness of the second insulating layer 740 may be greater than the thickness of the first insulating layer 710. In another embodiment, the thickness of the second insulating layer 740 may be less than or equal to the thickness of the first insulating layer 710.

[0174] In an embodiment, insulating layers (e.g., a first insulating layer 710 and a second insulating layer 740) may be disposed above and below the planarization layer 720 to prevent or reduce infiltration of moisture and / or lifting of the film during and after the process of forming the planarization layer 720.

[0175] The planarization layer 720 may form a step difference with a layer located below the planarization layer 720. Fig.11 and Fig.13 , the first end 720E1 of the planarization layer 720 may form a step difference with a layer located below the planarization layer 720 (e.g., an upper surface of the first insulating layer 710). In the operation of manufacturing the display panel 10 or / and the operation of using the display panel 10 after manufacturing the display panel 10, in order to prevent the problem of the planarization layer 720 being separated or peeled off from the layer located below the planarization layer 720 due to the step difference, the first end 720E1 of the planarization layer 720 may be covered by the second insulating layer 740 and / or the covering layer 730. The covering layer 730 may include a material different from that of each of the first insulating layer 710 and the second insulating layer 740. For example, the covering layer 730 may include the same material as that of the first conductive layer 410 and / or the second conductive layer 420 of the input sensing layer 40 arranged in the display area DA. In an embodiment, the covering layer 730 may include a metal layer.

[0176] The third width W3 of the cover layer 730 may be in the range of about tens of μm to about hundreds of μm. For example, the third width W3 of the cover layer 730 may be in the range of about 50 μm to about 500 μm, in the range of about 50 μm to about 400 μm, in the range of about 50 μm to about 300 μm, in the range of about 50 μm to about 200 μm, in the range of about 50 μm to about 100 μm, or in the range of about 60 μm to about 100 μm.

[0177] The cover layer 730 may be disposed on the planarization layer 720. For example, the cover layer 730 may be directly disposed on the second insulating layer 740. The first end 730E1 of the cover layer 730 may be disposed closer to the display area DA than the first end 720E1 of the planarization layer 720. Therefore, when viewed in a direction perpendicular to the substrate 100, the first portion of the cover layer 730 including the first end 730E1 may not overlap with the planarization layer 720. The second end 730E2 of the cover layer 730 may be disposed closer to the opening area OA than the first end 720E1 of the planarization layer 720. Therefore, when viewed in a direction perpendicular to the substrate 100, the second portion of the cover layer 730 including the second end 730E2 may overlap with the planarization layer 720. The width W31 of the first portion of the cover layer 730 may be less than or equal to the width W32 of the second portion of the cover layer 730.

[0178] The third insulating layer 750 and the fourth insulating layer 760 may be disposed on the capping layer 730. The third insulating layer 750 may include an inorganic insulating material, such as silicon oxide, silicon nitride and / or silicon oxynitride. In another embodiment, the third insulating layer 750 may include an organic insulating material. The fourth insulating layer 760 may include an inorganic insulating material or may include an organic insulating material. The fourth insulating layer 760 including an organic insulating material may have a relatively flat upper surface. The organic insulating material may include a photoresist (negative or positive) or a polymer-based organic material.

[0179] At least one of the first insulating layer 710, the second insulating layer 740, the third insulating layer 750, and the fourth insulating layer 760 may include the same material as that of the insulating layer included in the input sensing layer 40. In an embodiment, each of the first insulating layer 710, the second insulating layer 740, the third insulating layer 750, and the fourth insulating layer 760 may be formed by the same process as at least one insulating layer of the input sensing layer 40. For example, Fig.11 As shown in , the first insulating layer 710 may include the same material as the first sub-insulating layer 401a and may be formed integrally with the first sub-insulating layer 401a, which is a part of the lower insulating layer 401 of the input sensing layer 40. The second insulating layer 740 may include the same material as the second sub-insulating layer 401b as a part of the lower insulating layer 401, and may be formed integrally with the second sub-insulating layer 401b. The third insulating layer 750 may include the same material as the middle insulating layer 403 of the input sensing layer 40, and may be formed integrally with the middle insulating layer 403. The fourth insulating layer 760 may include the same material as the upper insulating layer 405 of the input sensing layer 40, and may be formed integrally with the upper insulating layer 405. In an embodiment, each of the first insulating layer 710, the second insulating layer 740, and the third insulating layer 750 may include an inorganic insulating material, and the fourth insulating layer 760 may include an organic insulating material. Herein, when A and B are described as including the same material, this may indicate that A and B are deposited during the same process and are separated or spaced apart by patterning, etc., and have the same stack structure, the same film quality, etc.

[0180] In an embodiment, the cover layer 730 may be disposed in the same layer as the first conductive layer 410 or the second conductive layer 420 of the input sensing layer 40 disposed in the display area DA. Fig.11 An embodiment is shown in which the cover layer 730 is disposed in the same layer as the first conductive layer 410 (eg, a layer between the second insulating layer 740 and the third insulating layer 750 ). In some embodiments, the cover layer 730 may include the same material as that of the first conductive layer 410 .

[0181] The crack sensing pattern 930 may be disposed on (or in) the middle area MA. The crack sensing pattern 930 may be disposed on the planarization layer 720. The crack sensing pattern 930 may be disposed in the same layer as the first conductive layer 410 or the second conductive layer 420 of the input sensing layer 40 disposed in the display area DA. For example, Fig.11 An embodiment is shown in which the crack sensing pattern 930 is disposed in the same layer as the second conductive layer 420 (eg, a layer between the third insulating layer 750 and the fourth insulating layer 760 ). In some embodiments, the crack sensing pattern 930 may include the same material as that of the second conductive layer 420 .

[0182] The panel hole 10H in the display panel 10 may be formed by forming the above-mentioned components and layers on the substrate 100 and then performing a cutting or scribing process. Fig.11 It can be understood as showing a cross section of the display panel 10 in which the panel hole 10H is formed by performing a cutting or scribing process. At the boundary of the opening area OA, the end of the layer disposed on the substrate 100 may be disposed on the same vertical line as the end 100E of the substrate 100 defining the panel hole 10H. For example, the second end 720E2 disposed on the opposite side of the first end 720E1 of the planarization layer 720 may be disposed on the same vertical line as the end 100E of the substrate 100.

[0183] Fig.14A and Fig. 14B is a schematic plan view of a portion of a display panel according to an embodiment. For ease of explanation, Fig.14A and Fig. 14B A fragment of the planarization layer 720 , the capping layer 730 , and the crack sensing portion 900 is shown.

[0184] Reference Fig.14A and Fig. 14B The planarization layer 720 is arranged in the middle area MA and may have a closed loop shape surrounding the opening area OA (eg, extending around the periphery of the opening area OA). The planarization layer 720 is arranged in the middle area MA, but when perpendicular to the substrate 100 (see Fig.11 ), the second end 720E2 of the planarization layer 720 may be substantially identical to a boundary of the opening area OA (eg, may be aligned with a boundary of the opening area OA or may form a boundary of the opening area OA).

[0185] The cover layer 730 may cover the first end 720E1 of the planarization layer 720. For example, when viewed in a direction perpendicular to the substrate 100, the first end 730E1 of the cover layer 730 may be disposed closer to the display area DA than the first end 720E1 of the planarization layer 720, and the second end 730E2 of the cover layer 730 may be disposed closer to the opening area OA than the first end 720E1 of the planarization layer 720. Therefore, when viewed in a direction perpendicular to the substrate 100, a first portion of the cover layer 730 including the first end 730E1 may not overlap with the planarization layer 720, and a second portion of the cover layer 730 including the second end 730E2 may overlap with the planarization layer 720.

[0186] The cover layer 730 may have a closed loop shape to completely cover the first end 720E1 of the planarization layer 720. For example, the cover layer 730 may have a ring shape completely surrounding the opening area OA. In some embodiments, the cover layer 730 may have a ring shape having an opening area to partially surround the opening area OA.

[0187] The crack sensing portion 900 may include a first connection line 910 and a second connection line 920 extending to the outside of the middle area MA, and a crack sensing pattern 930 disposed adjacent to the opening area OA. One end of the crack sensing pattern 930 may be connected to the first connection line 910, and the other end of the crack sensing pattern 930 may be connected to the second connection line 920. For example, the first connection line 910 and the second connection line 920 may be connected to each other via the crack sensing pattern 930.

[0188] like Fig.14A As shown in , the crack sensing pattern 930 may have a ring shape with one side open that partially surrounds the opening area OA. Fig. 14B As shown in , the crack sensing pattern 930 may include a first portion having a ring shape with one side opening surrounding a portion of the opening area OA, a second portion connecting one end of the first portion to the first connection line 910, and a third portion connecting the other end of the first portion to the second connection line 920. For example, the crack sensing pattern 930 may have a shape in which a first ring portion 931 with one side opening and a second ring portion 933 having a larger diameter than the first ring portion 931 and having both sides opening surround the opening area OA in two layers.

[0189] The crack sensing pattern 930 may be disposed closer to the opening area OA than the second end 730E2 of the cover layer 730. For example, when viewed in a direction perpendicular to the substrate 100, the crack sensing pattern 930 may be disposed between the opening area OA and the cover layer 730.

[0190] The first connection line 910 and the second connection line 920 may be arranged to cross the cover layer 730. In this regard, Fig.14A and Fig. 14B The first connection line 910 and the second connection line 920 are shown to extend in the second direction (e.g., the y direction), but depending on the position of the opening area OA, the first connection line 910 and the second connection line 920 may extend in various directions and may cross the cover layer 730. When viewed in a direction perpendicular to the substrate 100, a portion of the first connection line 910 and a portion of the second connection line 920 may overlap the cover layer 730.

[0191] In an embodiment, the first connection line 910 and the crack sensing pattern 930 may be disposed in a different layer from the cover layer 730. The second connection line 920 may include a first sub-connection line 921 disposed in the same layer as the first connection line 910 and the crack sensing pattern 930, and a second sub-connection line 923 disposed in the same layer as the cover layer 730. In some embodiments, the second sub-connection line 923 may be provided integrally with the cover layer 730 (e.g., integrally formed).

[0192] In an embodiment, the first connection line 910 and the crack sensing pattern 930 may be provided in the same layer as the cover layer 730, and the second connection line 920 may include a first sub-connection line 921 provided in the same layer as the cover layer 730 and a second sub-connection line 923 provided in a different layer from the cover layer 730. In some embodiments, the first connection line 910 and the cover layer 730 may be integrally provided (e.g., integrally formed).

[0193] Fig.15A is a schematic plan view of a portion of a display panel according to an embodiment, and Fig. 15B and Fig. 15C is a schematic cross-sectional view of a portion of a display panel according to an embodiment. Fig. 15B It is along Fig.15A A schematic cross-sectional view taken along line VIII-VIII' in FIG. Fig. 15C It is along Fig.15A Schematic diagram of a cross section taken along line IX-IX'.

[0194] Reference FIG. 15A to FIG. 15C , the cover layer 730 may cover the first end 720E1 of the planarization layer 720 adjacent to the display area DA. Fig.11), the first end 730E1 of the cover layer 730 may be arranged closer to the display area DA than the first end 720E1 of the planarization layer 720, and the second end 730E2 of the cover layer 730 may be arranged closer to the opening area OA than the first end 720E1 of the planarization layer 720 (for example, see Fig. 14B ).

[0195] The crack sensing portion 900 may include a first connection line 910 and a second connection line 920 extending to the outside of the middle area MA and a crack sensing pattern 930 disposed adjacent to the opening area OA. The crack sensing pattern 930 may be disposed closer to the opening area OA than the second end 730E2 of the cover layer 730. Fig. 14B As described above, the crack sensing pattern 930 may have a shape in which a first annular portion 931 having one side open and a second annular portion 933 having a larger diameter than the first annular portion 931 and having both sides open surround the opening area OA in two layers.

[0196] The first connection line 910 and the second connection line 920 may be arranged to cross the cover layer 730. For example, FIG. 15A to FIG. 15C An embodiment in which the first connection line 910 and the second connection line 920 extend in a first direction (eg, x direction) is shown. When viewed in a direction perpendicular to the substrate 100 , a portion of the first connection line 910 and a portion of the second connection line 920 may overlap the cover layer 730 .

[0197] In an embodiment, the first connection line 910 may be disposed in the same layer as the crack sensing pattern 930. In some embodiments, the second connection line 920 may include a first sub-connection line 921 disposed in the same layer as the first connection line 910 and a second sub-connection line 923 disposed in a different layer from the first connection line 910 and the crack sensing pattern 930. The second sub-connection line 923 may be disposed in the same layer as the cover layer 730. The second sub-connection line 923 may be electrically connected to the cover layer 730.

[0198] For example, Fig. 15B and Fig. 15C An embodiment is shown in which the first connection line 910, the first annular portion 931 of the crack sensing pattern 930 and the first sub-connection line 921 are arranged between the third insulating layer 750 and the fourth insulating layer 760, and the second sub-connection line 923 and the covering layer 730 are arranged between the second insulating layer 740 and the third insulating layer 750.

[0199] like Fig. 15C As shown in , the second sub-connection line 923 may be provided integrally with (eg, integrally formed with) the cover layer 730. In another embodiment, as shown in Fig. 15BAs shown in , one or more insulating layers (eg, the third insulating layer 750 ) are disposed between the first connection line 910 and the cover layer 730 , and thus, the first connection line 910 may not be in direct contact with the cover layer 730 .

[0200] As above Fig.11 As described above, the first connection line 910, the crack sensing pattern 930, and the first sub-connection line 921 may be disposed in the same layer as the second conductive layer 420 of the input sensing layer 40, and the second sub-connection line 923 and the cover layer 730 may be disposed in the same layer as the first conductive layer 410 of the input sensing layer 40. For example, the first connection line 910, the crack sensing pattern 930, and the first sub-connection line 921 may each include the same material as the second conductive layer 420 of the input sensing layer 40, and the second sub-connection line 923 and the cover layer 730 may each include the same material as the first conductive layer 410 of the input sensing layer 40.

[0201] One end of the crack sensing pattern 930 may be electrically connected to the first connection line 910 via the first contact portion CNT1, and the other end of the crack sensing pattern 930 may be electrically connected to the second connection line 920 via the second contact portion CNT2. The first sub connection line 921 of the second connection line 920 may be electrically connected to the second sub connection line 923 via the third contact portion CNT3. As described above, the second sub connection line 923 is electrically connected to the cover layer 730, and therefore, the cover layer 730 may be electrically connected to the crack sensing line and the crack sensing pad via the second sub connection line 923 and the first sub connection line 921.

[0202] As a comparative example, when the cover layer is electrically isolated, charges may accumulate in the cover layer, causing defects in the display panel due to static electricity. In the embodiment of the present disclosure, since the cover layer 730 is electrically connected to any one of the connection lines of the crack sensing part 900, a path through which charges can be discharged is provided, thereby preventing or reducing defects due to static electricity.

[0203] According to the embodiment, a display panel having an opening in a display area, around which components may be arranged, may be implemented. However, the scope of the present disclosure is not limited thereto.

[0204] It should be understood that the embodiments described herein should be considered illustrative rather than for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although the embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made in the embodiments without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A display panel, wherein: The display panel comprises: A substrate having an opening area, a display area, and an intermediate area between the opening area and the display area; a plurality of display elements in the display area; an encapsulation layer covering the plurality of display elements and extending from the display area to the middle area; a planarization layer in the intermediate region and overlapping a portion of the encapsulation layer; a crack sensing portion on the planarization layer and extending around a portion of the opening region; and A covering layer covers a first end of the planarization layer and is electrically connected to the crack sensing portion, the first end of the planarization layer being on the encapsulation layer.

2. The display panel according to claim 1, wherein: The crack sensing part comprises: A first connecting line and a second connecting line, each extending to the outside of the middle area; and A crack sensing pattern electrically connects the first connection line to the second connection line and is adjacent to the opening area.

3. The display panel according to claim 2, wherein: The first connecting line and the crack sensing pattern are in a first conductive layer, and The second connection line includes a first sub-connection line in the first conductive layer and a second sub-connection line in a second conductive layer different from the first conductive layer.

4. The display panel according to claim 3, wherein: The covering layer is in the second conductive layer.

5. The display panel according to claim 3, wherein: The second sub-connection line is provided integrally with the cover layer.

6. The display panel according to claim 2, wherein: The crack sensing pattern has a ring shape with one side opened.

7. The display panel according to claim 2, wherein: The crack sensing pattern comprises: The first part has a ring shape with an opening on one side; a second part, connecting one end of the first part to the first connecting line; and The third part connects the other end of the first part to the second connecting line.

8. The display panel according to claim 1, wherein: The cover layer has a closed loop shape when viewed in a direction perpendicular to the substrate.

9. The display panel according to claim 1, wherein: The display panel further includes a groove in the middle region and extending around the opening region, and Wherein, the planarization layer covers the groove.

10. The display panel according to claim 9, wherein: The groove has an undercut shape.

11. A display panel, wherein: The display panel comprises: A substrate having an opening area, a display area, and an intermediate area between the opening area and the display area; a plurality of display elements in the display area; an encapsulation layer covering the plurality of display elements and extending from the display area to the middle area; An input sensing layer, on the packaging layer; a planarization layer in the intermediate region and overlapping a portion of the encapsulation layer; a crack sensing portion on the planarization layer and extending around a portion of the opening region; and A covering layer covers a first end of the planarization layer and is electrically connected to the crack sensing portion, the first end of the planarization layer being on the encapsulation layer.

12. The display panel according to claim 11, wherein: The input sensing layer includes a first conductive layer, a second conductive layer, and an insulating layer between the first conductive layer and the second conductive layer, and The covering layer and the first conductive layer include the same material.

13. The display panel according to claim 12, wherein: The crack sensing part comprises: A first connecting line and a second connecting line, each extending to the outside of the middle area; and A crack sensing pattern electrically connects the first connection line to the second connection line and is adjacent to the opening area.

14. The display panel according to claim 13, wherein: Each of the first connection line and the crack sensing pattern includes the same material as the second conductive layer, and The second connection line includes a first sub-connection line made of the same material as the second conductive layer and a second sub-connection line made of the same material as the first conductive layer.

15. The display panel according to claim 14, wherein: The cover layer is provided integrally with the second sub-connection line.

16. The display panel according to claim 13, wherein: When viewed in a direction perpendicular to the substrate, a portion of the first connection line and a portion of the second connection line overlap the cover layer.

17. The display panel according to claim 13, wherein: The crack sensing pattern has a ring shape with one side opened.

18. The display panel according to claim 13, wherein: The crack sensing pattern comprises: The first part has a ring shape with an opening on one side; a second part, connecting one end of the first part to the first connecting line; and The third part connects the other end of the first part to the second connecting line.

19. The display panel according to claim 11, wherein: The cover layer has a closed loop shape when viewed in a direction perpendicular to the substrate.

20. The display panel according to claim 11, wherein: The display panel further includes a groove in the middle region and extending around the opening region, and Wherein, the planarization layer covers the groove.

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