Power management integrated circuit (PMIC) power monitoring without external monitoring circuitry

Abstract

Techniques and apparatus for power monitoring in an in-vehicle system, such as an Advanced Assisted Driving System (ADAS), an in-vehicle infotainment (IVI) system, and / or an Automatic Driving (AD) system. One example method of power monitoring generally includes: using at least one primary domain (MD) power management integrated circuit (PMIC) to regulate power to a primary domain of a system on chip (SoC); regulating power to a security domain of the SoC using at least one security domain (SD) PMIC; powering the at least one SD PMIC using an SD PMIC power rail; and monitoring the SD PMIC power rail using the at least one MD PMIC. For certain aspects, the method further includes powering the at least one MD PMIC using the MD PMIC power rail, and monitoring the MD PMIC power rail using the at least one SD PMIC.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 18 / 457,066, filed on August 28, 2023, which claims the benefit and priority of U.S. Provisional Application No. 63 / 374,043, filed on August 31, 2022, entitled “Power Management Integrated Circuit (PMIC) Power Supply Monitoring without External Monitoring Circuitry,” both of which are expressly incorporated herein by reference as if fully set forth below and in their entirety for all applicable purposes. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic components and, more particularly, to power management integrated circuit (PMIC) power monitoring in vehicle systems. Background Art

[0004] Ideally, a voltage regulator provides a constant direct current (DC) output voltage regardless of changes in load current or input voltage. Voltage regulators can be classified as linear regulators or switching regulators. Although linear regulators are small and compact, many applications can benefit from the improved efficiency of switching regulators. For example, linear regulators can be implemented by low dropout (LDO) regulators. Switching regulators can be implemented by switch mode power supplies (SMPS) such as buck converters, boost converters, buck-boost converters, or charge pumps.

[0005] A power management integrated circuit (PMIC) is used to manage the power requirements of a host system and may include and / or control one or more voltage regulators (e.g., LDO and / or SMPS). A PMIC may be used in devices such as vehicles to control the flow and direction of power in the device. A PMIC may perform various functions for a device such as DC to DC conversion (e.g., using a voltage regulator as described above), battery charging, power source selection, voltage scaling, power sequencing, etc. Summary of the invention

[0006] The systems, methods, and devices of the present disclosure each have several aspects, no single aspect of which is solely responsible for its desired characteristics. Without limiting the scope of the present disclosure as expressed by the claims that follow, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description," one will understand how the features of the present disclosure provide the advantages described herein.

[0007] Certain aspects of the present disclosure are generally directed to techniques and apparatus for power monitoring in a system having multiple independent domains, such as an in-vehicle system having a primary domain and a safety domain.

[0008] Certain aspects of the present disclosure provide an apparatus for vehicle operation. The apparatus as a whole includes: a system on chip (SoC), the system on chip (SoC) including a main domain and a security domain; at least one main domain (MD) power management integrated circuit (PMIC); at least one MD power rail, the at least one MD power rail is coupled between the at least one MD PMIC and the main domain of the SoC for supplying power to the main domain of the SoC; at least one security domain (SD) PMIC; at least one SD power rail, the at least one SD power rail is coupled between the at least one SD PMIC and the security domain of the SoC for supplying power to the security domain of the SoC; an MD PMIC power rail, the MD PMIC power rail is coupled to the at least one MD PMIC for supplying power to the at least one MD PMIC; and an SD PMIC power rail, the SD PMIC power rail is coupled to the at least one SD PMIC for supplying power to the at least one SD PMIC. The at least one MD PMIC has an input terminal coupled to the SD PMIC power rail for monitoring the SD PMIC power rail.

[0009] Certain aspects of the present disclosure provide an apparatus for vehicle operation. The apparatus as a whole includes: a SoC, the SoC including a main domain and a security domain; at least one MD PMIC; at least one MD power rail, the at least one MD power rail coupled between the at least one MD PMIC and the main domain of the SoC for powering the main domain of the SoC; at least one SD PMIC; at least one SD power rail, the at least one SD power rail coupled between the at least one SD PMIC and the security domain of the SoC for powering the security domain of the SoC; an MD PMIC power rail, the MD PMIC power rail coupled to the at least one MD PMIC for powering the at least one MD PMIC; and an SD PMIC power rail, the SD PMIC power rail coupled to the at least one SD PMIC for powering the at least one SD PMIC, wherein the at least one SD PMIC has an input coupled to the MDPMIC power rail for monitoring the MD PMIC power rail.

[0010] Certain aspects of the present disclosure provide a method for power monitoring. The method as a whole includes: using at least one MD PMIC to regulate power to a primary domain of a SoC; using at least one SD PMIC to regulate power to a secure domain of the SoC; using an SD PMIC power rail to supply power to the at least one SD PMIC; and using the at least one MD PMIC to monitor the SD PMIC power rail.

[0011] Certain aspects of the present disclosure provide a method for power monitoring. The method as a whole includes: using at least one MD PMIC to regulate power to a primary domain of a SoC; using at least one SD PMIC to regulate power to a secure domain of the SoC; using an MD PMIC power rail to supply power to the at least one MD PMIC; and using the at least one SD PMIC to monitor the MD PMIC power rail.

[0012] To achieve the aforementioned and related purposes, one or more aspects include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail certain exemplary features of the one or more aspects. However, these features indicate only some of the various ways in which the principles of the various aspects can be employed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description briefly summarized above may be obtained by reference to various aspects, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only certain aspects of the present disclosure and therefore should not be considered as limiting its scope, as the description may allow for other equally effective aspects.

[0014] Figure 1 is a block diagram of an example vehicle having an in-vehicle system in which aspects of the disclosure may be practiced.

[0015] Figure 2 is a block diagram of an example in-vehicle system with primary and safety domain PMIC power rail monitoring performed by external monitoring circuits.

[0016] Figure 3 is a block diagram of an example in-vehicle system with primary and safety domain PMIC power rail monitoring performed by a safety domain PMIC and one or more primary domain PMICs, respectively, in accordance with certain aspects of the present disclosure.

[0017] Figure 4 and Figure 5 is a flow chart depicting example operations for power supply monitoring in accordance with certain aspects of the present disclosure.

[0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0019] Certain aspects of the present disclosure generally relate to power management integrated circuit (PMIC) power monitoring without using external monitoring circuits in in-vehicle systems such as advanced driver assistance systems (ADAS), in-vehicle infotainment (IVI) systems, and / or autonomous driving (AD) systems. An example method generally includes: using at least one main domain (MD) PMIC to regulate power to a main domain of a system on chip (SoC); using at least one safety domain (SD) PMIC to regulate power to a safety domain of the SoC; using an SD PMIC power rail to supply power to the at least one SD PMIC; and using the at least one MD PMIC to monitor the SDPMIC power rail. For certain aspects, the method further includes: using an MD PMIC power rail to supply power to the at least one MD PMIC, and using the at least one SD PMIC to monitor the MD PMIC power rail. As used herein, "external monitoring circuitry" generally refers to circuitry that is external to a module or other unit that includes an SoC, an MD PMIC, and / or an SD PMIC. However, for certain aspects, the external monitoring circuitry may be disposed on the same printed circuit board (PCB) as other components described herein (including the SoC, the MD PMIC, and / or the SD PMIC).

[0020] The various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms, and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the disclosure disclosed herein, whether it is implemented independently or in combination with any other aspect of the present disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such a device or method that is practiced using other structures, functions, or structures and functions in addition to or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein can be embodied by one or more elements of the claims.

[0021] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0022] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that element A is directly connected to element B or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the context of electronic components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect element A and element B (and any components electrically connected therebetween).

[0023] Example vehicles and vehicle systems

[0024] Modern vehicles have multiple features for safety, navigation, entertainment, etc., such as ADAS and IVI. Modern vehicles are able to sense and / or communicate with other vehicles and / or objects on the road, which allows for improved predictive safety features and AD. IVI is no longer just for entertainment purposes, and can ideally work closely with safety features (including ADAS), especially in modern vehicles equipped with AD capabilities. As the automotive industry transitions to AD vehicles, ADAS is merged with IVI. Merging ADAS and IVI will improve driving safety and improve the overall driving experience. In other words, as the driving experience becomes autonomous, the demand for both passenger safety and entertainment increases.

[0025] Figure 1 1 is a block diagram of an example vehicle 100 having an in-vehicle system in which aspects of the present disclosure may be practiced. For example, the vehicle 100 may include an in-vehicle ADAS / IVI electrical control unit (ECU) 102. The combined ADAS / IVI ECU may include at least one SoC having an MD and an SD. In some aspects, the in-vehicle ADAS / IVI ECU 102 may be coupled to at least one external ECU ( Figure 1 not shown).

[0026] Example PMIC Power Monitoring Using External Monitoring Circuit

[0027] Figure 22 is a block diagram of an example ADAS / IVI ECU 202 having master and safety domain PMIC power rail monitoring performed by external monitoring circuitry. The ADAS / IVI ECU 202 may include a SoC 210 having at least two independent domains: at least one master domain (MD) 212 and at least one safety domain (SD) 214, the latter also referred to as a "safety island" or "SAIL". For ease of description and illustration, the remainder of this disclosure may refer to MD 212 and SD 214, but the reader should understand that there may be more than one MD and / or more than one SD.

[0028] In certain aspects, according to the ISO 26262 automotive standard, for example, MD 212 and one or more MD PMICs 222 meet integrity requirements up to Automotive Safety Integrity Level (ASIL) B. SD 214 and one or more SD PMICs 224 may meet integrity requirements up to ASIL D. In other words, SD 214 is generally configured to support more stringent safety standards than MD 212.

[0029] MD 212 may be coupled to and receive power from at least one MD PMIC 222 via MD power rail 232. MD PMIC power rail 242 from an MD external voltage source (not shown) may be coupled to and used to power MD PMIC 222.

[0030] SD 214 may be coupled to and receive power from at least one SD PMIC 224 via SD power rail 234. MD PMIC power rail 244 from an external SD voltage source (not shown) may be coupled to and used to power SD PMIC 224. In this manner, MD 212 and SD 214 are independent from a voltage domain perspective, meaning that MD 212 and SD 214 are powered from separate voltage rails supplied by independent PMICs (MD PMIC 222 and SD PMIC 224, respectively).

[0031] In order to ensure safe operation of a vehicle (e.g., vehicle 100), it may be desirable to monitor the PMIC power rails provided by two external power supplies (e.g., MD PMIC power rail 242 and SD PMIC power rail 244) to detect faults that may affect the PMIC (e.g., MD PMIC 222 and / or SD PMIC 224) and, in turn, the SoC 210, since the SoC 210 may be executing a safety-critical application. Therefore, an external voltage monitoring circuit 250 may be coupled to the two PMIC power rails (e.g., MD PMIC power rail 242 and SD PMIC power rail 244) provided by each respective external power supply. In some cases, the external voltage monitoring circuit 250 may be a circuit external to a printed circuit board (PCB) supporting the SoC 210, the MD PMIC 222, and / or the SD PMIC 224, or may be a circuit external to an ECU that includes the SoC 210, the MD-PMIC 222, and / or the SD-PMIC 224. In other cases, the external voltage monitoring circuit 250 may be a circuit located on the same PCB as the SoC 210, the MD PMIC 222, and / or the SD PMIC 224, or in an ECU, such as Figure 2 exemplified in .

[0032] The external voltage monitoring circuit 250 may be a system-level supervisor that may be implemented, for example, by a microcontroller. A first input 252 of the external voltage monitoring circuit 250 may be coupled to the MD PMIC power rail 242, and a second input 254 of the external voltage monitoring circuit 250 may be coupled to the SD PMIC power rail 244, as shown in FIG. Figure 2 224. The external voltage monitoring circuit 250 may be used to detect a fault in the MD PMIC power rail 242 provided to the MD PMIC 222 and / or a fault in the SDPMIC power rail 244 provided to the SD PMIC 224. The external voltage monitoring circuit 250 may provide the status of the MD PMIC power rail 242 and / or the SD PMIC power rail 244 to the external safety monitoring circuit 260. In some cases, the external safety monitoring circuit 260 may be a circuit external to a PCB supporting the SoC 210, the MD PMIC 222, and / or the SD PMIC 224, or may be a circuit external to an ECU that includes the SoC 210, the MD-PMIC 222, and / or the SD-PMIC 224. In such cases, the external safety monitoring circuit 260 may be implemented as a microcontroller or an external ECU that may be coupled to the onboard ADAS / IVI ECU 202. In other cases, the external safety monitoring circuit 260 may be a circuit located on the same PCB or in the same ECU as one or more of the SoC 210, the MD PMIC 222, and the SD PMIC 224, such as Figure 2 For example, the external voltage monitoring circuit 250 may provide the status of the MD PMIC power rail 242 and / or the SD PMIC power rail 244 continuously, periodically, intermittently, or in response to a query.

[0033] However, adding the external voltage monitoring circuit 250 increases bill of materials (BOM) cost and adds additional dependencies, thus adding additional design complexity to system integrators (eg, automotive original equipment manufacturers (OEMs)).

[0034] Example PMIC Power Monitoring Without External Monitoring Circuitry

[0035] To reduce BOM cost and design complexity for PMIC rail monitoring, certain aspects of the present invention use a PMIC in one domain to monitor the voltage of a PMIC power rail in another domain. For example, the SD PMIC power rail 244 can be monitored by the MDPMIC 222, and the MD PMIC power rail 242 can be monitored by the SD PMIC 224, so that the external voltage monitoring circuit 250 can be eliminated.

[0036] Figure 3 is a block diagram of an example ADAS / IVI ECU 302 with primary and safety domain PMIC power rail monitoring performed by the SD PMIC 224 and the MD PMIC 222 , respectively, in accordance with certain aspects of the present disclosure. Figure 3 The ADAS / IVI ECU 302 may be similar to Figure 2 The ADAS / IVI ECU 302 may be implemented as a module including the SoC 210, the MD PMIC 222, and the SD PMIC 224.

[0037] In the ADAS / IVI ECU 302, at least one MD PMIC 222 may have an input 362 coupled to an SD PMIC power rail 244 supplied by an external SD voltage source (not shown). Additionally or alternatively, the at least one SD PMIC 224 may have an input 364 coupled to an MD PMIC power rail 242 supplied by an external MD voltage source (not shown). The SD PMIC power rail 244 may be coupled to a sense input 326 (e.g., an analog-to-digital converter (ADC) channel, a remote sense pin, or another circuit configured to measure the voltage of the power rail 244) of one or more of the MD PMICs 222. The MD PMIC power rail 242 may be coupled to a sense input 328 (e.g., an ADC channel, a remote sense pin, or another circuit configured to measure the voltage of the power rail 242) of one or more of the SD PMICs 224. Advantageously, the MD PMIC 222 can monitor the SD PMIC power rail 244, and the SD PMIC 224 can monitor the MD PMIC power rail 242, so that the external voltage monitoring circuit 250 can be eliminated. The power rail monitoring can include sensing the voltage and / or current of the power rail.

[0038] The MD PMIC 222 may have an output 372 coupled to an input 373 of the MD 212 and may be used to indicate to the MD 212 the status of the SD PMIC power rail 244. For example, the MD PMIC 222 may report to the MD 212 whether the SD PMIC power rail 244 has a voltage outside the acceptable voltage range or below a threshold voltage value and is experiencing a fault. The SD PMIC 224 may have an output 374 coupled to an input 375 of the SD 214 and may be used to indicate to the SD 214 whether the MD PMIC power rail 242 has a voltage outside the acceptable voltage range or below a threshold voltage value and is experiencing a fault.

[0039] Utilizing the architecture described above, there are several different strategies for monitoring the MD PMIC power rail 242 and / or the SD PMIC power rail 244. For example, at a first level, the PMIC itself (e.g., one or more of the MD PMIC 222 and / or the SD PMIC 224) may detect an input voltage out-of-range (e.g., of ±5%) from an expected or configured PMIC input voltage value (e.g., at an input 392 coupled to the MD PMIC power rail 242 and / or an input 394 coupled to the SD PMIC power rail 244).

[0040] At the second level, when the SD PMIC 224 determines that the MD PMIC power rail 242 is in a fault state, the SD PMIC 224 may notify the SD 214 of the SoC 210 that the MD PMIC 222 is experiencing an error (e.g., a functional safety (FuSa) error). In addition, the SD 214 may notify (the safety domain of) the external safety monitoring circuit 260 (e.g., a microcontroller unit (MCU)) of the fault on the MD PMIC power rail 242 through a suitable interface 376 (such as a serial peripheral interface (SPI) or a universal asynchronous receiver transmitter (UART) interface). Alternatively, the SD PMIC 224 may notify (the safety domain of) the external safety monitoring circuit system 260 of the fault on the MD PMIC power rail 242 through a suitable interface (not shown, but coupled between the SD PMIC 224 and the circuit system 260). In addition to or as an alternative to notifying SD 214 and / or external safety monitoring circuit 260, SD 214 (or SDPMIC 224) may also notify an external ECU (e.g., a safety domain of the external ECU) of a fault on the MD PMIC power rail 242 via a suitable connection, such as bus 378 (e.g., a controller area network (CAN) or Ethernet (ETH) bus).

[0041] When the MD PMIC 222 determines that the SD PMIC power rail 244 is in a fault state, the MD PMIC 222 may notify the safety monitor software running on the MD 212 that the SD PMIC power rail 244 is experiencing an error (e.g., a FuSa error). The safety monitor software may then further notify the external safety monitor circuit 260 of the error on the SD PMIC power rail 244 via a suitable interface 386, such as an SPI or UART interface. Additionally or alternatively, the safety monitor software may notify one or more other ECUs of the fault regarding the error via a connected interface, such as a bus 388 (e.g., Ethernet, UART, or CAN bus).

[0042] For example, in the case of a common cause failure, it is possible that the supply voltage to both the MD PMIC 222 and the SD PMIC 224 may be equally affected in time and in terms of failure mode, such that the previously described approach may not work correctly. For example, in the system safety concept of a system integrator (e.g., an Automotive OEM or Tier 1), this situation may be considered a residual failure. Alternatively, the system integrator may implement a separation of the power rail sources from the MD PMIC 222 and from the SDPMIC 224 to minimize such residual failures associated with the previously described approach. In other words, the external power supplies to the MDPMIC 222 and the SD PMIC 224 may be implemented as separate and independent power supplies so that it is unlikely that both power supplies will be affected when a problem occurs.

[0043] With the architecture described above, there are several different strategies for PMIC rail monitoring. In one example, the PMIC 222, 224 can monitor the PMIC power rail voltage through its respective sense inputs 326, 328 (e.g., ADC channels, remote sense pins, or other circuits configured to measure the voltage level of the power rail voltage). For example, the MD PMIC 222 can determine the SD PMIC power rail voltage through one or more of their respective ADCs. The internal MD PMIC controller or other logic components of each of these MDPMICs 222 can read the voltage value of the SD PMIC power rail 244 and store indications of these values ​​in a memory (such as a local MD PMIC random access memory (RAM)). The local RAM can be read, for example, by the security monitoring software running on the MD 212 of the SoC 210 through the system power management interface (SPMI) bus. For some aspects, the values ​​stored in the local RAM can be read out at a defined periodic rhythm (e.g., every 5ms), continuously or intermittently (e.g., on demand). Similarly, the SD PMIC 224 may determine the MD PMIC power rail voltage via one or more of their respective ADCs. An internal SD PMIC controller or other logic component of each of these SD PMICs may read the voltage values ​​of the MD PMIC power rail 242 and store indications of these values ​​in a memory, such as a local SD PMIC RAM. The local SD PMIC RAM may be, for example, stored via an inter-integrated circuit (I 2 C) The bus is read by software running on the SD. For some aspects, the values ​​stored in the local SD PMIC RAM can be read out at some defined periodic rhythm (e.g., every 5ms) or at some other opportunity. If the ADC is not available, the same operation can also be performed by the remote sense pin of the PMIC (or vice versa).

[0044] In certain aspects, the PMIC itself may (continuously) check the ADC input against one or more thresholds and, if a limit violation is detected, communicate an error indication to the MD 212 or SD 214 of the SoC 210. When an external signal passes through the voltage monitor, the PMIC (e.g., one or more of the MD PMIC 222 and / or the SD PMIC 224) may generate a fault (e.g., Warning / Level 1 or Error / Level 2) when a programmed threshold is exceeded.

[0045] According to certain aspects, the SoC 210 may include two or more SDs 214. For example, the two or more SDs 214 may include a first SD configured to meet integrity levels up to ASIL C and a second SD configured to meet integrity levels up to ASIL D. The two or more SDs 214 may be coupled to and receive power from the same SD PMIC 224, or receive power from separate SD PMICs 224. Rails of the SD PMIC (e.g., the SD PMIC power rails 244) may be monitored without external voltage monitoring circuitry, as described herein.

[0046] Example Power Operation

[0047] Figure 4 4 is a flow chart depicting example operations 400 for power supply monitoring according to certain aspects of the present disclosure. Operations 400 may be performed by circuitry (e.g., Figure 3 ADAS / IVI ECU 302) is executed.

[0048] At block 402, operations 400 may begin with at least one master domain (MD) power management integrated circuit (PMIC) (e.g., MD PMIC 222) regulating power to at least one master domain (e.g., MD 212) of a system on chip (SoC) (e.g., SoC 210). At block 404, at least one secure domain (SD) PMIC (e.g., SD PMIC 224) may regulate power to at least one secure domain (e.g., SD 214) of the SoC. At block 406, an SD PMIC power rail (e.g., SD PMIC power rail 244) may provide power to at least one SD PMIC. At block 408, at least one MD PMIC may monitor the SD PMIC power rail.

[0049] According to certain aspects, the operations 400 further include transmitting, from the at least one MD PMIC to the at least one master domain of the SoC, an indication of a status of the SDPMIC power rail.

[0050] According to certain aspects, operation 400 also includes transmitting an indication of a status of a SD PMIC power rail from at least one MD PMIC to a control unit external to a module (e.g., ADAS / IVI ECU 302) including the SoC (e.g., via Ethernet, UART, or CAN bus, such as bus 388).

[0051] According to certain aspects, operation 400 also includes: using the MD PMIC power rail (e.g., MD PMIC power rail 242) to power at least one MD PMIC, and using at least one SD PMIC to monitor the MD PMIC power rail. Operation 400 may also include: transmitting an indication of the state of the MD PMIC power rail from the at least one SD PMIC to at least one safety domain of the SoC. In certain aspects, operation 400 may also include: transmitting an indication of the state of the MD PMIC power rail from the at least one SD PMIC to a control unit (e.g., via a CAN or Ethernet bus, such as bus 378) or a safety monitor (e.g., external safety monitoring circuit 260) external to a module (e.g., ADAS / IVI ECU 302) including the SoC.

[0052] Figure 5 is a flow chart depicting example operations 500 for power supply monitoring according to certain aspects of the present disclosure. Operations 500 may be performed by circuitry (e.g., Figure 3 ADAS / IVI ECU 302) is executed.

[0053] At block 502, operations 500 may begin with at least one MD PMIC (e.g., MD PMIC 222) regulating power to a primary domain (e.g., MD 212) of a SoC (e.g., SoC 210). At block 504, at least one SD PMIC (e.g., SDPMIC 224) may regulate power to at least one safety domain (e.g., SD 214, also referred to as a “safety island” or “SAIL” domain) of the SoC. At block 506, an MD PMIC power rail (e.g., MD PMIC power rail 242) may provide power to the at least one MD PMIC. At block 508, at least one SD PMIC may monitor the MD PMIC power rail.

[0054] According to certain aspects, the operations 500 further include transmitting, from the at least one SD PMIC to the at least one secure domain of the SoC, an indication of a status of a MD PMIC power rail.

[0055] According to certain aspects, operation 500 also includes transmitting an indication of the status of the MD PMIC power rail from at least one SD PMIC to a control unit external to the module including the SoC (e.g., via a CAN or Ethernet bus, such as bus 378) or a safety monitor (e.g., external safety monitoring circuit 260).

[0056] Example aspects

[0057] Specific implementation examples are described in the following numbered aspects:

[0058] Aspect 1: A device for vehicle operation, the device comprising: a system on chip (SoC), the system on chip (SoC) comprising a main domain and a security domain; at least one main domain (MD) power management integrated circuit (PMIC); at least one MD power rail, the at least one MD power rail coupled between the at least one MD PMIC and the main domain of the SoC for powering the main domain of the SoC; at least one security domain (SD) PMIC; at least one SD power rail, the at least one SD power rail coupled between the at least one SD PMIC and the security domain of the SoC for powering the security domain of the SoC; an MD PMIC power rail, the MD PMIC power rail coupled to the at least one MD PMIC for powering the at least one MD PMIC; and an SD PMIC power rail, the SD PMIC power rail coupled to the at least one SD PMIC for powering the at least one SD PMIC, wherein the at least one MD PMIC has an input coupled to the SD PMIC power rail for monitoring the SD PMIC power rail.

[0059] Aspect 2: The apparatus of aspect 1, wherein the at least one MD PMIC has an output coupled to an input of the primary domain of the SoC for indicating a status of the SD PMIC power rail.

[0060] Aspect 3: The apparatus according to aspect 1 or 2, wherein the at least one MD PMIC has an output terminal for coupling to an input terminal of a control unit external to the apparatus for indicating the status of the SD PMIC power rail.

[0061] Aspect 4: The apparatus according to any one of the preceding aspects, wherein the input terminal of the at least one MD PMIC is coupled to an analog-to-digital converter (ADC) channel or a remote sensing pin of the at least one MD PMIC.

[0062] Aspect 5: The apparatus of any of the preceding aspects, wherein the at least one SD PMIC has an input coupled to the MD PMIC power rail for monitoring the MD PMIC power rail.

[0063] Aspect 6: The apparatus according to any of the preceding aspects, wherein the at least one SD PMIC has an output coupled to an input of the security domain of the SoC for indicating a status of the MD PMIC power rail.

[0064] Aspect 7: The apparatus of aspect 5 or 6, wherein the input terminal of the at least one SD PMIC is coupled to an analog-to-digital converter (ADC) channel or a remote sensing pin of the at least one SD PMIC.

[0065] Aspect 8: The apparatus according to any one of aspects 5 to 7, wherein the at least one SD PMIC has an output terminal for coupling to an input terminal of a control unit or a safety monitor external to the apparatus for indicating the status of the MD PMIC power rail.

[0066] Aspect 9: The apparatus according to any of the preceding aspects, wherein the security domain of the SoC is independent of the primary domain of the SoC.

[0067] Aspect 10: The apparatus according to any one of the preceding aspects, wherein the security domain of the SoC is configured to support a stricter security standard than the primary domain of the SoC.

[0068] Aspect 11: An apparatus according to any of the preceding aspects, wherein the safety domain of the SoC is configured to comply with requirements up to Automotive Safety Integrity Level (ASIL) D, and wherein the primary domain of the SoC is configured to comply with requirements up to ASIL B.

[0069] Aspect 12: The apparatus of any of the preceding aspects, wherein the at least one SD PMIC is configured to comply with up to the ASIL D requirements, and wherein the at least one MD PMIC is configured to comply with up to the ASIL B requirements.

[0070] Aspect 13: A device for operating a vehicle, the device comprising: a system on a chip (SoC), the system on a chip (SoC) comprising a main domain and a security domain; at least one main domain (MD) power management integrated circuit (PMIC); at least one MD power rail, the at least one MD power rail coupled between the at least one MD PMIC and the main domain of the SoC for supplying power to the main domain of the SoC; at least one security domain (SD) PMIC; at least one SD power rail, the at least one SD power rail coupled between the at least one SD PMIC and the security domain of the SoC for supplying power to the security domain of the SoC; an MD PMIC power rail, the MD PMIC power rail coupled to the at least one MD PMIC for supplying power to the at least one MD PMIC; and an SD PMIC power rail, the SD PMIC power rail coupled to the at least one SD PMIC for supplying power to the at least one SD PMIC, wherein the at least one SD PMIC has an input coupled to the MD PMIC power rail for monitoring the MD PMIC power rail.

[0071] Aspect 14: The apparatus of aspect 13, wherein the at least one SD PMIC has an output coupled to an input of the secure domain of the SoC for indicating a status of the MD PMIC power rail.

[0072] Aspect 15: The apparatus of aspect 13 or 14, wherein the input terminal of the at least one SD PMIC is coupled to an analog-to-digital converter (ADC) channel or a remote sensing pin of the at least one SD PMIC.

[0073] Aspect 16: The apparatus according to any one of aspects 13 to 15, wherein the at least one SD PMIC has an output terminal for coupling to an input terminal of a control unit or a safety monitor external to the apparatus for indicating the status of the MDPMIC power rail.

[0074] Aspect 17: The apparatus according to any one of Aspects 13 to 16, wherein the security domain of the SoC is independent of the primary domain of the SoC.

[0075] Aspect 18: The apparatus according to any one of aspects 13 to 17, wherein the security domain of the SoC is configured to support a stricter security standard than the primary domain of the SoC.

[0076] Aspect 19: An apparatus according to any one of Aspects 13 to 18, wherein the safety domain of the SoC is configured to comply with requirements up to Automotive Safety Integrity Level (ASIL) D, and wherein the primary domain of the SoC is configured to comply with requirements up to ASIL B.

[0077] Aspect 20: The apparatus of any one of Aspects 13 to 19, wherein the at least one SD PMIC is configured to comply with up to the ASIL D requirements, and wherein the at least one MD PMIC is configured to comply with up to the ASIL B requirements.

[0078] Aspect 21: A method for power monitoring, the method comprising: using at least one main domain (MD) power management integrated circuit (PMIC) to regulate power to a main domain of a system on chip (SoC); using at least one security domain (SD) PMIC to regulate power to a security domain of the SoC; using an SD PMIC power rail to power the at least one SD PMIC; and using the at least one MD PMIC to monitor the SD PMIC power rail.

[0079] Aspect 22: The method according to aspect 21, the method further comprising: transmitting an indication of a status of the SD PMIC power rail from the at least one MD PMIC to the primary domain of the SoC.

[0080] Aspect 23: The method according to aspect 21 or 22, the method further comprising: transmitting an indication of the status of the SD PMIC power rail from the at least one MD PMIC to a control unit external to a module including the SoC.

[0081] Aspect 24: The method according to any one of aspects 21 to 23, further comprising: using an SD PMIC power rail to power the at least one SD PMIC; and using the at least one SD PMIC to monitor the MDPMIC power rail.

[0082] Aspect 25: The method according to aspect 24, the method further comprising: transmitting an indication of the status of the MD PMIC power rail from the at least one SD PMIC to the secure domain of the SoC.

[0083] Aspect 26: The method according to aspect 24 or 25, the method further comprising: transmitting an indication of the status of the MD PMIC power rail from the at least one SD PMIC to a control unit or safety monitor external to a module including the SoC.

[0084] Aspect 27: A method for power monitoring, the method comprising: using at least one main domain (MD) power management integrated circuit (PMIC) to regulate power to a main domain of a system on chip (SoC); using at least one security domain (SD) PMIC to regulate power to a security domain of the SoC; using an MD PMIC power rail to power the at least one MD PMIC; and using the at least one SD PMIC to monitor the MD PMIC power rail.

[0085] Aspect 28: The method according to aspect 27, the method further comprising: transmitting an indication of the status of the MD PMIC power rail from the at least one SD PMIC to the secure domain of the SoC.

[0086] Aspect 29: The method according to aspect 27 or 28, the method further comprising: transmitting an indication of the status of the MD PMIC power rail from the at least one SD PMIC to a control unit or safety monitor external to a module including the SoC.

[0087] Additional considerations

[0088] Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior or superior to other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed features, advantages, or modes of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C may still be considered to be coupled to each other, even though objects A and C are not in direct physical contact with each other. For example, a first object may be coupled to a second object, even though the first object has never been in direct physical contact with the second object. The term "circuit" is used broadly and is intended to include hardware implementations of both electronic devices and conductors that, when connected and configured, enable the functions described in this disclosure to be performed without limitation to the type of electronic circuit.

[0089] The apparatuses and methods described in the detailed description are illustrated in the drawings by various blocks, modules, components, circuits, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using, for example, hardware.

[0090] One or more of the components, steps, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, step, feature, or function, or embodied in several components, steps, or functions. Additional elements, components, steps, and / or functions may also be added without departing from the features disclosed herein. The devices, equipment, and / or components illustrated herein may be configured to perform one or more of the methods, features, or steps described herein.

[0091] It should be understood that the specific order or hierarchy of steps in the disclosed methods is an illustration of an exemplary process. It should be understood that the specific order or hierarchy of steps in these methods can be rearranged based on design preferences. The attached method claims provide elements of various steps in an exemplary order, but are not intended to be limited to the specific order or hierarchy provided unless explicitly stated herein.

[0092] The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects. Therefore, the claims are not intended to be limited to the various aspects shown herein, but to conform to the full scope consistent with the text of the claims, wherein unless explicitly stated so, the reference to the element in the singular form is not intended to mean "one and only one", but "one or more". Unless otherwise specified, the term "some" refers to one or more. The phrase "at least one" mentioned in the list of items refers to any combination of those items, including a single member. For example, "at least one of the following: a, b or c" is intended to at least cover: a, b, c, ab, ac, bc and abc, and any combination with multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc and ccc or any other order of a, b and c). All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are or later become known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is expressly recited in the claims. No claim element should be interpreted under the provisions of 35 U.S.C. §112(f) unless the element is expressly recited using the phrase “means for…” or, in the case of a method claim, the phrase “step for…” is used to recite the element.

[0093] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A device for operating a vehicle, the device comprising: A system on chip (SoC), wherein the system on chip (SoC) includes a primary domain and a security domain; at least one master domain (MD) power management integrated circuit (PMIC); at least one MD power rail coupled between the at least one MD PMIC and the main domain of the SoC for supplying power to the main domain of the SoC; At least one safety domain (SD) PMIC; at least one SD power rail coupled between the at least one SD PMIC and the security domain of the SoC for supplying power to the security domain of the SoC; MD PMIC power rail, the MD PMIC power rail is coupled to the at least one an MD PMIC for supplying power to the at least one MD PMIC; and An SD PMIC power rail is coupled to the at least one SDPMIC for powering the at least one SD PMIC, wherein the at least one MDPMIC has an input coupled to the SD PMIC power rail for monitoring the SDPMIC power rail. 2 . The apparatus of claim 1 , wherein the at least one MD PMIC has an output coupled to an input of the primary domain of the SoC for indicating a status of the SD PMIC power rail.

3. The apparatus of claim 1, wherein the at least one MD PMIC has an output for coupling to an input of a control unit external to the apparatus for indicating a state of the SD PMIC power rail. 4 . The apparatus of claim 1 , wherein the input terminal of the at least one MD PMIC is coupled to an analog-to-digital converter (ADC) channel or a remote sensing pin of the at least one MD PMIC. 5 . The apparatus of claim 1 , wherein the at least one SD PMIC has an input coupled to the MD PMIC power rail for monitoring the MD PMIC power rail. 6 . The apparatus of claim 5 , wherein the at least one SD PMIC has an output coupled to an input of the secure domain of the SoC for indicating a status of the MDPMIC power rail. 7 . The apparatus of claim 5 , wherein the input terminal of the at least one SD PMIC is coupled to an analog-to-digital converter (ADC) channel or a remote sense pin of the at least one SD PMIC.

8. The apparatus of claim 5, wherein the at least one SD PMIC has an output for coupling to an input of a control unit or safety monitor external to the apparatus for indicating a status of the MD PMIC power rail.

9. The apparatus of claim 1, wherein the security domain of the SoC is independent of the primary domain of the SoC. 10 . The apparatus of claim 1 , wherein the security domain of the SoC is configured to support a more stringent security standard than the primary domain of the SoC.

11. The apparatus of claim 1, wherein the safety domain of the SoC is configured to comply with up to Automotive Safety Integrity Level (ASIL) D requirements, and wherein the primary domain of the SoC is configured to comply with up to ASIL B requirements. 12 . The apparatus of claim 11 , wherein the at least one SD PMIC is configured to comply with up to the ASIL D requirements, and wherein the at least one MD PMIC is configured to comply with up to the ASIL B requirements.

13. A device for operating a vehicle, the device comprising: A system on chip (SoC), wherein the system on chip (SoC) includes a primary domain and a security domain; at least one master domain (MD) power management integrated circuit (PMIC); at least one MD power rail coupled between the at least one MD PMIC and the main domain of the SoC for supplying power to the main domain of the SoC; At least one safety domain (SD) PMIC; at least one SD power rail coupled between the at least one SD PMIC and the security domain of the SoC for supplying power to the security domain of the SoC; MD PMIC power rail, the MD PMIC power rail is coupled to the at least one an MD PMIC for supplying power to the at least one MD PMIC; and an SD PMIC power rail coupled to the at least one SDPMIC for powering the at least one SD PMIC, wherein the at least one SDPMIC has an input coupled to the MD PMIC power rail for monitoring the MDPMIC power rail.

14. The apparatus of claim 13, wherein the at least one SD PMIC has an output coupled to an input of the secure domain of the SoC for indicating a state of the MDPMIC power rail. 15 . The apparatus of claim 13 , wherein the input of the at least one SD PMIC is coupled to an analog-to-digital converter (ADC) channel or a remote sense pin of the at least one SD PMIC.

16. The apparatus of claim 13, wherein the at least one SD PMIC has an output for coupling to an input of a control unit or safety monitor external to the apparatus for indicating a status of the MD PMIC power rail.

17. The apparatus of claim 13, wherein the security domain of the SoC is independent of the primary domain of the SoC.

18. The apparatus of claim 13, wherein the security domain of the SoC is configured to support a more stringent security standard than the primary domain of the SoC.

19. The apparatus of claim 13, wherein the safety domain of the SoC is configured to comply with up to Automotive Safety Integrity Level (ASIL) D requirements, and wherein the primary domain of the SoC is configured to comply with up to ASIL B requirements.

20. The apparatus of claim 19, wherein the at least one SD PMIC is configured to comply with up to the ASIL D requirements, and wherein the at least one MD PMIC is configured to comply with up to the ASIL B requirements.

21. A method for power supply monitoring, the method comprising: regulating power to a master domain of a system on chip (SoC) using at least one master domain (MD) power management integrated circuit (PMIC); regulating power to a security domain of the SoC using at least one security domain (SD) PMIC; powering the at least one SD PMIC using an SD PMIC power rail; as well as The SD PMIC power rail is monitored using the at least one MD PMIC.

22. The method according to claim 21, further comprising: An indication of a status of the SD PMIC power rail is communicated from the at least one MD PMIC to the primary domain of the SoC.

23. The method according to claim 21, further comprising: An indication of a status of the SD PMIC power rail is communicated from the at least one MD PMIC to a control unit external to a module including the SoC.

24. The method according to claim 21, further comprising: powering the at least one MD PMIC using a MD PMIC power rail; as well as The MD PMIC power rail is monitored using the at least one SD PMIC.

25. The method according to claim 24, further comprising: An indication of a status of the MD PMIC power rail is communicated from the at least one SDPMIC to the secure domain of the SoC.

26. The method according to claim 24, further comprising: An indication of the status of the MD PMIC power rail is communicated from the at least one SDPMIC to a control unit or safety monitor external to a module including the SoC.

27. A method for power supply monitoring, the method comprising: regulating power to a master domain of a system on chip (SoC) using at least one master domain (MD) power management integrated circuit (PMIC); regulating power to a security domain of the SoC using at least one security domain (SD) PMIC; powering the at least one MD PMIC using a MD PMIC power rail; as well as The MD PMIC power rail is monitored using the at least one SD PMIC.

28. The method according to claim 27, further comprising: An indication of a status of the MD PMIC power rail is communicated from the at least one SDPMIC to the secure domain of the SoC.

29. The method according to claim 27, further comprising: An indication of the status of the MD PMIC power rail is communicated from the at least one SDPMIC to a control unit or safety monitor external to a module including the SoC.

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