Bandgap reference voltage generation circuit and semiconductor device including same

Abstract

The present invention relates to a bandgap reference voltage generation circuit capable of stably generating a bandgap reference voltage by implementing a stable start-up operation regardless of a change in a driving environment. According to an embodiment, a bandgap reference voltage generation circuit may include: a start-up circuit that outputs a start-up signal when a first power supply voltage rises; in one embodiment, a start-up circuit for a bandgap reference circuit includes a bandgap reference core circuit where operation is enabled in response to a start-up signal, and the bandgap reference core circuit generates and outputs a bandgap reference voltage, where the start-up circuit may include: a beta multiplier reference circuit including a cascade current mirror circuit, the cascade current mirror circuit forms a first current path and a second current path between the first power line and the second power line; a start-up output unit that outputs a start-up signal in response to a voltage of an output node of the second current path; and a comparator that compares a bandgap reference voltage with a target voltage to disable operation of the start-up circuit.

Description

Technical Field

[0001] The present invention relates to a bandgap reference voltage generating circuit capable of reliably generating a bandgap reference voltage and a semiconductor device having the bandgap reference voltage generating circuit. Background Art

[0002] Various electronic devices including home appliances, smart phones, wearable devices, etc. include semiconductor devices such as a microcontroller unit (MCU), a memory, and the like.

[0003] A semiconductor device includes a bandgap reference voltage generation circuit that supplies stable internal power using power supplied from an external source.

[0004] The bandgap reference voltage generation circuit requires a characteristic of being able to stably generate and supply a reference voltage even when driving environments such as power supply voltage, process, and temperature change.

[0005] Recently, a bandgap reference voltage generating circuit may malfunction during an initial startup operation due to a change in a driving environment, resulting in an abnormal reference voltage being output; therefore, a stable startup operation is required regardless of the change in the driving environment. Summary of the invention

[0006] Technical issues

[0007] The present invention provides a bandgap reference voltage generation circuit capable of stably generating a bandgap reference voltage by achieving a stable start-up operation independent of a driving environment change, and a semiconductor device having the bandgap reference voltage generation circuit.

[0008] Technical Solution

[0009] A bandgap reference voltage generating circuit according to an embodiment of the present invention may include: a startup circuit, which is configured to output a startup signal when a first power supply voltage rises; and a bandgap reference core circuit, which is configured to be activated in response to the startup signal and generate and output a bandgap reference voltage, wherein the startup circuit may include: a β multiplier reference circuit, which includes a cascade current mirror circuit, and the cascade current mirror circuit forms a first current path and a second current path between a first power line and a second power line; a startup output unit, which is configured to output the startup signal in response to a voltage at an output node of the second current path; and a comparator, which is configured to compare the bandgap reference voltage with a target voltage to disable the operation of the startup circuit.

[0010] A semiconductor device according to an embodiment of the present invention may include: the bandgap reference voltage generation circuit; and a device circuit configured to receive and use the bandgap reference voltage from the bandgap reference voltage generation circuit.

[0011] Technical Effects

[0012] According to one embodiment of the present invention, a bandgap reference voltage generating circuit can stably generate and output a bandgap reference voltage by using a β multiplier reference circuit to allow a startup circuit to stably start each circuit stage of a bandgap reference core circuit regardless of changes in a driving environment (such as a rise time of a power supply voltage, process variations, and temperature variations).

[0013] According to an embodiment of the present invention, a bandgap reference voltage generating circuit can generate and output a bandgap reference voltage that is highly (insensitive) to power supply noise using a startup circuit through a Schmitt trigger circuit.

[0014] According to an embodiment of the present invention, a bandgap reference voltage generating circuit can terminate the operation of a startup circuit by using a comparator when the bandgap reference voltage is higher than a target voltage, thereby realizing a stable startup circuit independent of changes in a driving environment without additional power consumption.

[0015] According to one embodiment of the present invention, a semiconductor device including a bandgap reference voltage generating circuit can ensure operation reliability by stably receiving and using a reference voltage independently of changes in a driving environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a block diagram schematically showing a semiconductor device according to one embodiment of the present invention.

[0017] Figure 2 is a block diagram showing a bandgap reference voltage generating circuit according to one embodiment of the present invention.

[0018] Figure 3 : is a circuit diagram specifically showing a startup circuit in a bandgap reference voltage generation circuit according to an embodiment of the present invention.

[0019] Figure 4 Detailed description of a bandgap reference core circuit in a bandgap reference voltage generating circuit according to an embodiment of the present invention.

[0020] Figure 5 is a graph showing start-up operation characteristics of a bandgap reference voltage generating circuit under a first driving condition according to an embodiment of the present invention.

[0021] Figure 6 is a graph showing the start-up operation characteristics of the bandgap reference voltage generating circuit according to one embodiment of the present invention under the second driving condition. DETAILED DESCRIPTION

[0022] Throughout the specification, the same reference numerals represent substantially the same components. In the following description, if the configurations and features known in the art are irrelevant to the core configuration of the present invention, their detailed descriptions may be omitted. The terms used in this specification should be understood as follows.

[0023] From the embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present invention and the methods for achieving them will become apparent. However, the present invention is not limited to the following embodiments, but can be implemented in various different forms; on the contrary, this embodiment is provided to make the description of the present invention complete and to enable those skilled in the art to fully understand the scope of the present invention, and the present invention is limited only within the scope of the appended claims.

[0024] Throughout the specification, the same reference numerals may denote the same components. Furthermore, in describing the present invention, if it is deemed that a detailed description of known related art unnecessarily obscures the gist of the present invention, the detailed description thereof may be omitted.

[0025] Terms such as "including," "having," "comprising," etc. used herein are generally intended to allow the addition of other components unless these terms are used with the term "only." Reference to a component of a singular noun includes the plural of the noun unless specifically stated otherwise.

[0026] When describing a temporal context, for example, such as "after," "following," "next," or "before," unless "immediately" or "directly" is used, the term may also include non-sequential cases.

[0027] First, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component referred to herein may also be the second component within the technical concept of the present invention.

[0028] It should be understood that the term "at least one" includes any combination that can be presented from one or more related items. For example, the meaning of "at least one of a first item, a second item, and a third item" can represent each of the first item, the second item, and the third item, and any combination of items that can be presented from two or more of the first item, the second item, and the third item.

[0029] Each feature of the various embodiments of the present invention may be coupled or combined with each other in whole or in part, and may be technically interlocked and operated in various ways, and each embodiment may be performed independently or in combination with each other.

[0030] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 is a block diagram schematically showing a semiconductor device according to one embodiment of the present invention.

[0032] Reference Figure 1 , the semiconductor device 10 may include a bandgap reference voltage generating circuit 100 and a device circuit 200 .

[0033] In one embodiment, the semiconductor device 10 may be an electronic device such as a semiconductor chip that generates a data signal based on power supplied from an external source. For example, the semiconductor device 10 may be any of various semiconductor devices such as a microcontroller unit (MCU), a processor, a power management integrated circuit (PMIC), a memory, etc., included in a device such as a computer, a smart phone, a tablet computer, etc.

[0034] The device circuit 200 may include analog and digital circuits such as analog circuits, digital circuits, analog-to-digital converters, and digital-to-analog converters, or a combination thereof, which require the bandgap reference voltage VBGR in the semiconductor device 10 .

[0035] The bandgap reference voltage generation circuit 100 can stably generate a reference voltage VBGR using a power supply voltage provided from an external source regardless of a change in a driving environment (including at least one of a power supply voltage change, a process change, and a temperature change), and can output the reference voltage VBGR to the device circuit 200. The bandgap reference voltage generation circuit 100 can generate a normal reference voltage VBGR by achieving a stable startup operation regardless of a change in a driving environment, and output the normal reference voltage VBGR to the device circuit 200.

[0036] Figure 2 is a block diagram showing a bandgap reference voltage generating circuit according to one embodiment of the present invention.

[0037] Reference Figure 2 The bandgap reference voltage generating circuit 100 may include a startup circuit 110 and a bandgap reference core circuit 120 .

[0038] The startup circuit 110 may be activated to output the startup signal Sout when the power supply voltage rises, thereby reliably starting the operation of the bandgap reference core circuit 120 .

[0039] The startup circuit 110 may stably start each circuit stage of the bandgap reference core circuit 120 by using a beta multiplier reference (BMR) circuit regardless of variations in driving environments such as power supply voltage, process, and temperature.

[0040] The startup circuit 110 may stably start the bandgap reference core circuit 120 regardless of power supply noise by using a Schmitt trigger circuit.

[0041] The startup circuit 110 may use a comparator to monitor the bandgap reference voltage VBGR fed back from the bandgap reference core circuit 120. The comparator may disable the startup circuit 110 after the bandgap reference voltage VBGR reaches a target voltage, thereby preventing the bandgap reference voltage VBGR from being output as an abnormal voltage and reducing power consumption.

[0042] The bandgap reference core circuit 120 may include a bias circuit 122, a bandgap reference voltage VBGR generator 124, and an amplification circuit 126. The bias circuit 122, the bandgap reference voltage VBGR generator 124, and the amplification circuit 126 may be activated in response to a startup output signal Sout output from the startup circuit 11.

[0043] The bias circuit 122 may generate a bias and allow current to flow through the reference voltage generator 124 via a current mirror circuit.

[0044] The amplifier circuit 126 may perform gain amplification and feedback loop operations to make a pair of input nodes connected to the bandgap reference voltage VBGR generator 124 equipotential.

[0045] The reference voltage generator 124 may stably generate and output the bandgap reference voltage VBGR regardless of changes in driving environments such as power supply voltage, process, and temperature.

[0046] Figure 3 and Figure 4 is a detailed circuit diagram showing a bandgap reference voltage generating circuit according to one embodiment of the present invention.

[0047] Reference Figure 3 and Figure 4 The bandgap reference voltage generating circuit 100 may include a startup circuit 110 and a bandgap reference core circuit 120 .

[0048] The startup circuit 110 and the bandgap reference core circuit 120 are commonly connected to a first power line VDDL supplied with a first power voltage VDD and a second power line VSSL supplied with a second power voltage VSS. The first power voltage VDD may be a positive power voltage, and the second power voltage VSS may be a ground voltage or a negative power voltage.

[0049] Reference Figure 3 The startup circuit 110 may include a beta multiplier reference (BMR) circuit 112 , a startup control section 114 , a startup output section 116 , and a comparator 118 .

[0050] The BMR circuit 112 may have a cascade current mirror circuit structure, in which a first PMOS transistor PM1 and a second PMOS transistor PM2 constituting a P-type metal oxide semiconductor (PMOS) current mirror circuit and a first NMOS transistor NM1 and a second NMOS transistor NM2 constituting an N-type metal oxide semiconductor (NMOS) current mirror circuit are connected in a cascade form between a first power line VDDL and a second power line VSSL, and the BMR circuit 112 may further include a resistor R9 connected between the first power line VDDL and a source terminal of the second PMOS transistor PM2.

[0051] A gate terminal of the first PMOS transistor PM1 and a gate terminal of the second PMOS transistor PM2 may be commonly connected to a first node N1, and a gate terminal of the first NMOS transistor NM1 and a gate terminal of the second NMOS transistor NM2 may be commonly connected to a second node N2. A gate terminal and a drain terminal of the first PMOS transistor PM1 may be commonly connected to the first node N1, and a gate terminal and a drain terminal of the second NMOS transistor NM2 may be commonly connected to a second node N2. A drain terminal of the first PMOS transistor PM1 and a drain terminal of the first NMOS transistor NM1 may be connected via a third node N3, and a drain terminal of the second PMOS transistor PM2 and a drain terminal of the second NMOS transistor NM2 may be connected via a fourth node N4. A first current path may be formed by the first PMOS transistor PM1 and the first NMOS transistor NM1, and a second current path may be formed by the second PMOS transistor PM2 and the second NMOS transistor NM2.

[0052] The BMR circuit 112 may further include a third PMOS transistor PM3 connected between the second PMOS transistor PM2 and the second NMOS transistor NM2, and an eleventh NMOS transistor NM11 connected between the second node N2 and the second power line VSSL. The gate terminals of the second PMOS transistor PM2 and the eleventh NMMOS transistor NM11 are commonly connected to the output terminal of the comparator 112, and a switching operation may be performed according to an output signal V12_OK of the comparator 112 to terminate the operation of the startup circuit 110.

[0053] The start-up control section 114 may include a third NMOS transistor NM3 connected between the first node N1 and the second node N2 of the BMR circuit 112 in a diode form to start the operation of the BMR circuit 112 .

[0054] Specifically, when the first power supply voltage VDD rises from 0V to 5V, the first PMOS transistor PM1, the third NMOS transistor NM3 and the second NMOS transistor NM2 act as diodes through the operation of the third NMOS transistor NM3 of the startup control part 114 to allow the startup START_UP current to flow so that the BMR circuit 112 can start and operate.

[0055] After the BMR circuit 112 operates, the first current flows to the third node N3 through the first current path of the first PMOS transistor PM1 and the first NMOS transistor NM1, and the second current flows to the fourth node N4 through the second current path of the second PMOS transistor PM2 and the second NMOS transistor NM2. Based on the operating principle of the BMR circuit 112, the second current "I" flowing to the fourth node N can be determined as in the following equation 1:

[0056] [Equation 1]

[0057]

[0058] In Equation 1, R9 represents a resistance value of the resistor R9 , β represents a current gain of the first PMOS transistor PM1 , and K represents an area multiple of the second PMOS transistor PM2 with respect to the first PMOS transistor PM1 .

[0059] During operation of the BMR circuit 112, when the voltages at the third node N3 and the fourth node N4 of the BMR circuit 112 become equal to each other as the first power supply voltage VDD rises, the voltages at the first node N1 and the second node N2 become equal to each other, thereby turning off the third NMOS transistor NM3. The fourth node N4 of the BMR circuit 112 may be represented as an output node of the BMR circuit 112.

[0060] The startup output section 116 may output a startup signal Sout to the bandgap reference core circuit 120 via the output node N5 in response to the voltage at the fourth node N4 of the BMR circuit 112. The startup output section 116 may include a Schmitt trigger circuit 117, a fifth NMOS transistor NM5 as a switching element, and a resistor R3.

[0061] When the voltage of the fourth node N4 becomes higher than the rising threshold voltage (Vth=0.8V) of the Schmitt trigger circuit 117 by the operation of the BMR circuit 122, the Schmitt trigger circuit 117 may output a high signal. The fifth NMOS transistor NM5 may be turned on in response to the high output of the Schmitt trigger circuit 117. Therefore, the startup output section 116 may start each circuit stage of the bandgap reference core circuit 120 by outputting the startup output signal Sout in a low state to the output node N5 via the turned-on fifth NMOS transistor NM and the resistor R3. The output terminal of the Schmitt trigger circuit 117 may be represented by a BGR_start node.

[0062] The comparator 118 may compare the bandgap reference voltage VBGR supplied to the first input terminal (+) fed back from the bandgap reference core circuit 120 with the target voltage Vref supplied to the second input terminal (-) to output an output signal V12_OK. When the bandgap reference voltage VBGR generated by the bandgap reference core circuit 120 reaches the target voltage Vref and stabilizes at the target voltage Vref, the comparator 118 may terminate the operation of the startup circuit 110 by outputting the signal V12_OK. The target voltage Vref may be generated by a voltage dividing node between the voltage dividing resistors R10 and R11 connected in series between the first power line VDDL and the second power line VSSL, and may be provided to the second input terminal (-) of the comparator 118.

[0063] When the bandgap reference voltage VBGR is lower than the target voltage Vref, the comparator 118 may output an output signal V12_OK in a low state. In response to the output signal V12_OK in a low state, the third PMOS transistor PM3 may be turned on to form a current path through which the current I flows to the fourth node N4 of the BMR circuit 112, and the eleventh NMOS transistor NM11 may be turned off.

[0064] When the bandgap reference voltage VBGR is stable and becomes higher than the target voltage Vref, the comparator 118 may output an output signal V12_OK in a high state to terminate the operation of the startup circuit 110. In response to the output signal V12_OK in a high state, the third PMOS transistor PM3 is turned off and the eleventh NMMOS transistor NM11 is turned on, thereby discharging the voltage at the second node N2 to the second power supply line VSSL. When the third PMOS transistor PM3 is turned off, the fourth node N4 may be in a low state, and the output of the Schmitt trigger circuit 117 may be switched to a low state. The fifth NMOS transistor NM5 may be turned off by the low state output of the Schmitt trigger circuit 117, and the operation of the startup circuit 110 may be terminated.

[0065] Reference Figure 4 The bandgap reference core circuit 120 may include a bias circuit 122 , a bandgap reference voltage VBGR generator 124 , and an amplification circuit 126 .

[0066] The bias circuit 122 may include a fourth PMOS transistor PM4 and a third bipolar junction transistor (BJT) Q3 connected in series between the first power line VDDL and the second power line VSSL, a resistor R7 connected in series between the first power line VDDL and the base terminal of the third BJT Q3, a fifth PMOS transistor PM5 and a sixth NMOS transistor NM6.

[0067] A gate terminal of the fourth PMOS transistor PM4 may be connected to the output node N5 of the startup circuit 110 , a source terminal thereof may be connected to the first power line VDDL, and a drain terminal thereof may be connected to the collector terminal of the third BJT Q3 .

[0068] A base terminal of the third BJT Q3 may be connected to a source terminal of the sixth NMOS transistor NM6 , and an emitter terminal of the third BJT Q3 may be connected to the first power line VSSL.

[0069] The gate terminal of the fifth PMOS transistor PM5 is connected to its drain terminal, the source terminal of the fifth PMOS transistor PM5 is connected to the first power line VDDL via the resistor R7 , and the drain terminal of the fifth PMOS transistor PM5 may be connected to the drain terminal of the sixth NMOS transistor NM6 .

[0070] A gate terminal of the sixth NMOS transistor NM6 may be connected to a drain terminal of the fourth PMOS transistor PM4 and a collector terminal of the third BJT Q3 .

[0071] The bandgap reference voltage VBGR generator 124 may include: a sixth PMOS transistor PM6, which forms a current mirror circuit together with the fifth PMOS transistor PM5 of the bias circuit 122; a seventh PMOS transistor PM7 and an eighth PMOS transistor PM8, which form a cascade current mirror circuit between the first power line VDDL and the second power line VSSL; a second BJT Q2 and a first BJT Q1; and resistors R1, R2 and R8.

[0072] A gate terminal of the sixth PMOS transistor PM6 is connected to the gate terminal of the fifth PMOS transistor PM4, a source terminal of the sixth PMOS transistor PM6 is connected to the first power line VDDL through the eighth resistor R8, and a drain terminal of the sixth PMOS transistor PM6 can be connected to the base terminals of the second BJT Q2 and the first BJT Q1.

[0073] The gate terminals of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are connected to the output node N5 of the startup circuit 110, and the source terminals of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 can be connected to the first power supply line VDDL. The drain terminal of the seventh PMOS transistor PM7 can be connected to the collector terminal of the second BJT Q2 via the sixth node N6. The drain terminal of the eighth PMOS transistor PM8 can be connected to the collector terminal of the first BJT Q1 via the seventh node N7.

[0074] A base terminal of the second BJT Q2 may be connected to a base terminal of the first BJT Q1 , and an emitter terminal of the second BJT Q2 may be connected to a second power supply line VSSL through resistors R2 and R1 connected in series.

[0075] A base terminal of the first BJT Q1 is connected to a collector terminal thereof, and an emitter terminal of the first BJT Q1 may be connected to a connection node between the second resistor R2 and the first resistor R1 .

[0076] The first to third BJTs Q1 to Q3 are NPN type bipolar junction transistors, but PNP type bipolar junction transistors may also be applied without limitation.

[0077] The amplification circuit 126 may include: a ninth PMOS transistor PM9 and a tenth PMOS transistor PM10 and resistors R4 and R5, which are connected to the first power line VDDL and form a current mirror circuit; a seventh NMOS transistor NM7 and an eighth NMOS transistor NM8, which form an amplification input part connected to the sixth node N6 and the seventh node N7 of the bandgap reference voltage generator 124; a ninth NMOS transistor NM9 and a tenth NMOS transistor NM10, which form a self-bias circuit; an eleventh PMOS transistor PM11; and a resistor R6.

[0078] The gate terminals of the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 may be connected to each other, the source terminals of the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 may be commonly connected to the first power supply line VDDL, and the drain terminals of the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 may be connected to the drain terminals of the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8. A fourth resistor R4 may be connected between the gate terminal and the drain terminal of the ninth PMOS transistor PM9, and a fifth resistor R5 may be connected between the gate terminal and the drain terminal of the tenth PMOS transistor PM10.

[0079] Gate terminals of the seventh and eighth NMOS transistors NM7 and NM8 are input nodes of the amplification circuit 126 connected to the sixth and seventh nodes N6 and N7, and source terminals of the seventh and eighth NMOS transistors NM7 and NM8 may be commonly connected to a drain terminal of the ninth NMOS transistor NM9.

[0080] A gate terminal of the ninth NMOS transistor NM9 may be connected to a gate terminal of the tenth NMOS transistor NM10 , and source terminals of the ninth and tenth NMOS transistors NM9 and NM10 are commonly connected to the second power line VSSL, and a drain terminal and a gate terminal of the tenth NMOS transistor NM10 may be connected.

[0081] A gate electrode of the eleventh PMOS transistor PM11 may be connected to the output node N5 of the startup circuit 110 , a source terminal of the eleventh PMOS transistor PM11 may be connected to the first power line VDDL, and a drain terminal of the eleventh PMOS transistor PM11 may be connected to the drain terminal of the tenth NMOS transistor NM10 via the sixth resistor R6 .

[0082] The eighth node N8 connected between the ninth PMOS transistor PM9 and the seventh NMOS transistor NM7 can be the output node of the amplification circuit 126, and can be commonly connected to the gate terminals of the fourth PMOS transistor PM4, the seventh PMOS transistor PM7, the eighth PMOS transistor PM8 and the eleventh PMOS transistor PM11 connected to the output node N5 of the startup circuit 110.

[0083] In response to the low-state start output signal Sout output by the start circuit 110, the fourth PMOS transistor PM4 of the bias circuit 122 of the bandgap reference core circuit 120, the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 of the bandgap reference voltage VBGR generator 124, and the eleventh PMOS transistor PM11 of the amplifier circuit 126 are turned on, so that each stage of the circuit is started and operates.

[0084] The bias circuit 122 can generate a bias through an activation loop of the fourth PMOS transistor PM4, the third BJT Q3 and the sixth NMOS transistor NM6, and generate a base current I_BASE through the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 to provide it to the bases of the second BJT Q2 and the first BJT Q1 of the bandgap reference voltage VBGR generator 124.

[0085] The bandgap reference voltage VBGR generator 124 may generate a current flowing through a sixth node N6 of the second BJT Q2 and a current I_BJT flowing through a seventh node N7 of the first BJT Q1 through the activated seventh and eighth PMOS transistors PM7 and PM8 and a base current I_BASE.

[0086] The amplifier circuit 126 can perform gain amplification and feedback loop operations to make the sixth node N6 and the seventh node N7 equal in potential by differentially amplifying the voltages of the sixth node N6 and the seventh node N7 and outputting the amplified signal through the eighth node N8 to adjust the currents of the fourth PMOS transistor PM4, the seventh PMOS transistor PM7, the eighth PMOS transistor PM8 and the eleventh PMOS transistor PM11.

[0087] The bandgap reference voltage VBGR generator 124 may generate the bandgap reference voltage VBGR using the current I_BJT flowing to the seventh node N7 and output the bandgap reference voltage VBGR via the seventh node N7. The bandgap reference voltage VBGR may be determined as in Equation 2 below.

[0088] [Equation 2]

[0089]

[0090] In the above equation 2, VBE1 represents the voltage between the base and the emitter of the first BJT Q1, ΔVBE represents the voltage difference between the voltage VBE2 between the base and the emitter of the second BJT Q2 and the voltage VBE1 between the base and the emitter of the first BJT Q1, and R2 and R1 represent the resistance values ​​of the resistors R2 and R1 connected to the emitter terminals of the second BJT Q2 and the first BJT Q1. Referring to equation 2, the bandgap reference voltage VBGR generator 124 can be generated by eliminating the VBE1 term inversely proportional to the absolute temperature and the 2ΔV proportional to the absolute temperature. BE ×(R2 / R1) term to generate a bandgap reference voltage VBGR that is independent of (insensitive to) temperature variations. Referring to equation 2 above, it can also be seen that the bandgap reference voltage VBGR is independent of process variations and variations in the power supply voltage VDD.

[0091] When the bandgap reference voltage VBGR becomes higher than the target voltage Vref, the operation of the startup circuit 110 is terminated by the high output V12_OK of the comparator 118 .

[0092] After the operation of the startup circuit 110 is terminated, the bandgap reference core circuit 120 can stably generate and output the bandgap reference voltage VBGR as the target voltage Vref by performing a feedback loop operation to make the sixth node N6 and the seventh node N7 equipotential through the gain amplification operation of the amplification circuit 126. In this case, the first BJT Q1 and the second BJT Q2 can ensure a sufficiently large voltage VBE between the base and the emitter, and can generate and output the bandgap reference voltage VBGR as the target voltage regardless of the rising time, process variation, and temperature variation of the first power supply voltage VDD.

[0093] Figure 5 is a graph showing startup operation characteristics of a bandgap reference voltage generating circuit according to an embodiment of the present invention in a first driving environment.

[0094] Figure 5 Operation characteristics of the bandgap reference voltage generating circuit 100 according to one embodiment are shown in a first driving environment, in which the rise time of the first power supply voltage VDD is 1 ms, the process corner TT (typical-typical), and the temperature is 25°C.

[0095] Reference Figures 3 to 5 , when the first power supply voltage VDD rises from 0V to 5V, the startup circuit 110 can operate from the first time point t1 to the second time point t2 to output the startup output signal Sout in a low state, and the bandgap reference core circuit 120 can generate and output the bandgap reference voltage VBGR rising from 0V. It can be seen that when the bandgap reference voltage VBGR increases to be higher than the target voltage Vref=1.2V at the second time point t2, the operation of the startup circuit 110 is terminated by the high output V12_OK of the comparator 118, and the bandgap reference core circuit 120 can stably generate and output the bandgap reference voltage VBGR corresponding to the target voltage Vref=1.2V.

[0096] Figure 6 is a graph showing startup operation characteristics of a bandgap reference voltage generating circuit according to an embodiment of the present invention in a second driving environment.

[0097] Figure 6 The operation characteristics of the bandgap reference voltage generating circuit 100 according to one embodiment in a second driving environment are shown, in which the rise time of the first power supply voltage VDD is 2s, the process corner SS (slow-slow), and the temperature is -40°C.

[0098] Reference Figure 3 , Figure 4 and Figure 6, when the first power supply voltage VDD rises from 0V to 5V, the startup circuit 110 may operate from the third time point t3 to the fourth time point t4 to output the startup output signal Sout in a low state, and the bandgap reference core circuit 120 may generate and output the bandgap reference voltage VBGR rising from 0V. It can be seen that when the bandgap reference voltage VBGR increases to be higher than the target voltage Vref=1.2V at the fourth time point t4, the operation of the startup circuit 110 is terminated by the high output V12_OK of the comparator 118, and the bandgap reference core circuit 120 stably generates and outputs the bandgap reference voltage VBGR corresponding to the target voltage Vref=1.2V.

[0099] As described above, the bandgap reference voltage generating circuit according to one embodiment of the present invention utilizes a β multiplier reference circuit to stably start each circuit stage of the bandgap reference core circuit, thereby being able to stably generate and output a bandgap reference voltage independently of changes in the driving environment such as the rise time of the power supply voltage, process variations, and temperature variations.

[0100] According to an embodiment of the present invention, a bandgap reference voltage generating circuit can generate and output a bandgap reference voltage that is highly (insensitive) to power supply noise using a startup circuit through a Schmitt trigger circuit.

[0101] According to an embodiment of the present invention, a bandgap reference voltage generating circuit can terminate the operation of a startup circuit by using a comparator when the bandgap reference voltage is higher than a target voltage, thereby realizing a stable startup circuit independent of changes in a driving environment without additional power consumption.

[0102] According to one embodiment of the present invention, a semiconductor device including a bandgap reference voltage generating circuit can ensure operation reliability by stably receiving and using a reference voltage independently of changes in a driving environment.

[0103] A bandgap reference voltage generating circuit according to an embodiment of the present invention may include: a startup circuit, which is configured to output a startup signal when a first power supply voltage rises; and a bandgap reference core circuit, which is configured to be activated in response to the startup signal and generate and output a bandgap reference voltage, wherein the startup circuit may include: a β multiplier reference circuit, which includes a cascade current mirror circuit, and the cascade current mirror circuit forms a first current path and a second current path between a first power line and a second power line; a startup output unit, which is configured to output the startup signal in response to a voltage at an output node of the second current path; and a comparator, which is configured to compare the bandgap reference voltage with a target voltage to disable the operation of the startup circuit.

[0104] The β multiplier reference circuit may include: a PMOS current mirror and an NMOS current mirror, the PMOS current mirror and the NMOS current mirror being connected in cascade between the first power line and the second power line; and

[0105] A startup control section is connected between a first node connected to a gate terminal of the PMOS current mirror and a second node connected to a gate terminal of the NMOS current mirror and is configured to start an operation of the beta multiplier reference circuit.

[0106] The PMOS current mirror may include: a first PMOS transistor included in the first current path and having a gate terminal and a drain terminal connected to the first node; a second PMOS transistor included in the second current path, having a gate terminal connected to the first node, and having an area that is K times (where K is a positive number) larger than the area of ​​the first PMOS transistor; and a resistor connected in series between the first power line and the second PMOS transistor, wherein a current flowing in the second current path may be determined by a current gain β of the first PMOS transistor, a multiple of K, and a resistance value of the resistor.

[0107] The NMOS current mirror may include: a first NMOS transistor included in the first current path and having a gate terminal connected to the second node; and a second NMOS transistor included in the second current path and having a gate terminal and a drain terminal connected to the second node.

[0108] The startup control section may include a third NMOS transistor connected between the first node and the second node in the form of a diode.

[0109] The startup control section may be configured to start the β multiplier reference circuit through the first PMOS transistor, the third NMOS transistor, and the second NMOS transistor connected in the form of a diode when the first power supply voltage supplied to the first power supply line rises.

[0110] When the first power supply voltage rises, the third NMOS transistor may be configured to be turned off when a voltage of a third node connected between the first PMOS transistor and the first NMOS transistor is equal to a voltage of an output node connected between the second PMOS transistor and the second NMOS transistor.

[0111] The β multiplier reference circuit may further include a third PMOS transistor configured to be controlled by the output of the comparator and connected between the second NMOS transistor and the second PMOS transistor.

[0112] The β multiplier reference circuit may further include an eleventh NMOS transistor configured to be controlled by the output of the comparator and connected between the second node and the second power line.

[0113] The comparator may be configured to turn on the third PMOS transistor and turn off the eleventh NMOS transistor when the bandgap reference voltage is lower than the target voltage, and to turn off the third PMOS transistor and turn on the eleventh NMOS transistor when the bandgap reference voltage is higher than the target voltage.

[0114] The startup output unit may include: a Schmitt trigger circuit connected to the output node between the third PMOS transistor and the second NMOS transistor; a fifth NMOS transistor configured to be controlled by the output of the Schmitt trigger circuit and connected between the output node of the startup circuit and the second power line; and a resistor connected between the output node of the startup circuit and the fifth NMOS transistor.

[0115] The enable output section may be configured to output the enable signal through the fifth NMOS transistor in response to an output of the Schmitt trigger circuit when a voltage of an output node of the β multiplier reference circuit is higher than a rising threshold voltage of the Schmitt trigger circuit.

[0116] The third PMOS transistor may be turned off in response to the output of the comparator, and the fifth NMOS transistor may be turned off in response to the output of the Schmitt trigger circuit.

[0117] The bandgap reference core circuit may include: a bias circuit, which is configured to generate a bias and generate a base current through the current mirror circuit when it is activated by the start signal; a bandgap reference voltage generator, which is configured to generate a bipolar junction transistor current using the base current and generate the bandgap reference voltage using the bipolar junction transistor current when it is activated by the start signal; and an amplifier circuit, which is configured to differentially amplify the voltages of the sixth node and the seventh node of the bandgap reference voltage generator to feed back to the bias circuit and the bandgap reference voltage generator when it is activated by the start signal, and control the bipolar junction transistor current.

[0118] A semiconductor device according to an embodiment of the present invention may include: the bandgap reference voltage generation circuit; and a device circuit configured to receive and use the bandgap reference voltage from the bandgap reference voltage generation circuit.

[0119] Those skilled in the art to which the present invention pertains will appreciate that the present invention described above may be implemented in other specific forms without changing its technical ideas or essential features.

[0120] Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present invention. The scope of the present invention is represented by the appended claims rather than the above detailed description, and should be interpreted as all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

[0121] Modes for carrying out the invention

[0122] Various ways of practicing the invention have been described in the preceding heading "Detailed Description of the Invention".

[0123] Industrial Applicability

[0124] The present invention can be applied to various electronic devices related to semiconductors and has industrial applicability.

Claims

1. A bandgap reference voltage generating circuit, the bandgap reference voltage generating circuit comprising: a startup circuit, the startup circuit being configured to output a startup signal when the first power supply voltage rises; as well as a bandgap reference core circuit configured to be activated in response to the start signal and to generate and output a bandgap reference voltage, Wherein, the starting circuit comprises: a beta multiplier reference circuit, the beta multiplier reference circuit comprising a cascade current mirror circuit forming a first current path and a second current path between a first power line and a second power line; an enable output section configured to output the enable signal in response to a voltage at an output node of the second current path; and A comparator is configured to compare the bandgap reference voltage with a target voltage to disable operation of the startup circuit.

2. The bandgap reference voltage generating circuit according to claim 1, wherein: The beta multiplier reference circuit comprises: A PMOS current mirror and an NMOS current mirror, wherein the PMOS current mirror and the NMOS current mirror are connected between the first power line and the second power line in a cascade form; and A startup control section is connected between a first node connected to a gate terminal of the PMOS current mirror and a second node connected to a gate terminal of the NMOS current mirror and is configured to start an operation of the beta multiplier reference circuit.

3. The bandgap reference voltage generating circuit according to claim 2, wherein: The PMOS current mirror comprises: a first PMOS transistor included in the first current path and having a gate terminal and a drain terminal connected to the first node; a second PMOS transistor included in the second current path, having a gate terminal connected to the first node and having an area K times larger than that of the first PMOS transistor, where K is a positive number; and a resistor connected in series between the first power line and the second PMOS transistor, and The current flowing in the second current path is determined by the current gain β of the first PMOS transistor, the multiple of K, and the resistance value of the resistor.

4. The bandgap reference voltage generating circuit according to claim 3, wherein: The NMOS current mirror comprises: a first NMOS transistor included in the first current path and having a gate terminal connected to the second node; and A second NMOS transistor is included in the second current path and has a gate terminal and a drain terminal connected to the second node.

5. The bandgap reference voltage generating circuit according to claim 4, wherein: The startup control unit includes: A third NMOS transistor is connected between the first node and the second node in the form of a diode.

6. The bandgap reference voltage generating circuit according to claim 5, wherein: The startup control section is configured to start up the β multiplier reference circuit through the first PMOS transistor, the third NMOS transistor, and the second NMOS transistor connected in the form of a diode when the first power supply voltage supplied to the first power supply line rises.

7. The bandgap reference voltage generating circuit according to claim 5, wherein: When the first power supply voltage rises, when the voltage of the third node connected between the first PMOS transistor and the first NMOS transistor is equal to the voltage of the output node connected between the second PMOS transistor and the second NMOS transistor, the third NMOS transistor is turned off.

8. The bandgap reference voltage generating circuit according to claim 4, wherein: The beta multiplier reference circuit also includes: a third PMOS transistor configured to be controlled by the output of the comparator and connected between the second NMOS transistor and the second PMOS transistor.

9. The bandgap reference voltage generating circuit according to claim 8, wherein: The beta multiplier reference circuit also includes: an eleventh NMOS transistor configured to be controlled by the output of the comparator and connected between the second node and the second power line.

10. The bandgap reference voltage generating circuit according to claim 9, wherein: The comparator is configured as: When the bandgap reference voltage is lower than the target voltage, the third PMOS transistor is turned on and the eleventh NMOS transistor is turned off, and When the bandgap reference voltage is higher than the target voltage, the third PMOS transistor is turned off and the eleventh NMOS transistor is turned on.

11. The bandgap reference voltage generating circuit according to claim 8, wherein: The startup output unit comprises: a Schmitt trigger circuit connected to the output node between the third PMOS transistor and the second NMOS transistor; a fifth NMOS transistor configured to be controlled by the output of the Schmitt trigger circuit and connected between an output node of the startup circuit and the second power line; and A resistor is connected between the output node of the startup circuit and the fifth NMOS transistor.

12. The bandgap reference voltage generating circuit according to claim 11, wherein: The enable output section is configured to output the enable signal through the fifth NMOS transistor in response to the output of the Schmitt trigger circuit when the voltage of the output node of the beta multiplier reference circuit is higher than a rising threshold voltage of the Schmitt trigger circuit.

13. The bandgap reference voltage generating circuit according to claim 12, wherein: When the third PMOS transistor is turned off in response to the output of the comparator, the fifth NMOS transistor is turned off in response to the output of the Schmitt trigger circuit.

14. The bandgap reference voltage generating circuit according to claim 11, wherein: The bandgap reference core circuit comprises: a bias circuit configured to generate a bias and generate a base current through the current mirror circuit when the bias circuit is activated by the start signal; a bandgap reference voltage generator configured to generate a bipolar junction transistor current using the base current and generate the bandgap reference voltage using the bipolar junction transistor current when the bandgap reference voltage generator is activated by the start signal; and an amplifier circuit configured to differentially amplify the voltages of the sixth node and the seventh node of the bandgap reference voltage generator to feed back to the bias circuit and the bandgap reference voltage generator, and control the current of the bipolar junction transistor when the amplifier circuit is activated by the start signal.

15. A semiconductor device, comprising: The bandgap reference voltage generating circuit according to any one of claims 1 to 14; as well as A device circuit is configured to receive and use the bandgap reference voltage from the bandgap reference voltage generating circuit.

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