Routing circuit for computer resource topology

Abstract

A routing circuit for an integrated circuit is configured to access a set of resources organized according to a topology having a plurality of dimensions. The router receives a request for a particular resource of the set of resources, the request including an address including a first set of bits and a second set of bits, the topology having a first dimension with n routing options (where n is not a power of two) and a second dimension with m routing options. The routing circuitry determines a first routing selection and a second routing selection for the first dimension and the second dimension by performing respective modulo-n operations and div-n operations on values formed by the addresses including the first bit set and the second bit set. The routing circuitry then activates one or more selection signals according to the first routing selection and the second routing selection, the one or more selection signals being usable to cause the particular resource to be selected in response to the request.

Description

Background Art Technical Field

[0001] The present disclosure relates generally to computer systems and, more generally, to routing requests for computer resources in a topology having a dimension where the number of options is not equal to a power of two.

[0002] Related technical description

[0003] Modern computer systems have become extremely complex. There are many different types of resources within such systems, and resources of a given type are often replicated to achieve performance benefits. A memory system is one such example of a hierarchical collection of resources within a computer system. Requests for these resources often include addresses that must be interpreted in order to determine a route to the appropriate resource. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The following detailed description refers to the accompanying drawings, which are now briefly described.

[0005] Figure 1 is a block diagram of routing circuitry in a computer system, the routing circuitry configured to determine routing selections for resources in a collection of resources having a topology with multiple dimensions, at least one of the multiple dimensions having a number of options that is not a power of two.

[0006] Figure 2 is an example of a memory system that is a collection of resources with multiple dimensions.

[0007] FIG. 3A to FIG. 3B An example of routing in a multi-dimensional topology is provided, where one dimension has a number of options n, where n is not a power of two.

[0008] FIG. 3C to FIG. 3D Provides examples of aliasing problems that can occur when addressing multi-dimensional topologies.

[0009] Figure 4A illustrates a lookup table that can be used to implement a mod-3 circuit.

[0010] FIG. 4B to FIG. 4C Depicted is a method for performing mod-3 operations on a number through a series of mod-3 operations on its components.

[0011] Figure 4D One embodiment of a circuit that can be used to calculate mod-3 on a number is illustrated.

[0012] Figure 5A A lookup table that may be used to implement one embodiment of a div-3 circuit is illustrated.

[0013] FIG. 5B to FIG. 5CA method for performing a div-3 operation is depicted.

[0014] Figure 5D One embodiment of a circuit that can be used to perform a div-3 operation is illustrated.

[0015] Fig. 6A Illustrated are lookup tables as well as functions and circuits that can be used to implement mod-15 functionality.

[0016] FIG. 6B to FIG. 6C One embodiment of a method for performing mod-15 operations is depicted.

[0017] Fig.6D One embodiment of a circuit that may be used to perform a mod-15 operation is illustrated.

[0018] Fig. 7A A lookup table that may be used to implement one embodiment of a div-15 circuit is illustrated.

[0019] FIG. 7B to FIG. 7C One embodiment of a method for performing a div-15 operation is depicted.

[0020] Fig.7D One embodiment of a circuit that can be used to calculate a div-15 operation is illustrated.

[0021] Figure 8 is a flow chart illustrating one embodiment of a method for performing routing on a collection of resources organized according to a topology having multiple dimensions.

[0022] Fig. 9 is a block diagram illustrating an example computing device for implementing the disclosed techniques.

[0023] Fig.10 is a diagram illustrating an example application of systems and devices employing the disclosed technology.

[0024] Fig.11 is a block diagram illustrating an example computer-readable medium storing circuit design information for implementing a device employing the disclosed techniques. DETAILED DESCRIPTION

[0025] A collection of computer resources may be arranged in a topology so that each "dimension" in the topology has multiple possible options. The number of options in a given one of these dimensions is usually equal to a power of two, because binary arithmetic has long been a building block of computer architecture. However, the inventors have recognized that it is desirable to be able to accommodate routing options that are not a power of two in one or more dimensions in the resource topology. Therefore, when faced with a scenario in which the number of routing (or hashing) options n for a first dimension is desired and n is not a power of two, a first value and a second value may be generated from a request address for a first dimension and a different second dimension in the topology. A series of mod-n operations may be performed on the first value to determine the routing selection for the first dimension, while a series of div-n operations (also using the mod-n result) may be performed on the second value to determine the routing selection for the second dimension. In this way, efficient routing that does not leave "holes" in the address space may be achieved. This method may be particularly useful in a setting in which one dimension of a previous topology (e.g., in a previous product release) has been changed from a value of a power of two to a value that is not a power of two in a new topology (e.g., for a new product release).

[0026] Overview

[0027] exist Figure 1 In the context of , the present application begins with a general discussion of using mod-n and div-n operations to perform routing on a hierarchical structure having at least one dimension with a number of routing options that is not a power of two. Figure 2 describes a specific use case for resources within the memory system, and FIG. 3A to FIG. 3B An example of routing within this use case is illustrated. FIG. 3C to FIG. 3D An example of aliasing is described. The present application next turns to mod 3 ( FIG. 4A to FIG. 4D ); div 3( FIG. 5A to FIG. 5D ); mod 15( FIG. 6A to FIG. 6D );div 15( FIG. 7A to FIG. 7D ) for specific possible mod-n and div-n implementations. Figure 8 A flow chart of a method for routing is described. Fig. 9 Exemplary devices are described on which the disclosed techniques may be employed (e.g., in computer circuits). Fig.10 Exemplary applications and platforms for such devices are described, and Fig.11 Computer-readable media storing design information that can be used to fabricate computer circuits configured to implement the disclosed techniques are described.

[0028] Hash that is not a power of two

[0029] This example is in Figure 1Example in Figure 1 A computer system 100 is depicted that includes a collection of resources 110. Various entities (not depicted) within computer system 100 will require access to one or more resources in collection 110. Accordingly, the requesting entity will generate a request for a resource that includes a request address 104. Routing circuitry 120 within computer system 100 is configured to receive request address 104 and generate a selection signal 150 that causes the requested resource to be selected for access.

[0030] like Figure 1 As shown, resource collection 110 is organized according to a topology having multiple dimensions. In order to use different terminology, resource collection 110 can also be considered as a hierarchical structure with different levels. Figure 2 An example organization of resources 110 is provided. Resource set 110 has at least two dimensions. Dimension a has n routing options (i.e., routing circuit 120 needs to select one of n different possibilities for dimension a), where n is not a power of two. Thus, n can be 3, 5, or 6, but not 2, 4, 8, 16, etc. Dimension b is a different dimension with m routing options.

[0031] One possible option for routing dimension a is to use an extra bit. For example, if n=3, then 2 bits can be used for routing in this dimension. However, the inventors recognize that this would be inefficient from a hashing perspective, and would mean that a portion of the memory space addressed by request address 104 would not be mapped to one of resources 110. That is, while address bits 00, 01, and 10 can be mapped to routing options 0, 1, and 2, address bit 11 will not be mapped to a viable option.

[0032] On the contrary, the inventor proposes to determine the routing selection for dimension a and b by utilizing a part of the request address 104 corresponding to both dimension a and b. As shown in the figure, address 104 has a first set of one or more positions 106f and a second set of one or more positions 106s, which correspond to the number of options in dimension a and b (that is, n and m, respectively). Position 106f can correspond to dimension a, and position 106s corresponds to dimension b, or vice versa. As shown in the figure, in some cases, there is an intermediate position 106i between position 106f and position 106s, because the inventor has found that when using more positions, the hash balance for dimension a (it has the option of the number that is not a power of two) is better. In address 104, there can also be a more effective position than position 106f and a more effective position than position 106s.

[0033] Address 104 is supplied to blocks 128 and 138, which generate first value 129 and second value 139, respectively. (As will be described with respect to FIG. 3, blocks 128 and 138 may apply mask values ​​to address 104 to generate first value 129 and second value 139. The masks used by blocks 128 and 138 may be the same or different.) In various embodiments, first value 129 and second value 139 may be generated so that they include bits 106f and 106s. Values ​​129 and 139 are then supplied to arithmetic circuit 126 including mod-n circuit 130 and div-n circuit 140.

[0034] Mod-n circuit 130 is configured to perform a mod-n operation on first value 129 to determine routing 132 for dimension a. Similarly, div-n circuit 140 is configured to perform a div-n operation on second value 139 to determine routing 142 for dimension b. As will be described below, in some implementations of arithmetic circuit 126, routings 132 and 142 may be determined together; for example, the div-n operation performed by circuit 140 may use a result from the mod-n operation performed by circuit 130 (e.g., Figure 1 140). For the example where n=3 and m=2, route selection 132 can be 0, 1, or 2, while route selection 142 can be 0 or 1. This arrangement provides a more efficient distribution (i.e., better hashing) of routing decisions for dimensions a and b than simply routing dimension a on its own using the extra address bits.

[0035] In conclusion, Figure 1Thus, an apparatus is illustrated, the apparatus comprising an integrated circuit comprising a set of storage locations (e.g., a set of resources 110) arranged according to a hierarchical structure having a plurality of levels, including a first dimension (or level) (e.g., dimension a) having n hash (or routing) options (n ​​being an integer that is not a power of two) and a second dimension (level) (dimension b) having m hash options. The apparatus also comprises a routing circuit (or hash circuit) (e.g., routing circuit 120). The circuit is configured to receive a request to access a particular storage location in the set of storage locations, the request comprising an address (e.g., request address 104) having a first set of bits (106f) and a second set of non-overlapping bits (106s). The routing circuit is further configured to determine a first hash value for the first level by performing a modulo-n operation on a first value formed by the address (e.g., using mod-n circuit 130). The routing circuit is further configured to determine a second hash value for the second level by performing a div-n operation on a second value formed by the address (e.g., using div-n circuit 130 and potential information from mod-n circuit 130). Furthermore, the routing circuit is configured to generate a plurality of selection signals (eg, selection signal 150 ) based on the first hash value and the second hash value that can be used to cause a particular storage location to be selected.

[0036] Consider an example where the request address is a 10-bit value 01 0101 1110 (of the form [9:0]). Assume that only bits [8:2] are of interest, and bits [8:7] are bits 106f, bits [4:2] are bits 106s, and bits [6:5] are bits 106i. In some embodiments, mask values ​​and combinatorial logic including an AND function (or its equivalent) may be used to implement Figure 1 Blocks 128 and 138 shown in FIG. In this example, the binary mask value 01 1001 1100 can be ANDed with the 10-bit address, with the highest bit [9] and the two lowest bits [1:0] discarded. (Alternatively, only bits [8:2] can be ANDed with the 7-bit mask 1100111.)

[0037] The following is about FIG. 4A to FIG. 4D (in the case of n=3) and FIG. 6A to FIG. 6D The potential structure and exemplary operation of mod-n circuit 130 are further described in the following (where n=15). FIG. 5A to FIG. 5D (in the case of n=3) and FIG. 7A to FIG. 7D The potential structure and exemplary operation of the div-n circuit 140 are further described (in the case of n=15). However, Figure 1 Without limitation to the cases of n=3 and n=15, these cases are provided as example implementations for values ​​of n that are not powers of two.

[0038] Figure 2 An exemplary resource set 110 is illustrated. Here, the resource set 110 corresponds to the memory system of the computer system 100. The memory system has a topology 200, which includes five dimensions: a memory controller dimension 212A, a memory plane dimension 212B, a memory bank dimension 212C, a memory row dimension 212D, and a memory column dimension 212E. Any type and number of dimensions are possible, and the memory system is simply shown for illustrative purposes. In this hierarchical structure, a "memory plane" is a combination of constituent memory banks and associated caches for those memory banks. This arrangement can produce a more scalable memory than a single cache for all memory banks. Each memory plane can also have its own independent memory pipeline.

[0039] Consider a request for memory location 220 based on address 104. In order to select memory location 220, five routing selections must be made, one for each dimension. First, routing selection is made for dimension 212A. Dimension 212A in this example includes two memory controllers 214A-214B. Secondly, routing selection is made for dimension 212B. Dimension 212B in this example includes three memory planes: 0, 1, and 2. Next, routing selection is made for dimension 212C. Dimension 212C includes multiple memory banks ranging from 0 to z. Once the memory banks are selected, routing selection is made for dimension 212D (rows) and dimension 212E (columns).

[0040] Portions of address 104 may be used to make various routing decisions for topology 200. For example, a single bit of address 104 may be used to select memory controller 0 or 1. In some computer systems, the number of options for routing decisions for each dimension in topology 200 may all be equal to a power of 2 (e.g., 2 options in one dimension, 4 options in another dimension, and 16 options in yet another dimension). However, different versions of a computer system may have different configurations. Thus, while computer topologies are often organized around powers of two, there may be desirable configurations in which a topology has dimensions with a number of options that are not a power of two. For example, if Figure 2 The dimension 212B shown has three options.This topology may be motivated by a desire to expand the memory hierarchy by adding another plane to an existing topology that has only two planes.

[0041] One possible solution is to use two bits to select a memory plane. Two bits can encode four possibilities (00, 01, 10, 11). However, the inventors have recognized that this method will create a "hole" in the memory space because one of the four possibilities will never be selected. Another method may be to completely redesign the routing logic. But because topology 200 may be a revision of a previous topology (for example, the only change may be the addition of a third memory plane), it is advantageous to retain a portion of the existing routing logic rather than completely redesigning the routing logic from scratch. Therefore, the techniques disclosed herein are particularly useful for modifying existing designs that are configured to select resources from a topology in which all levels have options that are powers of two. These techniques can therefore be used to change one or more levels to have options that are not a power of two, without affecting those parts of the design whose processing is not affected by the topology change.

[0042] Figure 3A An example 300 of routing in a topology including three memory planes, four memory banks per plane, four columns and two rows per memory bank is provided. Thus, there will be 3×4×4×2=96 possible routes, which may be represented as 0 to 95d. Example 300 shows how the value 95 may be routed.

[0043] In example 300, address 104 (which in one embodiment may be a physical address) has 7 bits, which are represented as follows: Figure 3A The format [6:0] is arranged as shown. Bits 6 and 5 correspond to Figure 1 , while bit 0 corresponds to bit set 106s (labeled here as y1). The presence of a single bit in y1 illustrates that a "set" can have one or more bits. Bits 4, 3, 2, and 1 correspond to Figure 1 The bit set 106i in .

[0044] Bits 3 and 4 are used to route the bank dimension, which has 4 options, while bits 1 and 2 are used to route the column dimension, which also has 4 options. An XOR hashing technique can be applied to bits 3 and 4 to determine their values ​​(e.g., address 104 can be masked with 0001000b and 0010000b consecutively to determine the values ​​of bits 3 and 4). This technique results in the routing of bank 3. Similarly, an XOR hash can be applied to bits 1 and 2, which results in the routing of column 3 of bank 3.

[0045] The memory plane dimensions and row dimensions are calculated differently. Block 128 applies the mask value M to address 104 to generate a first value 129. In example 300, M is 1100001b, which has the effect of producing a 7-bit value, where bits 1 through 4 will necessarily be 0. Thus, the mask M in this example has the effect of clearing bit 106i from address 104. Bits 0, 5, and 6 would be 1 if a corresponding 1 existed in address 104. Because address 104 is equal to 1011111, 1 exists at bits 0 and 6, but not at bit 5. Therefore, applying the mask value M to address 104 produces 1000001 for the first value 129, which is equivalent to 65d. The mod-3 circuit 130 can then evaluate mod 3 (65), which produces the value 2.

[0046] In example 300, the routing determination for the row dimension is calculated in a slightly similar manner. Block 129 applies the mask value M to address 104 to generate a second value 139 that is the same as first value 129 (65d). A bit extraction function may then be performed to obtain bits 6, 5, and 0 of second value 139 (101b or 5d). Div-3 circuit 140 may then evaluate div 3 (5), which produces a value of 1 for the row dimension.

[0047] Thus, 95d in example 300 is routed to memory plane 2, bank 3, row 1, and column 3.

[0048] In example 300, the same mask value is used to generate the first value 129 and the second value 139. However, the inventors have recognized that in some cases it may be desirable to use a larger number of bits for one of the dimensions. The inventors have found that this approach adds entropy to the hash.

[0049] Figure 3B Provides the use of Figure 3A Example 310 of routing with the same topology and address value (95d) as in Example 300. However, in Example 310, two different mask values ​​are used to generate the first value 129 and the second value 139. The mask value M2 used with respect to the row dimension is the same as the mask value M (1100001) in Example 300. However, the mask value M1 used for the plane dimension includes more bits. M1=1100 11 1, where the bits relative to M / M2 are underlined.

[0050] Therefore, the given form is <y1iiiiy2>The address of , where y1 (106f) and y2 (106s) represent the bits that were not masked out in the original mask, and iiii (106i) represents the middle bits, and additional middle bits i can be added to the mask to increase the hash entropy.

[0051] Thus, the first value 129 in example 310 is 71d, which also results in a selection that hashes to plane 2. The second value 139 is calculated in the same manner as in example 300, and thus also results in a selection of row 1. Thus, 95d in example 310 is also routed to memory plane 2, bank 3, row 1, and column 3.

[0052] Aliasing

[0053] Another design issue is aliasing, where two different addresses hash to the same set of routing decisions. For example, aliasing has occurred when two different addresses hash to the same plane, bank, row, and column. The inventors have determined that certain constraints can be applied to the selection of bits in the address used for routing decisions and to the selection of the mask used.

[0054] These constraints may vary in different applications. Consider FIG. 3A to FIG. 3B Continuation of the example of a memory hierarchy of , where addresses encode memory planes (determined by mod-n operations), memory rows (determined by div-n operations), memory banks (determined by XOR hashing), and memory columns (determined by XOR hashing). A possible set of restrictions on the hashing includes four separate constraints. First, the mask (M) for the plane dimension p ) is equal to the row dimension (M r ), or in M r The bits set in M p A subset of the bits set in M r can be 110 0001b, and M p It can be 110 0111b. Second, relative to M r In M p Any additional bits set in should belong to the memory column dimension. Consider a 7-bit address of the form [6:0], where bits [6:5] correspond to y2, bits [4:3] correspond to the bank dimension, bits [2:1] correspond to the column dimension, and bit [0] corresponds to y1, where y2+y1 jointly encodes the plane and row dimensions. In this scenario, 110 0001b and 110 0111b are M r and M p Third, although in M r and M p Any number of groups is permitted in M ​​(a "group" is a contiguous set of bits set to 1), but p There must be an even number of zeros between any two groups of ones in . Therefore, under this constraint, 110 0001b and 110 0111b are also M r and M p The effective value of p =110 0111b, there are two zeros between the two ones. r and M p The highest and lowest bits in M ​​are consistent, and r Between the highest group and the lowest group, M p There must be an even number of extra ones in M. Again, r =110 0001b and M p =110 0111b satisfies this constraint. r The highest and lowest groups in are as follows: 11 0 000 1 b. Between these groups, M p There are two extra ones in: 110 0 11 1b.

[0055] Figure 3C An example 320 is provided, where M r and M p The constraints listed above are violated. In particular, constraint 3 is violated because there is an odd number of zeros between y2 and y1. Figure 3C As can be seen, for M r and M p Of these values, the values ​​2 and 32 (in decimal) will both be hashed to the same plane (2), bank (0), row (0), and column (0).

[0056] Various other constraints may apply in other settings. For example, for an intermediate bit set 106i that separates a more significant first bit set 106f (which may also be referred to as y2) from a less significant second bit set 106s (y1), an anti-aliasing constraint may require an even number of zeros and ones between y2 and y1.

[0057] Figure 3D An example of how aliasing can occur is illustrated. Example 330 addresses the simple scenario where there are three memory planes, 4 banks per plane, four rows per bank, and 4 columns per row. An 8-bit address (which happens to be the physical address (PA) in this case) is used to encode the memory rows (bits [7:6]; labeled y2), banks (bits [5:4]; b), planes (bits [3:2]; p), and columns (bits [1:0]; c). Note that two bits are used to encode the plane dimension. Note also that constraint 1 is violated because M r =1100 0000b and M p =000 1100b. r The bits set in M p In fact, the bits set in FIG. 3A to FIG. 3B In contrast to the example shown, the hashing of the plane dimension has been decoupled from the hashing of the row dimension. Figure 3D As can be seen in , this leads to aliasing: for M r and M p Of these values, the values ​​0 and 12 (in decimal) will both be hashed to the same plane (0), bank (0), row (0), and column (0).

[0058] therefore, Figure 3D This illustrates the problem of trying to hash a single dimension with a number of options from the address bit group that is not a power of two. For the case of n=3, using one bit is not enough to generate 3 possible options. Figure 3D As exemplified in , using two (or more) bits for mod-3 arithmetic is problematic, Figure 3D It is shown that independently performing two-dimensional hashing on two different bit groups having a number of options that is not a power of two in one dimension may result in aliasing.

[0059] This problem is particularly problematic for physical memory. Consider Figure 3D A set of 8-bit values ​​that address rows, banks, planes, and columns in the memory, where each 8-bit value is different. Each 8-bit value should address a different combination of rows, banks, planes, and columns. If not Figure 3D If the situation in FIG. 5 is a case where the aliasing is caused, the resulting aliasing may cause data problems due to conflicting mappings (overwrites, incorrect data, etc.). The aliasing may also cause some parts of the physical memory to be unused.

[0060] However, the method of the present disclosure avoids these problems by encoding the first dimension and the second dimension using a set of bits (e.g., <106f><106i><106s>), where the first dimension has n options (where n is not a power of two) and is determined by a mod-n operation, and where the second dimension is determined by a div-n operation. This method avoids aliasing because for a distinct set of address values ​​(e.g., 8-bit values), the combination of mod-n and div-n will produce distinct values.<mod-n,div-n> In other words, given two different address values ​​a1 and a2 and n is an integer greater than two, it will not be the case that mod n(a1) = mod n(a2) AND div n(a1) = div n(a2). In short, the combination of mod-n and div-n will produce unique combinations of mod-n / div-n when given different inputs (with Figure 3D different).

[0061] Therefore, if an appropriate set of constraints specified at design time are followed, address aliasing should not occur. In some embodiments, routing circuitry 120 may also include checking circuitry that verifies at run time whether constraints are being violated or whether conditions exist that could cause aliasing. Such circuitry may have constraints / conditions stored in memory and may execute programs to verify that each constraint / condition is satisfied at different points in time (e.g., before allowing routing operations to occur).

[0062] Mod 3 and div 3 specific implementation

[0063] There are various ways to achieve Figure 1 1 and 2. The mod-n circuit 130 and div-n circuit 140 within arithmetic circuit 126 are shown in FIG. 1. One possible implementation for n=3 (meaning that circuit 130 computes a mod-3 operation and circuit 140 computes a div-3 operation) relies on the recognition that mod-3 and div-3 operations on numbers having a first bit width can be performed by performing mod-3 and div-3 operations on sub-portions of the number having a second smaller bit width. The method can be implemented using combinational and / or sequential logic and, in some cases, a look-up table (LUT). The LUT eliminates the need to employ full modulo and divide circuits, which can be expensive in terms of chip effective area.

[0064] Consider a bit width of 2 k+1 The binary number z, where the most significant half of the bits of z are represented by x, and the least significant half of the bits of z are represented by y. For a bit width of 16 bits, k = 3; for a bit width of 8 bits, k = 2. In either case, The inventors have recognized that mod 3(z) and div 3(z) can be found using the following formulas:

[0065] (1) mod 3(z) = mod 3(mod 3(x) + mod 3(y)); and

[0066] (2)

[0067] It can be seen that equation (1) depends on the mod-3 values ​​of the components x and y, while equation (2) depends on both the mod-3 and div-3 values ​​of x and y.

[0068] As an example of mod-3 and div-3 calculations for an 8-bit number, consider z=19d(0001 0011b), where x=1d=0001b and y=3d=0011b. The LUT can be queried to determine mod 3(x)=1, div3(x)=0, mod 3(y)=0, and div 3(y)=1.

[0069] Equation (1) can be evaluated to determine mod 3 (z = 19d) as follows:

[0070] mod 3(z)=mod 3(mod 3(0001b)+mod 3(0000b))=mod 3(1+0)=1.

[0071] On the other hand, equation (2) can be decomposed into multiple components:

[0072] (2.1)

[0073] (2.2)div 3(y);

[0074] (2.3)

[0075] (2.4) = div 3((2.3)); and

[0076] div 3(z)=(2.1)+(2.2)+(2.4).

[0077] Therefore, div 3 (z=19d) can be estimated as follows:

[0078] (2.1) (2.2)=div 3(y)=1d=0001b;

[0079] Left shifted by 4=0001 0000b=16d;

[0080] mod 3(y)=0000b;

[0081] (2.3)

[0082] (2.4)div 3((2.3))=div 3(16d)=5d=0101b;

[0083] div 3(z)=(2.1)+(2.2)+(2.4)=0000 0000b+0001m+0101b=6d; and div 3(z)=6d.

[0084] As mentioned previously, a LUT may facilitate calculation of mod-n and div-n values. Figure 4A An embodiment of a LUT 410 is shown that includes mod 3 values ​​for each possible 4-bit binary number and can be used for mod-3 and div-3 operations. LUT 410 is also referred to as LUT3-M to indicate that it stores mod-3 values, which distinguishes this LUT from other LUTs discussed later. LUT 410 can be used to calculate mod 3 for large values ​​of z by using equation (1) with respect to the constituent subdivisions of z. LUT 410 is relatively small and can advantageously provide fast lookup times.

[0085] Figure 4B A method 420 is illustrated in which mod 3 can be calculated for a 16-bit value (referred to as z) using LUT 410. At 422, z is divided into four 4-bit vectors z1 (z[15:12]), z2 (z[11:8]), z3 (z[7:4]), and z4 (z[3:0]). At 424, mod 3 is calculated for z1 to z4 using LUT 410; these values ​​are stored as m1 to m4, such that m1=mod3(z1), m2=mod3(z2), etc. At 426, m1 and m2 are combined using equation (1) to calculate mod 3 for {z1, z2}, and m3 and m4 are combined to calculate mod 3 for {z3, z4}. The value m5 is calculated by performing a lookup in LUT 410 to calculate mod 3 for the sum of m1 and m2. Similarly, the value m6 is calculated by performing a lookup in LUT 410 to calculate mod 3 for the sum of m3 and m4. (Because m1 through m4 have a maximum value of 2, the sum of m1+m2 and m3+m4 will not exceed 15, and thus the mod-3 of these sums can be found in LUT 410.) This process is repeated in 428, which includes performing a lookup in LUT 410 to calculate mod 3 for the sum of m5 and m6. The result is mod 3(z).

[0086] This method can be used for any width 2 k+1 Specifically, given an input z, z can be padded with leading zeros to obtain a width of 2 k+1 Next, z can be divided into blocks of four consecutive bits. Then, for each block of four consecutive bits, the LUT can be used to calculate div 3 and mod 3. Pairs of consecutive 4-bit blocks can be combined to calculate div 3 and mod 3 for 8-bit blocks according to equations (1) and (2). Subsequently, pairs of consecutive 8-bit blocks can be combined to calculate div 3 and mod 3 for 16-bit blocks again according to equations (1) and (2). The process of combining adjacent pairs of blocks is repeated until the result is a value of length z.

[0087] The method 420 thus illustrates a modulo-n operation where n=3. The method 420 includes determining, at 422, a modulo-n value for each of the equal sub-portions (z1 to z4) of the first value, which produces a current set of modulo-n results (m1 to m4). The method 420 then includes combining pairs of the current set of modulo-n results (e.g., combining m1 / m2 and combining m3 / m4) at 424 to obtain a new set of modulo-n results (m5, m6) having a greater number of bits than the previous modulo-n result, wherein the new set of modulo-n results becomes the current set of modulo-n results. Further, the method 420 includes repeating the combining of the current set of modulo-n results at 426 until the new set of modulo-n results has a single modulo-n result (m6) at the output of 428, which is the final result of the modulo-n operation on the first value. In some embodiments, the combining of 424 includes combining a given pair of a current set of modulo-n results corresponding to a first subportion of the address (denoted as x) and an immediately less significant subportion of the address (denoted as y), and combining a corresponding one of a new set of modulo-n results generated by computing the expression mod n (mod n(x)+mod n(y).

[0088] Figure 4C The use of method 420 to calculate mod 3 for a particular number is illustrated, in this case, z=55,618d, which can also be written as 1101 1001 0100 0010b. This z value can be divided by three 18,539 times, leaving a remainder of 1. The same result can also be calculated by method 420. In 422, the 16-bit value is divided into four-bit parts, and in 424, the mod-3 values ​​m1 to m4 (1, 0, 1, and 2, respectively) are calculated using LUT 410 using equation (1). This process is repeated in 426, as m1 is added to m2, and then mod 3 is calculated for the sum using LUT 410, resulting in m5=1. Similarly, m3 is added to m4, and then mod 3 is calculated for the sum using LUT 410, resulting in m6=0. Finally, in 428, m5 and m6 are added and mod 3 is calculated for the sum using LUT 410 again, yielding mod 3(z=55,618)=1.

[0089] The method 420 can be used to calculate mod 3 for any 16-bit binary number. In addition, the method 420 can be extended to calculate mod 3 for larger values.

[0090] Figure 4D An embodiment of a mod-3 circuit 130-3 is illustrated that takes a first value 129 (which is a 16-bit value) as input and computes a 4-bit version of the mod 3 of the first value 129 as a routing selection 132 for dimension a. As shown, the mod-3 circuit 130-3 may use an adder and a LUT 3-M (in Figure 4D This is accomplished using reference numerals 410A to 410G).

[0091] The mod-3 circuit 130-3 stores a first value in register 430A, which is represented as a variable z. Then, z is divided into four 4-bit vectors 432A to 432D, representing z[15:12]), z[11:8]), (z[7:4]), and (z[3:0]). The vectors 432A to 432D are then provided to the LUT3-M modules 410A to 410D. Each of the lookup table modules 410 returns a mod-3 value as an output 436A to 436D (also represented as m1 to m4). This approach eliminates the complexity of a custom mod-3 circuit and is feasible because there are only a small number of values ​​in the lookup table. Values ​​436A and 436B (m1 and m2) are summed using adder 438A, and a 4-bit sum 439A is provided to another lookup table 410E, which outputs a value 440A (m5), which corresponds to the mod-3 value of 432A cascaded with 432B (i.e., z[15:8]). Similarly, 436C to 436D (m3 and m4) are provided to adder 438B to produce a 4-bit sum 439B, which is provided to another lookup table 410F, which outputs 440B (m6). This value corresponds to the mod-3 value of 432C cascaded with 432D (i.e., z[7:0]). Next, 440A and 440B (m5 and m6) are summed using adder 438C to output a 4-bit sum 439C. The sum 439C is then provided to a lookup table 410G, which outputs a 4-bit routing selection 132 corresponding to the mod-3 value of the first value 129. This value can be used, for example, as a Figure 1 Routing of dimensions in the context of.

[0092] In some embodiments, mod-3 circuit 130-3 may be used as a stand-alone circuit external to arithmetic circuit 126 that is used to find the mod-3 value of any 16-bit input. Similarly, its output may be wired to any other circuit to efficiently generate a mod-3 value for a given input. In some embodiments, other computational components are used to implement the same operation. For example, a demultiplexer may be used to separate the value z in register 430A into 4 equal vectors. mod-3 circuit 130-3 may be implemented as a combinational circuit, but in other embodiments, the mod-3 circuit may be a sequential circuit whose subcomponents (e.g., register 430A, LUTs 410A to 410G) are clocked. In the embodiments below, LUTs 410A to 410G are separate LUTs, each with their own I / O, but in other embodiments, a single LUT (or LUTs) may be used. Figure 4D In some embodiments, the LUTs 410A to 410B and adder 438A can be replaced with a single 16-bit LUT by storing all possible values ​​of the calculation mod 3 (z1+z2), rather than calculating 436A to 436B, 439A, and 440A independently.

[0093] Steering FIG. 5A to FIG. 5D , LUT 410 may also be used in conjunction with other LUTs to calculate div 3(z) according to equation (2). Figure 5A A plurality of LUTs are shown that may be used in one embodiment of a div 3 (z) operation. LUT 510A (also referred to as LUT3-D4) includes a div 3 value for each 4-bit binary number. When x and y are each 4 bits, LUT 510B (LUT3-D8) includes a value for component (2.4) of equation (2). When x and y are each 8 bits, LUT 510C (LUT3-D16) includes a value for component (2.4). When x and y are each 16 bits, LUT 510D (LUT3-D32) includes a value for component (2.4). LUTs 510A through 510D may be used to calculate div 3 for large values ​​of z by employing equation (2) with respect to the constituent sub-portions of z.

[0094] Figure 5B Method 520 is illustrated, where div3(z) can be calculated for 16-bit values ​​using LUTs 410 and 510A. Similar to method 420, method 520 begins at 522, where z is divided into four 4-bit vectors z1 (z[15:12]), z2 (z[11:8]), z3 (z[7:4]), and z4 (z[3:0]). At 524, mod 3 is calculated for z1 to z4 using LUT 410, and div 3 is calculated for z1 to z4 using LUT 510A; these values ​​are stored as m1 to m4 and d1 to d4, such that m1=mod3(z1), m2=mod3(z2), d1=div3(z1), d2=div3(z2), etc. In 526, m1 and m2 are combined using equation (1) to find m5, and m3 and m4 are combined to find m6 (as in 426 of method 420). Equation (2) uses d1, d2, m1, and m2 to calculate div 3(d5) for {z1, z2}, and uses d3, d4, m3, and m4 to calculate div 3(d6) for {z3, z4}. This process is repeated in 528, which includes performing a lookup in LUT 510C to calculate component (2.4) of equation (2) and summing it with d5*16 and d6. The result of the sum is div 3(z).

[0095] As with mod 3(z), div 3(z) can be used for any width 2 if the appropriate LUT is implemented. k+1 For example, when z is 32 bits, LUT 510D may be used to find div3(z). LUTs of various widths may be utilized in arithmetic circuit 126 of routing circuit 120 as needed.

[0096] Method 520 thus illustrates a div-n operation where n=3. Method 520 includes determining a div-n value for each of the equal sub-portions of the value (z1 to z4 from 522), thereby producing a current set of div-n results at 524. For example, the value here may be from Figure 1 The second value of 139 is obtained by combining the pairs of the current set of div-n results to obtain a new set of div-n results having a greater number of bits than the previous div-n results, which becomes the current set of div-n results. In some embodiments, when calculating a value with a bit width of 2, the current set of div-n results is obtained. 2^k+1 , a given pair of the current set of div-n results includes the first sub-portion of the address (x') and the immediately less significant sub-portion of the address (y'), and combining the given pair includes calculating the expression div n(x')·2 2^k +div n(y')+div n(mod n(x')·2 2^k +mod n(y')) to generate a corresponding one of the new set of div-n results. In addition, method 520 includes repeating the combination of the current set of div-n results at 528 until the new set of div-n results has a number of bits equal to the number of bits of the second value, which produces a div-n of the input value.

[0097] Figure 5C The use of method 520 is illustrated to calculate div 3 about a particular number, in this case z=55,618d, which can also be written as 1101 1001 0100 0010b. In 522, the 16-bit value is divided into four-bit portions, and in 524, the mod 3 values ​​m1 to m4 (1d, 0d, 1d, and 2d, respectively) are calculated using LUT 410 using equation 1. In addition, the div 3 values ​​d1 to d4 (4d, 3d, 1d, and 0d, respectively) are calculated using LUT 510. This process is repeated in 526 as LUT 410 is used to find the mod 3 for m1+m2 and m3+m4, resulting in m5=1 and m6=0, respectively. LUT 510B is used for m1, m2 to find component (2.4), while d1*16 is component (2.1) and d2 is component (2.2) of equation (2), which produces d5. Similarly, LUT 510B is used for m3 and m4 to find component (2.4), which is applied to equation (2) to produce d6. Finally, in 528, equation (2) is applied by adding d5*256, d6, and the result of the table lookup on LUT 510C for the sum of m5 and m6, which produces div 3(55,618d)=18,539d.

[0098] The method of method 520 can be used to calculate div 3 for any 16-bit binary number. In addition, method 520 can be extended to calculate div 3 for larger values. Such calculations can be performed using a circuit including a set of adders, LUT 410 and LUT 510, where the additional LUTs depend on the width of the input value.

[0099] Figure 5D An embodiment of a div-3 circuit 140-3 is illustrated that generates a 4-bit div-3 value from an input second value 139, outputting a routing selection 142 for dimension b.

[0100] The div-3 circuit 140-3 receives the second value 139 having a length of 16 bits and stores it as z in the register 530. The value z is divided into four 4-bit vectors 531A to 531D: z1 (which includes z[15:12]), z2 (which includes z[11:8]), z3 (which includes z[7:4]), and z4 (which includes z[3:0]). The circuit 140-3 also receives mod-3 values ​​for z1 (m1, indicated by reference numeral 535A), z2 (m2, indicated by reference numeral 535B), z3 (m3, indicated by reference numeral 535C), and z4 (m4, indicated by reference numeral 535D) from the mod-3 circuit 130-3. In addition, circuit 140 - 3 also receives mod-3 values ​​m5 (reference numeral 535E) and m6 (reference numeral 535F) from mod-3 circuit 130 - 3 , which are mod-3 values ​​for the most significant 8 bits and the least significant 8 bits in z, respectively.

[0101] The operation of circuit 140-3 is first described at a high level. Circuit 140-3 initially uses equation (2) to calculate div 3 for both halves of z, where the value z has component values ​​x and y. For the "left" half of z, z1 corresponds to x and z2 corresponds to y. Div 3 for these values ​​using equation (2) is d5, indicated by reference numeral 547A. Similarly, for the "right" half of z, z3 corresponds to x and z4 corresponds to y. Div 3 for these values ​​using equation (2) is d6, indicated by reference numeral 547B. This process is then repeated to calculate div 3 for the cascade of z=d5 / d6, where d5 is the component value x and d6 is the component value y. The output of equation (2) for these values ​​is routing 142, which can be used for dimension b.

[0102] The operation of each of these div 3 calculations can now be described in more detail. To calculate div 3 for the left half of the second value 139 (consisting of z1 and z2), equation (2) is used. In this equation, z1 is x and z2 is y. Element (2.1) of this equation is generated by LSL-4 542A. The left shift circuit 542A receives the output of LUT3-D4 510A-1, which is div 3(x), and shifts the input left by 4 bits to generate d1*16 or 533A. Element (2.2) of equation (2) is generated by LUT3-D4 510A-3, which is div 3(y), indicated by reference numeral 534A. In addition, element (2.4) of equation (2) is generated by LUT3-D8510B-1. As Figure 5A As shown, lookup table 510B-1 takes two inputs: mod 3(x) (also referred to as m1) and mod 3(y) (also referred to as m2), and then outputs div 3 of the sum of 1) m1 shifted left by 4 bits and 2) m2. This output is indicated by reference numeral 536A. Adder 547A then sums 533A, 534A, and 536A to generate d5 (reference numeral 548), which is div 3 for the left half of the second value 139.

[0103] To calculate div 3 for the right half of the second value 139 (consisting of z3 and z4), equation (2) is used again. In this equation, z3 is x and z4 is y. Element (2.1) of this equation is generated by LSL-4 542B. Left shift circuit 542B receives the output of LUT3-D4 510A-2, which is div 3(x), and shifts the input left by 4 bits to generate d3*16 or 533B. Element (2.2) of equation (2) is generated by LUT3-D4 510A-4, which is div 3(y), indicated by reference numeral 534B. In addition, element (2.4) of equation (2) is generated by LUT3-D8 510B-2. As Figure 5A As shown, the lookup table 510B-2 takes two inputs: mod 3(x) (also referred to as m3) and mod 3(y) (also referred to as m4), and then outputs div 3 of the sum of 1) m3 shifted left by 4 bits and 2) m4. This output is indicated by reference numeral 536B. Adder 547B then sums 533B, 534B, and 536B to generate d6 (reference numeral 554), which is div 3 for the left half of the second value 139.

[0104] Next, circuit 140-3 calculates div 3(z) by applying equation (2), where z[15:8] constitutes the component value x and z[7:0] constitutes the component value y. In summary, equation (2) is the sum of components (2.1), (2.2), and (2.4). The bit width of the calculated div 3 value is 16 bits; therefore, for this application of equation (2), k=3. Component (2.1) is div 3(x) multiplied by or 256. is a left shifted version of div 3(x). This is equivalent to shifting div 3(x) left by 8 bits. Circuit 140-3 has already calculated d5 as div 3(x). Therefore, component (2.1) is calculated by shifting d5 (reference numeral 548) left as value 552. Component (2.2) of equation (2) is div 3(y), which has already calculated d6 as div 3(y) (reference numeral 554). Finally, component (2.4) of equation (2) is calculated by LUT3-D16 (510C), which receives mod 3(x)(m5) and mod 3(y)(m6) as inputs. The output of lookup table 510C is indicated by reference numeral 556. Where its components are calculated, equation (2) may thus be calculated by summing values ​​552, 554 and 556 using adder 558 to produce div 3(z), which is the routing selection 142 that may be used for routing dimension b.

[0105] Mod 15 and div 15 specific implementation

[0106] Another possible non-power of two routing paradigm is based on mod 15 and div 15 calculations. Elements of the approach for mod 3 / div 3 can be reused here as shown below. These two examples illustrate how the design can be adapted to any desired number of routing options that is not a power of two.

[0107] The inventors have recognized that mod 15(z) and div 15(z) can be found using the following formulas, where z has a bit width of 2 k+1 , the most significant half of the bits of the calculated value of z are represented by x, and the least significant half of the bits of z are represented by y, such that

[0108] (3) mod 15(z) = mod 15(mod 15(x) + mod 15(y)); and

[0109] (4)

[0110]

[0111] It can be seen that equation (3) relies on the mod-15 values ​​of the components x and y, while equation (4) is slightly more complicated.

[0112] Equation (4) is the sum of four components:

[0113] (4.1)

[0114] (4.2)div 15(y);

[0115] (4.3)

[0116] (4.4) = mod15(x) + mod15(y);

[0117] (4.5) = div 15((4.4)); and

[0118] div 15(z)=(4.1)+(4.2)+(4.3)+(4.5).

[0119] Depending on the size of x and y being combined, the values ​​k and n will have different values. When x and y are 4 bits each, n = 4 and k = 2. When x and y are 8 bits each, n = 8 and k = 3.

[0120] As with the mod 3 / div 3 example, the LUT facilitates calculation of the mod 15 and div 15 values. Fig. 6A One embodiment of a LUT 610 (also referred to as LUT15-M) is shown that includes a mod 15 value for every possible 4-bit binary number. Thus, LUT 610 enables fast calculation of mod 15 for any 4-bit number.

[0121] As shown in equation (3), finding mod 15 for z requires finding mod 15 for the sum of mod 15(x) and mod 15(y). The sum can be wider than 4 bits. For example, if mod 15(x) = 7 and mod 15(y) = 14, then mod 15(x) + mod 15(y) = 21, which is 10101b.

[0122] Fig. 6A Function 611 in (also referred to as mod15-F) describes one possible way to evaluate mod 15(x)+mod 15(y). The function shows the calculation of two different four-bit values: (1) tmp_mod15, which is equal to mod 15(x)+mod 15(y), and (2) tmp_mod15_p1, which is equal to mod 15(x)+mod 15(y)+1, or formula (1) plus one. In addition, cout is the carry value of the most significant bit of tmp_mod15_p1, which indicates that the sum is greater than 15. If cout=0, tmp_mod15 is selected as mod 15(z); on the other hand, if cout=1, tmp_mod15_p1 is selected as mod 15(z). The operation of this function can be seen by considering a few examples. If x=7 and y=7, then tmp_mod15=14, tmp_mod15_p1=15, and cout=0. Since cout = 0, tmp_mod15(14) is selected as mod 15(z). If x = 7 and y = 8, then tmp_mod15 = 15, tmp_mod15_p1 = 0 (this is a four-bit output, a five-bit output would be 10000b), and cout = 1. Since cout = 1, tmp_mod15_p1(0) is selected as mod 15(z). Finally, if x = 7 and y = 9, then tmp_mod15 = 16, tmp_mod15_p1 = 1 (this is a four-bit output, a five-bit output would be 10001b), and cout = 1. Since cout = 1, tmp_mod15_p1(1) is selected as mod 15(z).

[0123] One possible hardware implementation of function 611 for calculating mod 15 (z) is circuit 612. As shown, mod 15 (x) (reference numeral 613A) and mod 15 (y) (reference numeral 613B) are supplied to adder 614, which generates two 4-bit outputs: sum 616A (equivalent to tmp_mod15 in function 611) and sum_p1 616B (equivalent to tmp_mod15_p1 in function 611). Adder 614 also generates cout 616C (carry value) for the calculation of sum_p1 616B. sum 616A and sum_p1 616B are supplied to multiplexer 617, which receives cout 616C as a selection signal. If cout 616C=0, then select sum 616A as output 618 to represent mod 15 (z). On the other hand, if cout 616C = 1, then sum_p1 616B is selected as output 618 to represent mod 15(z). This implementation avoids the use of a larger LUT.

[0124] In other possible hardware implementations, adder 614 is a compound adder that further optimizes circuit 612. Such a compound adder can calculate both tmp_mod_15 and tmp_mod_15_p1 using a single compound add operation, as opposed to two separate "classical" addition operations (as shown in function 611). Using a compound adder can reduce the total number of operations required to implement function 611.

[0125] Figure 6B Method 620 is illustrated, where mod 15(z) is calculated for a 16-bit value using LUT 610A and function 611 (which may be implemented by circuit 612). At 622, z is divided into four 4-bit vectors z1 (z[15:12]), z2 (z[11:8]), z3 (z[7:4]), and z4 (z[3:0]). At 624, mod 15 is calculated for z1 to z4 using LUT 610; these values ​​are stored as m1 to m4, such that m1=mod 15(z1), m2=mod 15(z2), etc. At 626, function 611 is used to implement equation (3), which combines m1 and m2 to calculate mod 15 for {z1, z2}, and combines m3 and m4 to calculate mod 15 for {z3, z4}. The value m5 is calculated by performing function 611 on m1 and m2, and m6 is calculated by performing function 611 on m3 and m4. This process is repeated in 628, which includes performing function 611 on m5 and m6, which produces mod 15(z). This method can be used for any width 2 k+1 z implementation.

[0126] Figure 6C The use of method 620 to calculate mod 15 for a particular number is illustrated, in this case, z=55,618d, which can also be written as 1101 1001 0100 0010b. This value of z can be divided by fifteen 3,707 times, leaving a remainder of 13. The same result can also be calculated by method 620 using mod 15 operations on the components of z. In 622, the 16-bit value is divided into four-bit parts, and in 624, LUT 610A is used to calculate mod-15 values ​​m1 to m4 (13, 9, 4, and 2, respectively). This process is repeated in 626, as m1 and m2 are used in function 611 to calculate mod 15 for the sum, resulting in m5=7. Similarly, m3 and m4 are added, and then function 611 is used to calculate mod 15 for the sum, resulting in m6=6. Finally, at 628, m5 and m6 are used in function 611 to calculate mod 15 for the sum, yielding mod 15(z=55,618)=13.

[0127] The method 620 (which is an embodiment of the method 420) can be used to calculate mod 15 for any 16-bit binary number. In addition, the method 620 can be extended to calculate mod 15 for larger values. Such calculations can be performed using a circuit including a set of adders, LUT 610, and implementing function 611 (e.g., using circuit 612). Fig.6D One possible implementation of mod-15 circuit 130-15 is shown. First value 129 is received as input value z. Lookup tables 610A to 610D (which are Fig. 6A ) then computes mod 15 for the four four-bit components of z, labeled outputs m1 to m4. m1 and m2 are supplied to Fig. 6A 612A) to produce output m5, while m3 and m4 are supplied to a second instance (612B) of circuit 612 to produce output m6. The process is then repeated as m5 and m6 are supplied to a third instance (612C) of circuit 612. The output of 612C is a 16-bit value mod 15(z) that can be used as a routing selection for dimension a.

[0128] LUT 610 (mod 15(x)) can be combined with function 611, Fig. 7A The other LUTs, left shifters and adders shown in are used to calculate div 15(z) according to equation (4). The various components of equation (4) may be calculated as follows: component (4.1), which multiplies a value by a power of two, may be implemented by a left shifter operating on the output of LUT 710A (LUT15-D4) receiving a portion of z (in a subsequent state, component (4.1) is calculated based on a left shift of d5); component (4.2), which includes div15 values ​​for any given value of mod 15(y), may be estimated using LUT 710A (also referred to as LUT15-D4); component (4.3) may be estimated using LUTs 710B to 710D, depending on the size of the values ​​being combined; component (4.4) may be estimated by an adder; and component (4.5), which includes div15 values ​​for values ​​between 0 and 28 (the maximum possible sum of mod 15(x) + mod 15(y)), may also be estimated using LUT 710A. More specifically, LUT 710B (LUT15-D8) is used to estimate the component (4.3) when combining two 4-bit numbers. (Note, however, that the output of LUT 710B is the same as the input because div15(16) is equal to 1. Therefore, Fig.7D The 710B is not used in the circuit shown. However, it is included Fig. 7A In the figure, Figure 7C and Fig.7D ) LUT 710C (LUT15-D16) and 710D (LUT15-D32) are used to estimate component (4.3) when combining two 8-bit or two 16-bit numbers, respectively. Lookup table 710D is not used in the example of FIG. 7-D because the output is 16 bits, which means that only four-bit values ​​and eight-bit values ​​are combined.

[0129] Figure 7B Method 720 is illustrated, where LUTs 610 and 710A can be used with function 611 and other hardware to calculate div15(z) for a 16-bit value. Similar to method 620, method 720 begins at 722, where z is divided into four 4-bit vectors z1 (z[15:12]), z2 (z[11:8]), z3 (z[7:4]), and z4 (z[3:0]). At 724, mod 15 is calculated for z1 to z4 using LUT 610, and div 15 is calculated for z1 to z4 using LUT 710A; these values ​​are stored as m1 to m4 and d1 to d4, such that m1=mod3(z1), m2=mod3(z2), d1=div3(z1), d2=div3(z2), etc. At 726, m1 and m2 are combined using function 611 to find m5, and m3 and m4 are combined to find m6. Equation (4) uses d1, d2, m1, and m2 to calculate div 15(d5) for {z1, z2}, and uses d3, d4, m3, and m4 to calculate div 15(d6) for {z3, z4}. This process is repeated at 728, which includes summing the following quantities: the lookup item in LUT 710C used to calculate component (4.3), the lookup item in LUT 710A used to calculate components (4.2) and (4.5), and the left shift operation on d5 used to calculate component (4.1). The result is div 15(z).

[0130] Figure 7C The use of method 720 is illustrated to calculate div 15 about a particular number, in this case z=55,618d, which can also be written as 1101 1001 0100 0010b. In 722, the 16-bit value is divided into four-bit parts, and in 724, the mod 15 values ​​m1 to m4 (13d, 9d, 4d, and 2d, respectively) are calculated using LUT 710A. In addition, the div 15 values ​​d1 to d4 (which are all zero) are calculated using LUT 710A. In 726, the mod 15 for m1+m2 and m3+m4 is found using function 611, resulting in m5=7 and m6=6, respectively. To calculate d5, components (4.1), (4.2), (4.3), and (4.5) are summed, where (4.5) is div 15 ((4.4) or mod 15(x)+mod 15(y)). Component (4.1) is calculated by left shifting d1 (which in this case is 0, so (4.1) is also 0). Component (4.2) is the already calculated d2, which is also 0. For x=m1=13, component (4.3) is calculated by accessing LUT 710B. Component (4.4) is equal to mod 15(x)+mod 15(y)=m1+m2=13+9=22. Component (4.5) is obtained by looking up the value for x=22 in LUT 710A, which is 1. The value d5 is therefore equal to 0+0+13+1, or equal to 14. The value d6 is evaluated in a similar manner to obtain 4.

[0131] A similar process is performed in 728. To calculate div 15(z), components (4.1), (4.2), (4.3), and (4.5) are again summed. Component (4.1) is calculated by shifting d5 left, which is equivalent to 14*256(2 8 ) or 3,584. Component (4.2) is the already calculated d6, which is 4. For x=m5=7, component (4.3) is calculated by accessing LUT 710C, which yields 119. Component (4.4) is equal to mod 15(x)+mod15(y)=m5+m6=7+6=13. Component (4.5) is obtained by looking up the value for x=13 in LUT 710A, which is 0. The value div 15(z) is therefore equal to 3,584+4+119+0, or equal to 3,707.

[0132] As with mod 15(z), div 15(z) can be used for any width 2 if the appropriate LUT is implemented. k+1 For example, when z is 32 bits, LUT 710D may be used to find div15(z). Therefore, LUTs of various widths may be utilized in arithmetic circuit 126 of routing circuit 120 as needed.

[0133] Fig.7D is a block diagram of one embodiment of a div 15 circuit 140-15. As shown, the circuit 140-15 receives a value z and utilizes Fig. 7A 15(z). Circuit 140-15 also receives values ​​m1, m2, m3, and m4 (the mod 15 values ​​for the four four-bit components of z) from circuit 130-15, as well as m5 and m6 (also calculated by circuit 130-15), which are mod 15 values ​​for the two halves of z.

[0134] It can be seen that Fig.7D The operation of the circuit depicted in includes the three calculations of equation (4). The equation is calculated on the "left" half of z to produce d5, which is the output of adder 760A, whose four inputs are the four components of equation (4). Equation (4) is calculated again on the "right" half of z to produce d6, which is the output of adder 760B, which also has four inputs similar to the inputs to adder 760A. (Note that m1 is one of the inputs to adder 760A. This addend is equivalent to component (4.3), but since div 15(16)=1, div 15(16)*m1 is simply equal to m1. The same observation applies to m3 and adder 760B.) Once d5 and d6 are calculated, d5 and d6 are again used to evaluate equation (4) along with inputs m5 and m6 from circuit 130-15. The output of adder 760C is div 15(z), or routing 142 for dimension b.

[0135] Example Method

[0136] Figure 8 is a flow chart of one embodiment of a method 800 for performing routing for a computer system. In various embodiments, the method 800 is performed on routing circuitry of a computer system.

[0137] Method 800 begins at step 810, where routing circuitry (e.g., routing circuitry 120) of a computer system (e.g., computer system 100) that includes a collection of resources (e.g., collection of resources 110) organized according to a topology having multiple dimensions receives a request for a particular resource within the collection of resources. The request includes an address (e.g., request address 104) having a first set of bits and a second non-overlapping set of bits. The topology has a first dimension (e.g., dimension a) with n routing options and a second dimension (e.g., dimension b) with m routing options, where n and m are both integers greater than two, and where n is not a power of two.

[0138] In some embodiments, the first set of bits and the second set of bits are separated by an intermediate set of bits within the address, wherein the first value is formed by masking the address with a first mask value that includes the first set of bits and the second set of bits separated by a first intermediate set of bits. The second value is formed by masking the address with a different second mask value that includes the first set of bits and the second set of bits separated by a second intermediate set of bits.

[0139] The method 800 continues at step 820, where the routing circuit determines a first routing selection (e.g., routing selection (a)) for the first dimension by performing a modulo-n operation (e.g., mod-n 130) on a first value formed from the address (e.g., first value 130), the first value including a first set of bits and a second set of bits. In some embodiments, the modulo-n operation includes determining a modulo-n value for each of equal sub-portions of the first value, thereby producing a current set of modulo-n results. After the determination, pairs of the current set of modulo-n results are combined to obtain a new set of modulo-n results having a greater number of bits than previous modulo-n results, where the new set of modulo-n results becomes the current set of modulo-n results. The circuit then repeats the combining of the current set of modulo-n results until the new set of modulo-n results has a single modulo-n result that is a final result of the modulo-n operation on the first value. In some embodiments, a given pair of the current set of modulo-n results includes a first subportion of the address (x) and an immediately less significant subportion of the address (y), and a corresponding one of the new set of modulo-n results for the given pair is equal to mod n (mod n(x)+mod n(y).

[0140] Next, in step 830, the routing circuit determines a second routing selection (e.g., routing selection (b) 142) for the second dimension by performing a div-n operation (e.g., div-n 140) on a second value formed by the address (e.g., second value 139), the second value including the first set of bits and the second set of bits.

[0141] In some embodiments, the div-n operation includes determining a div-n value for each of the equal sub-portions of the second value, thereby producing a current set of div-n results. The div-n operation also includes combining pairs of the current set of div-n results to obtain a new set of div-n results having a greater number of bits than the previous div-n results, the new set of div-n results becoming the current set of div-n results. In addition, the div-n operation includes repeating the combination of the current set of div-n results until the new set of div-n results has a number of bits equal to the number of bits of the second value. In some specific implementations, a given pair of the current set of div-n results includes a first sub-portion (x') of the address and an immediately less significant sub-portion (y') of the address. A corresponding one of the new set of div-n results for a given pair is equal to div n(x')·2 2^k +div n(y')+div n(mod n(x')·2 2^k +mod n(y')), where the second value has a bit width of 2 2^k+1 .

[0142] In step 840, the routing circuit activates one or more selection signals (eg, selection signals 150 for dimensions a and b) according to the first routing selection and the second routing selection. The one or more selection signals may be used to cause a particular resource to be selected in response to the request.

[0143] In some embodiments, method 800 may also include checking the set of constraints to prevent aliasing.In some cases, checking the second set of constraints for the first dimension and the second dimension may include ensuring that the first set of intermediate bits and the second set of intermediate bits each include an even number of zeros and an even number of ones.

[0144] Example Device

[0145] Reference now Fig. 9 , a block diagram of an example implementation of an exemplary device 900 is shown. In some embodiments, elements of the device 900 may be included in a system on a chip. In some embodiments, the device 900 may be included in a mobile computing device that may be battery powered. Therefore, the power consumption of the device 900 may be an important design consideration. In the illustrated embodiment, the device 900 includes a structure 910, a computing complex 920, an input / output (I / O) bridge 950, a cache / memory controller 945, a graphics unit 975, and a display unit 965. In some embodiments, in addition to or in place of the illustrated components, the device 900 may include other components (not shown), such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0146] The structure 910 may include various interconnects, buses, MUXs, controllers, etc., and may be configured to facilitate communication between various elements of the device 900. In some embodiments, portions of the structure 910 may be configured to implement a variety of different communication protocols. In other embodiments, the structure 910 may implement a single communication protocol, and elements coupled to the structure 910 may be internally converted from the single communication protocol to other communication protocols.

[0147] In the illustrated embodiment, the computing complex 920 includes a bus interface unit (BIU) 925, a cache 930, and cores 935 and 940. In various embodiments, the computing complex 920 may include various numbers of processors, processor cores, and caches. For example, the computing complex 920 may include 1, 2, or 4 processor cores, or any other suitable number of processor cores. In one embodiment, the cache 930 is a group-associative L2 cache. In some embodiments, the cores 935 and 940 may include internal instruction and data caches. In some embodiments, a consistency unit (not shown) in the structure 910, the cache 930, or elsewhere in the device 900 may be configured to maintain consistency between the various caches of the device 900. The BIU 925 may be configured to manage communications between the computing complex 920 and other elements of the device 900. Processor cores (such as cores 935 and 940) may be configured to execute instructions of a specific instruction set architecture (ISA) that may include operating system instructions and user application instructions.

[0148] The cache / memory controller 945 may be configured to manage data transfers between the structure 910 and one or more caches and memories. For example, the cache / memory controller 945 may be coupled to an L3 cache, which in turn may be coupled to system memory. In other embodiments, the cache / memory controller 945 may be directly coupled to the memory. In some embodiments, the cache / memory controller 945 may include one or more internal caches.

[0149] As used herein, the term "coupled to" may indicate one or more connections between elements, and a coupling may include intermediate elements. Fig. 9 In FIG. 1 , graphics unit 975 may be described as being "coupled to" memory via structure 910 and cache / memory controller 945. In contrast, in Fig. 9 In the illustrated embodiment, graphics unit 975 is "directly coupled" to structure 910 because there are no intervening elements.

[0150] Graphics unit 975 may include one or more processors, such as one or more graphics processing units (GPUs). For example, graphics unit 975 may receive graphics-oriented instructions, such as Metal or Instructions. Graphics unit 975 may execute dedicated GPU instructions or perform other operations based on the received graphics-oriented instructions. Graphics unit 975 may generally be configured to process large blocks of data in parallel and may construct images in a frame buffer for output to a display, which may be included in the device or may be a separate device. Graphics unit 975 may include transformation, lighting, triangle, and rendering engines in one or more graphics processing pipelines. Graphics unit 975 may output pixel information for display images. In various embodiments, graphics unit 975 may include programmable shader circuits, which may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks, and computational tasks (which may be graphics-related or may not be graphics-related).

[0151] The display unit 965 may be configured to read data from the frame buffer and provide a stream of pixel values ​​for display. In some embodiments, the display unit 965 may be configured as a display pipeline. In addition, the display unit 965 may be configured to blend multiple frames to produce an output frame. In addition, the display unit 965 may include one or more interfaces (e.g., a touch screen or an external display) for coupling to a user display (e.g., or embedded DisplayPort (eDP).

[0152] The I / O bridge 950 may include various elements configured to implement, for example, universal serial bus (USB) communications, security, audio, and low-power always-on functionality. The I / O bridge 950 may also include, for example, interfaces such as pulse width modulation (PWM), general purpose input / output (GPIO), serial peripheral interface (SPI), and inter-integrated circuit (I2C). Various types of peripherals and devices may be coupled to the device 900 via the I / O bridge 950.

[0153] In some embodiments, the device 900 includes a network interface circuit (not explicitly shown), which can be connected to the structure 910 or the I / O bridge 950. The network interface circuit can be configured to communicate via various networks, which can be wired networks, wireless networks, or both. For example, the network interface circuit can be configured to communicate via a wired local area network, a wireless local area network (e.g., via WiFi) or a wide area network (e.g., the Internet or a virtual private network). In some embodiments, the network interface circuit is configured to communicate via one or more cellular networks using one or more radio access technologies. In some embodiments, the network interface circuit is configured to communicate using device-to-device communication (e.g., Bluetooth or WiFi Direct) and the like. In various embodiments, the network interface circuit can provide a connection with various types of other devices and networks for the device 900.

[0154] Sample Application

[0155] Now turn to Fig.10 , various types of systems that may include any of the circuits, devices, or systems discussed above are shown. The system or device 1000, which may incorporate or otherwise utilize one or more of the techniques described herein, may be used in a wide variety of fields. For example, the system or device 1000 may be used as part of the hardware of a system such as a desktop computer 1010, a laptop computer 1020, a tablet computer 1030, a cellular or mobile phone 1040, or a television 1050 (or a set-top box coupled to a television).

[0156] Similarly, the disclosed elements can be used in a wearable device 1060, such as a smart watch or a health monitoring device. In many embodiments, a smart watch can implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. A wearable device can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also contemplated, including devices worn around the neck, devices implantable in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0157] The system or device 1000 may also be used in various other environments. For example, the system or device 1000 may be used in the environment of a server computer system (such as a dedicated server) or on shared hardware that implements a cloud-based service 1070. Further, the system or device 1000 may be implemented in a wide range of dedicated everyday devices, including common devices 1080 in the home, such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the "Internet of Things" (IoT). Elements may also be implemented in various modes of transportation. For example, the system or device 1000 may be used for control systems, guidance systems, entertainment systems, etc. of various types of vehicles 1090.

[0158] Fig.10 The applications illustrated in the examples are merely exemplary and are not intended to limit the potential future applications of the disclosed system or device. Other example applications include, but are not limited to: portable game devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0159] Example Computer Readable Medium

[0160] The disclosure has described various example circuits in detail above. It is intended that the disclosure encompass not only embodiments including such circuits, but also computer-readable storage media including design information specifying such circuits. Thus, the disclosure is intended to support claims that encompass not only devices including the disclosed circuits, but also storage media that specify the circuits in a format recognized by a manufacturing system configured to produce hardware (e.g., an integrated circuit) that includes the disclosed circuits. Claims to such storage media are intended to cover, for example, entities that generate a circuit design but do not manufacture the design itself.

[0161] Fig.11 1 is a block diagram illustrating an example non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, semiconductor manufacturing system 1120 is configured to process design information 1115 stored on non-transitory computer-readable medium 1110 and manufacture integrated circuit 1130 based on design information 1115.

[0162] The non-transitory computer-readable storage medium 1110 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1110 may be an installation medium, such as a CD-ROM, a floppy disk, or a tape device; a computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory, such as flash memory, a magnetic medium, for example, a hard drive or an optical storage device; a register, or other similar type of memory element, etc. The non-transitory computer-readable storage medium 1110 may include other types of non-transitory memory or a combination thereof. The non-transitory computer-readable storage medium 1110 may include two or more memory media that may reside in different locations, such as different computer systems connected by a network.

[0163] The design information 1115 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 1115 may be used by the semiconductor manufacturing system 1120 to manufacture at least a portion of the integrated circuit 1130. The format of the design information 1115 may be recognizable by at least one semiconductor manufacturing system 1120. In some embodiments, the design information 1115 may also include one or more cell libraries that specify the synthesis, layout, or both of the integrated circuit 1130. In some embodiments, the design information is specified in whole or in part in the form of a netlist that specifies the cell library elements and their connectivity. The design information 1115 obtained separately may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, the design information 1115 may specify the circuit elements to be manufactured, but not their physical layout. In this case, the design information 1115 may need to be combined with the layout information to actually manufacture the specified circuit.

[0164] In various embodiments, integrated circuit 1130 may include one or more custom macrocells, such as memory and analog or mixed signal circuits, etc. In this case, design information 1115 may include information related to the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to a graphic data system (GDSII) or any other suitable format.

[0165] Semiconductor manufacturing system 1120 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 1120 may also be configured to perform various tests of the manufactured circuits for proper operation.

[0166] In various embodiments, integrated circuit 1130 is configured to operate according to the circuit design specified by design information 1115, which may include performing any of the functionality described herein. In addition, integrated circuit 1130 may be configured to perform various functions described herein in conjunction with other components. In addition, the functionality described herein may be performed by multiple connected integrated circuits.

[0167] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0168] ***

[0169] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," and "a particular embodiment," etc. do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the present disclosure.

[0170] The present disclosure may discuss potential advantages that may be generated by the disclosed embodiments. Not all of these implementations will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of the present disclosure. In fact, there are many reasons why an implementation that falls within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuits outside the scope of the present disclosure that, in combination with one of the disclosed embodiments, negate or reduce one or more of the disclosed advantages. In addition, suboptimal design execution of a particular implementation (e.g., a specific implementation technique or tool) may also negate or reduce the disclosed advantages. Even assuming a specific implementation of the technology, the realization of the advantages may still depend on other factors, such as the environmental conditions in which the specific implementation is deployed. For example, the input provided to a particular implementation may prevent one or more problems solved in the present disclosure from occurring in a particular occasion, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors external to the present disclosure, it is hereby clarified that any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Instead, the identification of such potential advantages is intended to illustrate the types of improvements available to designers who benefit from the present disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantage typically depends on technical realities of additional factors.

[0171] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on the present disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any contrary statement in the present disclosure. Therefore, the present application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications and equivalents, which will be apparent to those skilled in the art who are aware of the beneficial effects of the present disclosure.

[0172] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be made during the prosecution of this application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined, where appropriate, with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may be combined, where appropriate.

[0173] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent upon a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated and may be claimed in this or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0174] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0175] ***

[0176] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0177] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim does not exclude additional instances of that item without the accompanying context. A "plurality" of an item refers to a collection of two or more of the items.

[0178] The word “may” is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0179] The terms "include" and "including" and forms thereof are open ended and mean "including, but not limited to,".

[0180] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either, but not both, x or y" make it clear that "or" is used in an exclusive sense.

[0181] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in the list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0182] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "first circuit", "second circuit", "particular circuit", "given circuit", etc.) refer to different instances of the feature. In addition, unless otherwise stated, the labels "first", "second", and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0183] The phrase "based on" or is used to describe one or more factors that influence a determination. The term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." The phrase specifies that B is a factor used to determine A or that B influences the determination of A. The phrase does not exclude that the determination of A may also be based on some other factor such as C. The phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0184] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with the specified factors or independently of the specified factors. That is, the effect may be responsive to these factors alone, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "A is performed in response to B." The phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. The phrase does not exclude that the execution of A may also be responsive to some other factor, such as C. The phrase also does not exclude that the execution of A may be performed jointly in response to B and C. The phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0185] ***

[0186] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. The expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be considered to be "configured to" perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as "configured to" perform a task refers to a physical thing for implementing the task, such as a device, a circuit, a system with a processor unit, and a memory storing executable program instructions, etc. The phrase is not used herein to refer to an intangible thing.

[0187] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0188] The term "configured to" is not intended to mean "capable of being configured to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function. After appropriate programming, the FPGA may then be considered "configured to" perform the particular function.

[0189] For purposes of a U.S. patent application based on the present disclosure, stating in a claim that a structure is "configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the "means for [performing the function]" construct to phrase the claim element.

[0190] Different "circuits" may be described in the present disclosure. These circuits or "circuits" constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or taken from a standard library. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., decode units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuits.

[0191] Thus, the disclosed circuits / units / components and other elements illustrated in the drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode for an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For one skilled in the computer arts, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0192] In various embodiments, as described in the preceding paragraphs, circuits, units, and other elements may be defined by the functions or operations they are configured to implement. The arrangement relative to each other and such circuits / units / components and the way they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall into the broader structure described by the microarchitecture definition. That is, a technician with a microarchitecture definition provided in accordance with the present disclosure can implement the structure by coding a description of a circuit / unit / component in a hardware description language (HDL) such as Verilog or VHDL without excessive experimentation and using the application of ordinary technicians. HDL descriptions are often expressed in a way that can be displayed as functional. However, for those skilled in the art, the HDL description is a way to convert the structure of a circuit, unit, or component into the next level of specific implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized for a library of cells designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit design along with the synthesized circuits. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented in an FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to a situation where a circuit or logic designer never specifies a particular set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0193] The fact that many different low-level combinations of circuit elements can be used to achieve the same specification of a circuit results in a large number of identical structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries provided for a particular project, etc. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0194] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

Claims

1. A device, comprising: An integrated circuit, the integrated circuit comprising: a set of storage locations arranged according to a hierarchical structure having a plurality of levels, the plurality of levels including a first level having n hash options and a second level having m hash options, where n is an integer that is not a power of two; A hash circuit, the hash circuit being configured to: receiving a request to access a particular storage location in the set of storage locations, the request comprising an address having a first set of bits and a second non-overlapping set of bits; determining a first hash value for the first level by performing a modulo-n operation on a first value formed from the address; determining a second hash value for the second level by performing a div-n operation on a second value formed from the address; and A plurality of selection signals are generated based on the first hash value and the second hash value that can be used to cause the particular storage location to be selected.

2. The apparatus of claim 1, wherein the particular storage location is a memory location, and wherein the storage location set is within a memory system of a computer system.

3. The apparatus of claim 1 , wherein the hash circuit is configured to: forming the first value by masking the address with a first mask value, the first mask value comprising the first set of bits and the second set of bits separated by a first intermediate set of bits; and The second value is formed by masking the address with a second mask value comprising the first set of bits and the second set of bits separated by a second intermediate set of bits. 4 . The apparatus of claim 3 , wherein the first intermediate set of bits and the second intermediate set of bits have different numbers of bit sets.

5. The apparatus of claim 3 , wherein the hash circuit comprises a rule checking circuit configured to check a set of addressing constraints to prevent aliasing, wherein the hash circuit is configured to check, for the first level and the second level, whether the first set of intermediate bits and the second set of intermediate bits each include an even number of zeros and an even number of ones.

6. The apparatus of claim 1 , wherein the hash circuit comprises an arithmetic circuit, the arithmetic circuit further comprising a modulo-n circuit, the modulo-n circuit configured to perform a modulo-n operation by: determining a modulo-n value for each of equal sub-portions of the first value, thereby producing a current set of modulo-n results; combining pairs of the current set of modulo-n results to obtain a new set of modulo-n results having a greater number of bits than a previous modulo-n result, wherein the new set of modulo-n results becomes the current set of modulo-n results; and The combining of the current set of modulo-n results is repeated until the new set of modulo-n results has a single modulo-n result, the single modulo-n result being a final result of the modulo-n operation on the first value.

7. An apparatus according to claim 6, wherein a given pair of the current set of modulo-n results includes a first sub-portion (x) of the address and an immediately less significant sub-portion (y) of the address, and wherein the modulo-n circuit is configured to generate a corresponding one of the new set of modulo-n results formed by combining the given pair by computing an expression mod n (modn(x)+modn(y)).

8. The apparatus of claim 6, wherein the arithmetic circuit further comprises a div-n circuit, the div-n circuit being configured to perform a div-n operation by: determining a div-n value for each of equal subparts of the second value, thereby producing a current set of div-n results; combining pairs of the current set of div-n results to obtain a new set of div-n results having a greater number of bits than previous div-n results, the new set of div-n results becoming the current set of div-n results; and The combining of the current set of div-n results is repeated until the number of bits of the new set of div-n results equals the number of bits of the second value.

9. The apparatus of claim 8, wherein a given pair of the current set of div-n results comprises a first sub-portion (x') of the address and an immediately less significant sub-portion (y') of the address, and wherein the div-n circuit is configured to generate the result by computing the expression divn(x')·2 2^k +div n(y')+div n(mod n(x')·2 2^k +mod n(y′)) to generate a corresponding one of the new set of div-n results formed by combining the given pair, wherein the second value has a bit width of 2 2^k+1 .

10. The apparatus of claim 1 , wherein the plurality of levels comprises one or more other levels having respective options, each of the respective options being an integer that is a power of two, and wherein the hash circuit is configured to perform respective routing for the one or more other levels using one or more XOR operations on respective values ​​formed from the addresses via masking.

11. A method comprising: receiving, at routing circuitry of a computer system including a collection of resources organized according to a topology having a plurality of dimensions, a request for a particular resource within the collection of resources, the request including an address having a first set of bits and a second non-overlapping set of bits, the topology having a first dimension with n routing options and a second dimension with m routing options, wherein n and m are both integers greater than two, and wherein n is not a power of two; determining, by the routing circuitry, a first routing selection for the first dimension by performing a modulo-n operation on a first value formed from the address, the first value comprising the first set of bits and the second set of bits; determining, by the routing circuitry, a second routing selection for the second dimension by performing a div-n operation on a second value formed from the address, the second value comprising the first set of bits and the second set of bits; as well as One or more selection signals are activated by the routing circuitry based on the first routing selection and the second routing selection, the one or more selection signals being operable to cause the particular resource to be selected in response to the request.

12. The method of claim 11, wherein performing the modulo-n operation comprises: determining a modulo-n value for each of equal sub-portions of the first value, thereby producing a current set of modulo-n results; combining pairs of the current set of modulo-n results to obtain a new set of modulo-n results having a greater number of bits than a previous modulo-n result, wherein the new set of modulo-n results becomes the current set of modulo-n results; and repeating said combining of said current set of modulo-n results until said new set of modulo-n results has a single modulo-n result, said single modulo-n result being a final result of said modulo-n operation on said first value; and The execution of the div-n operation includes: determining a div-n value for each of equal subparts of the second value, thereby producing a current set of div-n results; combining pairs of the current set of div-n results to obtain a new set of div-n results having a greater number of bits than previous div-n results, the new set of div-n results becoming the current set of div-n results; and The combining of the current set of div-n results is repeated until the number of bits of the new set of div-n results equals the number of bits of the second value.

13. A method according to claim 12, wherein a given pair of the current set of modulo-n results includes a first sub-portion (x) of the address and an immediately less significant sub-portion (y) of the address, and wherein a corresponding one of the new set of modulo-n results for the given pair is equal to mod n (mod n(x)+mod n(y)).

14. The method of claim 12, wherein a given pair of the current set of div-n results comprises a first sub-portion (x') of the address and an immediately less significant sub-portion (y') of the address, and wherein a corresponding one of the new set of div-n results for the given pair is equal to div n(x')·2 2^k +div n(y')+div n(mod n(x')·2 2^k +modn(y')), where the second value has a bit width of 2 2^k+1 .

15. The method of claim 11, wherein the first set of bits and the second set of bits are separated by an intermediate set of bits within the address, wherein the first value is formed by masking the address with a first mask value, the first mask value comprising the first set of bits and the second set of bits separated by a first intermediate set of bits, and wherein the second value is formed by masking the address with a different second mask value, the second mask value comprising the first set of bits and the second set of bits separated by a second intermediate set of bits, the method further comprising checking a set of constraints to prevent aliasing.

16. The method of claim 15, wherein checking the set of constraints for the first dimension and the second dimension comprises ensuring that the first set of intermediate bits and the second set of intermediate bits each include an even number of zeros and an even number of ones.

17. A device, comprising: An integrated circuit, the integrated circuit comprising: A memory system arranged according to a hierarchical structure having a plurality of dimensions, the plurality of dimensions including a first dimension having n hash options and a second dimension having m hash options, wherein n and m are integers greater than two, and wherein n is not a power of two; A hash circuit, the hash circuit being configured to: receiving a request to access a particular memory location of the memory system, the request comprising a memory address having a first set of bits and a second set of bits separated by an intermediate set of bits, the first set of bits and the second set of bits together encoding the first dimension and the second dimension; determining a first hash value for the first dimension by performing a modulo-n operation on a first value formed from the memory address using a first mask value, the first mask value comprising the first set of bits, the second set of bits, and a first intermediate set of bits; determining a second hash value for the second dimension by performing a div-n operation on a second value formed from the memory address using a second mask value, the second mask value comprising the first set of bits, the second set of bits, and a second intermediate set of bits; and A plurality of selection signals are generated based on the first hash value and the second hash value that can be used to cause the particular memory location to be selected.

18. The apparatus of claim 17, wherein the plurality of dimensions comprises: a memory controller dimension specifying a memory controller among a plurality of memory controllers in the memory system; a memory plane dimension specifying a memory plane of a plurality of memory planes for a specified memory controller; a memory bank dimension, the memory bank dimension specifying a memory bank among a plurality of memory banks for a specified memory controller and a memory plane; a row dimension specifying one of a plurality of rows for a specified memory bank, memory plane, and memory controller; as well as A column dimension specifies one of a plurality of columns for a specified memory bank, memory plane, and memory controller.

19. The apparatus of claim 17, wherein the first intermediate set of bits and the second intermediate set of bits have different numbers of sets of bits.

20. The apparatus of claim 19, wherein the hash circuit comprises a rule checking circuit configured to enforce a set of addressing constraints, wherein: The set of addressing constraints specifies, for the first dimension and the second dimension, that the first set of middle bits and the second set of middle bits include an even number of zeros and an even number of ones.

Images