System and method for overcurrent detection for inverter for electric vehicle

Abstract

A system includes an inverter configured to convert DC power from a battery to AC power to drive a motor, where the inverter includes: a power switch including a drain terminal, a source terminal, and a gate terminal; and a controller configured to detect a change in current at the source terminal of the power switching member using a complex impedance of a metal trace connected to the source terminal of the power switching member, and to control a gate control signal to the gate terminal based on the detected change in current.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 377,486 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 377,501 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 377,512 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 378,601 filed on October 6, 2022, and U.S. Non-Provisional Patent Application No. 18 / 063,304 filed on December 8, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure relate generally to systems and methods for overcurrent detection for an inverter for an electric vehicle, and more particularly to systems and methods for monitoring overcurrent for power device switches of an inverter for an electric vehicle. Background Art

[0004] Inverters, such as those used to drive motors in electric vehicles, are responsible for converting high voltage direct current (HVDC) to alternating current (AC) to drive the motor, for example. In an inverter, overcurrent in power device switching elements can impair proper operation of the inverter.

[0005] The present disclosure is directed to overcoming one or more of these aforementioned challenges. Summary of the invention

[0006] In some aspects, the technology described herein relates to a system comprising: an inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter comprises: a power switch comprising a drain terminal, a source terminal, and a gate terminal; and a controller configured to detect a change in current at the source terminal of the power switch using a complex impedance of a metal trace connected to the source terminal of the power switch, and to control a gate control signal to the gate terminal based on the detected change in current.

[0007] In some aspects, the technology described herein relates to a system in which the controller is a point-of-use controller on a power module having a power switch.

[0008] In some aspects, the technology described herein relates to a system in which a drain terminal of a power switch is configured to connect to a positive terminal of a battery and a source terminal of the power switch is configured to connect to a phase terminal of a motor.

[0009] In some aspects, the technology described herein relates to a system in which a source terminal of a power switch is configured to connect to a negative terminal of a battery and a drain terminal of the power switch is configured to connect to a phase terminal of a motor.

[0010] In some aspects, the technology described herein relates to a system in which a controller includes a current rate of change detector connected to a metal trace connected to a source terminal of a power switch, the current rate of change detector configured to detect a change in current.

[0011] In some aspects, the technology described herein relates to a system wherein the controller further includes: an integrated gate driver computation engine (IGDCE) connected to the gate terminal, the IGDCE configured to provide a gate control signal to the gate terminal based on the detected change in current.

[0012] In some aspects, the technology described herein relates to a system in which an IGDCE is configured to receive corresponding instantaneous, short duration, and long duration current information based on detected changes in current, and to provide a gate control signal to a gate terminal based on the corresponding instantaneous, short duration, and long duration current information.

[0013] In some aspects, the techniques described herein relate to a system wherein a current change rate detector is configured to provide a current change rate overcurrent signal to an IGDCE, and the IGDCE is configured to immediately initiate shutoff of a power switch using a turn-off gate drive curve to provide a gate control signal.

[0014] In some aspects, the technology described herein relates to a system wherein the controller further comprises: an M-bit flash thermometer analog-to-digital converter configured to receive an analog signal from a current rate of change detector and provide a digital signal to the IGDCE.

[0015] In some aspects, the technology described herein relates to a system wherein the controller further includes: a low-pass analog filter and a sample and hold circuit configured to receive an analog signal from a current rate of change detector and provide an analog output signal, and a programmable gain controller and an N-bit analog to digital converter configured to receive the analog output signal from the low-pass analog filter and the sample and hold circuit and provide a digital signal to the IGDCE.

[0016] In some aspects, the technology described herein relates to a system that further includes a battery configured to supply DC power to the inverter and a motor configured to receive AC power from the inverter to drive the motor.

[0017] In some aspects, the technology described herein relates to a method comprising: receiving, by one or more controllers, a sensing signal of a metal trace connected to a source terminal of a power switching device, the sensing signal comprising one or more of a voltage signal or a current signal; determining, by the one or more controllers, a change in current at the source terminal of the power switching device based on the received sensing signal; determining, by the one or more controllers, a gate control signal to a gate terminal of the power switching device based on the determined change in current; and sending, by the one or more controllers, the determined gate control signal to the gate terminal of the power switching device.

[0018] In some aspects, the technology described herein relates to a method in which the one or more controllers are point-of-use controllers on a power module having a power switch.

[0019] In some aspects, the technology described herein relates to a method wherein determining a gate control signal by the one or more controllers comprises: determining, by the one or more controllers, instantaneous current information based on a determined change in current; determining, by the one or more controllers, short-duration current information based on the determined change in current; determining, by the one or more controllers, long-duration current information based on the determined change in current; and determining, by the one or more controllers, the gate control signal based on one or more of the determined instantaneous, short-duration, and long-duration current information.

[0020] In some aspects, the technology described herein relates to a method wherein determining instantaneous current information by the one or more controllers includes: determining, by the one or more controllers, a current rate of change overcurrent signal based on the determined change in current; and wherein determining, by the one or more controllers, a gate control signal is based on the determined instantaneous current information and includes immediately initiating shutoff of a power switching element using a uniquely calculated shutoff gate drive curve.

[0021] In some aspects, the technology described herein relates to a method wherein determining short duration current information by the one or more controllers includes: determining a fast response digital signal by the one or more controllers based on an analog-to-digital conversion of a determined change in current; and wherein determining a gate control signal by the one or more controllers is based on the determined short duration current information and includes adjusting the operation of a power switching element based on the short duration current information.

[0022] In some aspects, the technology described herein relates to a method wherein determining long duration current information by the one or more controllers includes: determining a slow response digital signal by the one or more controllers based on low pass filtering and analog-to-digital conversion of determined changes in current; and wherein determining a gate control signal by the one or more controllers is based on the determined long duration current information and includes adjusting the operation of a power switching element based on the long duration current information.

[0023] In some aspects, the technology described herein relates to a system comprising: a power module, the power module being for an inverter for an electric vehicle, the power module comprising: a power switch element, the power switch element comprising a drain terminal, a source terminal, and a gate terminal; and a point-of-use controller, the point-of-use controller being configured to detect a change in current at the source terminal of the power switch element using a complex impedance of a metal trace connected to the source terminal of the power switch element, and to control a gate control signal to the gate terminal based on the detected change in current.

[0024] In some aspects, the technology described herein relates to a system wherein a point-of-use controller includes: a current rate of change detector connected to a metal trace connected to a source terminal of a power switching element, the current rate of change detector being configured to detect a change in current; an integrated gate driver computation engine (IGDCE) connected to a gate terminal, the IGDCE being configured to provide a gate control signal to the gate terminal based on the detected change in current, wherein the IGDCE is configured to receive corresponding instantaneous, short duration, and long duration current information based on the detected change in current, and to provide a gate control signal to the gate terminal based on the corresponding instantaneous, short duration, and long duration current information.

[0025] In some aspects, the technology described herein relates to a system wherein a current change rate detector is configured to provide a current change rate overcurrent signal to an IGDCE, and the IGDCE is configured to immediately initiate cutting off a power switching element using a turn-off gate drive curve to provide a gate control signal, and wherein a point-of-use controller further comprises: an M-bit flash thermometer analog-to-digital converter, the M-bit flash thermometer analog-to-digital converter being configured to receive an analog signal from the current change rate detector and provide a digital signal to the IGDCE, a low-pass analog filter and a sample and hold circuit, the low-pass analog filter and the sample and hold circuit being configured to receive the analog signal from the current change rate detector and provide an analog output signal, and a programmable gain controller and an N-bit analog-to-digital converter, the programmable gain controller and the N-bit analog-to-digital converter being configured to receive the analog output signal from the low-pass analog filter and the sample and hold circuit and provide a digital signal to the IGDCE.

[0026] Other objects and advantages of the disclosed embodiments will be described in part in the following description, and in part will be obvious from the description, or can be understood by practicing the disclosed embodiments. The objects and advantages of the disclosed embodiments will be realized and achieved by means of the elements and combinations particularly pointed out in the appended claims.

[0027] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosed embodiments, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various exemplary embodiments and, together with the description, serve to explain the principles of the disclosed embodiments.

[0029] Figure 1 An exemplary system infrastructure for a vehicle including a combined inverter and converter is depicted according to one or more embodiments.

[0030] Figure 2 Depicted is a method for providing a point-of-use switching controller according to one or more embodiments. Figure 1 An exemplary system infrastructure of a combined inverter and converter.

[0031] Figure 3 Describes a method for Figure 2 An exemplary system infrastructure for a controller of FIG.

[0032] Figure 4 Describes a method for Figure 2 An exemplary system infrastructure for a point-of-use switching controller.

[0033] Figure 5 Describes a method for Figure 4 An exemplary system infrastructure of an upper power module.

[0034] Figure 6 An exemplary system for detecting overcurrent in a power device switch according to one or more embodiments is depicted.

[0035] Figure 7 An exemplary method for detecting overcurrent of a power device switch according to one or more embodiments is depicted. DETAILED DESCRIPTION

[0036] Both the foregoing general description and the following detailed description are exemplary and explanatory only and do not constrain the claimed features. As used herein, the terms "comprises," "comprising," "has," "having," "includes," "including," or other variations thereof are intended to encompass non-exclusive inclusions such that a process, method, article, or device that includes a series of elements includes not only those elements, but may also include other elements that are not explicitly listed or inherent to such process, method, article, or device. In the present disclosure, unless otherwise stated, relative terms (such as, for example, "about," "substantially," and "approximately") are used to indicate possible ±10% variations in the stated values. In the present disclosure, unless otherwise stated, any numerical value may include possible ±10% variations in the stated values.

[0037] The terms used below may be interpreted in their broadest reasonable manner, although they are being used in conjunction with a detailed description of certain specific examples of the present disclosure. Indeed, certain terms may even be emphasized below; however, any term intended to be interpreted in any constrained manner will be explicitly and specifically defined as such in this detailed description. For example, in the context of the present disclosure, a switching device may be described as a switching element or device, but may refer to any device for controlling power flow in a circuit. For example, a switching element may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT) or a relay, or any combination thereof, but is not limited thereto.

[0038] Various embodiments of the present disclosure relate generally to systems and methods for overcurrent detection for an inverter for an electric vehicle, and more particularly to systems and methods for monitoring overcurrent for power device switches of an inverter for an electric vehicle.

[0039] Inverters (such as those used to drive motors in electric vehicles) are responsible for converting high voltage direct current (HVDC) into alternating current (AC) to drive the motor. A three-phase inverter may include a bridge having six power device switches (e.g., power transistors such as IGBTs or MOSFETs) that are controlled by pulse width modulation (PWM) signals generated by a controller. The inverter may include three-phase switches to control phase voltages, upper and lower gate drivers to control the switches, a PWM controller, and glue logic between the PWM controller and the gate driver. The PWM controller may generate signals to define the expected state of the system. The gate driver may send signals from the PWM controller to the phase switches. The phase switches may drive the phase voltages. The inverter may include an isolation barrier between a low voltage plane and a high voltage plane. The signal may be passed from the PWM controller to the phase switch by passing through an isolation barrier, which may employ optical, converter-based, or capacitor-based isolation. The PWM signal may be distorted when passing through the glue logic, which may include resistive, capacitive, or other types of filtering. Due to the electrical isolation barrier and other delays within the gate driver, the PWM signal may be distorted when passing through the gate driver. The PWM signal may be distorted when the signal is processed by the phase switching device via the gate driver output.

[0040] Gate drivers withstand common-mode transients that occur during field effect transistor (FET) switching and when one side of a floating high voltage terminal is shorted to ground or subjected to electrostatic discharge. These voltage transients can cause fast edges that can form common-mode current bursts through electrical isolation. Gate drivers may need to demonstrate common-mode transient immunity (CMTI) in order to be effective and safe.

[0041] The gate driver may have a high voltage domain in common with the voltage plane of the associated FET. Further, the high voltage plane may be supplied by a flyback converter, which may be isolated from the low voltage plane by a transformer. The high voltage domain power supply may be used to provide power to such a circuit that sources and sinks gate current to drive the FET and can detect FET faults, thereby acting on the faults and / or transmitting the faults to the low voltage domain. The gate driver may include an electrical channel dedicated to FET commands, and one or more bidirectional or unidirectional electrical channels dedicated to FET communications.

[0042] High current switching transients can form strong electromagnetic (EM) fields that can couple into nearby metal traces. The magnitude and frequency of the coupled current can depend on the layout of the FET packaging solution and the direction and length of the metal traces between the FET and the control integrated circuit (IC). For example, a typical value for the coupled current can be up to 1A at an AC frequency of up to 100MHz. Typically, within the circuit, the gate driver IC can be placed far enough away from the FET so that the high EM field is not directly coupled into the internal metal traces within the gate driver IC. The gate driver is placed at a distance from the EM field so that the induced current within the circuit is below the level that will cause the gate driver to malfunction, or a metal shield is placed between the gate driver and the source of the EM field to protect the gate driver circuit. The output terminals of the gate driver connected to the FET are exposed to the EM field at a point where the output terminals are no longer covered by the shield. The gate driver switches large currents (e.g., such as 5A to 15A) through these exposed terminals. The large currents switched are usually larger in magnitude than the EM induced current. The gate driver can overdrive the induced current to maintain control of the FET. The gate driver and the high side of the FET may share a common ground and gate control signal trace, both of which may be susceptible to coupled currents.

[0043] The gate driver can turn on low resistance switches to source and sink gate current. Sometimes a series resistor can be added to limit the gate current. The switched gate current can be greater than the coupling current in order to maintain control of their respective FETs.

[0044] The gate driver may be able to sense the FET operating voltage or current in order to provide feedback and react to faults. An overcurrent fault may typically be detected by sensing the FET drain to source voltage and comparing the sensed voltage to a reference value. The sensed voltage may be heavily filtered to reject coupled currents. Filtering may slow the response to a fault condition, causing a delay in response. For example, the rate of current increase due to a low resistance short may reach damaging levels before being detected by a heavily filtered drain to source voltage detection strategy. The resulting short may damage the FET or the vehicle before being detected and cut off.

[0045] According to one or more embodiments, a FET driver circuit may provide fast overcurrent detection by shunt current sensing, or by diverting a portion of the load current through a parallel FET that may have a current sensing circuit. Utilizing either strategy may require a "point of use IC" in which the sensing circuit is very close to the FET. Even if the point of use IC and the remote controller are resistant to EM fields, the communication between the point of use IC and the remote controller is still susceptible to induced currents. Point of use ICs have been implemented in low EM field applications, such as smart FETs for automotive applications. However, point of use ICs have not yet been used in high EM field applications. High EM fields can be fields that (i) induce a current within the IC that exceeds the operating current of the IC and causes a malfunction, or (ii) induce a differential voltage within the IC that exceeds the operating differential voltage and causes a malfunction. High EM fields can be, for example, fields greater than about 10A or about 100V.

[0046] As described above, the gate driver may be able to sense the FET operating voltage or current to provide feedback and react to faults. One or more embodiments may use a metal trace resistance in the source terminal of the power FET to provide overcurrent detection. For a low-side power FET, the trace resistance may be between the source terminal of the power FET and the negative terminal of the battery. For a high-side power FET, the trace resistance may be between the source terminal of the power FET and the phase terminal or low-side drain terminal. The effective complex impedance of the metal trace may have an inductive component in series with a resistive component and may have a parallel shunt distributed or displacement capacitance component.

[0047] A series inductive element can provide a large voltage term that is proportional to the time rate of change of the current in the source trace inductance itself. This can allow sensing and acting on hard shorts and / or faults in durations of hundreds of nanoseconds to easily meet short circuit withstand times of less than 1.5 μs as required by fast power FETs. A series resistive element can be used to generate a voltage signal that is a shaped version of the amplitude current in the source trace resistance itself. This can provide the system with a sensed soft short or fault signal to appropriately act on faults in durations of 1.0 μs or longer, and can vary based on specific system requirements.

[0048] The shaped current component can be further utilized by the integrated gate driver calculation engine (IGDCE) to calculate the optimal next cycle gate drive PWM drive curve to help minimize the switching loss of the power FET, while enabling the PWM duration to be reduced and the minimum dead time between the low-side power FET and the high-side power FET to be reduced. In the event of a hard short circuit, the IGDCE can immediately receive an overcurrent flag signal from the overcurrent detector, and can immediately use a uniquely calculated or predetermined turn-off gate drive curve to initiate the cut-off of the faulty power FET to ensure the safe shutdown of the faulty device. In the event of a soft short circuit, the IGDCE can continuously receive a shaped digital code representing the current amplitude flowing in the faulty device, which can achieve an almost noise-free signal of the current flowing through the faulty device. The accurate and noise-free device current signal can enable the protection of the power module while maintaining the safety functionality of the power module. When the soft short circuit begins to cause an unsafe system operating condition, the IGDCE can immediately use the calculated turn-off gate drive curve to initiate the shutdown of the faulty power FET to ensure the safe and correct shutdown of the faulty device.

[0049] One or more embodiments may provide overcurrent detection for power devices that uses both the time rate of change and the shaped pattern of the current of the power FET. One or more embodiments may provide a high-speed overcurrent detection fault indicator to meet the short circuit withstand time required by, for example, fast power devices (such as SiC power FETs). One or more embodiments may provide an accurate shaped pattern of the current amplitude that is used to protect the health of the power module while maintaining the safety functionality of the module. One or more embodiments may use a calculated or predetermined turn-off gate drive curve to provide a shutdown of the faulty power FET to ensure safe shutdown of the faulty device. One or more embodiments may be highly reliable due to integration into such a single IC that resides in the same package as the power FET or is provided in a point-of-use controller for the power FET. One or more embodiments may provide a lower cost solution due to fewer components. One or more embodiments may provide excellent immunity to external system noise transients compared to some desaturation and external shunt resistor methods of overcurrent detection. One or more embodiments may be able to be configured for any number of module power FETs, RMS current levels, and varying battery voltages.

[0050] Silicon carbide (SiC) MOSFETs are increasingly replacing silicon (Si) IGBTs in motor drive inverter systems. SiC MOSFETs have more stringent overcurrent circuit protection requirements than Si IGBTs. One or more embodiments may provide a fast and reliable overcurrent circuit protection circuit to protect the health of SiC MOSFETs and ensure safe system operation.

[0051] Compared to IGBTs, which may have similar blocking voltage and current ratings, SiC MOSFETs have a smaller chip area, which can make parasitic capacitance smaller than IGBTs, thereby increasing inherent switching speeds. However, the smaller chip area of ​​the SiC MOSFET die may also provide lower heat dissipation capabilities than IGBTs. During an overcurrent condition, the rapidly increasing current can generate a significant amount of Joule heat, and if the ability to dissipate enough heat is not met, the SiC MOSFET die may be destroyed in a short period of time. For smaller die sizes, the surge current capability of the SiC MOSFET may be significantly lower than that of the IGBT counterpart.

[0052] The output characteristics of SiC MOSFETs may be different from those of IGBTs. IGBTs typically function in the saturation region during the normal on-state. When an overcurrent event occurs, the collector current increases and undergoes a sharp transition from the saturation region to the active region. The collector current is self-limiting and becomes independent of the collector-to-emitter voltage. Therefore, the increase in IGBT current and power dissipation becomes self-limiting. On the other hand, SiC MOSFETs function in the linear region during normal on-operation. During an overcurrent event, SiC MOSFETs enter the saturation region. SiC MOSFETs have a larger linear region than IGBTs. The transition from the linear region to the saturation region occurs at a significantly higher drain-to-source voltage. The drain current keeps increasing with the increased drain-to-source voltage. The device is destroyed before reaching the transition point. These characteristics make overcurrent circuit protection for SiC MOSFETs very different from IGBT devices.

[0053] Some overcurrent protections are either too slow in response, consume a significant amount of power, or are too expensive.One or more embodiments may provide an integrated overcurrent detection system that has a fast response and low cost.

[0054] Figure 1 An exemplary system infrastructure for a vehicle including a combined inverter and converter according to one or more embodiments is depicted. In the context of the present disclosure, the combined inverter and converter may be referred to as an inverter. Figure 1As shown, the electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include a component for receiving electric power from an external source and outputting electric power to charge the battery 195 of the electric vehicle 100. For example, the inverter 110 may convert DC power from the battery 195 in the electric vehicle 100 into AC power to drive the motor 190 of the electric vehicle 100, but the embodiment is not limited thereto. For example, the inverter 110 may be bidirectional and may convert DC power into AC power, or convert AC power into DC power, such as during regenerative braking. The inverter 110 may be a three-phase inverter, a single-phase inverter, or a multi-phase inverter.

[0055] Figure 2 Depicted is a method for providing a point-of-use switching controller according to one or more embodiments. Figure 1 The electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include an inverter controller 300 ( Figure 3 14). The inverter 110 may include a low voltage upper phase controller 120 separated from a high voltage upper phase controller 130 by an electrical isolator 150, and an upper phase power module 140. The upper phase power module 140 may include a point-of-use upper phase controller 142 and an upper phase switch 144. The inverter 110 may include a low voltage lower phase controller 125 separated from a high voltage lower phase controller 135 by an electrical isolator 150, and a lower phase power module 145. The lower phase power module 145 may include a point-of-use lower phase controller 146 and a lower phase switch 148. The upper phase switch 144 and the lower phase switch 148 may be connected to a motor 190 and a battery 195. The electrical isolator 150 may be one or more of optical, converter-based, or capacitor-based isolation. For example, the electrical isolator 150 may be one or more capacitors having a value from about 20 fF to about 100 fF, having a breakdown voltage from about 6 kV to about 12 kV. The electrical isolator 150 may include a pair of capacitors, wherein one capacitor of the pair carries a complementary (180 degrees out of phase) data signal from the other capacitor of the pair to form a differential signal that is rejected for common mode noise. The electrical isolator 150 may include more than one capacitor in series. The electrical isolator 150 may include one capacitor located on a first IC, or may include a first capacitor located on a first IC and a second capacitor located on a second IC that communicates with the first IC.

[0056] The inverter 110 may include a low voltage region (e.g., where the voltage is typically less than 5V) and a high voltage region (e.g., where the voltage may exceed 500V). The low voltage region may be separated from the high voltage region by an electrical isolator 150. The inverter controller 300 may be in the low voltage region of the inverter 110, and may send a signal to and receive a signal from the low voltage upper phase controller 120. The low voltage upper phase controller 120 may be in the low voltage region of the inverter 110, and may send a signal to and receive a signal from the high voltage upper phase controller 130. The low voltage upper phase controller 120 may send a signal to and receive a signal from the low voltage lower phase controller 125. The high voltage upper phase controller 130 may be in the high voltage region of the inverter 110. Therefore, the signal between the low voltage upper phase controller 120 and the high voltage upper phase controller 130 passes through the electrical isolator 150. The high voltage upper phase controller 130 may send signals to and receive signals from a point-of-use upper phase controller 142 in the upper phase power module 140. The point-of-use upper phase controller 142 may send signals to and receive signals from an upper phase switch 144. The upper phase switch 144 may be connected to a motor 190 and a battery 195. For example, the upper phase switch 144 and the lower phase switch 148 may be used to transfer energy from the motor 190 to the battery 195, from the battery 195 to the motor 190, from an external source to the battery 195, or from the battery 195 to an external source. The lower phase system of the inverter 110 may be similar to the upper phase system described above.

[0057] Figure 3 Describes a method for Figure 2 FIG. 3 is an exemplary system infrastructure of an inverter controller 300 . The inverter controller 300 may include one or more controllers.

[0058] The inverter controller 300 may include a set of instructions that can be executed to cause the inverter controller 300 to perform any one or more of the methods or computer-based functions disclosed herein. The inverter controller 300 may operate as a standalone device, or may be connected to other computer systems or peripheral devices, for example using a network.

[0059] In a networked deployment, the inverter controller 300 can operate in the capacity of a server, or as a client in a server-client user network environment, or as a peer computer system in a peer (or distributed) network environment. The inverter controller 300 can also be implemented as or incorporated into various devices, such as a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile device, a palmtop computer, a laptop computer, a desktop computer, a communication device, a wireless phone, a landline phone, a control system, a camera, a scanner, a fax machine, a printer, a pager, a personal trusted device, a network device, a network router, a switch or bridge, or any other machine capable of executing a set of instructions (sequentially or otherwise) (the set of instructions specifies the actions to be taken by the machine). In a specific implementation, the inverter controller 300 can be implemented using an electronic device that provides voice, video or data communication. Further, although the inverter controller 300 is illustrated as a single system, the term “system” should also be understood to include any collection of systems or subsystems that individually or jointly execute one or more sets of instructions to perform one or more computer functions.

[0060] like Figure 3 As shown, the inverter controller 300 may include a processor 302, such as a central processing unit (CPU), a graphics processing unit (GPU), or both. The processor 302 may be a component in a variety of systems. For example, the processor 302 may be part of a standard inverter. The processor 302 may be one or more general-purpose processors, digital signal processors, application-specific integrated circuits, field programmable gate arrays, servers, networks, digital circuits, analog circuits, combinations thereof, or other devices now known or later developed for analyzing and processing data. The processor 302 may implement a software program, such as a manually generated (i.e., programmed) code.

[0061] The inverter controller 300 may include a memory 304 that can communicate via a bus 308. The memory 304 may be a main memory, a static memory, or a dynamic memory. The memory 304 may include, but is not limited to, computer-readable storage media, such as various types of volatile and non-volatile storage media, including but not limited to random access memory, read-only memory, programmable read-only memory, electrically programmable read-only memory, electrically erasable read-only memory, flash memory, tape or disk, optical media, etc. In one specific implementation, the memory 304 includes a cache or random access memory for the processor 302. In an alternative specific implementation, the memory 304 is separated from the processor 302, such as a cache memory, system memory, or other memory of the processor. The memory 304 may be an external storage device or database for storing data. Examples include a hard drive, a compact disk ("CD"), a digital video disk ("DVD"), a memory card, a memory stick, a floppy disk, a universal serial bus ("USB") storage device, or any other device operable to store data. The memory 304 is operable to store instructions that can be executed by the processor 302. The functions, actions, or tasks illustrated in the figures or described herein may be performed by the processor 302 executing instructions stored in the memory 304. The functions, actions, or tasks are not related to a particular type of instruction set, storage medium, processor, or processing strategy, and may be performed by software, hardware, integrated circuits, firmware, microcode, etc. operating alone or in combination. Likewise, processing strategies may include multi-processing, multi-tasking, parallel processing, etc.

[0062] As shown, the inverter controller 300 may further include a display 310, such as a liquid crystal display (LCD), an organic light emitting diode (OLED), a flat panel display, a solid state display, a cathode ray tube (CRT), a projector, a printer, or other display devices known now or later developed for outputting the determined information. The display 310 may serve as an interface for a user to view the operation of the processor 302, or specifically serve as an interface with the software stored in the memory 304 or in the drive unit 306.

[0063] Additionally or alternatively, the inverter controller 300 may include an input device 312 configured to allow a user to interact with any of the components of the inverter controller 300. The input device 312 may be a numeric keypad, a keyboard or a cursor control device (such as a mouse or a joystick), a touch screen display, a remote control, or any other device operable to interact with the inverter controller 300.

[0064] The inverter controller 300 may also or alternatively include a drive unit 306 implemented as a disk or optical drive. The drive unit 306 may include a computer-readable medium 322 in which one or more sets of instructions 324 (e.g., software) may be embedded. Further, the instructions 324 may embody one or more of the methods or logics described herein. The instructions 324 may reside completely or partially within the memory 304 and / or within the processor 302 during execution by the inverter controller 300. The memory 304 and the processor 302 may also include computer-readable media as described above.

[0065] In some systems, the computer-readable medium 322 includes instructions 324 or receives and executes instructions 324 in response to a propagated signal, so that a device connected to the network 370 can transmit voice, video, audio, images, or any other data through the network 370. Further, the instructions 324 can be transmitted or received through the network 370 and / or using the bus 308 via the communication port or interface 320. The communication port or interface 320 can be part of the processor 302 or can be an independent component. The communication port or interface 320 can be formed in software or can be a physical connector in hardware. The communication port or interface 320 can be configured to connect to the network 370, external media, display 310, or any other component in the inverter controller 300, or a combination thereof. The connection to the network 370 can be a physical connection (such as a wired Ethernet connection) or can be established wirelessly, as described below. Similarly, additional connections to other components of the inverter controller 300 can be physical connections or can be established wirelessly. The network 370 can alternatively be directly connected to the bus 308.

[0066] Although the computer-readable medium 322 is shown as a single medium, the term "computer-readable medium" may include a single medium or multiple media (such as a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" may also include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processor or causing a computer system to perform any one or more of the methods or operations disclosed herein. The computer-readable medium 322 may be non-transitory and may be tangible.

[0067] Computer readable medium 322 may include solid-state memory, such as a memory card or other package that accommodates one or more non-volatile read-only memories. Computer readable medium 322 may be random access memory or other volatile rewritable memory. Additionally or alternatively, computer readable medium 322 may include magneto-optical or optical media, such as a disk or tape or other storage device for capturing carrier signals (such as signals transmitted through a transmission medium). Digital file attachments to emails or other self-contained information archives or archive sets may be considered distribution media as tangible storage media. Therefore, the present disclosure is considered to include any one or more of computer-readable media or distribution media and other equivalents and successor media in which data or instructions may be stored.

[0068] In alternative implementations, dedicated hardware implementations (such as application specific integrated circuits, programmable logic arrays, and other hardware devices) may be constructed to implement one or more of the methods described herein. Applications that may include the apparatus and systems of various implementations may broadly include a variety of electronic and computer systems. One or more implementations described herein may use two or more specific interconnected hardware modules or devices with associated control and data signals that may be transmitted between and through the modules or as part of an application specific integrated circuit to implement functionality. Thus, the present system encompasses software, firmware, and hardware implementations.

[0069] The inverter controller 300 may be connected to a network 370. The network 370 may define one or more networks, including wired or wireless networks. The wireless network may be a cellular telephone network, an 802.11, 802.16, 802.20, or WiMAX network. Further, such networks may include public networks (such as the Internet), private networks (such as intranets), or combinations thereof and may utilize a variety of networking protocols that are now available or later developed, including but not limited to TCP / IP-based networking protocols. The network 370 may include a wide area network (WAN) (such as the Internet), a local area network (LAN), a campus area network, a metropolitan area network, a direct connection (such as through a universal serial bus (USB) port), or any other network that allows data communication. The network 370 may be configured to couple one computing device to another computing device to enable data communication between devices. The network 370 may generally be enabled to use any form of machine-readable media to transmit information from one device to another. The network 370 may include a communication method by which information can travel between computing devices. The network 370 may be divided into subnetworks. A subnetwork may allow access to all other components connected to it, or a subnetwork may restrict access between components. Network 370 may be considered a public or private network connection and may include, for example, a virtual private network or encryption or other security mechanisms employed over the public Internet.

[0070] According to various implementations of the present disclosure, the methods described herein may be implemented by a software program that can be executed by a computer system. Further, in an exemplary non-limiting implementation, the implementation may include distributed processing, component or object distributed processing, and parallel processing. Alternatively, a virtual computer system process may be constructed to implement one or more of the methods or functionalities described herein.

[0071] Although this specification describes components and functions that can be implemented in a specific implementation with reference to specific standards and protocols, the present disclosure is not limited to such standards and protocols. For example, standards for Internet and other packet-switched network transmissions (e.g., TCP / IP, UDP / IP, HTML, HTTP) represent examples of the prior art. Such standards are periodically replaced by faster or more efficient equivalents having substantially the same functionality. Therefore, alternative standards and protocols having the same or similar functionality as those disclosed herein are considered equivalents thereof.

[0072] It will be appreciated that, in one embodiment, the operations of the methods discussed are performed by an appropriate processor (or processors) of a processing (i.e., computer) system executing instructions (computer readable code) stored in a storage device. It will also be appreciated that the present disclosure is not limited to any particular implementation or programming technique, and that the present disclosure may be implemented using any suitable technique for implementing the functionality described herein. The present disclosure is not limited to any particular programming language or operating system.

[0073] Figure 4 Describes a method for Figure 2 An exemplary system infrastructure of a point-of-use switching controller. For a three-phase inverter, each of the upper phase and the lower phase may include three phases related to phases A, B, and C. For example, the upper phase power module 140 may include an upper phase power module 140A for upper phase A, an upper phase power module 140B for upper phase B, and an upper phase power module 140C for upper phase C. The upper phase power module 140A may include a point-of-use upper phase A controller 142A and an upper phase A switching element 144A. The upper phase power module 140B may include a point-of-use upper phase B controller 142B and an upper phase B switching element 144B. The upper phase power module 140C may include a point-of-use upper phase C controller 142C and an upper phase C switching element 144C. Each of the upper phase A switching member 144A, the upper phase B switching member 144B, and the upper phase C switching member 144C may be connected to the motor 190 and the battery 195 . Figure 4 Details of the upper phase power module 140 are depicted. Although not shown, the lower phase power module 145 may include a similar structure as the upper phase power module 140 for the lower phases A, B, and C.

[0074] Figure 5 Describes a method for Figure 4 Example system infrastructure for the upper power module. For example, Figure 5 Additional details of upper phase power module 140A are provided. Although not shown, upper phase power module 140B, upper phase power module 140C, and respective lower phase power modules of lower phase power module 145 may include components related to Figure 5 The upper phase power module 140A shown in FIG. 1 is similar in structure to the upper phase power module 140A shown in FIG. 1. In addition, the terms "upper", "lower", "northern", and "southern" as used in this disclosure are used for reference only, do not limit the elements to a particular orientation, and are generally interchangeable throughout the text. For example, the upper phase power module 140 may be referred to as a lower phase power module, a northern phase power module, a southern phase power module, a first phase power module, or a second phase power module.

[0075] The upper phase power module 140A may include a point-of-use upper phase A controller 142A and an upper phase A switch 144A. The upper phase A switch 144A may include one or more sets of switches. Figure 5 As shown, the upper phase A switch 144A may include an upper phase A north switch 144A-N and an upper phase A south switch 144A-S. The point-of-use upper phase A controller 142A may include one or more memories, controllers, or sensors. For example, the point-of-use upper phase A controller 142A may include a communication manager 405, a functional safety controller 410, a test interface and controller 415, a north thermal sensor 420A, a south thermal sensor 420B, a self-test controller 425, a command manager 430, a waveform adjuster 435, a memory 440, a north switch control and diagnostic controller 450N, and a south switch control and diagnostic controller 450S. The point-of-use upper phase A controller 142A may include a controller 405, a functional safety controller 410, a test interface and controller 415, a north thermal sensor 420A, a south thermal sensor 420B, a self-test controller 425, a command manager 430, a waveform adjuster 435, a memory 440, a north switch control and diagnostic controller 450N, and a south switch control and diagnostic controller 450S. Figure 5 More or fewer components than those shown. For example, the point-of-use upper phase A controller 142A may include more or less than two switch controls and diagnostic controllers, and may include more than two thermal sensors.

[0076] The communication manager 405 may control inter-controller communications to and from the point-of-use upper phase A controller 142A and / or may control intra-controller communications between components of the point-of-use upper phase A controller 142A. The functional safety controller 410 may control safety functions of the point-of-use upper phase A controller 142A. For example, the test interface and controller 415 may control test functions of the point-of-use upper phase A controller 142A, such as end-of-line testing in manufacturing. The north thermal sensor 420A may sense the temperature at a first location in the point-of-use upper phase A controller 142A, and the south thermal sensor 420B may sense the temperature at a second location in the point-of-use upper phase A controller 142A. For example, the self-test controller 425 may control self-test functions of the point-of-use upper phase A controller 142A, such as during initialization of the point-of-use upper phase A controller 142A after an inverter 110 power-on event. The command manager 430 may control commands received from the communication manager 405 and issued to the north switch control and diagnostic controller 450N and the south switch control and diagnostic controller 450S. The waveform adjuster 435 may control the waveform timing and shape of the commands received from the communication manager 405 and issued to the north switch control and diagnostic controller 450N and the south switch control and diagnostic controller 450S. The memory 440 may include one or more volatile and non-volatile storage media for the operation of the point-of-use upper phase A controller 142A. The north switch control and diagnostic controller 450N may send one or more signals to the north switch 144A-N to control the operation of the north switch 144A-N, and may receive one or more signals from the north switch 144A-N that provide information about the north switch 144A-N. The south switch control and diagnostic controller 450S may send one or more signals to the south switches 144A-S to control the operation of the south switches 144A-S, and may receive one or more signals from the south switches 144A-S providing information about the south switches 144A-S. As described above, the terms "north" and "south" are used for reference only, and the north switch control and diagnostic controller 450N may send one or more signals to the south switches 144A-S, and the south switch control and diagnostic controller 450S may send one or more signals to the south switches 144A-N.

[0077] Figure 6 An exemplary system for detecting overcurrent of a power device switch according to one or more embodiments is depicted. For example, the overcurrent detection system 600 may be a specific implementation of the upper phase power module 140 and the lower phase power module 145. Figure 6As shown, the upper power switch 644U (MB) can be a specific implementation of the upper phase A switch 144A, and the lower power switch 644L (MA) can be a specific implementation of the lower phase A switch paired with the upper phase A switch 144A. Figure 6 As shown, the point-of-use upper phase controller 642U can be a specific implementation of the point-of-use upper phase A controller 142A, for example, which has a corresponding point-of-use lower phase A controller 642L. Even more specifically, for example, the point-of-use upper phase controller 642U can be a specific implementation of the north switching member control and diagnostic controller 450N and the south switching member control and diagnostic controller 450S.

[0078] like Figure 6 As shown, for example, the overcurrent detection system 600 may include a positive battery connector 620 and a negative battery connector 621, which may be respective connectors from the battery 195. The positive battery connector 620 may be connected to a drain terminal of an upper power switch 644U, a source terminal of the upper power switch 644U may be connected to a drain terminal of a lower power switch 644L, and a source terminal of the lower power switch 644L may be connected to the negative battery connector 621. The upper power switch 644U and the lower power switch 644L may control the flow of energy from the positive battery connector 620 and the negative battery connector 621 to the phase connector 610, which may be connected to the motor 190 to control the rotation of the motor 190, for example.

[0079] The metal trace from the source terminal of the upper power switch 644U may provide a first sense input SNSP_U and a second sense input SNSM_U to the point-of-use upper phase controller 642U, for example, using a bump, and the point-of-use upper phase controller 642U may provide a gate control signal 630 to the gate terminal of the upper power switch 644U. The distance between the first sense input SNSP_U and the second sense input SNSM_U may be, for example, less than 30 cm or less than 3 cm. The point-of-use upper phase controller 642U may include a current change rate detector 632, an M-bit flash thermometer analog-to-digital converter 636, a low-pass analog filter and a sample and hold circuit 622, a programmable gain controller and an N-bit analog-to-digital converter 626, and an integrated gate driver calculation engine (IGDCE) 628.

[0080] The current change rate detector 632 may receive signals from the first sense input SNSP_U and the second sense input SNSM_U and provide signals to the M-bit flash thermometer analog-to-digital converter 636, the low-pass analog filter and sample and hold circuit 622, and the IGDCE 628. The M-bit flash thermometer analog-to-digital converter 636 may provide a signal to the IGDCE 628. The low-pass analog filter and sample and hold circuit 622 may provide a signal to the programmable gain controller and N-bit analog-to-digital converter 626, and the programmable gain controller and N-bit analog-to-digital converter 626 may provide a signal to the IGDCE 628. The signal from the current change rate detector 632 directly to the IGDCE 628 may immediately indicate an over-current condition to the IGDCE 628. The M-bit flash thermometer analog-to-digital converter 636 may provide a signal to the IGDCE 628 of the current in a relatively short duration window. The low pass analog filter and sample and hold circuit 622 and the programmable gain controller and N-bit analog to digital converter 626 can provide a relatively long duration window for the current IGDCE 628. Utilizing the instantaneous, short duration, and long duration current information, the IGDCE 628 can provide an improved response relative to systems that do not provide control based on this information.

[0081] One or more embodiments may provide an overcurrent detection system 600 that uses a metal trace in the source terminal of a power FET as a current sensing complex impedance. For the lower power switch 644L, the trace impedance may be between the source terminal of the lower power switch 644L and the negative battery connector 621. For the upper power switch 644U, the trace impedance may be between the source terminal of the upper power switch 644U and the phase connector 610, or between the source terminal of the upper power switch 644U and the drain terminal of the lower power switch 644L. For the upper power switch 644U, for example, the effective complex impedance of the metal trace may include an inductive component 614 in series with a resistive component 616 and a parallel shunt distributed / displacement capacitor component 618. Although in Figure 6614 are shown as electrical devices, but the inductor component 614, the resistor component 616, and the capacitor component 618 are not additional devices, but rather electrical characteristics of the metal traces themselves. The effective complex impedance can be defined as Z(s)=(Rsrc+SLs)||(1 / SCp), where Rsrc is the resistance of the resistor component 616, S=jω, where ω is the rad / sec frequency, Ls is the inductance of the inductor component 614, and Cp is the capacitance of the capacitor component 618. During an overcurrent event, the series inductor component 614 can provide a large voltage term (e.g., the voltage difference between SNSP_U and SNSM_U) that is proportional to the time rate of the flowing current in the source trace inductance itself. The metal trace of the source terminal of the lower power switch 644L can have a similar inductor / resistor / capacitor structure.

[0082] For example, in the case where the upper power switch 644U is turned on due to a hard fault, such as when the drain of the lower power switch 644L is shorted to the negative battery connection 621, the rate of change of the drain current can become large, which can cause the voltage across the resistor component 616 to increase according to Vsrc_metal_trace=Ls*dids / dt. This can allow sensing and acting on hard shorts in a duration of hundreds of nanoseconds to easily meet the short-circuit withstand time of less than 1.5μs required for fast power FETs. The resistor component 616 can be used to generate a voltage signal that is a shaped version of the drain current of the resistor component 616. A low-pass analog filter and a sample and hold circuit 622 can be used to generate a shaped version of the drain current, where the output is provided to a programmable gain controller and an N-bit analog to digital converter 626. This presents a sensed soft short or fault signal for the overcurrent detection system 600 to appropriately act on the fault in a duration of 1.0μs or longer, which can be configured based on specific system requirements. The shaped current component may be used by the IGDCE 628 to determine an optimal next cycle gate drive PWM drive curve to help minimize the switching losses of the upper power switch 644U while enabling a reduction in PWM duration and a reduction in the minimum dead time between the lower power switch 644L and the upper power switch 644U. The optimal next cycle gate drive PWM drive curve may be provided as a gate control signal 630 to the upper power switch 644U.

[0083] In the event of a hard short circuit, the IGDCE 628 may immediately receive a current change rate overcurrent signal from the current change rate detector 632, and may immediately initiate the shutoff of the upper power switch 644U using a uniquely calculated or predetermined shutoff gate drive curve to ensure safe shutoff of the faulty upper power switch 644U. The M-bit flash thermometer analog-to-digital converter 636 is a fast response circuit that may provide M logic signals to the IGDCE 628 to further assist in making the most appropriate decision in the case of hard and soft overcurrent events. For example, the IGDCE 628 may determine that the most appropriate decision is to use a predetermined shutoff curve to determine the safest shutoff curve, or to determine not to take immediate shutoff action when monitoring the current amplitude trajectory.

[0084] In the event of a soft short, the IGDCE may continuously receive digital codes from the programmable gain controller and the N-bit analog-to-digital converter 626, wherein the digital code represents a shaped version of the drain current amplitude flowing for the faulty upper power switching element 644U, which may achieve an almost noise-free signal of the current flowing in the faulty upper power switching element 644U. The accurate and noise-free device current signal may enable protection of the upper power switching element 644U while maintaining the safety functionality of the overcurrent detection system 600. When a soft short begins to cause an unsafe system operating condition, the IGDCE 628 may immediately initiate a shutdown process for the faulty upper power switching element 644U using the calculated shutdown gate drive curve to ensure a safe and correct shutdown process. One or more embodiments may provide current detection for a power device that uses both the time rate of change of the power FET current and the shaped version.

[0085] Figure 7An exemplary method 700 for detecting overcurrent of a power device switch according to one or more embodiments is depicted. The method 700 may include receiving, by one or more controllers (such as a point-of-use upper phase controller 642U), a sense signal (e.g., SNSP_U and SNSM_U) of a metal trace connected to a source terminal of a power switch (such as one or more of the upper power switches 644U), the sense signal including one or more of a voltage signal or a current signal (operation 705). The method 700 may include determining, by the one or more controllers, a change in current at the source terminal of the power switch based on the received sense signal (operation 710). The method 700 may include determining, by the one or more controllers, a gate control signal to a gate terminal of the power switch based on the determined change in current (operation 715). The method 700 may include sending, by the one or more controllers, the determined gate control signal to a gate terminal of the power switch (operation 720). The one or more controllers may be a point-of-use controller on a power module (such as the upper phase power module 140) having a power switch. For example, in the event that the upper power switch 644U is turned on due to a hard fault, such as when the drain of the lower power switch 644L is shorted to the negative battery connection 621, the rate of change of the drain current may become large, which may cause an increase in the voltage across the resistive component 616. This may allow sensing and acting on a hard short circuit in a duration of hundreds of nanoseconds to easily meet the short circuit withstand time of less than 1.5 μs required for fast power FETs.

[0086] The method 700 may include: determining instantaneous current information based on the determined change in current by the one or more controllers (operation 725). In the event of a hard short circuit, the IGDCE 628 may immediately receive a current change rate overcurrent signal from the current change rate detector 632, and may immediately initiate the shutoff of the upper power switch 644U using a uniquely calculated or predetermined shutoff gate drive curve to ensure safe shutoff of the faulty upper power switch 644U.

[0087] The method 700 may include determining, by the one or more controllers, short duration current information based on the determined change in current (operation 730). The M-bit flash thermometer analog-to-digital converter 636 is a fast response circuit that can provide M logic signals to the IGDCE 628 to further assist in making the most appropriate decision in the case of hard and soft over-current events. For example, the IGDCE 628 may determine that the most appropriate decision is to use a predetermined shutdown curve to determine the safest shutdown curve, or to determine not to take immediate shutdown action when monitoring the current amplitude trajectory.

[0088] The method 700 may include: determining, by the one or more controllers, long duration current information based on the determined change in current (operation 735). In the event of a soft short, the IGDCE may continuously receive a digital code from the programmable gain controller and the N-bit analog-to-digital converter 626, wherein the digital code represents a shaped version of the drain current amplitude flowing for the faulty upper power switch 644U, which may achieve an almost noise-free signal of the current flowing in the faulty upper power switch 644U. The accurate and noise-free device current signal may enable protection of the upper power switch 644U while maintaining the safety functionality of the overcurrent detection system 600.

[0089] Method 700 may include determining, by the one or more controllers, a gate control signal based on one or more of the determined instantaneous, short duration, and long duration current information (operation 740). One or more embodiments may provide current sensing for a power device that uses both a time rate of change and a shaped version of a power FET current.

[0090] The method 700 may include: determining, by the one or more controllers, a current rate of change overcurrent signal based on the determined change in current (operation 745). In operation 740, a gate control signal may be determined based on the determined instantaneous current information. The method 700 may include: immediately initiating the shutoff of the power switching element using a uniquely calculated turn-off gate drive curve (operation 750). The method 700 may include: determining, by the one or more controllers, a fast response digital signal based on an analog-to-digital conversion of the determined change in current (operation 755). In operation 740, a gate control signal may be determined based on the determined short-duration current information. The method 700 may include: adjusting the operation of the power switching element based on the short-duration current information (operation 760). The method 700 may include: determining, by the one or more controllers, a slow response digital signal based on low-pass filtering and analog-to-digital conversion of the determined change in current (operation 765). In operation 740, a gate control signal may be determined based on the determined long-duration current information. The method 700 may include: adjusting the operation of the power switching element based on the long-duration current information (operation 770).

[0091] One or more embodiments may provide overcurrent detection for power devices that uses both the time rate of change and the shaped pattern of the current of the power FET. One or more embodiments may provide a high-speed overcurrent detection fault indicator to meet the short circuit withstand time required by, for example, fast power devices (such as SiC power FETs). One or more embodiments may provide an accurate shaped pattern of the current amplitude that is used to protect the health of the power module while maintaining the safety functionality of the module. One or more embodiments may use a calculated or predetermined turn-off gate drive curve to provide a shutdown of the faulty power FET to ensure safe shutdown of the faulty device. One or more embodiments may be highly reliable due to integration into such a single IC that resides in the same package as the power FET or is provided in a point-of-use controller for the power FET. One or more embodiments may provide a lower cost solution due to fewer components. One or more embodiments may provide excellent immunity to external system noise transients compared to some desaturation and external shunt resistor methods of overcurrent detection. One or more embodiments may be able to be configured for any number of module power FETs, RMS current levels, and varying battery voltages.

[0092] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

Claims

1. A system comprising: An inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter comprises: a power switch including a drain terminal, a source terminal, and a gate terminal; and A controller is configured to detect a change in current at the source terminal of the power switch using a complex impedance of a metal trace connected to the source terminal of the power switch and to control a gate control signal to the gate terminal based on the detected change in current. 2 . The system of claim 1 , wherein the controller is a point-of-use controller on a power module having the power switch. 3 . The system of claim 1 , wherein the drain terminal of the power switch is configured to be connected to a positive terminal of the battery, and the source terminal of the power switch is configured to be connected to a phase terminal of the motor. 4 . The system of claim 1 , wherein the source terminal of the power switch is configured to be connected to a negative terminal of the battery, and the drain terminal of the power switch is configured to be connected to a phase terminal of the motor.

5. The system of claim 1, wherein the controller comprises: A current rate of change detector is connected to the metal trace connected to the source terminal of the power switch, the current rate of change detector being configured to detect the change in current.

6. The system of claim 5, wherein the controller further comprises: An integrated gate driver computation engine (IGDCE) is connected to the gate terminal, the IGDCE being configured to provide the gate control signal to the gate terminal based on the detected change in current.

7. The system of claim 6, wherein the IGDCE is configured to receive corresponding instantaneous, short duration, and long duration current information based on the detected changes in current, and to provide the gate control signal to the gate terminal based on the corresponding instantaneous, short duration, and long duration current information.

8. The system of claim 6, wherein the current change rate detector is configured to provide a current change rate overcurrent signal to the IGDCE, and the IGDCE is configured to immediately initiate shutoff of the power switch using a turn-off gate drive curve to provide the gate control signal.

9. The system of claim 6, wherein the controller further comprises: An M-bit flash thermometer analog-to-digital converter is configured to receive an analog signal from the current rate of change detector and provide a digital signal to the IGDCE.

10. The system of claim 6, wherein the controller further comprises: a low pass analog filter and a sample and hold circuit configured to receive an analog signal from the current rate of change detector and provide an analog output signal, and A programmable gain controller and an N-bit analog-to-digital converter are configured to receive the analog output signal from the low-pass analog filter and the sample and hold circuit and provide a digital signal to the IGDCE.

11. The system of claim 1, further comprising: the battery, the battery being configured to supply the DC power to the inverter; as well as The motor is configured to receive the AC power from the inverter to drive the motor.

12. A method comprising: Receiving, by one or more controllers, a sense signal of a metal trace connected to a source terminal of a power switch, the sense signal comprising one or more of a voltage signal or a current signal; determining, by the one or more controllers, a change in current at the source terminal of the power switch based on the received sense signals; determining, by the one or more controllers, a gate control signal to a gate terminal of the power switch based on the determined change in current; as well as The determined gate control signal is sent by the one or more controllers to the gate terminal of the power switch.

13. The method of claim 12, wherein the one or more controllers are point-of-use controllers on a power module having the power switch.

14. The method of claim 12, wherein determining, by the one or more controllers, the gate control signal comprises: determining, by the one or more controllers, instantaneous current information based on the determined change in current; determining, by the one or more controllers, short duration current information based on the determined change in current; determining, by the one or more controllers, long duration current information based on the determined change in current; as well as The gate control signal is determined by the one or more controllers based on one or more of the determined instantaneous, short duration, and long duration current information.

15. The method according to claim 14, Wherein determining the instantaneous current information by the one or more controllers comprises: determining, by the one or more controllers, a current rate of change overcurrent signal based on the determined change in current; and Wherein determining the gate control signal by the one or more controllers is based on the determined instantaneous current information and includes immediately initiating shutoff of the power switch using a uniquely calculated turn-off gate drive curve.

16. The method according to claim 14, Wherein determining the short duration current information by the one or more controllers comprises: determining, by the one or more controllers, a fast response digital signal based on an analog-to-digital conversion of the determined change in current; and Wherein determining the gate control signal by the one or more controllers is based on the determined short duration current information, and includes adjusting operation of the power switch based on the short duration current information.

17. The method according to claim 14, Wherein determining the long duration current information by the one or more controllers comprises: determining, by the one or more controllers, a slow response digital signal based on low pass filtering and analog to digital conversion of the determined change in current; and Wherein determining the gate control signal by the one or more controllers is based on the determined long duration current information, and includes adjusting operation of the power switch based on the long duration current information.

18. A system comprising: A power module, the power module is for an inverter for an electric vehicle, the power module comprising: a power switch including a drain terminal, a source terminal, and a gate terminal; and A point-of-use controller is configured to detect changes in current at the source terminal of the power switching device using the complex impedance of a metal trace connected to the source terminal of the power switching device, and to control a gate control signal to the gate terminal based on the detected change in current.

19. The system of claim 18, wherein the point-of-use controller comprises: a current rate of change detector connected to the metal trace connected to the source terminal of the power switch, the current rate of change detector being configured to detect the change in current; an integrated gate driver computing engine (IGDCE), the IGDCE being connected to the gate terminal, the IGDCE being configured to provide the gate control signal to the gate terminal based on the detected change in current, wherein the IGDCE is configured to receive corresponding instantaneous, short duration and long duration current information based on the detected change in current, and to provide the gate control signal to the gate terminal based on the corresponding instantaneous, short duration and long duration current information.

20. The system of claim 19, wherein the current change rate detector is configured to provide a current change rate overcurrent signal to the IGDCE, and the IGDCE is configured to immediately initiate shutoff of the power switch using a turn-off gate drive curve to provide the gate control signal, and Wherein the point-of-use controller further comprises: an M-bit flash thermometer analog-to-digital converter configured to receive an analog signal from the current rate-of-change detector and provide a digital signal to the IGDCE, a low pass analog filter and a sample and hold circuit configured to receive an analog signal from the current rate of change detector and provide an analog output signal, and A programmable gain controller and an N-bit analog-to-digital converter are configured to receive the analog output signal from the low-pass analog filter and the sample and hold circuit and provide a digital signal to the IGDCE.

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