System and method for adaptive gate driver for inverter for electric vehicle

Abstract

In one embodiment, a system includes: one or more point of use controllers configured to: assert a command turn-on signal to load a first turn-on gate driver profile; controlling a gate driver to start a first phase of an on operation based on the loaded first on gate driver profile; receiving a first power switch signal based on one or more of the detected voltage or the detected current; performing a comparison of the received first power switch signal to a first turn-on threshold; loading a second gate-on driver profile when the comparison indicates that the first power switch signal is greater than the first on threshold; and controlling the gate driver to end the first phase of the turn-on operation and start a second phase of the turn-on operation based on the loaded second turn-on gate driver profile.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. non-provisional patent application No. 18 / 152,951 filed on January 11, 2023, which claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 377,486 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 377,501 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 377,512 filed on September 28, 2022, and U.S. Provisional Patent Application No. 63 / 378,601 filed on October 6, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure relate generally to systems and methods for an adaptive gate driver for an inverter for an electric vehicle, and more particularly to systems and methods for an adaptive gate driver for a power device switch of an inverter for an electric vehicle. Background Art

[0004] Inverters, such as those used to drive motors in electric vehicles, are responsible for, for example, converting high voltage direct current (HVDC) to alternating current (AC) to drive the motor. In an inverter, switching losses in the power device switches can lead to inverter inefficiencies.

[0005] The present disclosure is directed to overcoming one or more of these aforementioned challenges. Summary of the invention

[0006] In some aspects, the technology described herein relates to a system, comprising: one or more point-of-use controllers, the one or more point-of-use controllers being configured to: assert a command turn-on signal to load a first turn-on gate driver profile; control a gate driver for a power switching device for an inverter based on the loaded first turn-on gate driver profile to start a first phase of a turn-on operation of the power switching device, wherein the first phase of the turn-on operation of the power switching device increases a gate signal of the gate driver from a first turn-on value to a second turn-on value, the first turn-on value corresponding to a fully turned-off state of the power switching device, the second turn-on value being less than the fully turned-on value, and the fully turned-on value corresponding to a fully turned-on state of the power switching device ; receiving a first power switching element signal based on one or more of a detected voltage or a detected current of the power switching element; performing a comparison of the received first power switching element signal with a first turn-on threshold; loading a second gate turn-on driver distribution when the comparison indicates that the first power switching element signal is greater than the first turn-on threshold; and controlling a gate driver based on the loaded second turn-on gate driver distribution to end a first phase of the turn-on operation of the power switching element and start a second phase of the turn-on operation of the power switching element, wherein the second phase of the turn-on operation of the power switching element increases a gate signal of the gate driver from a second turn-on value to a third turn-on value, the third turn-on value being greater than the second turn-on value and less than a fully turn-on value.

[0007] In some aspects, the technology described herein relates to a system wherein the one or more point-of-use controllers are further configured to: measure an elapsed time from the beginning of a second phase of a turn-on operation of a power switching device until the end of the second phase of the turn-on operation; and assert a fault when the elapsed time is longer than a second turn-on gate driver distribution time.

[0008] In some aspects, the technology described herein relates to a system wherein the one or more point-of-use controllers are further configured to: receive a second power switching element signal based on one or more of a detected voltage or a detected current of the power switching element; perform a comparison of the received second power switching element signal with a second turn-on threshold, wherein the second turn-on threshold is greater than the first turn-on threshold; load a third gate turn-on driver distribution when the comparison indicates that the second power switching element signal is greater than the second turn-on threshold; and control a gate driver based on the loaded third turn-on gate driver distribution to end the second phase of the turn-on operation of the power switching element and start the third phase of the turn-on operation of the power switching element, wherein the third phase of the turn-on operation of the power switching element increases the gate signal of the gate driver from a third turn-on value to a fourth turn-on value, the fourth turn-on value being greater than the third turn-on value and less than the full turn-on value.

[0009] In some aspects, the technology described herein relates to a system wherein the one or more point-of-use controllers are further configured to: measure an elapsed time from the start of a third phase of a turn-on operation of a power switching device until the end of the third phase of the turn-on operation; and assert a fault when the elapsed time is shorter or longer than a third turn-on gate driver distribution time.

[0010] In some aspects, the technology described herein relates to a system wherein the one or more point-of-use controllers are further configured to: receive a third power switching element signal based on one or more of a detected voltage or a detected current of the power switching element; perform a comparison of the received third power switching element signal with a third turn-on threshold, wherein the third turn-on threshold is greater than the second turn-on threshold; when the comparison indicates that the third power switching element signal is greater than the third turn-on threshold, load a fourth gate turn-on driver distribution; and control a gate driver based on the loaded fourth turn-on gate driver distribution to end a third phase of the turn-on operation of the power switching element and start a fourth phase of the turn-on operation of the power switching element, a fully turn-on value, wherein the fourth phase of the turn-on operation of the power switching element increases the gate signal of the gate driver from the fourth turn-on value to the fully turn-on value, and the fully turn-on value corresponds to a fully turn-on state of the power switching element.

[0011] In some aspects, the technology described herein relates to a system, comprising: one or more point-of-use controllers, the one or more point-of-use controllers being configured to: assert a command shutdown signal to load a first shutdown gate driver profile; control a gate driver for a power switching device for an inverter based on the loaded first shutdown gate driver profile to start a first phase of a shutdown operation of the power switching device, wherein the first phase of the shutdown operation of the power switching device reduces a gate signal of the gate driver from a first shutdown value to a second shutdown value, the first shutdown value corresponding to a fully turned-on state of the power switching device, the second shutdown value being greater than the fully turned-off value, and the fully turned-off value corresponding to a fully turned-off state of the power switching device ; receiving a first power switching device signal based on one or more of a detected voltage or a detected current of the power switching device; performing a comparison of the received first power switching device signal with a first shutdown threshold; loading a second gate shutdown driver distribution when the comparison indicates that the first power switching device signal is less than the first shutdown threshold; and controlling a gate driver based on the loaded second shutdown gate driver distribution to end a first phase of a shutdown operation of the power switching device and start a second phase of a shutdown operation of the power switching device, wherein the second phase of the shutdown operation of the power switching device reduces a gate signal of the gate driver from a second shutdown value to a third shutdown value, the third shutdown value being less than the second shutdown value and greater than a full shutdown value.

[0012] In some aspects, the technology described herein relates to a system wherein the one or more point-of-use controllers are further configured to: measure an elapsed time from the beginning of a second phase of a shutdown operation of a power switching device until the end of the second phase of the shutdown operation; and assert a fault when the elapsed time is shorter or longer than a second shutdown gate driver distribution time.

[0013] In some aspects, the technology described herein relates to a system wherein the one or more point-of-use controllers are further configured to: receive a second power switching element signal based on one or more of a detected voltage or a detected current of the power switching element; perform a comparison of the received second power switching element signal with a second shutdown threshold, wherein the second shutdown threshold is less than the first shutdown threshold; load a third gate shutdown driver distribution when the comparison indicates that the second power switching element signal is less than the second shutdown threshold; and control a gate driver based on the loaded third shutdown gate driver distribution to end a second phase of a shutdown operation of the power switching element and start a third phase of a shutdown operation of the power switching element, wherein the third phase of the shutdown operation of the power switching element reduces a gate signal of the gate driver from a third shutdown value to a fourth shutdown value, the fourth shutdown value being less than the third shutdown value and greater than a full shutdown value.

[0014] In some aspects, the technology described herein relates to a system wherein the one or more point-of-use controllers are further configured to: measure an elapsed time from the start of a third phase of a shutdown operation of a power switching device until the end of the third phase of the shutdown operation; and assert a fault when the elapsed time is shorter or longer than a third shutdown gate driver distribution time.

[0015] In some aspects, the technology described herein relates to a system wherein the one or more point-of-use controllers are further configured to: receive a third power switching element signal based on one or more of a detected voltage or a detected current of the power switching element; perform a comparison of the received third power switching element signal with a third shutdown threshold, wherein the third shutdown threshold is less than the second shutdown threshold; when the comparison indicates that the third power switching element signal is less than the third shutdown threshold, load a fourth gate shutdown driver distribution; and control a gate driver based on the loaded fourth shutdown gate driver distribution to end a third phase of a shutdown operation of the power switching element and start a fourth phase of a shutdown operation of the power switching element, a full shutdown value, wherein the fourth phase of the shutdown operation of the power switching element reduces the gate signal of the gate driver from the fourth shutdown value to a full shutdown value, and the full shutdown value corresponds to a full shutdown state of the power switching element.

[0016] In some aspects, the technology described herein relates to a system comprising one or more point-of-use controllers, the one or more point-of-use controllers comprising: a gate-to-source amplifier configured to be connected to a power switch to measure a gate-to-source voltage of the power switch; a digital-to-analog converter configured to receive a digital threshold and output an analog threshold signal corresponding to the digital threshold; a threshold amplifier configured to receive the gate-to-source voltage and the analog threshold signal, and assert a comparison signal to a high state when the gate-to-source voltage is higher than the analog threshold signal; a logic AND gate configured to receive the comparison signal and an enable signal, and assert a load signal to a high state when both the comparison signal and the enable signal are in a high state; and a load register configured to load a gate driver distribution when the load signal is asserted to a high state, wherein the operation of the power switch is based on the gate driver distribution in the load register.

[0017] In some aspects, the technology described herein relates to a system further comprising: a gate driver configured to be connected to a power switch to operate the power switch; and one or more controllers configured to operate the gate driver based on a gate driver distribution in a load register.

[0018] In some aspects, the technology described herein relates to a system, wherein a gate driver includes: a first on-resistor, the first on-resistor connected in series with a first on-resistor switch; a second on-resistor, the second on-resistor connected in series with a second on-resistor switch, wherein the first on-resistor and the first on-resistor switch are connected in parallel with the second on-resistor and the second on-resistor switch; a first off-resistor, the first off-resistor connected in series with the first off-resistor switch; a second off-resistor, the second off-resistor connected in series with the second off-resistor switch, wherein the first A turn-off resistor and a first turn-off resistor switch are connected in parallel with a second turn-off resistor and a second turn-off resistor switch; a first clamp-on switch; and a first clamp-off switch; and wherein the one or more controllers are configured to operate each of the first turn-on resistor switch, the second turn-on resistor switch, the first turn-off resistor switch, the second turn-off resistor switch, the first clamp-on switch, and the first clamp-off switch of the gate driver to change the voltage applied by the gate driver to the gate terminal of the power switch based on the gate driver distribution in the loading register.

[0019] In some aspects, the technology described herein relates to a system wherein a first on resistor has a resistance value different from a second on resistor and wherein a first off resistor has a resistance value different from a second off resistor.

[0020] In some aspects, the technology described herein relates to a system in which a gate driver includes: a first on-current source, which is connected in series with a first on-current switch; a second on-current source, which is connected in series with the second on-current switch, wherein the first on-current source and the first on-current switch are connected in parallel with the second on-current source and the second on-current switch; a first off-current sink, which is connected in series with the first off-current switch; and a second off-current sink, which is connected in series with the second off-current switch, wherein the first off-current sink and the first off-current switch are connected in parallel with the second off-current sink and the second off-current switch; and wherein the one or more controllers are configured to operate each of the first on-current switch, the second on-current switch, the first off-current switch, and the second off-current switch of the gate driver to change the voltage applied by the gate driver to the gate terminal of the power switch based on the gate driver distribution in the load register.

[0021] In some aspects, the techniques described herein relate to a system in which a current value of a first on current source is different from a current value of a second on current source, and in which a current value of a first off current sink is different from a current value of a second off current sink.

[0022] In some aspects, the technology described herein relates to a system in which a gate driver includes: a first on-resistor, the first on-resistor being connected in series with a first on-resistor switch; a second on-resistor, the second on-resistor being connected in series with a second on-resistor switch, wherein the first on-resistor and the first on-resistor switch are connected in parallel with the second on-resistor and the second on-resistor switch; a first off-resistor, the first off-resistor being connected in series with the first off-resistor switch; a second off-resistor, the second off-resistor being connected in series with the second off-resistor switch, wherein the first off-resistor and the first off-resistor switch are connected in parallel with the second off-resistor and the second off-resistor switch; a first on-current source, the first on-current source being connected in series with the first on-current switch and in parallel with the second on-resistor and the second on-resistor switch; a second on-current source, the second on-current source being connected in series with the second on-current switch, wherein A first on-current source and a first on-current switch are connected in parallel with a second on-current source and a second on-current switch; a first off-current sink, the first off-current sink is connected in series with the first off-current switch and in parallel with a second off resistor and a second off resistor switch; and a second off-current sink, the second off-current sink is connected in series with the second off-current switch, wherein the first off-current sink and the first off-current switch are connected in parallel with the second off-current sink and the second off-current switch; and wherein the one or more controllers are configured to operate each of the first on-resistor switch, the second on-resistor switch, the first off-resistor switch, the second off-resistor switch, the first on-current switch, the second on-current switch, the first off-current switch, and the second off-current switch of the gate driver to change the voltage applied by the gate driver to the gate terminal of the power switch based on the gate driver distribution in the loading register.

[0023] In some aspects, the techniques described herein relate to a system in which a gate driver profile is determined based on one or more of intrinsic characteristics of a power switch, load current slope and amplitude values, high voltage battery amplitude, or operating temperature of the power switch.

[0024] In some aspects, the technology described herein relates to a system further comprising: an inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter includes the one or more point-of-use controllers.

[0025] In some aspects, the technology described herein relates to a system that further includes a battery configured to supply DC power to an inverter and a motor configured to receive AC power from the inverter to drive the motor.

[0026] Other objects and advantages of the disclosed embodiments will be described in part in the following description, and in part will be obvious from the description, or can be understood by practicing the disclosed embodiments. The objects and advantages of the disclosed embodiments will be realized and achieved by means of the elements and combinations particularly pointed out in the appended claims.

[0027] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosed embodiments, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various exemplary embodiments and, together with the description, serve to explain the principles of the disclosed embodiments.

[0029] Figure 1 An exemplary system infrastructure for a vehicle including a combined inverter and converter is depicted according to one or more embodiments.

[0030] Figure 2 Depicted is a method for providing a point-of-use switching controller according to one or more embodiments. Figure 1 An exemplary system infrastructure of a combined inverter and converter.

[0031] Figure 3 Describes a method for Figure 2 An exemplary system infrastructure for a controller of FIG.

[0032] Figure 4 Describes a method for Figure 2 An exemplary system infrastructure for a point-of-use switching controller.

[0033] Figure 5 Describes a method for Figure 4 An exemplary system infrastructure of an upper power module.

[0034] Figure 6 An exemplary system for a current-based adaptive gate driver for a power device switch according to one or more embodiments is depicted.

[0035] Figure 7 An exemplary system for a resistor-based adaptive gate driver for a power device switch according to one or more embodiments is depicted.

[0036] Figure 8 An exemplary system for a resistor-based adaptive gate driver with sensing and control for power device switches according to one or more embodiments is depicted.

[0037] Fig. 9 Depicted is an exemplary graph of correction factors for an adaptive gate driver for a power device switch according to one or more embodiments.

[0038] Fig.10 An exemplary system for a current / resistor hybrid adaptive gate driver for a power device switch according to one or more embodiments is depicted.

[0039] Fig.11 An exemplary system for a correction controller for an adaptive gate driver for a power device switch according to one or more embodiments is depicted.

[0040] Fig.12 An exemplary method for operating an adaptive gate driver for a power device switch according to one or more embodiments is depicted. DETAILED DESCRIPTION

[0041] Both the foregoing general description and the following detailed description are exemplary and explanatory only and do not constrain the claimed features. As used herein, the terms "comprises," "comprising," "has," "having," "includes," "including," or other variations thereof are intended to encompass non-exclusive inclusions such that a process, method, article, or device that includes a series of elements includes not only those elements, but may also include other elements that are not explicitly listed or inherent to such process, method, article, or device. In the present disclosure, unless otherwise stated, relative terms (such as, for example, "about," "substantially," and "approximately") are used to indicate possible ±10% variations in the stated values. In the present disclosure, unless otherwise stated, any numerical value may include possible ±10% variations in the stated values.

[0042] The terms used below may be interpreted in their broadest reasonable manner, although they are being used in conjunction with a detailed description of certain specific examples of the present disclosure. Indeed, certain terms may even be emphasized below; however, any term intended to be interpreted in any constrained manner will be explicitly and specifically defined as such in this detailed description. For example, in the context of the present disclosure, a switching device may be described as a switching element or device, but may refer to any device for controlling power flow in a circuit. For example, a switching element may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT) or a relay, or any combination thereof, but is not limited thereto.

[0043] Various embodiments of the present disclosure relate generally to systems and methods for an adaptive gate driver for an inverter for an electric vehicle, and more particularly to systems and methods for an adaptive gate driver for a power device switch of an inverter for an electric vehicle.

[0044] Inverters (such as those used to drive motors in electric vehicles) are responsible for converting high voltage direct current (HVDC) into alternating current (AC) to drive the motor. A three-phase inverter may include a bridge having six power device switches (e.g., power transistors such as IGBTs or MOSFETs) that are controlled by pulse width modulation (PWM) signals generated by a controller. The inverter may include three-phase switches to control phase voltages, upper and lower gate drivers to control the switches, a PWM controller, and glue logic between the PWM controller and the gate driver. The PWM controller may generate signals to define the expected state of the system. The gate driver may send signals from the PWM controller to the phase switches. The phase switches may drive the phase voltages. The inverter may include an isolation barrier between a low voltage plane and a high voltage plane. The signal may be passed from the PWM controller to the phase switch by passing through an isolation barrier, which may employ optical, converter-based, or capacitor-based isolation. The PWM signal may be distorted when passing through the glue logic, which may include resistive, capacitive, or other types of filtering. Due to the electrical isolation barrier and other delays within the gate driver, the PWM signal may be distorted when passing through the gate driver. The PWM signal may be distorted when the signal is processed by the phase switching device via the gate driver output.

[0045] Gate drivers withstand common-mode transients that occur during field effect transistor (FET) switching and when one side of a floating high voltage terminal is shorted to ground or subjected to electrostatic discharge. These voltage transients can cause fast edges that can form common-mode current bursts through electrical isolation. Gate drivers may need to demonstrate common-mode transient immunity (CMTI) in order to be effective and safe.

[0046] The gate driver may have a high voltage domain in common with the voltage plane of the associated FET. Further, the high voltage plane may be supplied by a flyback converter, which may be isolated from the low voltage plane by a transformer. The high voltage domain power supply may be used to provide power to such a circuit that sources and sinks gate current to drive the FET and can detect FET faults, thereby acting on the faults and / or transmitting the faults to the low voltage domain. The gate driver may include an electrical channel dedicated to FET commands, and one or more bidirectional or unidirectional electrical channels dedicated to FET communications.

[0047] High current switching transients can form strong electromagnetic (EM) fields that can couple into nearby metal traces. The magnitude and frequency of the coupled current can depend on the layout of the FET packaging solution and the direction and length of the metal traces between the FET and the control integrated circuit (IC). For example, a typical value for the coupled current can be up to 1A at an AC frequency of up to 100MHz. Typically, within the circuit, the gate driver IC can be placed far enough away from the FET so that the high EM field is not directly coupled into the internal metal traces within the gate driver IC. The gate driver is placed at a distance from the EM field so that the induced current within the circuit is below the level that will cause the gate driver to malfunction, or a metal shield is placed between the gate driver and the source of the EM field to protect the gate driver circuit. The output terminals of the gate driver connected to the FET are exposed to the EM field at a point where the output terminals are no longer covered by the shield. The gate driver switches large currents (e.g., such as 5A to 15A) through these exposed terminals. The large currents switched are usually larger in magnitude than the EM induced current. The gate driver can overdrive the induced current to maintain control of the FET. The gate driver and the high side of the FET may share a common ground and gate control signal trace, both of which may be susceptible to coupled currents.

[0048] The gate driver can turn on low resistance switches to source and sink gate current. Sometimes a series resistor can be added to limit the gate current. The switched gate current can be greater than the coupling current in order to maintain control of their respective FETs.

[0049] The gate driver may be able to sense the FET operating voltage or current in order to provide feedback and react to faults. An overcurrent fault may typically be detected by sensing the FET drain to source voltage and comparing the sensed voltage to a reference value. The sensed voltage may be heavily filtered to reject coupled currents. Filtering may slow the response to a fault condition, causing a delay in response. For example, the rate of current increase due to a low resistance short may reach damaging levels before being detected by a heavily filtered drain to source voltage detection strategy. The resulting short may damage the FET or the vehicle before being detected and cut off.

[0050] According to one or more embodiments, a FET driver circuit may provide fast overcurrent detection by shunt current sensing, or by diverting a portion of the load current through a parallel FET that may have a current sensing circuit. Utilizing either strategy may require a "point of use IC" in which the sensing circuit is very close to the FET. Even if the point of use IC and the remote controller are resistant to EM fields, the communication between the point of use IC and the remote controller is still susceptible to induced currents. Point of use ICs have been implemented in low EM field applications, such as smart FETs for automotive applications. However, point of use ICs have not yet been used in high EM field applications. High EM fields can be fields that (i) induce a current within the IC that exceeds the operating current of the IC and causes a malfunction, or (ii) induce a differential voltage within the IC that exceeds the operating differential voltage and causes a malfunction. High EM fields can be, for example, fields greater than about 10A or about 100V.

[0051] As described above, for the phase power drive circuit, some circuits may include a gate driver to drive the gate terminal of the power switch. When the upper phase power switch and the lower phase power switch are of the same type, the on resistors of the upper phase power switch and the lower phase power switch are generally selected to have low and equal resistance values, and the off resistors of the upper phase power switch and the lower phase power switch also have low and equal resistance values. The on resistor generally has a resistance value different from the off resistor. In order to avoid through currents in the upper phase power switch and the lower phase power switch, some circuits include dead time between the upper phase power switch turn-off and the lower phase power switch turn-on time and between the lower phase power switch turn-off and the upper phase power switch turn-on time. The switching loss of the power switch is directly determined by the value of the above-mentioned gate resistor and the total capacitance at the gate terminal of the power switch.

[0052] The values ​​of these series gate resistors are selected so that the turn-on gate voltage and drain current amplitude ringing and the turn-off drain-to-source voltage overshoot and ringing amplitude do not exceed the maximum allowed values ​​under worst-case conditions. Worst-case conditions may include inherent parameters of the power switching device, operating temperature, phase (load) current amplitude / slope, battery voltage magnitude, and parameter drift during the service life of the power switching device due to component aging. Any violation of the compliance voltage and current values ​​may damage the health of the power switching device and may cause permanent damage to the power switching device. Therefore, the value of the gate resistor is increased to a suitable value higher than the optimal resistance value so that the power switching device does not experience any inappropriate voltage and / or current stress. However, selecting a higher value of gate resistance will significantly increase the switching loss of the power switching device, resulting in higher heat sink and overall system costs.

[0053] One or more embodiments may provide a gate driver system that significantly reduces switching power losses while protecting the power switch in terms of gate voltage and drain current ringing amplitude and drain to source voltage overshoot and ringing amplitude. One or more embodiments may provide a gate driver system that calculates an optimal gate drive on and off voltage profile that incorporates the inherent characteristics of the power device, load current slope and amplitude, high voltage battery amplitude, and operating temperature. One or more embodiments may provide a gate driver system that continuously measures the threshold voltage drift of the power device over time, which can be used to calculate the optimal gate drive on and off voltage profile, and for detecting open gate terminal faults. One or more embodiments may provide a gate driver system that uses a hybrid variable resistor driver and a fast transition switching mode circuit, characterized by a very low drive impedance to minimize the switch on and off current and / or voltage ringing while shortening the transition time to the full on time window. One or more embodiments may provide a gate driver system that continuously detects hard and / or soft short and / or open faults throughout the switching on, off, and conduction cycles by continuously checking the gate voltage amplitude and the rate of change of the gate voltage over time for several threshold voltages and pre-programmed time windows. One or more embodiments may provide a gate driver system that calculates a special turn-off profile to ensure safe turn-off of the power switch for the turn-on to hard short case.

[0054] Figure 1 An exemplary system infrastructure for a vehicle including a combined inverter and converter according to one or more embodiments is depicted. In the context of the present disclosure, the combined inverter and converter may be referred to as an inverter. Figure 1 As shown, the electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include a component for receiving electric power from an external source and outputting electric power to charge the battery 195 of the electric vehicle 100. For example, the inverter 110 may convert DC power from the battery 195 in the electric vehicle 100 into AC power to drive the motor 190 of the electric vehicle 100, but the embodiment is not limited thereto. For example, the inverter 110 may be bidirectional and may convert DC power into AC power, or convert AC power into DC power, such as during regenerative braking. The inverter 110 may be a three-phase inverter, a single-phase inverter, or a multi-phase inverter.

[0055] Figure 2 Depicted is a method for providing a point-of-use switching controller according to one or more embodiments. Figure 1The electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include an inverter controller 300 ( Figure 3 14). The inverter 110 may include a low voltage upper phase controller 120 separated from a high voltage upper phase controller 130 by an electrical isolator 150, and an upper phase power module 140. The upper phase power module 140 may include a point-of-use upper phase controller 142 and an upper phase switch 144. The inverter 110 may include a low voltage lower phase controller 125 separated from a high voltage lower phase controller 135 by an electrical isolator 150, and a lower phase power module 145. The lower phase power module 145 may include a point-of-use lower phase controller 146 and a lower phase switch 148. The upper phase switch 144 and the lower phase switch 148 may be connected to a motor 190 and a battery 195. The electrical isolator 150 may be one or more of optical, converter-based, or capacitor-based isolation. For example, the electrical isolator 150 may be one or more capacitors having a value from about 20 fF to about 100 fF, having a breakdown voltage from about 6 kV to about 12 kV. The electrical isolator 150 may include a pair of capacitors, wherein one capacitor of the pair carries a complementary (180 degree phase shifted) data signal from the other capacitor of the pair to form a differential signal that is rejected for common mode noise. The electrical isolator 150 may include more than one capacitor in series. The electrical isolator 150 may include one capacitor located on a first IC, or may include a first capacitor located on a first IC and a second capacitor located on a second IC that communicates with the first IC.

[0056] The inverter 110 may include a low voltage region (e.g., where the voltage is typically less than 5V) and a high voltage region (e.g., where the voltage may exceed 500V). The low voltage region may be separated from the high voltage region by an electrical isolator 150. The inverter controller 300 may be in the low voltage region of the inverter 110, and may send a signal to and receive a signal from the low voltage upper phase controller 120. The low voltage upper phase controller 120 may be in the low voltage region of the inverter 110, and may send a signal to and receive a signal from the high voltage upper phase controller 130. The low voltage upper phase controller 120 may send a signal to and receive a signal from the low voltage lower phase controller 125. The high voltage upper phase controller 130 may be in the high voltage region of the inverter 110. Therefore, the signal between the low voltage upper phase controller 120 and the high voltage upper phase controller 130 passes through the electrical isolator 150. The high voltage upper phase controller 130 may send signals to and receive signals from a point-of-use upper phase controller 142 in the upper phase power module 140. The point-of-use upper phase controller 142 may send signals to and receive signals from an upper phase switch 144. The upper phase switch 144 may be connected to a motor 190 and a battery 195. For example, the upper phase switch 144 and the lower phase switch 148 may be used to transfer energy from the motor 190 to the battery 195, from the battery 195 to the motor 190, from an external source to the battery 195, or from the battery 195 to an external source. The lower phase system of the inverter 110 may be similar to the upper phase system described above.

[0057] Figure 3 Describes a method for Figure 2 FIG. 3 is an exemplary system infrastructure of an inverter controller 300 . The inverter controller 300 may include one or more controllers.

[0058] The inverter controller 300 may include a set of instructions that can be executed to cause the inverter controller 300 to perform any one or more of the methods or computer-based functions disclosed herein. The inverter controller 300 may operate as a standalone device, or may be connected to other computer systems or peripheral devices, for example using a network.

[0059] In a networked deployment, the inverter controller 300 can operate in the capacity of a server, or as a client in a server-client user network environment, or as a peer computer system in a peer (or distributed) network environment. The inverter controller 300 can also be implemented as or incorporated into various devices, such as a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile device, a palmtop computer, a laptop computer, a desktop computer, a communication device, a wireless phone, a landline phone, a control system, a camera, a scanner, a fax machine, a printer, a pager, a personal trusted device, a network device, a network router, a switch or bridge, or any other machine capable of executing a set of instructions (sequentially or otherwise) (the set of instructions specifies the actions to be taken by the machine). In a specific implementation, the inverter controller 300 can be implemented using an electronic device that provides voice, video or data communication. Further, although the inverter controller 300 is illustrated as a single system, the term “system” should also be understood to include any collection of systems or subsystems that individually or jointly execute one or more sets of instructions to perform one or more computer functions.

[0060] like Figure 3 As shown, the inverter controller 300 may include a processor 302, such as a central processing unit (CPU), a graphics processing unit (GPU), or both. The processor 302 may be a component in a variety of systems. For example, the processor 302 may be part of a standard inverter. The processor 302 may be one or more general-purpose processors, digital signal processors, application-specific integrated circuits, field programmable gate arrays, servers, networks, digital circuits, analog circuits, combinations thereof, or other devices now known or later developed for analyzing and processing data. The processor 302 may implement a software program, such as a manually generated (i.e., programmed) code.

[0061] The inverter controller 300 may include a memory 304 that can communicate via a bus 308. The memory 304 may be a main memory, a static memory, or a dynamic memory. The memory 304 may include, but is not limited to, computer-readable storage media, such as various types of volatile and non-volatile storage media, including but not limited to random access memory, read-only memory, programmable read-only memory, electrically programmable read-only memory, electrically erasable read-only memory, flash memory, tape or disk, optical media, etc. In one specific implementation, the memory 304 includes a cache or random access memory for the processor 302. In an alternative specific implementation, the memory 304 is separated from the processor 302, such as a cache memory, system memory, or other memory of the processor. The memory 304 may be an external storage device or database for storing data. Examples include a hard drive, a compact disk ("CD"), a digital video disk ("DVD"), a memory card, a memory stick, a floppy disk, a universal serial bus ("USB") storage device, or any other device operable to store data. The memory 304 is operable to store instructions that can be executed by the processor 302. The functions, actions, or tasks illustrated in the figures or described herein may be performed by the processor 302 executing instructions stored in the memory 304. The functions, actions, or tasks are not related to a particular type of instruction set, storage medium, processor, or processing strategy, and may be performed by software, hardware, integrated circuits, firmware, microcode, etc. operating alone or in combination. Likewise, processing strategies may include multi-processing, multi-tasking, parallel processing, etc.

[0062] As shown, the inverter controller 300 may further include a display 310, such as a liquid crystal display (LCD), an organic light emitting diode (OLED), a flat panel display, a solid state display, a cathode ray tube (CRT), a projector, a printer, or other display devices known now or later developed for outputting the determined information. The display 310 may serve as an interface for a user to view the operation of the processor 302, or specifically serve as an interface with the software stored in the memory 304 or in the drive unit 306.

[0063] Additionally or alternatively, the inverter controller 300 may include an input device 312 configured to allow a user to interact with any of the components of the inverter controller 300. The input device 312 may be a numeric keypad, a keyboard or a cursor control device (such as a mouse or a joystick), a touch screen display, a remote control, or any other device operable to interact with the inverter controller 300.

[0064] The inverter controller 300 may also or alternatively include a drive unit 306 implemented as a disk or optical drive. The drive unit 306 may include a computer-readable medium 322 in which one or more sets of instructions 324 (e.g., software) may be embedded. Further, the instructions 324 may embody one or more of the methods or logics described herein. The instructions 324 may reside completely or partially within the memory 304 and / or within the processor 302 during execution by the inverter controller 300. The memory 304 and the processor 302 may also include computer-readable media as described above.

[0065] In some systems, the computer-readable medium 322 includes instructions 324 or receives and executes instructions 324 in response to a propagated signal, so that a device connected to the network 370 can transmit voice, video, audio, images, or any other data through the network 370. Further, the instructions 324 can be transmitted or received through the network 370 and / or using the bus 308 via the communication port or interface 320. The communication port or interface 320 can be part of the processor 302 or can be an independent component. The communication port or interface 320 can be formed in software or can be a physical connector in hardware. The communication port or interface 320 can be configured to connect to the network 370, external media, display 310, or any other component in the inverter controller 300, or a combination thereof. The connection to the network 370 can be a physical connection (such as a wired Ethernet connection) or can be established wirelessly, as described below. Similarly, additional connections to other components of the inverter controller 300 can be physical connections or can be established wirelessly. The network 370 can alternatively be directly connected to the bus 308.

[0066] Although the computer-readable medium 322 is shown as a single medium, the term "computer-readable medium" may include a single medium or multiple media (such as a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" may also include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processor or causing a computer system to perform any one or more of the methods or operations disclosed herein. The computer-readable medium 322 may be non-transitory and may be tangible.

[0067] Computer readable medium 322 may include solid-state memory, such as a memory card or other package that accommodates one or more non-volatile read-only memories. Computer readable medium 322 may be random access memory or other volatile rewritable memory. Additionally or alternatively, computer readable medium 322 may include magneto-optical or optical media, such as a disk or tape or other storage device for capturing carrier signals (such as signals transmitted through a transmission medium). Digital file attachments to emails or other self-contained information archives or archive sets may be considered distribution media as tangible storage media. Therefore, the present disclosure is considered to include any one or more of computer-readable media or distribution media and other equivalents and successor media in which data or instructions may be stored.

[0068] In alternative implementations, dedicated hardware implementations (such as application specific integrated circuits, programmable logic arrays, and other hardware devices) may be constructed to implement one or more of the methods described herein. Applications that may include the apparatus and systems of various implementations may broadly include a variety of electronic and computer systems. One or more implementations described herein may use two or more specific interconnected hardware modules or devices with associated control and data signals that may be transmitted between and through the modules or as part of an application specific integrated circuit to implement functionality. Thus, the present system encompasses software, firmware, and hardware implementations.

[0069] The inverter controller 300 may be connected to a network 370. The network 370 may define one or more networks, including wired or wireless networks. The wireless network may be a cellular telephone network, an 802.11, 802.16, 802.20, or WiMAX network. Further, such networks may include public networks (such as the Internet), private networks (such as intranets), or combinations thereof and may utilize a variety of networking protocols that are now available or later developed, including but not limited to TCP / IP-based networking protocols. The network 370 may include a wide area network (WAN) (such as the Internet), a local area network (LAN), a campus area network, a metropolitan area network, a direct connection (such as through a universal serial bus (USB) port), or any other network that allows data communication. The network 370 may be configured to couple one computing device to another computing device to enable data communication between devices. The network 370 may generally be enabled to use any form of machine-readable media to transmit information from one device to another. The network 370 may include a communication method by which information can travel between computing devices. The network 370 may be divided into subnetworks. A subnetwork may allow access to all other components connected to it, or a subnetwork may restrict access between components. Network 370 may be considered a public or private network connection and may include, for example, a virtual private network or encryption or other security mechanisms employed over the public Internet.

[0070] According to various implementations of the present disclosure, the methods described herein may be implemented by a software program that can be executed by a computer system. Further, in an exemplary non-limiting implementation, the implementation may include distributed processing, component or object distributed processing, and parallel processing. Alternatively, a virtual computer system process may be constructed to implement one or more of the methods or functionalities described herein.

[0071] Although this specification describes components and functions that can be implemented in a specific implementation with reference to specific standards and protocols, the present disclosure is not limited to such standards and protocols. For example, standards for Internet and other packet-switched network transmissions (e.g., TCP / IP, UDP / IP, HTML, HTTP) represent examples of the prior art. Such standards are periodically replaced by faster or more efficient equivalents having substantially the same functionality. Therefore, alternative standards and protocols having the same or similar functionality as those disclosed herein are considered equivalents thereof.

[0072] It will be appreciated that, in one embodiment, the operations of the methods discussed are performed by an appropriate processor (or processors) of a processing (i.e., computer) system executing instructions (computer readable code) stored in a storage device. It will also be appreciated that the present disclosure is not limited to any particular implementation or programming technique, and that the present disclosure may be implemented using any suitable technique for implementing the functionality described herein. The present disclosure is not limited to any particular programming language or operating system.

[0073] Figure 4 Describes a method for Figure 2 An exemplary system infrastructure of a point-of-use switching controller. For a three-phase inverter, each of the upper phase and the lower phase may include three phases related to phases A, B, and C. For example, the upper phase power module 140 may include an upper phase power module 140A for upper phase A, an upper phase power module 140B for upper phase B, and an upper phase power module 140C for upper phase C. The upper phase power module 140A may include a point-of-use upper phase A controller 142A and an upper phase A switching element 144A. The upper phase power module 140B may include a point-of-use upper phase B controller 142B and an upper phase B switching element 144B. The upper phase power module 140C may include a point-of-use upper phase C controller 142C and an upper phase C switching element 144C. Each of the upper phase A switching member 144A, the upper phase B switching member 144B, and the upper phase C switching member 144C may be connected to the motor 190 and the battery 195 . Figure 4 Details of the upper phase power module 140 are depicted. Although not shown, the lower phase power module 145 may include a similar structure as the upper phase power module 140 for the lower phases A, B, and C.

[0074] Figure 5 Describes a method for Figure 4 Example system infrastructure for the upper power module. For example, Figure 5 Additional details of upper phase power module 140A are provided. Although not shown, upper phase power module 140B, upper phase power module 140C, and respective lower phase power modules of lower phase power module 145 may include components related to Figure 5 The upper phase power module 140A shown in FIG. 1 is similar in structure to the upper phase power module 140A shown in FIG. 1. In addition, the terms "upper", "lower", "northern", and "southern" as used in this disclosure are used for reference only, do not limit the elements to a particular orientation, and are generally interchangeable throughout the text. For example, the upper phase power module 140 may be referred to as a lower phase power module, a northern phase power module, a southern phase power module, a first phase power module, or a second phase power module.

[0075] The upper phase power module 140A may include a point-of-use upper phase A controller 142A and an upper phase A switch 144A. The upper phase A switch 144A may include one or more sets of switches. Figure 5 As shown, the upper phase A switch 144A may include an upper phase A north switch 144A-N and an upper phase A south switch 144A-S. The point-of-use upper phase A controller 142A may include one or more memories, controllers, or sensors. For example, the point-of-use upper phase A controller 142A may include a communication manager 405, a functional safety controller 410, a test interface and controller 415, a north thermal sensor 420A, a south thermal sensor 420B, a self-test controller 425, a command manager 430, a waveform adjuster 435, a memory 440, a north switch control and diagnostic controller 450N, and a south switch control and diagnostic controller 450S. The point-of-use upper phase A controller 142A may include a controller 405, a functional safety controller 410, a test interface and controller 415, a north thermal sensor 420A, a south thermal sensor 420B, a self-test controller 425, a command manager 430, a waveform adjuster 435, a memory 440, a north switch control and diagnostic controller 450N, and a south switch control and diagnostic controller 450S. Figure 5 More or fewer components than those shown. For example, the point-of-use upper phase A controller 142A may include more or less than two switch controls and diagnostic controllers, and may include more than two thermal sensors.

[0076] The communication manager 405 may control inter-controller communications to and from the point-of-use upper phase A controller 142A and / or may control intra-controller communications between components of the point-of-use upper phase A controller 142A. The functional safety controller 410 may control safety functions of the point-of-use upper phase A controller 142A. For example, the test interface and controller 415 may control test functions of the point-of-use upper phase A controller 142A, such as end-of-line testing in manufacturing. The north thermal sensor 420A may sense the temperature at a first location in the point-of-use upper phase A controller 142A, and the south thermal sensor 420B may sense the temperature at a second location in the point-of-use upper phase A controller 142A. For example, the self-test controller 425 may control self-test functions of the point-of-use upper phase A controller 142A, such as during initialization of the point-of-use upper phase A controller 142A after an inverter 110 power-on event. The command manager 430 may control commands received from the communication manager 405 and issued to the north switch control and diagnostic controller 450N and the south switch control and diagnostic controller 450S. The waveform adjuster 435 may control the waveform timing and shape of the commands received from the communication manager 405 and issued to the north switch control and diagnostic controller 450N and the south switch control and diagnostic controller 450S. The memory 440 may include one or more volatile and non-volatile storage media for the operation of the point-of-use upper phase A controller 142A. The north switch control and diagnostic controller 450N may send one or more signals to the north switch 144A-N to control the operation of the north switch 144A-N, and may receive one or more signals from the north switch 144A-N that provide information about the north switch 144A-N. The south switch control and diagnostic controller 450S may send one or more signals to the south switches 144A-S to control the operation of the south switches 144A-S, and may receive one or more signals from the south switches 144A-S providing information about the south switches 144A-S. As described above, the terms "north" and "south" are used for reference only, and the north switch control and diagnostic controller 450N may send one or more signals to the south switches 144A-S, and the south switch control and diagnostic controller 450S may send one or more signals to the south switches 144A-N.

[0077] Figure 6 An exemplary system for a current-based adaptive gate driver for a power device switch according to one or more embodiments is depicted.

[0078] One or more embodiments may provide a gate driver system to significantly reduce switching power losses while preventing the problems associated with the above-mentioned gate voltage and drain current ringing amplitude and drain-to-source voltage overshoot and ringing amplitude.

[0079] refer to Figure 2 For example, the gate driver system 600 may be a specific implementation of the upper phase power module 140 and the lower phase power module 145. Figure 6 As shown, the upper phase power switch 644 (M2) can be connected to the positive terminal 695P of the battery 195 and the phase terminal 690A (e.g., phase A) of the motor 190, and the lower phase power switch 648 (M1) can be connected to the negative terminal 695N of the battery 195 and the phase terminal 690A of the motor 190. For example, the upper phase power switch 644 can be a specific implementation of one of the upper phase switches 144 (e.g., the upper phase A switch 144A), and the lower phase power switch 648 can be a specific implementation of one of the lower phase switches 148.

[0080] The gate terminal of the lower phase power switch 648 may be driven with a varying source current driver 615 and a varying sink gate current driver 616 based on the lower phase drive signal 635. Respectively, Isrc1 to Isrcn may be source current drivers 615 having varying values ​​during an on period, and Isnk1 to Isnkn may be sink current drivers 616 having varying values ​​during an off period of the lower phase power switch 648. The source current driver 615 and the sink gate current driver 616 may be dynamically selected by operation of the respective φ switches based on respective on and off control signals. The source current driver 615 and the sink gate current driver 616 may be selected using the sensing and control methods presented below to drive the gate terminal of the lower phase power switch 648 to minimize switching losses based on one or more of inherent parameters of the lower phase power switch 648, parameter drift during the service life of the lower phase power switch 648, or changes in operating temperature of the lower phase power switch 648.

[0081] like Figure 6As shown, both the lower phase power switch 648 and the upper phase power switch 644 may have independent gate driver systems. More specifically, the gate terminal of the upper phase power switch 644 may be driven using a varying source current driver 610 and a varying gate current driver 611 based on the upper phase drive signal 630. The upper phase power switch 644 may include a source current driver 610 having a varying value during an on period, and a sink current driver 611 having a varying value during an off period of the upper phase power switch 644. The source current driver 610 and the gate current driver 611 may be dynamically selected by the operation of the corresponding φ switch based on the corresponding on and off control signals. The source current driver 610 and the sink gate current driver 611 can be selected using the sensing and control methods presented below to drive the gate terminal of the upper phase power switch element 644 to minimize switching losses based on one or more of inherent parameters of the upper phase power switch element 644, parameter drift during the service life of the upper phase power switch element 644, or changes in the operating temperature of the upper phase power switch element 644.

[0082] Figure 7 An exemplary system for a resistor-based adaptive gate driver for a power device switch according to one or more embodiments is depicted.

[0083] like Figure 7 As shown, the gate driver system 700 may include turn-on and turn-off programmable distributed resistors in addition to or in place of the current sourcing and sinking drivers of the gate driver system 600. The gate driver system 700 may provide continuous low impedance to the gate terminals of the upper phase power switch 644 and the lower phase power switch 648 during respective turn-on and turn-off events, and may provide maximum immunity to high intensity electromagnetic disruptive fields.

[0084] The gate terminal of the lower phase power switch 648 may be driven with a varying on resistor 715 and a varying off resistor 716 based on the lower phase drive signal 635. Respectively, Ron1 to Ronm may be on resistors 715 having varying values ​​during an on period, and Roff1 to Roffm may be off resistors 716 having varying values ​​during an off period of the lower phase power switch 648. The on resistor 715 and the off resistor 716 may be dynamically selected by operation of the corresponding φ switch based on corresponding on and off control signals. The on resistor 715 and the off resistor 716 may be selected using the sensing and control methods presented below to drive the gate terminal of the lower phase power switch 648 to minimize switching losses based on one or more of an inherent parameter of the lower phase power switch 648, a parameter drift during the service life of the lower phase power switch 648, or a change in the operating temperature of the lower phase power switch 648.

[0085] like Figure 7 As shown, both the lower phase power switch 648 and the upper phase power switch 644 may have independent gate driver systems. More specifically, the gate terminal of the lower phase power switch 648 may be driven with a varying on resistor 710 and a varying off resistor 711 based on the upper phase drive signal 635. Respectively, Ron1 to Ronm may be on resistors 710 having varying values ​​during an on period, and Roff1 to Roffm may be off resistors 711 having varying values ​​during an off period of the upper phase power switch 644. The on resistor 710 and the off resistor 711 may be dynamically selected by operation of the corresponding φ switch based on the corresponding on and off control signals. The sensing and control methods presented below can be used to select the on resistor 710 and the off resistor 711 to drive the gate terminal of the upper phase power switch element 644 to minimize switching losses based on one or more of inherent parameters of the upper phase power switch element 644, parameter drift during the service life of the upper phase power switch element 644, or changes in the operating temperature of the upper phase power switch element 644.

[0086] like Figure 7As shown, the gate driver system 700 may also include an upper phase clamp switch 712 (SU and SL) and a lower phase clamp switch 717 (SU and SL). The upper phase clamp switch 712 and the lower phase clamp switch 717 may play a key role in reducing the switching losses of the corresponding upper phase power switch 644 and the lower phase power switch 648. The Rdson values ​​of the clamp switches 712 and 717 are selected to be many times lower than the corresponding minimum gate drive series resistance. A further description of the operation of the upper phase clamp switch 712 and the lower phase clamp switch 717 will be provided below.

[0087] Figure 8 An exemplary system for a resistor-based adaptive gate driver 800 with sensing and control for power device switches according to one or more embodiments is depicted. Figure 8 As shown, differential amplifiers G1, G2, and G3 provide three different output signals to differential analog comparators A1, A2, A3, A4, and A5, which provide different output signals to AN1, AN2, AN3, and AN4 logic AND gates. The second inputs of the AN1, AN2, AN3, and AN4 logic AND gates are controlled by a set of logic signals named "enable_gate_drive" signals to load current distribution signals into the load register, for example, to successively activate each of the state 0, state 1, state 2, state 3, and state 4 current distributions of Isrc1 through the Isrcn gate pull current (for example, using the on resistor 715 and the lower phase clamp switch 717 as shown, or using the Figure 6 , Figure 7 and Fig.10 The gate driver configurations (any of the gate driver configurations shown) are used to turn on the lower phase power switch 648 with a uniquely calculated gate turn-on profile. This current profile signal achieves minimal turn-on switching power loss while accurately controlling gate voltage ringing, drain current ringing, and drain-to-source voltage overshoot and ringing to protect the lower phase power switch 648 from any undue current and voltage stress. Figure 8 An adaptive gate driver for the lower phase power switch 648 is depicted, but the adaptive gate driver for the upper phase power switch 644 may be similar to the adaptive gate driver for the lower phase power switch 648 .

[0088] The switch-on process may include various operations as described below.

[0089] The command-on signal 851 is first asserted to enable the "enable_gate_drive" signal and load the state 0 programming gate current / drive profile. This facilitates connecting several resistors (e.g., turn-on resistors 715) and / or several current source units (e.g., pull current drivers 615) to the gate terminal of the lower phase power switch 648 to initiate the gate voltage rise of the lower phase power switch 648. The G2 amplifier can continuously monitor the gate-to-source voltage of the lower phase power switch 648.

[0090] The output of the G2 amplifier may then be fed to a first input of each of comparators A2, A3, and A4, each of which has a second input fed by the output of three N-bit digital-to-analog converters (DACs) including DAC_VTH0_L, DAC_VTH1_L, and DAC_VTH2_L. The outputs of these DACs may be programmed to set any desired threshold voltage to the inputs of the A2, A3, and A4 comparators, which may each use the respective output of the DAC to perform comparisons. The threshold voltage of DAC_VTH2_L may be programmed to be higher than the threshold voltage of DAC_VTH1_L, which may be higher than the threshold voltage of DAC_VTH0_L. These threshold voltages may need to be set before initiating the next gate drive signal to turn on the current profile.

[0091] Once the output of the G2 amplifier crosses the programmed threshold voltage set by the output of DAC_VTH0_L, the A4 output signal V_comp_0 is asserted high to AN4, and the programmed gate current / resistor distribution of I_distribution_state 1 (stored values ​​determined using the electrical model of the lower phase power switch 648, the operating temperature, and the last cycle load current value) is then loaded to direct the gate voltage to rise further according to I_distribution_state 1 (whose source duration is set to the pre-calculated time value t1). The value "t1" can be the calculated duration of I_distribution_state 1 and can be used to detect short circuit or open circuit faults. If the monitored time is significantly shorter than the calculated value of t1, an open circuit fault exists. If the monitored time is significantly longer than the calculated value of t1, a short circuit fault exists. The equation for calculating t1 is: t1 = [(Cgs + Cgd (at high values ​​of Vds). (I load + Irmm) / (gfs. I_distribution_state 1)]. TCF. ICF. Here, gfs is the transconductance, Cgs and Cgd are the gate-to-source and gate-to-drain capacitances of the lower phase power switch 648, I load is the load current flowing through the lower phase power switch 648, Irmm is the reverse recovery peak current of the body diode of the lower phase power switch 648, TCF is the temperature correction factor, and ICF is the calculated load current correction factor. The value of t1 can also be pre-calculated and stored for I_distribution_state 1 turn-on timing and qualification. Before t1 expires, first The state of the A3 output signal V_comp_1 is checked to ensure that the logic state is high. If the logic state of the A3 output signal V_comp_1 is not high, a fault has occurred. Alternatively or in addition, a fault can be asserted when the elapsed time from when I_distribution_state 1 has been loaded is longer than t1. For the case of very low package stray values, a corresponding t1 timing value can be calculated for monitoring the t1 task mode timing. If the monitored t1 timing exceeds the calculated timing, it indicates that a fault may have occurred. For this case, once the state of the A3 output signal V_comp_1 becomes asserted to be high to AN3, the distribution of I_distribution_state 2 is loaded, which causes the gate voltage to rise further.

[0092] Next, after the output of the G2 amplifier exceeds the programmed threshold voltage set by the output of DAC_VTH1_L, the A3 output signal V_comp_1 is asserted high to AN3 and the programmed gate current / resistor distribution of I_distribution_state2 (stored value) is loaded to direct the gate voltage to rise according to the I_distribution_state2 value (whose source duration is set to the pre-calculated time value t2). The value "t2" can be the calculated duration of I_distribution_state2 and can be used to detect a short or open fault. If the monitored time is significantly shorter than the calculated value of t1, an open fault exists. If the monitored time is significantly longer than the calculated value of t1, a short fault exists. The equation for calculating t2 is: t2 = [(Cgd(at low Vds).(Vbattery+Vforward_bias_body diode-Iload.rdson / I_distribution_state2)].TCF.ICF. Before t2 expires, the state of the comparator A2 output signal V_comp_2 is first checked to ensure that the logic state is high. If the logic state of the A2 output signal V_comp_2 is not high, a fault has occurred. The value of t2 can also be pre-calculated and stored for I_distribution_state2 turn-on timing and qualification. Again, for very low package stray values, the corresponding t2 timing value can be calculated for monitoring the t2 task mode timing. If the monitored t2 timing exceeds the calculated timing, it indicates that a fault may have occurred. For this case, once the state of the A2 output signal V_comp_2 becomes asserted high to AN2, the distribution of I_distribution_state 3 is loaded, which causes the gate voltage to rise further.

[0093] Next, when the state of the comparator A2 output signal V_comp_2 changes to logic high to AN2, the programmed gate current distribution of I_distribution_state3 (stored value) is loaded to guide the gate voltage to further rise according to I_distribution_state3.

[0094] As the gate voltage continues to rise until the state of the comparator A1 output V_comp_3 becomes a logic high to AN1, the programmed gate current / resistor distribution of I_distribution_state 4 (stored value) is loaded to guide the gate voltage to rise toward the positive supply of the gate drive power supply. At this point, the turn-on distribution process is complete and the lower phase power switch 648 has become fully turned on. The role of G1 is to measure the differential voltage of VPS_U or VPS_L relative to the upper phase drive signal 630 (voltage) or the lower phase drive signal 635 (voltage). This measured voltage is used to determine when I_distribution_state 4 begins for DAC_VPS_U or DAC_VPS_L.

[0095] The shutdown process is initiated by asserting the command shutdown signal 852 high, which in turn loads the programmed gate current / resistor distribution I_Distribution State 5. This turns off (immediately after the falling edge of the PWL signal) the resistor 715 and / or the source current driver 615, and turns on several current sink (or resistor) units connected to the gate terminal of the lower phase power switch 648 (e.g., turning off the resistor 716 and / or the sink gate current driver 616) to initiate the reduction of the gate voltage. At the moment when the output of the G2 amplifier crosses the programmed threshold voltage set by the output of the DAC_VTH2_L block, the programmed gate current / resistor distribution of I_Distribution_State 6 (the stored value determined from the electrical model of the lower phase power switch 648) is then loaded to direct the gate voltage to decrease according to this current / resistor distribution value (whose source duration is set to the pre-calculated time value t3). For example, the digital input code value of the DAC_VTH2_L block may be updated twice during each PWM cycle, with the first update occurring immediately before the start of State_0 and the second update occurring immediately before the start of State_5. For example, the time zero value of the DAC value may be determined, stored, and used as an initial code during end-of-line testing of the inverter, where the value changes with any changes in temperature and / or parameters of the power switching components, load current amplitude and slope (see Fig. 9 ) or any changes in battery voltage. These values ​​can be calculated for each PWM cycle period. The equation for calculating t3 is: t3 = [Cgd(low Vds.(Vbattery+Vforward_bias_body diode-Iload.rdson / I_distribution_state6)].TCF.ICF. Before time t3 expires, the state of the A2 output signal V_comp_2 is first checked to ensure that the logic state is low. If the logic state of the A2 output signal V_comp_2 is not low, a fault has occurred. The value of t3 can also be pre-obtained and stored for state 6 shutdown timing and definition. Again, for very low package stray values, the corresponding t3 timing value can be calculated for monitoring the t3 task mode timing. If the monitored t3 timing exceeds the calculated timing, it indicates that a fault may have occurred.

[0096] Next, based on the output of the G2 amplifier crossing the programmed threshold voltage set by the output of the DAC_VTH1_L block, the programmed gate current / resistor distribution of I_Distribution_State 7 (stored value) is loaded to direct the gate voltage to further decrease according to the current / resistor distribution value (whose source duration is set to the pre-calculated time value t4). The equation for calculating t4 is: t4 = [(Cgs + Cgd (at low Vds)). (I load) / (gfs.I_Distribution_State 7)]. TCF. ICF. Before t4 expires, the state of the comparator A3 output signal V_comp_1 is first checked to ensure that the logic state has become low. If the logic state of the A3 output signal V_comp_1 is not low, a fault has occurred. The value of t4 can also be predetermined and stored for the shutdown timing and definition of state 7. Again, for very low package stray values, the corresponding t4 timing value can be calculated for monitoring the t4 task mode timing. If the monitored t4 timing exceeds the calculated timing, it indicates that a fault may have occurred. For this case, once the state of the A3 output signal V_comp_1 changes to asserted low, the distribution of I_distribution_state7 is loaded, causing the gate voltage to drop further.

[0097] Next, when the state of the comparator A4 output V_comp_0 becomes low, the programmed gate current distribution of I_distribution_state 8 (stored value) is loaded to guide the gate voltage to drop according to the current / resistor distribution value. The gate voltage continues to drop until the state of the comparator A5 output V_comp_4 becomes logically low, and then the programmed gate current / resistor distribution of I_distribution_state 9 (stored value) is loaded to guide the gate voltage to further drop toward the negative supply voltage rail of the gate drive power supply voltage. The role of G3 (Vg-VMS) can be operated so that when the amplitude of the differential amplifier G3 crosses the programmed threshold voltage value of "DAC_VMS_L", the shutdown state enters the next specified state, that is, the maintenance state, and a few clock cycles after entering the maintenance state, the SL clamp switch can be commanded to turn on. At this time, the shutdown distribution process is completed and the lower phase power switch 648 has become fully shut down.

[0098] The calculation of the gate current / resistor on and off distribution (I distribution) can be provided as: I distribution = Inom_prog_value.[Tref / (273+αTC.T)].βIds, where Tref is a reference temperature (e.g., such as room temperature), αTC is a stored fixed predetermined value representing a suitable temperature coefficient factor, and T is the operating temperature. The stored nominal current distribution (Inom_prog_value) is calculated at the module level so that the nominal current distribution takes into account the parameter variations of all power switching devices in the module and uses the measured values ​​of the power FET parameters Vth, gfs and Rdson at a given temperature (e.g., such as Tref). The two multiplication correction factors above take into account temperature variations (the terms in brackets) and the current distribution slope correction factor of βIds, which further modifies the I distribution to minimize switching power losses with the current flowing in the power FET device. The device current correction factor βIds is calculated during each PWM switching cycle to calculate βIds, which is then used to calculate the I distribution for the next PWM cycle.

[0099] refer to Figure 7 The lower phase power switching element 648, when Figure 8 When the output V_Comp_3 of the A1 comparator is in a high state, the switch SU of the lower phase clamp switch 717 can be turned on, thereby forcing the gate terminal voltage to reach the positive supply value of the gate drive power supply in the shortest amount of time, thereby minimizing the total power FET loss. In addition, when the output V_Comp_4 of the A5 comparator is in a high state, the switch SL of the lower phase clamp switch 717 can be turned on, thereby forcing the gate terminal voltage to reach the negative supply value of the gate drive power supply in the shortest amount of time, thereby minimizing the total power FET loss. State 4 can be a maintenance state, which is initiated when the gate potential is approaching the VPS_U or VPS_L voltage. The SU clamp switch is turned on several clock cycles after turning on the gate drive to enter State_4, and the SL clamp switch is turned on several clock cycles after entering State_9. The SU clamp switch is turned on immediately after the falling edge of the PWL signal.

[0100] Fig. 9 Depicted is an exemplary graph of correction factors for an adaptive gate driver for a power device switch according to one or more embodiments.

[0101] Fig. 9 A plot 900 of the trajectory of the βIds correction factor is shown. The βIds for each PWM cycle can be calculated based on previous measurements of the magnitude and slope of Ids. Fig. 9As shown, as Ids increases from zero, the βIds current distribution slope correction factor 905 may start at a maximum value, decrease in value along a slope ranging from about three to about one as Ids increases, and reach a minimum value of one at 910 at the maximum value of Ids. The two multiplication correction factors in the I distribution equation account for temperature changes (the terms in brackets) and the βIds current distribution slope correction factor, which further modifies the I distribution to minimize switching power losses with current flowing in the power FET device. The device current is calculated during each PWM switching cycle to calculate βIds, which is then used to calculate the I distribution for the next PWM cycle.

[0102] Fig.10 An exemplary system for a current / resistor hybrid adaptive gate driver for a power device switch according to one or more embodiments is depicted.

[0103] One or more embodiments may include a hybrid adaptive gate driver 1000 including a turn-on and turn-off (source / sink) programmable distributed current driver and a turn-on and turn-off programmable distributed resistor. The hybrid adaptive gate driver 1000 may provide low impedance to the gate terminals of the upper phase power switch 644 and the lower phase power switch 648 during turn-on and turn-off events while maintaining the ability to drive the gate with any desired current drive distribution. The infrastructure of the gate drive technology may include high-speed measurements of the current flowing into the upper phase power switch 644 and the lower phase power switch 648 for shutting down the upper phase power switch 644 and the lower phase power switch 648 in an over-current event of less than one microsecond.

[0104] For example, the lower phase power switching element 648 may include multiple parallel devices to deliver the maximum requested power transfer to the load. Due to the device parameter mismatch caused by the non-ideal manufacturing process of the power FET, the load current may not be shared equally between the parallel devices during both switching and conduction operations. However, one or more embodiments may independently drive the gate terminal of each device or device group. The independent drive may provide an opportunity to arrange the turn-on and turn-off timing and the calculated gate current distribution to minimize the current imbalance in the parallel devices. For example, in the case when two devices are connected in parallel, if one device (or a group of devices connected in parallel) has a higher threshold voltage than the second device, the turn-on of the device with the lower threshold voltage may be delayed relative to the turn-on time of the device with the higher threshold voltage, thereby causing a relatively equal current size flowing in the two devices. During the off period, the device with the higher threshold voltage can be a device with a delayed turn-off timing, which is opposite to the delay of the turn-on event. The independent drive can provide uniform and relatively equal temperatures and relatively matched long-term life between parallel devices.

[0105] In addition to introducing turn-on / turn-off delays between unmatched groups of devices, unique gate drive profiles may be calculated to further balance and improve current sharing between groups of devices. One or more embodiments may minimize current imbalance between parallel connected devices by prioritizing turn-on and turn-off delay timing and calculating appropriate gate drive profiles between devices.

[0106] Fig.11 An exemplary system for a correction controller 1100 for an adaptive gate driver for a power device switch is depicted in accordance with one or more embodiments.

[0107] like Figure 8 As shown, one or more embodiments may continuously measure the threshold voltage drift of a power switch over time. Fig.11 As shown, this can be achieved by continuously measuring the gate-to-source voltage Vgs of the power switch with a high-speed sensing circuit to convert it into a digital code A0-A(k-1) by a flash analog-to-digital converter 1105. For example, the digital code can be used by the drift correction calculation engine 1106 to calculate the optimal and / or safe gate drive turn-on and / or turn-off voltage distribution, or to clear the open gate terminal fault in extreme cases.

[0108] Fig.12 Depicted is an exemplary method 1200 for operating an adaptive gate driver for a power device switch according to one or more embodiments.

[0109] The method 1200 may include receiving, by one or more controllers (e.g., a point of use upper phase A controller 142A or a resistor-based adaptive gate driver 800 for the lower phase power switch 648), a voltage from a gate terminal to a source terminal for a power switch (e.g., an upper phase A switch 144A or a lower phase power switch 648) of an inverter 110 for an electric vehicle 100 (operation 1210). The method 1200 may include comparing, by one or more controllers, the voltage to one or more thresholds (e.g., DAC_VTH0_L, DAC_VTH1_L, or DAC_VTH2_L) (operation 1220). The method 1200 may include loading, by the one or more controllers, a gate driver distribution (e.g., I_Distribution_State 1) from a plurality of gate driver distributions based on the comparison (operation 1230). The method 1200 may include controlling, by the one or more controllers, a gate driver of the power switch based on the loaded gate driver distribution (operation 1240). The method 1200 may include controlling the operation of one or more switches of the gate driver to change one or more of a resistive gate driver, a variable resistance of the gate driver, or a current of the gate driver (operation 1250). For example, the on resistor 710 and the off resistor 711 may be dynamically selected by the operation of the corresponding φ switches based on the corresponding on and off control signals of the loaded gate driver profile. The gate driver profile may be determined based on one or more of the inherent characteristics of the power switch, the load current slope and amplitude value, the high voltage battery amplitude of the inverter, or the operating temperature of the power switch.

[0110] One or more embodiments may provide a gate driver system that significantly reduces switching power losses while protecting the power switch in terms of gate voltage and drain current ringing amplitude and drain to source voltage overshoot and ringing amplitude. One or more embodiments may provide a gate driver system that calculates an optimal gate drive on and off voltage profile that incorporates the inherent characteristics of the power device, load current slope and amplitude, high voltage battery amplitude, and operating temperature. One or more embodiments may provide a gate driver system that continuously measures the threshold voltage drift of the power device over time, which can be used to calculate the optimal gate drive on and off voltage profile, and for detecting open gate terminal faults. One or more embodiments may provide a gate driver system that uses a hybrid variable resistor driver and a fast transition switching mode circuit, characterized by a very low drive impedance to minimize the switch on and off current and / or voltage ringing while shortening the transition time to the full on time window. One or more embodiments may provide a gate driver system that continuously detects hard and / or soft short and / or open faults throughout the switching on, off, and conduction cycles by continuously checking the gate voltage amplitude and the rate of change of the gate voltage over time for several threshold voltages and pre-programmed time windows. One or more embodiments may provide a gate driver system that calculates a special turn-off profile to ensure safe turn-off of the power switch for the turn-on to hard short case.

[0111] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

Claims

1. A system comprising: One or more point-of-use controllers, the one or more point-of-use controllers being configured to: asserting a command-on signal to load a first on gate driver distribution; controlling a gate driver for a power switch for an inverter based on the loaded first turn-on gate driver profile to start a first phase of turn-on operation of the power switch, wherein the first phase of the turn-on operation of the power switch increases a gate signal of the gate driver from a first turn-on value to a second turn-on value, the first turn-on value corresponding to a fully off state of the power switch, the second turn-on value being less than a fully turn-on value, the fully turn-on value corresponding to a fully on state of the power switch; receiving a first power switch signal based on one or more of a detected voltage or a detected current of the power switch; performing a comparison of the received first power switch signal with a first turn-on threshold; loading a second gate-on driver distribution when the comparison indicates that the first power switch signal is greater than the first turn-on threshold; as well as The gate driver is controlled based on the loaded second turn-on gate driver distribution to end the first phase of the turn-on operation of the power switching device and start the second phase of the turn-on operation of the power switching device, wherein the second phase of the turn-on operation of the power switching device increases the gate signal of the gate driver from the second turn-on value to a third turn-on value, and the third turn-on value is greater than the second turn-on value and less than the full turn-on value.

2. The system of claim 1, wherein the one or more point-of-use controllers are further configured to: measuring an elapsed time from the start of the second phase of the switching operation of the power switching element until the end of the second phase of the switching operation; and When the elapsed time is longer than the second on-gate driver profile time, a fault is asserted.

3. The system of claim 1, wherein the one or more point-of-use controllers are further configured to: receiving a second power switch signal based on one or more of a detected voltage or a detected current of the power switch; performing a comparison of the received second power switch signal with a second on-threshold, wherein the second on-threshold is greater than the first on-threshold; When the comparison indicates that the second power switch signal is greater than the second turn-on threshold, loading a third gate turn-on driver distribution; and The gate driver is controlled based on the loaded third turn-on gate driver distribution to end the second phase of the turn-on operation of the power switching device and start the third phase of the turn-on operation of the power switching device, wherein the third phase of the turn-on operation of the power switching device increases the gate signal of the gate driver from the third turn-on value to a fourth turn-on value, and the fourth turn-on value is greater than the third turn-on value and less than the full turn-on value.

4. The system of claim 3, wherein the one or more point-of-use controllers are further configured to: measuring an elapsed time from the start of the third phase of the switching operation of the power switching element until the end of the third phase of the switching operation; and When the elapsed time is shorter or longer than the third on-gate driver profile time, a fault is asserted.

5. The system of claim 3, wherein the one or more point-of-use controllers are further configured to: receiving a third power switch signal based on one or more of a detected voltage or a detected current of the power switch; performing a comparison of the received third power switch signal with a third on-threshold, wherein the third on-threshold is greater than the second on-threshold; When the comparison indicates that the third power switch signal is greater than the third turn-on threshold, loading a fourth gate turn-on driver distribution; and The gate driver is controlled based on the loaded fourth turn-on gate driver distribution to end the third phase of the turn-on operation of the power switching device and start the fourth phase of the turn-on operation of the power switching device, the fully turn-on value, wherein the fourth phase of the turn-on operation of the power switching device increases the gate signal of the gate driver from the fourth turn-on value to the fully turn-on value, and the fully turn-on value corresponds to the fully turned-on state of the power switching device.

6. A system comprising: One or more point-of-use controllers, the one or more point-of-use controllers being configured to: asserting a command-off signal to load a first off gate driver profile; Controlling a gate driver for a power switch for an inverter based on the loaded first turn-off gate driver profile to start a first phase of a turn-off operation of the power switch, wherein the first phase of the turn-off operation of the power switch reduces a gate signal of the gate driver from a first turn-off value to a second turn-off value, the first turn-off value corresponding to a fully on state of the power switch, the second turn-off value being greater than a fully turn-off value, the fully turn-off value corresponding to a fully off state of the power switch; receiving a first power switch signal based on one or more of a detected voltage or a detected current of the power switch; performing a comparison of the received first power switching element signal with a first turn-off threshold; loading a second gate turn-off driver distribution when the comparison indicates that the first power switch signal is less than the first turn-off threshold; as well as The gate driver is controlled based on the loaded second shutdown gate driver distribution to end the first phase of the shutdown operation of the power switching device and start the second phase of the shutdown operation of the power switching device, wherein the second phase of the shutdown operation of the power switching device reduces the gate signal of the gate driver from the second shutdown value to a third shutdown value, and the third shutdown value is less than the second shutdown value and greater than the full shutdown value.

7. The system of claim 6, wherein the one or more point-of-use controllers are further configured to: measuring an elapsed time from the start of the second phase of the shutoff operation of the power switching element until the end of the second phase of the shutoff operation; and When the elapsed time is shorter or longer than the second off gate driver profile time, a fault is asserted.

8. The system of claim 6, wherein the one or more point-of-use controllers are further configured to: receiving a second power switch signal based on one or more of a detected voltage or a detected current of the power switch; performing a comparison of the received second power switching element signal with a second shutdown threshold, wherein the second shutdown threshold is less than the first shutdown threshold; loading a third gate turn-off driver distribution when the comparison indicates that the second power switch signal is less than the second turn-off threshold; as well as The gate driver is controlled based on the loaded third shutdown gate driver distribution to end the second phase of the shutdown operation of the power switching device and start the third phase of the shutdown operation of the power switching device, wherein the third phase of the shutdown operation of the power switching device reduces the gate signal of the gate driver from the third shutdown value to a fourth shutdown value, and the fourth shutdown value is less than the third shutdown value and greater than the full shutdown value.

9. The system of claim 8, wherein the one or more point-of-use controllers are further configured to: measuring an elapsed time from the start of the third phase of the shutoff operation of the power switching element until the end of the third phase of the shutoff operation; and When the elapsed time is shorter or longer than the third off gate driver profile time, a fault is asserted.

10. The system of claim 8, wherein the one or more point-of-use controllers are further configured to: receiving a third power switch signal based on one or more of a detected voltage or a detected current of the power switch; performing a comparison of the received third power switching element signal with a third shutdown threshold, wherein the third shutdown threshold is less than the second shutdown threshold; When the comparison indicates that the third power switch signal is less than the third turn-off threshold, loading a fourth gate turn-off driver distribution; and The gate driver is controlled based on the loaded fourth shutdown gate driver distribution to end the third phase of the shutdown operation of the power switching device and start the fourth phase of the shutdown operation of the power switching device, the full shutdown value, wherein the fourth phase of the shutdown operation of the power switching device reduces the gate signal of the gate driver from the fourth shutdown value to the full shutdown value, and the full shutdown value corresponds to the full shutdown state of the power switching device.

11. A system comprising one or more point-of-use controllers, the one or more point-of-use controllers comprising: a gate-to-source amplifier configured to be connected to a power switch to measure a gate-to-source voltage of the power switch; a digital-to-analog converter configured to receive a digital threshold and output an analog threshold signal corresponding to the digital threshold; a threshold amplifier configured to receive the gate-to-source voltage and the analog threshold signal and to assert a comparison signal to a high state when the gate-to-source voltage is higher than the analog threshold signal; a logic AND gate configured to receive the comparison signal and an enable signal and to assert a load signal to a high state when both the comparison signal and the enable signal are in a high state; and a load register configured to load a gate driver distribution when the load signal is asserted to a high state, The operation of the power switch is based on the gate driver profile in the load register.

12. The system of claim 11, further comprising: a gate driver configured to be connected to the power switch to operate the power switch; as well as One or more controllers configured to operate the gate drivers based on the gate driver profile in the load register.

13. The system according to claim 12, The gate driver comprises: a first on-resistor connected in series with a first on-resistor switch, a second on-resistor connected in series with a second on-resistor switch, wherein the first on-resistor and the first on-resistor switch are connected in parallel with the second on-resistor and the second on-resistor switch, a first turn-off resistor, wherein the first turn-off resistor is connected in series with a first turn-off resistor switch, a second off resistor, the second off resistor being connected in series with a second off resistor switch, wherein the first off resistor and the first off resistor switch are connected in parallel with the second off resistor and the second off resistor switch, The first clamping switch is turned on, and A first clamping off switching element; and wherein the one or more controllers are configured to operate each of the first on-resistor switch, the second on-resistor switch, the first off-resistor switch, the second off-resistor switch, the first clamp on-switching element and the first clamp off-switching element of the gate driver to change the voltage applied by the gate driver to the gate terminal of the power switching element based on the gate driver distribution in the loading register.

14. The system according to claim 13, wherein a resistance value of the first on-resistor is different from a resistance value of the second on-resistor, and The resistance value of the first off-resistance is different from the resistance value of the second off-resistance.

15. The system according to claim 12, The gate driver comprises: a first on-current source, the first on-current source being connected in series with the first on-current switching element, a second on-current source, the second on-current source being connected in series with a second on-current switching element, wherein the first on-current source and the first on-current switching element are connected in parallel with the second on-current source and the second on-current switching element, a first turn-off current sink connected in series with the first turn-off current switching element, and a second shut-off current sink, the second shut-off current sink being connected in series with a second shut-off current switching element, wherein the first shut-off current sink and the first shut-off current switching element are connected in parallel with the second shut-off current sink and the second shut-off current switching element; and wherein the one or more controllers are configured to operate each of the first on-current switch, the second on-current switch, the first off-current switch, and the second off-current switch of the gate driver to change a voltage applied by the gate driver to a gate terminal of the power switch based on the gate driver distribution in the loading register.

16. The system according to claim 15, wherein the current value of the first on-current source is different from the current value of the second on-current source, and The current value of the first turn-off current sink is different from the current value of the second turn-off current sink.

17. The system according to claim 12, The gate driver comprises: a first on-resistor connected in series with a first on-resistor switch, a second on-resistor connected in series with a second on-resistor switch, wherein the first on-resistor and the first on-resistor switch are connected in parallel with the second on-resistor and the second on-resistor switch, a first turn-off resistor, wherein the first turn-off resistor is connected in series with a first turn-off resistor switch, a second off resistor, the second off resistor being connected in series with a second off resistor switch, wherein the first off resistor and the first off resistor switch are connected in parallel with the second off resistor and the second off resistor switch, a first on-current source connected in series with the first on-current switching element and connected in parallel with the second on-resistor and the second on-resistor switching element, a second on-current source, the second on-current source being connected in series with a second on-current switching element, wherein the first on-current source and the first on-current switching element are connected in parallel with the second on-current source and the second on-current switching element, a first off current sink connected in series with the first off current switch and in parallel with the second off resistor and the second off resistor switch, and a second shut-off current sink, the second shut-off current sink being connected in series with a second shut-off current switching element, wherein the first shut-off current sink and the first shut-off current switching element are connected in parallel with the second shut-off current sink and the second shut-off current switching element; and wherein the one or more controllers are configured to operate each of the first on-resistor switch, the second on-resistor switch, the first off-resistor switch, the second off-resistor switch, the first on-current switch, the second on-current switch, the first off-current switch, and the second off-current switch of the gate driver to change the voltage applied by the gate driver to the gate terminal of the power switch based on the gate driver distribution in the loading register.

18. The system of claim 11, wherein the gate driver profile is determined based on one or more of an intrinsic characteristic of the power switch, a load current slope and amplitude value, a high voltage battery amplitude, or an operating temperature of the power switch.

19. The system of claim 11, further comprising: An inverter is configured to convert DC power from the battery into AC power to drive the motor, wherein the inverter includes the one or more point-of-use controllers.

20. The system of claim 19, further comprising: the battery, the battery being configured to supply the DC power to the inverter; as well as The motor is configured to receive the AC power from the inverter to drive the motor.

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