System and method for electrical isolation for inverter for electric vehicle

Abstract

A system includes an inverter including: a first electrical isolator separating a low voltage region from a high voltage region, the first electrical isolator having a first electrical isolator output path; a second electrical isolator having a second electrical isolator output path; an amplifier connected to the first electrical isolator via the first electrical isolator output path and to the second electrical isolator via the second electrical isolator output path, the amplifier having a first amplifier output path and a second amplifier output path; a comparator connected to the amplifier via the first amplifier output path and the second amplifier output path, the comparator having a first comparator output path and a second comparator output path; and a pulse reshaping and envelope detector connected to the comparator via the first comparator output path and the second comparator output path.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 377,486 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 377,501 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 377,512 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 378,601 filed on October 6, 2022, and U.S. Non-Provisional Patent Application No. 18 / 150,927 filed on January 6, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure relate generally to systems and methods for electrical isolation of inverters for electric vehicles, and more particularly to systems and methods for electrical isolation circuits for common mode noise rejection and wide range common mode transient immunity (CMTI) tolerance. Background Art

[0004] Inverters, such as those used to drive motors in electric vehicles, are responsible for converting high voltage direct current (HVDC) to alternating current (AC) to drive the motors. In inverters, electromagnetic interference issues, such as common mode RF interference due to RF noise being coupled or induced into the high voltage (non-ground referenced) operating plane, can impair the proper operation of the electrical transceiver.

[0005] The present disclosure is directed to overcoming one or more of these aforementioned challenges. Summary of the invention

[0006] In some aspects, the technology described herein relates to a system comprising: an inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter comprises: a first electrical isolator separating a low voltage region from a high voltage region, the first electrical isolator having a first electrical isolator output path; a second electrical isolator separating the low voltage region from the high voltage region, the second electrical isolator having a second electrical isolator output path; an amplifier in the high voltage region, connected to the first electrical isolator via the first electrical isolator output path and to the second electrical isolator via the second electrical isolator output path, the amplifier having a first amplifier output path and a second amplifier output path; a comparator in the high voltage region and connected to the amplifier via the first amplifier output path and the second amplifier output path, the comparator having a first comparator output path and a second comparator output path; and a pulse reshaping and envelope detector in the high voltage region and connected to the comparator via the first comparator output path and the second comparator output path.

[0007] In some aspects, the technology described herein relates to a system further comprising: a pulse transceiver, the pulse transceiver is in a low voltage region, the pulse transceiver is connected to a first electrical isolator via a first pulse transceiver output path and to a second electrical isolator via a second pulse transceiver output path.

[0008] In some aspects, the technology described herein relates to a system in which a pulse transceiver, an amplifier, a comparator, and a pulse reshaping and envelope detector are configured to operate together to transmit a pulse width modulated signal from a low voltage region to a high voltage region.

[0009] In some aspects, the technology described herein relates to a system in which a pulse transceiver is configured to output a first pulse on a first pulse transceiver output path and a second pulse on a second pulse transceiver output path.

[0010] In some aspects, the technology described herein relates to a system wherein the pulse transceiver is further configured to receive a main pulse and output a first pulse and a second pulse based on the received main pulse.

[0011] In some aspects, the technology described herein relates to a system wherein: a first galvanic isolator is configured to receive a first pulse on a first pulse transceiver output path and transmit a first galvanic isolator pulse on the first galvanic isolator output path based on the received first pulse, and a second galvanic isolator is configured to receive a second pulse on a second pulse transceiver output path and transmit a second galvanic isolator pulse on the second galvanic isolator output path based on the received second pulse.

[0012] In some aspects, the technology described herein relates to a system in which an amplifier is configured to: receive a first electrical isolator pulse on a first electrical isolator output path, amplify the first electrical isolator pulse based on one or more characteristics of the amplifier, and send a first amplified pulse on the first amplifier output path based on the amplified first electrical isolator pulse, and receive a second electrical isolator pulse on a second electrical isolator output path, amplify the second electrical isolator pulse based on one or more characteristics of the amplifier, and send a second amplified pulse on the second amplifier output path based on the amplified second electrical isolator pulse.

[0013] In some aspects, the technology described herein relates to a system in which a comparator is configured to: receive a first amplified pulse on a first amplifier output path, receive a second amplified pulse on a second amplifier output path, perform a comparison of the first amplified pulse and the second amplified pulse, output the first compared pulse on the first comparator output path based on the comparison, and output the second compared pulse on the second comparator output path based on the comparison.

[0014] In some aspects, the technology described herein relates to a system in which a pulse reshaping and envelope detector is configured to: receive a first compared pulse on a first comparator output path, receive a second compared pulse on a second comparator output path, and output an output pulse based on the first compared pulse and the second compared pulse.

[0015] In some aspects, the techniques described herein relate to a system wherein an amplifier includes: a trimmer and a tunable filter.

[0016] In some aspects, the technology described herein relates to a system further comprising: an out-of-range detector connected to the first electrical isolator, the second electrical isolator, and the pulse reshaping and envelope detector.

[0017] In some aspects, the techniques described herein relate to a system wherein the comparator further includes a resistor averaging circuit.

[0018] In some aspects, the technology described herein relates to a system that further includes a battery configured to supply DC power to an inverter and a motor configured to receive AC power from the inverter to drive the motor.

[0019] In some aspects, the technology described herein relates to a method comprising: receiving a first pulse by one or more controllers, and transmitting a first electrical isolator pulse by the one or more controllers based on the first pulse; receiving a second pulse by the one or more controllers, and transmitting a second electrical isolator pulse by the one or more controllers based on the second pulse; receiving the first electrical isolator pulse and the second electrical isolator pulse by the one or more controllers; generating a first amplified pulse based on the first electrical isolator pulse and generating a second amplified pulse based on the second electrical isolator pulse by the one or more controllers; receiving the first amplified pulse and the second amplified pulse by the one or more controllers; comparing the first amplified pulse and the second amplified pulse by the one or more controllers; determining a mitigation action by the one or more controllers based on the comparison; and generating an output pulse by the one or more controllers based on the mitigation action.

[0020] In some aspects, the technology described herein relates to a method wherein determining a mitigation action comprises: determining, by the one or more controllers, a difference between one or more signal characteristics of a first amplified pulse and one or more signal characteristics of a second amplified pulse; comparing, by the one or more controllers, the difference to a difference threshold; and determining, by the one or more controllers, the mitigation action based on the comparison of the difference to the difference threshold.

[0021] In some aspects, the technology described herein relates to a method in which generating an output pulse includes maintaining a previous signal state based on one or more of a previous first galvanic isolator pulse or a previous second galvanic isolator pulse.

[0022] In some aspects, the technology described herein relates to a method further comprising trimming, by the one or more controllers, one or more of the first electrical isolator pulse or the second electrical isolator pulse.

[0023] In some aspects, the technology described herein relates to a method further comprising determining, by the one or more controllers, one of an in-range indication or an out-of-range indication based on the first electrical isolator pulse and the second electrical isolator pulse.

[0024] In some aspects, the technology described herein relates to a method wherein generating an output pulse includes generating the output pulse based on the one of an in-range indication or an out-of-range indication.

[0025] In some aspects, the technology described herein relates to a system comprising: a first electrical isolator configured to receive a first pulse from a pulse transceiver and output a first electrical isolator pulse based on the received first pulse; a second electrical isolator configured to receive a second pulse from the pulse transceiver and generate a second electrical isolator pulse based on the received second pulse; an amplifier configured to receive the first electrical isolator pulse and the second electrical isolator pulse, amplify the first electrical isolator pulse and the second electrical isolator pulse into a first amplified pulse and a second amplified pulse, respectively, and output the first amplified pulse and the second amplified pulse; a comparator configured to receive the first amplified pulse and the second amplified pulse, perform a comparison of the first amplified pulse with the second amplified pulse, and generate a first compared pulse and a second compared pulse, respectively, based on the comparison; and a pulse reshaping and envelope detector configured to receive the first compared pulse and the second compared pulse, and generate an output pulse based on the first compared pulse and the second compared pulse.

[0026] Other objects and advantages of the disclosed embodiments will be described in part in the following description, and in part will be obvious from the description, or can be understood by practicing the disclosed embodiments. The objects and advantages of the disclosed embodiments will be realized and achieved by means of the elements and combinations particularly pointed out in the appended claims.

[0027] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosed embodiments, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various exemplary embodiments and, together with the description, serve to explain the principles of the disclosed embodiments.

[0029] Figure 1 An exemplary system infrastructure for a vehicle including a combined inverter and converter is depicted according to one or more embodiments.

[0030] Figure 2 Depicted is a method for providing a point-of-use switching controller according to one or more embodiments. Figure 1 An exemplary system infrastructure of a combined inverter and converter.

[0031] Figure 3 Describes a method for Figure 2 An exemplary system infrastructure for a controller of FIG.

[0032] Figure 4 Describes a method for Figure 2 An exemplary system infrastructure for a point-of-use switching controller.

[0033] Figure 5 Describes a method for Figure 4 An exemplary system infrastructure of an upper power module.

[0034] Figure 6 Depicted are exemplary methods for reducing the effects of interference from electrical components in accordance with one or more embodiments.

[0035] Figure 7 An exemplary controller for reducing interference effects from electrical components is depicted in accordance with one or more embodiments.

[0036] Figure 8 An exemplary resistor averaging circuit is depicted in accordance with one or more embodiments.

[0037] Fig. 9 An exemplary trimming process is depicted in accordance with one or more embodiments.

[0038] Fig.10 Depicted is an exemplary operation of an out of range detector in accordance with one or more embodiments.

[0039] Fig.11 An exemplary out-of-range detector is depicted in accordance with one or more embodiments.

[0040] Fig.12 An exemplary pulse reshaping and envelope detector is depicted in accordance with one or more embodiments. DETAILED DESCRIPTION

[0041] Both the foregoing general description and the following detailed description are exemplary and explanatory only and do not constrain the claimed features. As used herein, the terms "comprises," "comprising," "has," "having," "includes," "including," or other variations thereof are intended to encompass non-exclusive inclusions such that a process, method, article, or device that includes a series of elements includes not only those elements, but may also include other elements that are not explicitly listed or inherent to such process, method, article, or device. In the present disclosure, unless otherwise stated, relative terms (such as, for example, "about," "substantially," and "approximately") are used to indicate possible ±10% variations in the stated values. In the present disclosure, unless otherwise stated, any numerical value may include possible ±10% variations in the stated values.

[0042] The terms used below may be interpreted in their broadest reasonable manner, although they are being used in conjunction with a detailed description of certain specific examples of the present disclosure. Indeed, certain terms may even be emphasized below; however, any term intended to be interpreted in any constrained manner will be explicitly and specifically defined as such in this detailed description. For example, in the context of the present disclosure, a switching device may be described as a switching element or device, but may refer to any device for controlling power flow in a circuit. For example, a switching element may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT) or a relay, or any combination thereof, but is not limited thereto.

[0043] Various embodiments of the present disclosure relate generally to systems and methods for electrical isolation, and more particularly to electrical isolation circuits with respect to common-mode noise rejection and wide-range common-mode transient immunity (CMTI) tolerance as may be applied to electronic systems and / or components, such as those used in electric vehicles.

[0044] Inverters (such as those used to drive motors in electric vehicles) are responsible for converting high voltage direct current (HVDC) into alternating current (AC) to drive the motor. A three-phase inverter may include a bridge having six power device switches (e.g., power transistors such as IGBTs or MOSFETs) that are controlled by pulse width modulation (PWM) signals generated by a controller. The inverter may include three-phase switches to control phase voltages, upper and lower gate drivers to control the switches, a PWM controller, and glue logic between the PWM controller and the gate driver. The PWM controller may generate signals to define the expected state of the system. The gate driver may send signals from the PWM controller to the phase switches. The phase switches may drive the phase voltages. The inverter may include an isolation barrier between a low voltage plane and a high voltage plane. The signal may be passed from the PWM controller to the phase switch by passing through an isolation barrier, which may employ optical, converter-based, or capacitor-based isolation. The PWM signal may be distorted when passing through the glue logic, which may include resistive, capacitive, or other types of filtering. Due to the electrical isolation barrier and other delays within the gate driver, the PWM signal may be distorted when passing through the gate driver. The PWM signal may be distorted when the signal is processed by the phase switching device via the gate driver output.

[0045] Gate drivers withstand common-mode transients that occur during field effect transistor (FET) switching and when one side of a floating high voltage terminal is shorted to ground or subjected to electrostatic discharge. These voltage transients can cause fast edges that can form common-mode current bursts through electrical isolation. Gate drivers may need to demonstrate common-mode transient immunity (CMTI) in order to be effective and safe.

[0046] The gate driver may have a high voltage domain in common with the voltage plane of the associated FET. Further, the high voltage plane may be supplied by a flyback converter, which may be isolated from the low voltage plane by a transformer. The high voltage domain power supply may be used to provide power to such a circuit that sources and sinks gate current to drive the FET and can detect FET faults, thereby acting on the faults and / or transmitting the faults to the low voltage domain. The gate driver may include an electrical channel dedicated to FET commands, and one or more bidirectional or unidirectional electrical channels dedicated to FET communications.

[0047] High current switching transients can form strong electromagnetic (EM) fields that can couple into nearby metal traces. The magnitude and frequency of the coupled current can depend on the layout of the FET packaging solution and the direction and length of the metal traces between the FET and the control integrated circuit (IC). For example, a typical value for the coupled current can be up to 1A at an AC frequency of up to 100MHz. Typically, within the circuit, the gate driver IC can be placed far enough away from the FET so that the high EM field is not directly coupled into the internal metal traces within the gate driver IC. The gate driver is placed at a distance from the EM field so that the induced current within the circuit is below the level that will cause the gate driver to malfunction, or a metal shield is placed between the gate driver and the source of the EM field to protect the gate driver circuit. The output terminals of the gate driver connected to the FET are exposed to the EM field at a point where the output terminals are no longer covered by the shield. The gate driver switches large currents (e.g., such as 5A to 15A) through these exposed terminals. The large currents switched are usually larger in magnitude than the EM induced current. The gate driver can overdrive the induced current to maintain control of the FET. The gate driver and the high side of the FET may share a common ground and gate control signal trace, both of which may be susceptible to coupled currents.

[0048] The gate driver can turn on low resistance switches to source and sink gate current. Sometimes a series resistor can be added to limit the gate current. The switched gate current can be greater than the coupling current in order to maintain control of their respective FETs.

[0049] The gate driver may be able to sense the FET operating voltage or current in order to provide feedback and react to faults. An overcurrent fault may typically be detected by sensing the FET drain to source voltage and comparing the sensed voltage to a reference value. The sensed voltage may be heavily filtered to reject coupled currents. Filtering may slow the response to a fault condition, causing a delay in response. For example, the rate of current increase due to a low resistance short may reach damaging levels before being detected by a heavily filtered drain to source voltage detection strategy. The resulting short may damage the FET or the vehicle before being detected and cut off.

[0050] According to one or more embodiments, a FET driver circuit may provide fast overcurrent detection by shunt current sensing, or by diverting a portion of the load current through a parallel FET that may have a current sensing circuit. Utilizing either strategy may require a "point of use IC" in which the sensing circuit is very close to the FET. Even if the point of use IC and the remote controller are resistant to EM fields, the communication between the point of use IC and the remote controller is still susceptible to induced currents. Point of use ICs have been implemented in low EM field applications, such as smart FETs for automotive applications. However, point of use ICs have not yet been used in high EM field applications. High EM fields can be fields that (i) induce a current within the IC that exceeds the operating current of the IC and causes a malfunction, or (ii) induce a differential voltage within the IC that exceeds the operating differential voltage and causes a malfunction. High EM fields can be, for example, fields greater than about 10A or about 100V.

[0051] As introduced above, electrical isolation may include isolating functional sections of an electrical system to prevent current flow, such that, for example, no direct conduction path is permitted between such functional sections. For example, two circuits may be electrically isolated such that the circuits are configured to communicate with each other but may have respective reference grounds at different potentials. For example, some architectures use a circuit with four electrical isolators, such as four capacitors, to pass data between a low voltage plane and a high voltage plane. For example, electrical isolation may include optical, transformer-based, or capacitance-based isolation.

[0052] The gate driver may be a power amplifier or other electrical component that accepts a low power input from a controller and may generate a high current drive input for the gate of a high power transistor (such as a half H-bridge switch as described above). Galvanically isolated gate drivers may be used in automotive and industrial applications to communicate between low voltage planes and high voltage planes without causing harm to the user or equipment.

[0053] One or more embodiments may address electromagnetic interference (EMI) that may impair the operation of an electrical transceiver. For example, common mode transient immunity (CMTI) is a measurable metric for an electrical transceiver, and applicable industry standards describe applicable CMTI capability tests and requirements. One or more embodiments may address a wide range of CMTI tolerances. One or more embodiments may address electromagnetic compatibility (EMC) issues that may impair the operation of an electrical transceiver, such as common mode radio frequency interference (CMRFI) generated due to radio frequency (RF) noise being coupled or induced into a high voltage (e.g., non-ground reference voltage) operating plane. One or more embodiments may address common mode noise rejection.

[0054] One or more embodiments may address EMC issues including long duration common mode transient immunity (LD-CMTI) events, which may be longer in duration than conventional CMTI. Such events may be caused by switching of high voltage field effect transistors (FETs) in a phase switching device (e.g., half H-bridge) configuration. One or more embodiments may address slew events that may last from about 100 nanoseconds up to about 300 nanoseconds and may cause the input of a receiver to be driven out of range, which may interrupt communications for an extended period.

[0055] For example, one or more embodiments may include a circuit architecture for addressing interference such as CMTI, CMRFI, or LD-CMTI. According to one or more embodiments, CMRFI may be addressed by implementing a first input stage to an electrical receiver having given properties. Such properties may include filtering and not responding to a common mode RF signal generated in a gate drive system that appears as a differential signal. The differential signal may be due to an unbalanced electrical isolator or other mismatch including parasitic effects present in the signal path.

[0056] The input of the gate drive system may be trimmed to eliminate differences in current resulting from interference, such as differences based on or detected based on noisy and / or mismatched electrical isolator outputs, parasitic capacitances, and / or inductances associated with electromagnetic interfaces, for example, caused by one or more electrical components. Such interference may be caused by, for example, high voltage side components of the electrical system. Interference may be based on traces and / or mismatches at one or more front end amplifiers. The input of the gate terminal may be trimmed to eliminate such interference so that it has no effect on the output PWM signal as output by the gate drive system. Thus, the resulting PWM signal may not be based on a net differential component.

[0057] One or more embodiments may include a resistor averaging circuit that is placed before the comparator to provide an additional offset difference between the two inputs. Such a resistor averaging circuit may mitigate the effects of CMTI and / or CMRFI.

[0058] According to one or more embodiments, according to the techniques and designs disclosed herein, using an out-of-range detector to generate an output from a gate drive system can solve or mitigate problems caused by LD-CMTI. The out-of-range detector can trigger a sample and hold circuit to maintain its previous state based on the detection of an out-of-range signal. Detection of an out-of-range signal can trigger the out-of-range detector to cause the circuit to maintain a previous state, thereby preventing or mitigating the output from experiencing a glitch event during a slew event (e.g., a long slew event of approximately 300 nanoseconds). A slew event can be an event in which an interfering signal causes an unexpected input (e.g., outside the range of allowed signal inputs) as detected by the out-of-range detector. For example, the threshold for a long slew event can be a function of high voltage capacitance, frequency and amplitude of the drive signal, package parasitics, and other parameters (such as power and area).

[0059] Thus, one or more embodiments may provide a system that is configured to withstand a wide range of CMTI events. For example, a minimum CMTI rating of about 5V / ns to about 300V / ns and the use of CMTI pulses no longer than about 13ns may be used to specify optimal or target performance. The techniques and designs disclosed herein may provide a sample and hold structure that maintains a previous state of an output during a CMTI event. The techniques and designs disclosed herein have been tested and can perform up to about 30ns CMTI durations, thus providing a wide coverage range for CMTI (e.g., from about 5V / ns to about 300V / ns).

[0060] The techniques and designs provided herein can provide a system that is configured to withstand CMRFI events with various frequencies and peak-to-peak amplitude ranges. The techniques and designs can include adding additional offsets to the input signal pairs and through a resistor averaging circuit that compares the output of the amplifier with the offset and the average of the resistor averaging circuit. The techniques and designs provided herein can be implemented using a pair of electrical isolators for bidirectional communication.

[0061] Figure 1 An exemplary system infrastructure for a vehicle including a combined inverter and converter according to one or more embodiments is depicted. In the context of the present disclosure, the combined inverter and converter may be referred to as an inverter. Figure 1As shown, the electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include a component for receiving electric power from an external source and outputting electric power to charge the battery 195 of the electric vehicle 100. For example, the inverter 110 may convert DC power from the battery 195 in the electric vehicle 100 into AC power to drive the motor 190 of the electric vehicle 100, but the embodiment is not limited thereto. For example, the inverter 110 may be bidirectional and may convert DC power into AC power, or convert AC power into DC power, such as during regenerative braking. The inverter 110 may be a three-phase inverter, a single-phase inverter, or a multi-phase inverter.

[0062] Figure 2 Depicted is a method for providing a point-of-use switching controller according to one or more embodiments. Figure 1 The electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include an inverter controller 300 ( Figure 3 14). The inverter 110 may include a low voltage upper phase controller 120 separated from a high voltage upper phase controller 130 by an electrical isolator 150, and an upper phase power module 140. The upper phase power module 140 may include a point-of-use upper phase controller 142 and an upper phase switch 144. The inverter 110 may include a low voltage lower phase controller 125 separated from a high voltage lower phase controller 135 by an electrical isolator 150, and a lower phase power module 145. The lower phase power module 145 may include a point-of-use lower phase controller 146 and a lower phase switch 148. The upper phase switch 144 and the lower phase switch 148 may be connected to a motor 190 and a battery 195. The electrical isolator 150 may be one or more of optical, converter-based, or capacitor-based isolation. For example, the electrical isolator 150 may be one or more capacitors having a value from about 20 fF to about 100 fF, having a breakdown voltage from about 6 kV to about 12 kV. The electrical isolator 150 may include a pair of capacitors, wherein one capacitor in the pair carries a 180 degree phase shifted data signal from the other capacitor in the pair to form a differential signal that is rejected for common mode noise. The electrical isolator 150 may include more than one capacitor in series. The electrical isolator 150 may include one capacitor located on a first IC, or may include a first capacitor located on a first IC and a second capacitor located on a second IC that communicates with the first IC.

[0063] The inverter 110 may include a low voltage region (e.g., where the voltage is typically less than 5V) and a high voltage region (e.g., where the voltage may exceed 500V). The low voltage region may be separated from the high voltage region by an electrical isolator 150. The inverter controller 300 may be in the low voltage region of the inverter 110, and may send a signal to and receive a signal from the low voltage upper phase controller 120. The low voltage upper phase controller 120 may be in the low voltage region of the inverter 110, and may send a signal to and receive a signal from the high voltage upper phase controller 130. The low voltage upper phase controller 120 may send a signal to and receive a signal from the low voltage lower phase controller 125. The high voltage upper phase controller 130 may be in the high voltage region of the inverter 110. Therefore, the signal between the low voltage upper phase controller 120 and the high voltage upper phase controller 130 passes through the electrical isolator 150. The high voltage upper phase controller 130 may send signals to and receive signals from a point-of-use upper phase controller 142 in the upper phase power module 140. The point-of-use upper phase controller 142 may send signals to and receive signals from an upper phase switch 144. The upper phase switch 144 may be connected to a motor 190 and a battery 195. For example, the upper phase switch 144 and the lower phase switch 148 may be used to transfer energy from the motor 190 to the battery 195, from the battery 195 to the motor 190, from an external source to the battery 195, or from the battery 195 to an external source. The lower phase system of the inverter 110 may be similar to the upper phase system described above.

[0064] Figure 3 Describes a method for Figure 2 FIG. 3 is an exemplary system infrastructure of an inverter controller 300 . The inverter controller 300 may include one or more controllers.

[0065] The inverter controller 300 may include a set of instructions that can be executed to cause the inverter controller 300 to perform any one or more of the methods or computer-based functions disclosed herein. The inverter controller 300 may operate as a standalone device, or may be connected to other computer systems or peripheral devices, for example using a network.

[0066] In a networked deployment, the inverter controller 300 can operate in the capacity of a server, or as a client in a server-client user network environment, or as a peer computer system in a peer (or distributed) network environment. The inverter controller 300 can also be implemented as or incorporated into various devices, such as a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile device, a palmtop computer, a laptop computer, a desktop computer, a communication device, a wireless phone, a landline phone, a control system, a camera, a scanner, a fax machine, a printer, a pager, a personal trusted device, a network device, a network router, a switch or bridge, or any other machine capable of executing a set of instructions (sequentially or otherwise) (the set of instructions specifies the actions to be taken by the machine). In a specific implementation, the inverter controller 300 can be implemented using an electronic device that provides voice, video or data communication. Further, although the inverter controller 300 is illustrated as a single system, the term “system” should also be understood to include any collection of systems or subsystems that individually or jointly execute one or more sets of instructions to perform one or more computer functions.

[0067] like Figure 3 As shown, the inverter controller 300 may include a processor 302, such as a central processing unit (CPU), a graphics processing unit (GPU), or both. The processor 302 may be a component in a variety of systems. For example, the processor 302 may be part of a standard inverter. The processor 302 may be one or more general-purpose processors, digital signal processors, application-specific integrated circuits, field programmable gate arrays, servers, networks, digital circuits, analog circuits, combinations thereof, or other devices now known or later developed for analyzing and processing data. The processor 302 may implement a software program, such as a manually generated (i.e., programmed) code.

[0068] The inverter controller 300 may include a memory 304 that can communicate via a bus 308. The memory 304 may be a main memory, a static memory, or a dynamic memory. The memory 304 may include, but is not limited to, computer-readable storage media, such as various types of volatile and non-volatile storage media, including but not limited to random access memory, read-only memory, programmable read-only memory, electrically programmable read-only memory, electrically erasable read-only memory, flash memory, tape or disk, optical media, etc. In one specific implementation, the memory 304 includes a cache or random access memory for the processor 302. In an alternative specific implementation, the memory 304 is separated from the processor 302, such as a cache memory, system memory, or other memory of the processor. The memory 304 may be an external storage device or database for storing data. Examples include a hard drive, a compact disk ("CD"), a digital video disk ("DVD"), a memory card, a memory stick, a floppy disk, a universal serial bus ("USB") storage device, or any other device operable to store data. The memory 304 is operable to store instructions that can be executed by the processor 302. The functions, actions, or tasks illustrated in the figures or described herein may be performed by the processor 302 executing instructions stored in the memory 304. The functions, actions, or tasks are not related to a particular type of instruction set, storage medium, processor, or processing strategy, and may be performed by software, hardware, integrated circuits, firmware, microcode, etc. operating alone or in combination. Likewise, processing strategies may include multi-processing, multi-tasking, parallel processing, etc.

[0069] As shown, the inverter controller 300 may further include a display 310, such as a liquid crystal display (LCD), an organic light emitting diode (OLED), a flat panel display, a solid state display, a cathode ray tube (CRT), a projector, a printer, or other display devices known now or later developed for outputting the determined information. The display 310 may serve as an interface for a user to view the operation of the processor 302, or specifically serve as an interface with the software stored in the memory 304 or in the drive unit 306.

[0070] Additionally or alternatively, the inverter controller 300 may include an input device 312 configured to allow a user to interact with any of the components of the inverter controller 300. The input device 312 may be a numeric keypad, a keyboard or a cursor control device (such as a mouse or a joystick), a touch screen display, a remote control, or any other device operable to interact with the inverter controller 300.

[0071] The inverter controller 300 may also or alternatively include a drive unit 306 implemented as a disk or optical drive. The drive unit 306 may include a computer-readable medium 322 in which one or more sets of instructions 324 (e.g., software) may be embedded. Further, the instructions 324 may embody one or more of the methods or logics described herein. The instructions 324 may reside completely or partially within the memory 304 and / or within the processor 302 during execution by the inverter controller 300. The memory 304 and the processor 302 may also include computer-readable media as described above.

[0072] In some systems, the computer-readable medium 322 includes instructions 324 or receives and executes instructions 324 in response to a propagated signal, so that a device connected to the network 370 can transmit voice, video, audio, images, or any other data through the network 370. Further, the instructions 324 can be transmitted or received through the network 370 and / or using the bus 308 via the communication port or interface 320. The communication port or interface 320 can be part of the processor 302 or can be an independent component. The communication port or interface 320 can be formed in software or can be a physical connector in hardware. The communication port or interface 320 can be configured to connect to the network 370, external media, display 310, or any other component in the inverter controller 300, or a combination thereof. The connection to the network 370 can be a physical connection (such as a wired Ethernet connection) or can be established wirelessly, as described below. Similarly, additional connections to other components of the inverter controller 300 can be physical connections or can be established wirelessly. The network 370 can alternatively be directly connected to the bus 308.

[0073] Although the computer-readable medium 322 is shown as a single medium, the term "computer-readable medium" may include a single medium or multiple media (such as a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" may also include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processor or causing a computer system to perform any one or more of the methods or operations disclosed herein. The computer-readable medium 322 may be non-transitory and may be tangible.

[0074] Computer readable medium 322 may include solid-state memory, such as a memory card or other package that accommodates one or more non-volatile read-only memories. Computer readable medium 322 may be random access memory or other volatile rewritable memory. Additionally or alternatively, computer readable medium 322 may include magneto-optical or optical media, such as a disk or tape or other storage device for capturing carrier signals (such as signals transmitted through a transmission medium). Digital file attachments to emails or other self-contained information archives or archive sets may be considered distribution media as tangible storage media. Therefore, the present disclosure is considered to include any one or more of computer-readable media or distribution media and other equivalents and successor media in which data or instructions may be stored.

[0075] In alternative implementations, dedicated hardware implementations (such as application specific integrated circuits, programmable logic arrays, and other hardware devices) may be constructed to implement one or more of the methods described herein. Applications that may include the apparatus and systems of various implementations may broadly include a variety of electronic and computer systems. One or more implementations described herein may use two or more specific interconnected hardware modules or devices with associated control and data signals that may be transmitted between and through the modules or as part of an application specific integrated circuit to implement functionality. Thus, the present system encompasses software, firmware, and hardware implementations.

[0076] The inverter controller 300 may be connected to a network 370. The network 370 may define one or more networks, including wired or wireless networks. The wireless network may be a cellular telephone network, an 802.11, 802.16, 802.20, or WiMAX network. Further, such networks may include public networks (such as the Internet), private networks (such as intranets), or combinations thereof and may utilize a variety of networking protocols that are now available or later developed, including but not limited to TCP / IP-based networking protocols. The network 370 may include a wide area network (WAN) (such as the Internet), a local area network (LAN), a campus area network, a metropolitan area network, a direct connection (such as through a universal serial bus (USB) port), or any other network that allows data communication. The network 370 may be configured to couple one computing device to another computing device to enable data communication between devices. The network 370 may generally be enabled to use any form of machine-readable media to transmit information from one device to another. The network 370 may include a communication method by which information can travel between computing devices. The network 370 may be divided into subnetworks. A subnetwork may allow access to all other components connected to it, or a subnetwork may restrict access between components. Network 370 may be considered a public or private network connection and may include, for example, a virtual private network or encryption or other security mechanisms employed over the public Internet.

[0077] According to various implementations of the present disclosure, the methods described herein may be implemented by a software program that can be executed by a computer system. Further, in an exemplary non-limiting implementation, the implementation may include distributed processing, component or object distributed processing, and parallel processing. Alternatively, a virtual computer system process may be constructed to implement one or more of the methods or functionalities described herein.

[0078] Although this specification describes components and functions that can be implemented in a specific implementation with reference to specific standards and protocols, the present disclosure is not limited to such standards and protocols. For example, standards for Internet and other packet-switched network transmissions (e.g., TCP / IP, UDP / IP, HTML, HTTP) represent examples of the prior art. Such standards are periodically replaced by faster or more efficient equivalents having substantially the same functionality. Therefore, alternative standards and protocols having the same or similar functionality as those disclosed herein are considered equivalents thereof.

[0079] It will be appreciated that, in one embodiment, the operations of the methods discussed are performed by an appropriate processor (or processors) of a processing (i.e., computer) system executing instructions (computer readable code) stored in a storage device. It will also be appreciated that the present disclosure is not limited to any particular implementation or programming technique, and that the present disclosure may be implemented using any suitable technique for implementing the functionality described herein. The present disclosure is not limited to any particular programming language or operating system.

[0080] Figure 4 Describes a method for Figure 2 An exemplary system infrastructure of a point-of-use switching controller. For a three-phase inverter, each of the upper phase and the lower phase may include three phases related to phases A, B, and C. For example, the upper phase power module 140 may include an upper phase power module 140A for upper phase A, an upper phase power module 140B for upper phase B, and an upper phase power module 140C for upper phase C. The upper phase power module 140A may include a point-of-use upper phase A controller 142A and an upper phase A switching element 144A. The upper phase power module 140B may include a point-of-use upper phase B controller 142B and an upper phase B switching element 144B. The upper phase power module 140C may include a point-of-use upper phase C controller 142C and an upper phase C switching element 144C. Each of the upper phase A switching member 144A, the upper phase B switching member 144B, and the upper phase C switching member 144C may be connected to the motor 190 and the battery 195 . Figure 4 Details of the upper phase power module 140 are depicted. Although not shown, the lower phase power module 145 may include a similar structure as the upper phase power module 140 for the lower phases A, B, and C.

[0081] Figure 5 Describes a method for Figure 4 Example system infrastructure for the upper power module. For example, Figure 5 Additional details of upper phase power module 140A are provided. Although not shown, upper phase power module 140B, upper phase power module 140C, and respective lower phase power modules of lower phase power module 145 may include components related to Figure 5 The upper phase power module 140A shown in FIG. 1 is similar in structure to the upper phase power module 140A shown in FIG. 1. In addition, the terms "upper", "lower", "northern", and "southern" as used in this disclosure are used for reference only, do not limit the elements to a particular orientation, and are generally interchangeable throughout the text. For example, the upper phase power module 140 may be referred to as a lower phase power module, a northern phase power module, a southern phase power module, a first phase power module, or a second phase power module.

[0082] The upper phase power module 140A may include a point-of-use upper phase A controller 142A and an upper phase A switch 144A. The upper phase A switch 144A may include one or more sets of switches. Figure 5 As shown, the upper phase A switch 144A may include an upper phase A north switch 144A-N and an upper phase A south switch 144A-S. The point-of-use upper phase A controller 142A may include one or more memories, controllers, or sensors. For example, the point-of-use upper phase A controller 142A may include a communication manager 405, a functional safety controller 410, a test interface and controller 415, a north thermal sensor 420A, a south thermal sensor 420B, a self-test controller 425, a command manager 430, a waveform adjuster 435, a memory 440, a north switch control and diagnostic controller 450N, and a south switch control and diagnostic controller 450S. The point-of-use upper phase A controller 142A may include a controller 405, a functional safety controller 410, a test interface and controller 415, a north thermal sensor 420A, a south thermal sensor 420B, a self-test controller 425, a command manager 430, a waveform adjuster 435, a memory 440, a north switch control and diagnostic controller 450N, and a south switch control and diagnostic controller 450S. Figure 5 More or fewer components than those shown. For example, the point-of-use upper phase A controller 142A may include more or less than two switch controls and diagnostic controllers, and may include more than two thermal sensors.

[0083] The communication manager 405 may control inter-controller communications to and from the point-of-use upper phase A controller 142A and / or may control intra-controller communications between components of the point-of-use upper phase A controller 142A. The functional safety controller 410 may control safety functions of the point-of-use upper phase A controller 142A. For example, the test interface and controller 415 may control test functions of the point-of-use upper phase A controller 142A, such as end-of-line testing in manufacturing. The north thermal sensor 420A may sense the temperature at a first location in the point-of-use upper phase A controller 142A, and the south thermal sensor 420B may sense the temperature at a second location in the point-of-use upper phase A controller 142A. For example, the self-test controller 425 may control self-test functions of the point-of-use upper phase A controller 142A, such as during initialization of the point-of-use upper phase A controller 142A after an inverter 110 power-on event. The command manager 430 may control commands received from the communication manager 405 and issued to the north switch control and diagnostic controller 450N and the south switch control and diagnostic controller 450S. The waveform adjuster 435 may control the waveform timing and shape of the commands received from the communication manager 405 and issued to the north switch control and diagnostic controller 450N and the south switch control and diagnostic controller 450S. The memory 440 may include one or more volatile and non-volatile storage media for the operation of the point-of-use upper phase A controller 142A. The north switch control and diagnostic controller 450N may send one or more signals to the north switch 144A-N to control the operation of the north switch 144A-N, and may receive one or more signals from the north switch 144A-N that provide information about the north switch 144A-N. The south switch control and diagnostic controller 450S may send one or more signals to the south switches 144A-S to control the operation of the south switches 144A-S, and may receive one or more signals from the south switches 144A-S providing information about the south switches 144A-S. As described above, the terms "north" and "south" are used for reference only, and the north switch control and diagnostic controller 450N may send one or more signals to the south switches 144A-S, and the south switch control and diagnostic controller 450S may send one or more signals to the south switches 144A-N.

[0084] For example, Figure 6An exemplary method 600 for reducing interference effects (such as one or more of CMRFI, CMTI, or LD-CMTI) is depicted. In operation 602, a pulse transceiver (e.g., a controller transceiver) may generate a first pulse and a second pulse based on a main pulse. The first pulse and the second pulse may be generated based on, for example, a power supply amplitude voltage and a PWM input signal relative to a ground signal. The first pulse and the second pulse may be generated by the pulse transceiver to control an input sense terminal and / or to indicate that a subsequent control signal will be received by a gate. For example, the input terminal of the power device may be an upper phase switch 144. The pulse transceiver may be located at a low voltage section of an electrical system. For example, referring to Figure 2 , the low voltage upper phase controller 120 may receive a PWM input signal including a main pulse from the inverter controller 300 , and may generate a first pulse and a second pulse based on the received main pulse.

[0085] For example, the first pulse and the second pulse generated at the pulse transceiver in operation 602 can be complementary signals to each other. The first pulse and the second pulse can be transmitted via two different electrical paths, including a first path for the first pulse and a second path for the second pulse. In operation 604, the first pulse can be received at the first electrical isolator via the first path, and the second pulse can be received at the second electrical isolator via the second path. The first path and / or the first electrical isolator can be physically separated from the second path and / or the second electrical isolator and placed close to each other so that any noise affecting them can be interpreted as a common mode signal by the receiver. For example, the distance between the first electrical isolator and the second electrical isolator can be a maximum distance so that the electrical interference (e.g., generated via an electrical component) has a first effect on the first pulse at the first electrical isolator and has a second effect on the second pulse at the second electrical isolator that is the same as the first effect. For example, the first effect and the second effect can be, for example, changes in signal characteristics, such as changes in frequency or changes in amplitude. The difference between the first effect and the second effect can meet a detection threshold to be detected by a comparator, as further discussed herein.

[0086] In operation 606, a first galvanic isolator pulse may be output from the first galvanic isolator and received at the amplifier, and a second galvanic isolator pulse may be output from the second galvanic isolator and received at the amplifier. Thus, the amplifier may receive the first pulse and the second pulse after the first pulse and the second pulse traverse the first and second paths, respectively, and pass through the first and second galvanic isolators, respectively.

[0087] In operation 608, the amplifier may amplify the first electrical isolator pulse and the second electrical isolator pulse based on one or more amplifier characteristics. For example, the amplifier may increase the voltage, current and / or power of the first electrical isolator pulse and the second electrical isolator pulse, respectively. The amplifier may include a trimmer. In operation 608, the amplifier may use a trimmer to trim the first electrical isolator pulse and the second electrical isolator pulse. The amplifier may include one or more electrical components for filtering noise signals. Therefore, the amplifier may filter the noise frequency from the first electrical isolator pulse and the second electrical isolator pulse. The one or more electrical components of the amplifier may be configured to filter signals outside a given frequency range. For example, the amplifier may include one or more tunable bandpass filters, one or more tunable low-pass filters, one or more tunable high-pass filters, one or more tunable notch filters, or any combination thereof. For example, after the first amplification stage, the amplified output may be fed to a filter. The cutoff frequency and order of the filter may be set based on the noise frequency that should be discarded. For example, if the data rate is 50 MHz and noise below 30 MHz should be rejected, the filter may include a bandpass filter centered at approximately 50 MHz. The trimmer may be dynamically adjustable to apply a known offset between the DC values ​​of the first electrical isolator and the second electrical isolator. The dynamic trimming operation may include adjusting the DC offset between the first electrical isolator and the second electrical isolator, which may be adjusted by dynamically changing the load resistor or the aspect ratio of the input pair. A known number of pulses may be fed to the low voltage side PWM input, or the low voltage controller may generate a known number of pulses during the trimming routine. A sinusoidal noise signal with a predetermined amplitude and frequency may be applied to the high voltage ground. The number of pulses may be counted at the output of the high voltage receiver and may be used to adjust the load resistor or aspect ratio if necessary, such as Fig. 9 as described in the description.

[0088] In operation 610, the amplifier may output a first amplified trimmed pulse corresponding to the first electrical isolator pulse, and may output a second amplified trimmed pulse corresponding to the second electrical isolator pulse. Although the amplified trimmed pulse is generally discussed herein, the amplified pulse and / or the trimmed pulse may be output by the amplifier based on the operation performed at the amplifier. For example, the electrical isolator pulse may be amplified to generate the amplified pulse, or the electrical isolator pulse may be trimmed to generate the trimmed pulse. Each of the first amplified trimmed pulse and the second amplified trimmed pulse may be provided to a comparator. The comparator may include one or more electrical components for comparing the signal characteristics of the first amplified trimmed pulse with the signal characteristics of the second amplified trimmed pulse. For example, the comparator may compare one or more of the amplitude, frequency, or phase of the first amplified trimmed pulse and the second amplified trimmed pulse.

[0089] In operation 612, the comparator may determine whether the difference in the signal characteristic of the first amplified trimmed pulse and the signal characteristic of the second amplified trimmed pulse is within a threshold difference. For example, the threshold difference may be a function of the size of the electrical isolation capacitor or the frequency and amplitude of the coupled noise from the high voltage side. When the difference in the signal characteristic of the first amplified trimmed pulse and the signal characteristic of the second amplified trimmed pulse is below the threshold difference, the comparator may take a first mitigation action, which may include outputting the first amplified trimmed pulse and the second amplified trimmed pulse to a pulse reshaping and envelope detector. Alternatively, when the difference in the signal characteristic of the first amplified trimmed pulse and the signal characteristic of the second amplified trimmed pulse is above the threshold difference, then the comparator may take a second mitigation action, which is different from the first mitigation action. The second mitigation action may include, for example, hysteresis. As discussed herein, hysteresis may be used to prevent the use of input pulses that exhibit rapid continuous changes (e.g., based on signal interference, as discussed herein).

[0090] According to one or more embodiments, the comparator may include or may be connected to a resistor averaging circuit. The resistor averaging circuit may be part of the comparator or may be separated from the comparator. The resistor averaging circuit may provide an average value of the signals received from the two amplifiers, and an offset may be added to the averaged signal. The averaged signal may then be compared with a separate amplifier signal. Because the outputs of the amplifiers are complementary, only valid signals (e.g., signals greater than 60 mV) at the input of the amplifier will have sufficient amplification at the output of the amplifier stage to pass over the averaged signal with an offset generated by the resistor averaging circuit. Any error signal generated due to CMRFI or CMTI will not have sufficient amplitude to pass over the averaged signal with an offset. For example, the resistor averaging circuit may add an additional offset of approximately 100 mV. The outputs of the two comparators may be provided to an AND gate so that only the complementary signal at the input of the first stage amplifier can pass. Therefore, the output of the resistor averaging circuit may be used to provide additional immunity to CMTI and CMRFI.

[0091] The resistor averaging circuit requires two complementary signals. The output of the amplifier is then passed through the resistor averaging circuit as described above. The output of the comparator present in the resistor averaging circuit is provided to the AND gate so that only the complementary signal at the input of the first stage amplifier can pass. Therefore, the envelope detector circuit will only see a pulse if the inputs of the amplifier are complementary.

[0092] According to one or more embodiments, a first galvanic isolator pulse and a second galvanic isolator pulse may be provided to an out-of-range detector (see Fig.10 ). The out of range detector may determine whether the amplitude of the first electrical isolator pulse and / or the second electrical isolator pulse is within a threshold amplitude range (e.g., from about 1V to about 2.6V). When the amplitude range of the first electrical isolator pulse and / or the second electrical isolator pulse is within the threshold amplitude range, then the out of range detector may transmit an in range indication. When the amplitude of the first electrical isolator pulse and / or the second electrical isolator pulse is not within the threshold amplitude range, then the out of range detector may transmit an out of range indication. The in range indication or the out of range indication may be received by the pulse reshaping and envelope detector.

[0093] When an in-range indication is received, the pulse reshaping and envelope detector may use the first amplified trimmed pulse and the second amplified trimmed pulse corresponding to the first electrical isolator pulse and the second electrical isolator pulse, respectively. Alternatively, when an out-of-range indication is received, the pulse reshaping and envelope detector may not use the first amplified trimmed pulse and / or the second amplified trimmed pulse corresponding to the first electrical isolator pulse and the second electrical isolator pulse, respectively. When an out-of-range indication is received, the pulse reshaping and envelope detector may maintain a current state (e.g., based on a previous in-range indication) to maintain or generate a PWM output signal. For example, the envelope detector may include a rectifier and an RC filter. By adjusting the pulse width or RC time constant, the envelope may be reshaped. The pulse stream may turn on or off two switches connecting a capacitor to a power supply or ground. By adjusting the duty cycle or RC time constant of the incoming data pulse, the envelope may be reshaped. The output of the rectifier may be further filtered, and the amplitude may be boosted to the full supply range before being output to the final comparator.

[0094] The pulse reshaping and envelope detector may generate a PWM output signal based on one or both of the first amplified trimmed pulse and the second amplified trimmed pulse. For example, the PWM output signal may be generated by reshaping the first amplified trimmed pulse and / or the second amplified trimmed pulse, by using one or both of the first amplified trimmed pulse and the second amplified trimmed pulse to generate the PWM signal. The generation of the PWM signal may include one or more of the following: by averaging both the first amplified trimmed pulse and the second amplified trimmed pulse, or by performing an operation on one or both of them to select one or the other. According to one or more embodiments, a signal associated with the first amplified trimmed pulse and / or the second amplified trimmed pulse (e.g., a signal transmitted by a pulse transceiver) may be included or otherwise used based on the PWM output signal.

[0095] It will be understood that any operation disclosed herein (e.g., such as reference Figure 6 The processes of the present invention are not limited to being performed in any particular order or sequence. As will be appreciated by those skilled in the art, any order or sequence disclosed herein is disclosed only as an example, and one or more of the operations (e.g., of a given process) may be performed in any applicable manner.

[0096] therefore, Figure 6The techniques disclosed in method 600 of can be used to mitigate or prevent the use of pulses that can be modified due to interference. These techniques can prevent or mitigate undesirable effects of one or more of CMTI, CMRI or LD-CMTI. These techniques may include comparing two parallel pulses generated by a pulse transceiver. The comparison may include determining a difference between the two parallel pulses, wherein the two parallel pulses may be identical, similar, complementary or reverse when generated at the pulse transceiver. Interference caused by an electrical component may cause a drift in the signal characteristics for the two parallel pulses, so that comparing the two parallel pulses may identify the drift level (if any). For example, interference caused by an electrical component may have a different effect on a first electrical isolator and / or a first electrical isolator signal when compared to a physically remote second electrical isolator and / or a corresponding second electrical isolator signal. When a difference above a threshold difference is detected, it may be determined that an undesirable interference effect exists. An output signal cannot be generated based on a pulse that exhibits such an interference effect. Therefore, a circuit according to the techniques disclosed herein cannot generate an output (e.g., a PWM output) based on a pulse signal that exhibits an undesirable interference effect.

[0097] Figure 7 An exemplary phase controller 700 in accordance with the disclosed subject matter is depicted. For example, referring to Figure 2 , the phase controller 700 may be a specific implementation of the low voltage upper phase controller 120 and the high voltage upper phase controller 130. Figure 7As shown, the phase controller 700 may include a low voltage region 702 and a high voltage region 704. The low voltage region 702 and the high voltage region 704 may be specific implementations of the low voltage upper phase controller 120 and the high voltage upper phase controller 130, respectively. The low voltage region 702 may include a low voltage component relative to the high voltage region 704, connected to the low voltage component, or otherwise associated with the low voltage component. The low voltage region 702 may be referred to as the main region in this article, and the high voltage region 704 may be referred to as the secondary region in this article. The low voltage region 702 may include a pulse transceiver 706. The pulse transceiver 706 may include one or more electrical components, which are configured to receive a signal including a main pulse based on the drain voltage VDDL 702A, the PWM input signal 702B and / or the reference ground GNDL 702C. For example, the PWM input signal 702B may be generated by the inverter controller 300. The pulse transceiver 706 may include one or more electrical components configured to output parallel pulses based on the main pulse. The pulse transceiver 706 may be configured to output parallel pulses via a first pulse path 706A and a second pulse path 706B. Therefore, the pulse transceiver 706 may output a first pulse in the parallel pulses via the first pulse path 706A and output a second pulse in the parallel pulses via the second pulse path 706B.

[0098] The first pulse may be received at the first electrical isolator 722 via the first pulse path 706A, and the second pulse may be received by the second electrical isolator 724 via the second pulse path 706B. For example, the first electrical isolator 722 and the second electrical isolator 724 may be a specific implementation of the electrical isolator 150. The first pulse path 706A and / or the first electrical isolator 722 may be physically separated from the second pulse path 706B and / or the second electrical isolator 724, as discussed herein. The first electrical isolator 722 may output a first electrical isolator pulse on the first electrical isolator path 722A, and the second electrical isolator 724 may output a second electrical isolator pulse on the second electrical isolator path 724A. As discussed herein, when there is interference (e.g., as generated by an electrical component included in, connected to, or otherwise associated with the high voltage region 704), the signal characteristics of the first electrical isolator pulse may be different from the signal characteristics of the first electrical isolator pulse due to the interference.

[0099] The first galvanic isolator pulse and the second galvanic isolator pulse may be received at amplifier 708 at high voltage region 704. Thus, the amplifier may receive the first pulse and the second pulse after they traverse first pulse path 706A and second pulse path 706B, respectively, through first galvanic isolator 722 and second galvanic isolator 724, respectively, and traverse first galvanic isolator path 722A and second galvanic isolator path 724A.

[0100] The amplifier 708 may amplify the first electrical isolator pulse and the second electrical isolator pulse based on one or more amplifier characteristics. For example, the amplifier 708 may increase the voltage, current and / or power of the first electrical isolator pulse and the second electrical isolator pulse, respectively. The amplifier 708 may include a first stage amplifier 708-1, a tunable filter 708-2, a second stage amplifier 708-3 and a trimmer 709. The amplifier 708 and / or the trimmer 709 may trim the first electrical isolator pulse and the second electrical isolator pulse. The tunable filter 708-2 may include one or more electrical components for filtering noise signals. Therefore, the tunable filter 708-2 may filter the noise frequency from the first electrical isolator pulse and the second electrical isolator pulse. The one or more electrical components of the tunable filter 708-2 may be configured to filter signals outside a given frequency range. For example, the tunable filter 708-2 may include, for example, one or more bandpass filters, one or more low-pass filters, one or more high-pass filters, or one or more notch filters. For example, the filter may be configured to remove known noise components (such as the upper phase switch 144) and / or may be configured to isolate a known signal.

[0101] The amplifier 708 may output a first amplified trimmed pulse corresponding to the first electrical isolator pulse via a first output path 708A, and may output a second amplified trimmed pulse corresponding to the second electrical isolator pulse via a second output path 708B. Each of the first amplified trimmed pulse and the second amplified trimmed pulse may be provided to a comparator 710 of the high voltage region 704. The comparator 710 may include one or more electrical components for comparing a signal characteristic of the first amplified trimmed pulse to the second amplified trimmed pulse. For example, the comparator 710 may compare one or more of the amplitude, frequency, or phase of the first amplified trimmed pulse and the second amplified trimmed pulse.

[0102] The comparator 710 can determine whether the difference in the signal characteristic of the first amplified trimmed pulse and the signal characteristic of the second amplified trimmed pulse is within a threshold difference. For example, the comparator 710 can use one or more electrical components (such as filters) to extract the signal characteristic of the first amplified trimmed pulse and the signal characteristic of the second amplified trimmed pulse. For example, the comparator 710 can be configured to compare the voltage, current and / or frequency of the first amplified trimmed pulse and the second amplified trimmed pulse to detect the difference between the first amplified trimmed pulse and the second amplified trimmed pulse.

[0103] When the difference in the signal characteristic of the first amplified trimmed pulse and the signal characteristic of the second amplified trimmed pulse is below a threshold difference, then the comparator 710 may take a first mitigation action. The first mitigation action may be a pass action performed by outputting the first amplified trimmed pulse to the pulse reshaping and envelope detector 712 via the first comparator output path 710A and outputting the second amplified trimmed pulse to the pulse reshaping and envelope detector via the second comparator output path 710B. Alternatively, when the difference in the signal characteristic of the first amplified trimmed pulse and the signal characteristic of the second amplified trimmed pulse is above the threshold difference, then the comparator 710 may take a second mitigation action, the second mitigation action being different from the first mitigation action. The second mitigation action may include, for example, performing hysteresis. As discussed herein, hysteresis may be used to prevent use of input pulses that exhibit rapid, continuous changes (e.g., based on signal interference, as discussed herein).

[0104] According to one or more embodiments, the comparator 710 may include or be connected to a resistor averaging circuit 750, such as Figure 8 The resistor averaging circuit 750 may be part of the comparator 710 or may be separate from the comparator 710. Figure 8As shown, a first input (e.g., a first amplified trimmed pulse or a second amplified trimmed pulse) may be received at a first amplifier 756A, and a second input (e.g., a first amplified trimmed pulse or a second amplified trimmed pulse) may be received at a second amplifier 756B. The first input and the second input may pass through an electrical path including one or more electrical components. The resistor averaging circuit 750 may include a plurality of resistors 752 configured to provide an offset difference between the first input and the second input (e.g., the first amplified trimmed pulse and the second amplified trimmed pulse), and which may be modified by one or more electrical components. The outputs 754A and 754B of the resistor averaging circuit may be used to determine a mitigation action to be performed at the comparator 710. Therefore, the outputs 754A and 754B of the resistor averaging circuit may be used to provide additional immunity to CMTI or CMRFI.

[0105] The mitigation action may cause the comparator 710 to output the first amplified trimmed pulse and the second amplified trimmed pulse. Alternatively, when the difference between the first amplified trimmed pulse and the second amplified trimmed pulse is above a threshold difference, the mitigation action may cause the comparator 710 to hold (e.g., via hysteresis) or prevent output of the two pulses. In this scenario, according to one or more embodiments, the comparator 710 may ignore the first amplified trimmed pulse and the second amplified trimmed pulse so that the first amplified trimmed pulse and the second amplified trimmed pulse are not used to generate the PWM output signal, as further discussed herein.

[0106] Also like Figure 7 As shown, the first electrical isolator pulse and the second electrical isolator pulse may be provided to an out of range detector 714. The out of range detector 714 may determine whether the amplitude of the first electrical isolator pulse and / or the second electrical isolator pulse is within a threshold amplitude range. The threshold amplitude may be, for example, from about 1V to about 2.6V. When the amplitude of the first electrical isolator pulse and / or the second electrical isolator pulse is within the threshold amplitude range, then the out of range detector may transmit an in range indication. When the amplitude of the first electrical isolator pulse and / or the second electrical isolator pulse is not within the threshold amplitude range, then the out of range detector may transmit an out of range indication. The in range indication or the out of range indication may be received by the pulse reshaping and envelope detector 712. When the in range indication is received, the pulse reshaping and envelope detector 712 may use a first amplified trimmed pulse and a second amplified trimmed pulse corresponding to the first electrical isolator pulse and the second electrical isolator pulse, respectively. Alternatively, when an out of range indication is received, the pulse reshaping and envelope detector 712 may not use the first amplified shaped pulse and / or the second amplified shaped pulse.

[0107] The pulse reshaping and envelope detector 712 may generate a PWM output signal 704B based on one or both of the first amplified trimmed pulse and the second amplified trimmed pulse. For example, the PWM output signal 704B may be generated by reshaping the first amplified trimmed pulse and / or the second amplified trimmed pulse, by using one or both of the first amplified trimmed pulse and the second amplified trimmed pulse to generate a PWM signal (e.g., by selecting one or the other, by averaging both, by performing an operation on one or both, etc.). According to one or more embodiments, a signal associated with the first amplified trimmed pulse and / or the second amplified trimmed pulse (e.g., a signal transmitted by a pulse transceiver) may be included or otherwise used based on the PWM output signal 704B. The PWM output signal 704B may be output with reference to the high voltage region 704 drain voltage VDDH 704A and / or the high voltage region 704 reference ground GNDH 704C.

[0108] Fig. 9 An exemplary trimming process 900 is depicted in accordance with one or more embodiments. In operation 905, a predetermined number of pulses may be fed to the pulse transceiver 706 (e.g., via the PWM input signal 702B), or the pulse transceiver 706 may generate the predetermined number of pulses during the trimming process. In operation 910, while the predetermined number of pulses are transmitted from the pulse transceiver 706 to the amplifier 708, a noise signal (such as a sinusoidal signal having a predetermined amplitude and frequency) may be applied to the high voltage region 704 reference ground GNDH 704C of the phase controller 700. In operation 915, while the noise signal is applied, the pulse reshaping and envelope detector 712 may count the number of pulses received from the pulse transceiver 706. In operation 920, the pulse reshaping and envelope detector 712 may compare the counted number of pulses with the predetermined number of pulses.

[0109] In operation 925, if the counted number of pulses is equal to the predetermined number of pulses, the pulse reshaping and envelope detector 712 may determine whether any pulses are received when no pulses are transmitted from the pulse transceiver 706 to the amplifier 708 and the noise signal is applied. In operation 930, if no pulses are received, the trimming value of the tunable filter 708-2 may be correct. In operation 935, if a pulse is received in operation 925, the trimming value of the tunable filter 708-2 may be increased (an increase in the DC offset between the first electrical isolator 722 and the second electrical isolator 724) by increasing the load resistor or the width / length aspect ratio of the input pair. The trimming process 900 may then proceed to operation 905 to recheck the trimming value.

[0110] In operation 940, if the counted number of pulses in operation 920 is less than the predetermined number of pulses, then in operation 945, the trim value of the tunable filter 708-2 may be reduced (a reduction in the DC offset between the first electrical isolator 722 and the second electrical isolator 724) by reducing the width / length aspect ratio of the load resistor or the input pair. The trimming process 900 may then proceed to operation 905 to recheck the trim value. In operation 940, if the counted number of pulses in operation 920 is greater than the predetermined number of pulses, the trimming process 900 may proceed to operation 935 to increase the trim value of the tunable filter 708-2, and then proceed to operation 905 to recheck the trim value.

[0111] Fig.10 Depicted is example operation 1000 of the out of range detector 714 in accordance with one or more embodiments. Fig.10 The waveform at the input of the out-of-range detector 714 is shown. The complementary signal forms the input of the first stage amplifier 708-1 and should be located within the in-range region 1020. A -CMTI or +CMTI event causes the DC operating point of the first stage amplifier 708-1 to be in the out-of-range region 1010 or 1030, which saturates the first stage amplifier 708-1. When the input signal is in the out-of-range region 1010 or 1030 during a CMTI event, the out-of-range detector 714 may send a signal to the pulse reshaping and envelope detector 712 to maintain the previous state. The out-of-range detector 714 may also detect when the signal is in the out-of-detection range 1040.

[0112] Fig.11 An exemplary out-of-range detector 714 is depicted in accordance with one or more embodiments. Fig.11 As shown, the input of amplifier 708 is also connected to out of range detector 714. When the input signal is in the out of range region 1010 or 1030 during a CMTI event, the comparator of out of range detector 714 may send a signal to pulse reshaping and envelope detector 712 to maintain the previous state.

[0113] Fig.12 An exemplary pulse reshaping and envelope detector 712 is depicted in accordance with one or more embodiments. Fig.12As shown, a simplified schematic diagram of the pulse reshaping and envelope detector 712 may include a rectifier 1210 and an RC filter 1220. The pulse stream switches on or off two switches that connect the capacitor to the VDD supply or ground. By adjusting the duty cycle (pulse width) or RC time constant of the incoming data pulse, the envelope can be reshaped. The output of the rectifier 1210 can be further filtered and the amplitude can be boosted to the full supply range before sending the signal to the final comparator.

[0114] One or more embodiments may address electromagnetic interference (EMI) that may impair the operation of an electrical transceiver. One or more embodiments may address a wide range of CMTI tolerances. One or more embodiments may address electromagnetic compatibility (EMC) issues that may impair the operation of an electrical transceiver, such as common mode radio frequency interference (CMRFI) generated due to radio frequency (RF) noise being coupled or induced into a high voltage (e.g., non-ground reference voltage) operating plane. One or more embodiments may address common mode noise rejection. One or more embodiments may address EMC issues including long duration common mode transient immunity (LD-CMTI) events, which may be longer in duration than conventional CMTI. One or more embodiments may address slew events that may last up to approximately 300 nanoseconds and may cause the input of the receiver to be driven out of range, which may interrupt communications for an extended period.

[0115] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

Claims

1. A system comprising: An inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter comprises: a first electrical isolator separating a low voltage region from a high voltage region, the first electrical isolator having a first electrical isolator output path; a second electrical isolator separating the low voltage region from the high voltage region, the second electrical isolator having a second electrical isolator output path; an amplifier connected to the first electrical isolator via the first electrical isolator output path and to the second electrical isolator via the second electrical isolator output path in the high voltage region, the amplifier having a first amplifier output path and a second amplifier output path; a comparator in the high voltage region and connected to the amplifier via the first amplifier output path and the second amplifier output path, the comparator having a first comparator output path and a second comparator output path; and A pulse reshaping and envelope detector is in the high voltage region and connected to the comparator via the first comparator output path and the second comparator output path.

2. The system according to claim 1, further comprising: A pulse transceiver is in the low voltage region, the pulse transceiver being connected to the first galvanic isolator via a first pulse transceiver output path and to the second galvanic isolator via a second pulse transceiver output path.

3. The system of claim 2, wherein the pulse transceiver, the amplifier, the comparator, and the pulse reshaping and envelope detector are configured to operate together to transmit a pulse width modulated signal from the low voltage region to the high voltage region. 4 . The system of claim 2 , wherein the pulse transceiver is configured to output a first pulse on the first pulse transceiver output path and to output a second pulse on the second pulse transceiver output path. 5 . The system of claim 4 , wherein the pulse transceiver is further configured to receive a main pulse and output the first pulse and the second pulse based on the received main pulse.

6. The system of claim 4, wherein: The first galvanic isolator is configured to receive the first pulse on the first pulse transceiver output path and transmit a first galvanic isolator pulse on the first galvanic isolator output path based on the received first pulse, and The second galvanic isolator is configured to receive the second pulse on the second pulse transceiver output path and to transmit a second galvanic isolator pulse on the second galvanic isolator output path based on the received second pulse.

7. The system of claim 6, wherein the amplifier is configured to: receiving the first galvanic isolator pulse on the first galvanic isolator output path, amplifying the first galvanic isolator pulse based on one or more characteristics of the amplifier, and transmitting a first amplified pulse on the first amplifier output path based on the amplified first galvanic isolator pulse, and The second galvanic isolator pulse is received on the second galvanic isolator output path, the second galvanic isolator pulse is amplified based on one or more characteristics of the amplifier, and a second amplified pulse is sent on the second amplifier output path based on the amplified second galvanic isolator pulse.

8. The system of claim 7, wherein the comparator is configured to: The first amplified pulse is received on the first amplifier output path, the second amplified pulse is received on the second amplifier output path, a comparison of the first amplified pulse and the second amplified pulse is performed, a first compared pulse is output on the first comparator output path based on the comparison, and a second compared pulse is output on the second comparator output path based on the comparison.

9. The system of claim 8, wherein the pulse reshaping and envelope detector is configured to: The first compared pulse is received on the first comparator output path, the second compared pulse is received on the second comparator output path, and an output pulse is output based on the first compared pulse and the second compared pulse.

10. The system of claim 1, wherein the amplifier comprises: Dresser, and Tunable filter.

11. The system of claim 1, further comprising: An out-of-range detector is connected to the first electrical isolator, the second electrical isolator and the pulse reshaping and envelope detector.

12. The system of claim 1, wherein the comparator further comprises a resistor averaging circuit.

13. The system of claim 1, further comprising: the battery, the battery being configured to supply the DC power to the inverter; as well as The motor is configured to receive the AC power from the inverter to drive the motor.

14. A method comprising: receiving, by one or more controllers, a first pulse, and transmitting, by the one or more controllers, a first electrical isolator pulse based on the first pulse; receiving, by the one or more controllers, a second pulse, and transmitting, by the one or more controllers, a second electrical isolator pulse based on the second pulse; receiving, by the one or more controllers, the first electrical isolator pulse and the second electrical isolator pulse; generating, by the one or more controllers, a first amplified pulse based on the first electrical isolator pulse and a second amplified pulse based on the second electrical isolator pulse; receiving, by the one or more controllers, the first amplified pulse and the second amplified pulse; comparing, by the one or more controllers, the first amplified pulse and the second amplified pulse; determining, by the one or more controllers, a mitigation action based on the comparison; as well as An output pulse is generated by the one or more controllers based on the mitigating action.

15. The method of claim 14, wherein determining the mitigation action comprises: determining, by the one or more controllers, a difference between one or more signal characteristics of the first amplified pulse and one or more signal characteristics of the second amplified pulse; comparing, by the one or more controllers, the difference to a difference threshold; as well as The mitigating action is determined by the one or more controllers based on comparing the difference to the difference threshold.

16. The method of claim 14, wherein generating the output pulse comprises: A previous signal state is maintained based on one or more of a previous first galvanic isolator pulse or a previous second galvanic isolator pulse.

17. The method of claim 14, further comprising: One or more of the first electrical isolator pulse or the second electrical isolator pulse is trimmed by the one or more controllers.

18. The method of claim 14, further comprising: One of an in-range indication or an out-of-range indication is determined by the one or more controllers based on the first electrical isolator pulse and the second electrical isolator pulse.

19. The method of claim 18, wherein generating the output pulse comprises: The output pulse is generated based on the one of the in-range indication or the out-of-range indication.

20. A system comprising: a first galvanic isolator configured to receive a first pulse from the pulse transceiver and output a first galvanic isolator pulse based on the received first pulse; a second galvanic isolator configured to receive a second pulse from the pulse transceiver and to generate a second galvanic isolator pulse based on the received second pulse; an amplifier configured to receive the first electrical isolator pulse and the second electrical isolator pulse, amplify the first electrical isolator pulse and the second electrical isolator pulse into a first amplified pulse and a second amplified pulse, respectively, and output the first amplified pulse and the second amplified pulse; a comparator configured to receive the first amplified pulse and the second amplified pulse, perform a comparison of the first amplified pulse and the second amplified pulse, and generate a first compared pulse and a second compared pulse, respectively, based on the comparison; as well as A pulse reshaping and envelope detector is configured to receive the first compared pulse and the second compared pulse and to generate an output pulse based on the first compared pulse and the second compared pulse.

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