Analog-to-digital conversion
By introducing base plate sampling and mismatch error shaping into SAR ADCs, using multiple DAC arrays and configuration switching, the ADC linearity and compatibility problems in the prior art are solved, achieving higher linearity and accuracy.
Patent Information
- Application Number
- CN202280099900.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-16
- Publication Date
- 2025-04-25
AI Technical Summary
Existing SAR ADCs have limitations in improving linearity, especially when using binary search and data-weighted average, the scaling of the DAC will reduce linearity performance. At the same time, conventional mismatch error shaping is only suitable for top plate sampling and is incompatible with bottom plate sampling.
An ADC that uses bottom plate sampling and mismatch error shaping is designed to achieve bottom plate sampling and mismatch error shaping by including multiple DAC arrays in the ADC and switching between two configurations. This design improves the linearity of the ADC, especially in the presence of mismatched capacitors.
Through base plate sampling and mismatch error shaping, the linearity and accuracy of the ADC are improved, the signal-to-noise distortion ratio (SNDR) is enhanced, and the compatibility problem of conventional methods in base plate sampling is solved.
Smart Images
Figure CN119895723A_ABST
Abstract
Description
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS Background Art
[0002] A successive approximation (SAR) analog-to-digital converter (ADC) uses a binary search to convert a continuous analog waveform into a discrete digital representation. The most significant bit (MSB) in the ADC is used as an approximation to which the sample value is compared. In a binary search, the MSB is half of the maximum value the ADC can provide. If the sample value is greater than the MSB, the MSB is retained and the next consecutive bit is added to the approximation. In a binary search, the next consecutive bit is half of the MSB. This process continues until the approximation of the retained bits is greater than the sample value. If the approximation is greater than the sample value, the most recently added bit is not retained to the approximation. As each individual bit is retained or excluded from the approximation, the approximation approaches the sample value.
[0003] Linearity, such as signal-to-noise-distortion ratio (SNDR), is an important metric that represents or can be used to determine the accuracy of an analog-to-digital conversion. One way to improve the linearity of a SAR ADC is by using data-weighted averaging (DWA) for the MSB. DWA involves switching between multiple capacitors of the same value. Using multiple capacitors of the same value can be helpful because (e.g., due to manufacturing errors) the average of multiple capacitors is more likely to be closer to the desired MSB value than a single capacitor. However, DWA is typically only used for temperature digital-to-analog converters (DACs) where the DAC is not scaled. When the DAC includes scaling such as binary scaling, the linearity performance of DWA is reduced.
[0004] Another method to improve the linearity of a SAR ADC involves the use of mismatch error shaping (MES). MES operates by sampling from the top plate of the ADC's capacitor to add the LSB error from the previous sample to the current input in the analog domain and remove the same error from the digital domain. However, conventional MES is only used for top plate sampling and is not compatible with bottom plate sampling. Summary of the invention
[0005] This specification describes an ADC that converts a continuous analog waveform to a discrete digital representation using backplane sampling. The ADC includes a first DAC array that provides the MSB of the conversion, and the ADC includes second and third DAC arrays, each of which can provide the LSB of the conversion. The ADC can be switched between two configurations, wherein in each configuration, one of the LSB DAC arrays provides the LSB of the conversion and the other LSB DAC array provides the error in the previous conversion. Switching between the two configurations allows the ADC to use backplane sampling, which provides high linearity, and involves mismatch error shaping, which improves the accuracy of the conversion in the presence of mismatched capacitors.
[0006] Certain embodiments of the subject matter described in this specification can be implemented to achieve one or more of the following advantages. For example, some embodiments improve the linearity of the conversion, such as by backplane sampling. Additionally, some embodiments reduce the error in the MSB of the conversion, such as by data weighted averaging. Another advantageous embodiment allows backplane sampling and mismatch error shaping, which further improves the linearity of the conversion.
[0007] In one aspect, an analog-to-digital (ADC) converter includes a most significant bit (MSB) digital audio converter (DAC) array, the MSB DAC array being configured to generate corresponding sample values for one or more most significant bits of an output analog value; a first least significant bit (LSB) DAC array, the first LSB DAC array being configured to generate corresponding sample values for one or more least significant bits of the output ADC value; and a second LSB DAC array, the second LSB DAC array being configured to generate corresponding sample values for one or more least significant bits of the output ADC value, wherein each of the first LSB DAC array and the second LSB DAC array is configured to alternate between generating output ADC bit values and mismatch error values for the output ADC bit values.
[0008] In some implementations, the MSB DAC array is configured to generate sample values using data-weighted averaging.
[0009] In some implementations, the first LSB DAC and the second LSB DAC are configured to generate respective sample values using backplane sampling.
[0010] In some implementations, the first LSB DAC and the second LSB DAC are configured to use mismatch error shaping with backplane sampling to generate respective sample values.
[0011] In some implementations, the MSB DAC array includes a plurality of capacitors having substantially the same value, each of the plurality of capacitors representing half of a maximum value generated by the analog-to-digital converter.
[0012] In some implementations, where the first LSB DAC array includes a plurality of capacitors having substantially different values, each of the plurality of capacitors has a value smaller than a most significant bit of the output ADC value.
[0013] In some implementations, each of the plurality of capacitors in the first LSB DAC array follows a multiplication sequence.
[0014] In some implementations, the first LSB DAC array includes a plurality of capacitors, and the second LSB DAC array includes a plurality of capacitors that are substantially the same as the capacitors of the first LSB DAC array.
[0015] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 is a diagram of an example system.
[0017] Figure 2A A simulation of an example system is shown.
[0018] Figure 2B It shows Figure 2A A plot of the signal-to-noise-distortion ratio of the system.
[0019] Figure 3 is a flow chart of an example process for sampling an analog-to-digital converter.
[0020] Figure 4 is the behavioral model of the ADC with backplane sampling.
[0021] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION
[0022] Figure 1 is a diagram of an example system 100. The system 100 includes an audio digital converter (ADC) 100 in a first configuration 102 and a second configuration 104. The system 100 can be switched between the first configuration 102 and the second configuration 104 to provide a successive approximation register (SAR) ADC with high linearity.
[0023] In a first configuration 102, a plurality of digital-to-analog converter (DAC) arrays 106, 108, 110 are electrically connected to a comparator 112. Each DAC array 106, 108, 110 includes a capacitor that can provide a voltage value to the comparator 112. The first DAC array 106 includes one or more capacitors having the same capacitance value, and thus each capacitor provides substantially the same voltage value to the comparator 112. Providing multiple capacitors having the same value can reduce errors caused by the capacitance value, for example, due to manufacturing tolerances. For example, data weighted averaging (DWA) can utilize multiple capacitors having substantially the same capacitance value to reduce errors from slight variations in capacitance value. Each capacitor in the first DAC array 106 represents the most significant bit (MSB) of the conversion. The MSB is half of the maximum value that the ADC can provide.
[0024] The second DAC array 108 includes one or more capacitors. In an implementation with multiple capacitors, each capacitor has a different capacitance value. For example, the capacitors can provide voltages that follow a multiplication sequence, for example, the capacitor values multiply along the array. In some examples, the voltages do not follow a multiplication sequence. For example, each capacitor can provide a voltage that is greater than the previous capacitor by a predetermined step value, such as one volt, ten volts, or 100 volts.
[0025] The capacitors in the second DAC array 108 represent the least significant bit (LSB) of the conversion. For example, the LSB can be any value less than the MSB. In some implementations, the MSB provides the largest bit in the binary search, and the LSB provides a bit smaller than the MSB. In other implementations, the MSB provides the largest bit in the binary search, and the LSB provides ten bits that are each smaller than the MSB. Each additional bit provided by the LSB makes the conversion more accurate. For example, the ADC is limited to the accuracy of the LSB, so providing ten bits in the LSB is more accurate than providing one bit. In some implementations, the LSB can provide one to ten additional bits.
[0026] The largest capacitor in the second DAC array 108 can provide half the capacitance of the capacitor in the first DAC array 106. For example, if the largest capacitor in the second DAC array provides 16 volts, each capacitor in the first DAC array can provide 32 volts. The third DAC array 110 array is substantially the same as the second DAC array 108 and contains capacitors with the same capacitance values as the second DAC array 108.
[0027] The system 100 in the first configuration 102 can use a binary search process to determine the digital output of the incoming signal sample 114. The comparator 112 compares the incoming signal sample 114 with an approximation of a first capacitance value provided by one of the capacitors in the first DAC array 106. If the comparator determines that the sample value is greater than the first capacitance provided by the first DAC array 106, the first capacitance is retained and the second capacitance provided by the largest capacitor in the second DAC array is added to the approximation. However, if the comparator determines that the sample value is not greater than the first capacitance, the first capacitance is omitted and the sample is compared to the approximation of the second capacitance. This process is repeated until all capacitors in the second DAC array have been added to the approximation or omitted from the approximation. Each configuration 102, 104 operates by sampling the bottom plate of the capacitors in the DAC array. Sampling the bottom plate is advantageous and increases the linearity of the conversion.
[0028] The error in the capacitance value of the capacitor (e.g., due to manufacturing tolerance) can cause the ADC to have a corresponding error in the conversion. This error is also called a mismatch error. The system 100 allows the error in the LSB to be subtracted from the next sequential sample in the backplane sampling by providing two configurations 102, 104 and switching between the two configurations 102, 104, for example, with a switch after each iteration of sampling. For example, the configuration 102 provides a second input 116 to the third DAC array 110, which can provide a voltage corresponding to the error of the LSB in the previous sample. In the next iteration, the system utilizes the configuration 104. In the configuration 104, the second input 118 is provided to the second DAC array 108. The second input 118 provides a voltage corresponding to the error of the LSB in the previous sample. In other words, for each iteration in which the second DAC array is used, for example, by successive approximation to approximate the value of the sample, the third DAC array receives the previous error in the LSB as input 116. For each iteration in which the third DAC array is used to approximate the value of the sample, the second DAC array receives the previous error in the LSB as input 118. These additional inputs and the DAC array allow errors in the LSB to be taken into account while also providing backplane sampling. Both of these features improve the linearity of the conversion, for example, thereby improving the SNDR and accuracy of the conversion.
[0029] Figure 11, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 116, 114, 116, 124, 124, 124, 130, 114, 116, 124, 130, 1 This process is repeated for each cycle of the sampling, for example, cycle N, N+1.
[0030] Figure 2A The results of a simulation of an analog-to-digital converter 200 using the techniques described in this specification are shown. The ADC 200 has capacitors with values that simulate manufacturing variations that would be encountered when using an actual physical device. Ideally, the capacitors would provide their exact expected capacitance values. However, in real-world systems, capacitors may provide values that are slightly different from the expected capacitance values. The different values in the simulated converter 200 simulate differences in capacitance values, such as due to manufacturing tolerances. In the ADC 200, the first capacitor 202 provides a capacitance value that is four-fifths of the capacitance value of the corresponding capacitor 204. The first capacitor 202 and the second capacitor 204 may have the same expected value. Similarly, the third capacitor 206 provides a capacitance value that is three-fifths of the capacitance value of the corresponding capacitor 208, even though the third capacitor 206 and the fourth capacitor 208 may have the same expected value. The simulated converter 200 provides a simulation of a real-world converter by providing capacitors with slightly different values.
[0031] Figure 2BThe linearity of ADC 200 using different sampling techniques, in particular SNDR, is shown. For example, sample 210 shows the SNDR of ADC 200 without using the above-mentioned technique. Sample 210 shows the SNDR of the ADC without compensating the mismatch error between capacitors 202, 204 and between capacitors 206, 208. SNDR is calculated by integrating the noise and distortion from 0 kHz to 20 kHz. As shown, the SNDR of sample 210 is 56.6 decibels (dB). After converting the received signal and providing the desired signal 212, sample 210 also provides a plurality of undesirable signals 214, which correspond to harmonics such as 3rd order harmonics, 5th order harmonics, etc. Each of the undesirable signals 214 reduces the linearity and SNDR of sample 210.
[0032] In contrast, sample 216 shows the SNDR of ADC 200 when using the above-described technique (i.e., switching between the first configuration and the second configuration to subtract the error in the LSB). Sample 216 shows the SNDR of the ADC when compensating for the errors between capacitors 202, 204 and between capacitors 206, 208. As shown, the SNDR of sample 214 is 71.1 dB. After providing the desired signal 212, sample 216 does not provide the undesired signal 214 provided by sample 210. The reduction of the undesired signal 214 significantly increases the linearity and SNDR of sample 216, indicating that sample 216 is a more accurate conversion of the signal.
[0033] Figure 3 A flow chart of an example process 300 for sampling an analog-to-digital converter is shown. The example process may be performed by one or more components of the analog-to-digital converter. The example process will be described as being performed by, for example, a component configured accordingly according to the present specification. Figure 1 The ADC 100 performs
[0034] First, the ADC receives an analog signal in a first configuration (302). For example, the first configuration can be similar to configuration 102 of system 100 described above. The first configuration can operate by sampling the bottom plates of capacitors in the DAC array. Sampling the bottom plates is advantageous and increases the linearity of the conversion.
[0035] The ADC determines a digital output for the received analog signal (304). For example, determining the digital output may include successive approximation. As described above, the ADC may include a plurality of DAC arrays to determine the digital output through a binary search process.
[0036] The ADC determines an error in the digital output (306). For example, determining the error may include determining an error in the LSB of the sample. Determining the error in the LSB may include maintaining a previous LSB code during sampling, i.e., which capacitors contribute to the approximation.
[0037] The ADC switches from the first configuration to the second configuration (308). For example, the second configuration may be similar to configuration 104 described above. The ADC may switch between the first configuration and the second configuration as described above.
[0038] The ADC receives an analog signal in a second configuration (310). For example, as described above, the second configuration may have an input to receive an analog signal.
[0039] The ADC provides a voltage corresponding to the determined error (312). For example, as described above, configuration 104 provides second input 118 to provide a voltage corresponding to the error of the LSB in the previous sample. In some implementations, the input voltage can be an error of the LSB with opposite polarity.
[0040] The ADC determines a digital output for the analog signal (314). When the ADC is provided with a previous mismatch error in LSB as an additional input, as described above, the determined digital output takes this error into account while also providing backplane sampling.
[0041] Figure 4 The behavioral model 400 of a SAR-ADC for backplane sampling is shown. For example, as described above, the ADC can ping-pong between two LSB DACs. Both mismatch errors can be first-order high-pass filtered. As shown, when either LSB DAC receives a signal, the previous error is added as an additional input. For example, in the DAC LSB [n-1] The signal 402 received at 404 has the previous error E added to it 1(或2) [n] 406. The next LSB signal 408 is at the DAC LSB [n] is received at 410, and the previous error E 2(或1) [n] 412 is added as an additional input. As shown in the figure, the error is 1(或2) 406 and E 2(或1) 412. This shows that the error corresponds to the opposite DAC because the process ping-ponged between the two LSB DACs.
[0042] Embodiments of the subject matter and functional operations described in this specification can be implemented in digital electronic circuit systems, in computer hardware including the structures disclosed in this specification and their structural equivalents, or in a combination of one or more of them. The processes and logic flows can also be performed by a dedicated logic circuit system such as an FPGA or ASIC, or by a combination of a dedicated logic circuit system and one or more programmed computers.
[0043] In addition to the above embodiments, the following embodiments are also innovative:
[0044] Embodiment 1 is an analog-to-digital converter (ADC), comprising:
[0045] a most significant bit (MSB) digital audio converter (DAC) array configured to generate corresponding sample values for one or more most significant bits of the output modulus value;
[0046] a first least significant bit (LSB) DAC array configured to generate corresponding sample values for one or more least significant bits of the output ADC value;
[0047] a second LSB DAC array configured to generate corresponding sample values for the one or more least significant bits of the output ADC value,
[0048] Each of the first LSB DAC array and the second LSB DAC array is configured to alternate between generating an output ADC bit value and a mismatch error value for the output ADC bit value.
[0049] Embodiment 2 is the ADC of embodiment 1, wherein the MSB DAC array is configured to generate the sample values using data weighted averaging.
[0050] Embodiment 3 is the ADC of any one of embodiments 1-2, wherein the first LSB DAC array and the second LSB DAC array are configured to generate the respective sample values using backplane sampling.
[0051] Embodiment 4 is the ADC of embodiment 3, wherein the first LSB DAC array and the second LSB DAC array are configured to use mismatch error shaping with backplane sampling to generate corresponding sample values.
[0052] Embodiment 5 is the ADC of embodiment 3, wherein the MSB DAC array includes a plurality of capacitors having substantially the same value, each of the plurality of capacitors representing half of a maximum value generated by the analog-to-digital converter.
[0053] Embodiment 6 is the ADC of any one of embodiments 1 to 5, wherein the first LSB DAC array comprises a plurality of capacitors having substantially different values, each of the plurality of capacitors having a value smaller than a most significant bit of the output ADC value.
[0054] Embodiment 7 is the ADC of any one of embodiments 1 to 6, wherein each of the plurality of capacitors in the first LSB DAC array follows a multiplication sequence.
[0055] Embodiment 8 is the ADC of any one of embodiments 1 to 7, wherein the first LSB DAC array includes a plurality of capacitors, and the second LSB DAC array includes a plurality of capacitors substantially the same as the capacitors of the first LSB DAC array.
[0056] Embodiment 9 is a method performed by an analog-to-digital converter (ADC), the method comprising:
[0057] generating corresponding sample values for one or more most significant bits of the output analog value by a most significant bit (MSB) digital audio converter (DAC) array of the ADC;
[0058] generating corresponding sample values for one or more least significant bits of the output ADC value by a first LSB DAC array of the ADC;
[0059] generating, by a second LSB DAC array of the ADC, corresponding sample values for the one or more least significant bits of the output ADC value; and
[0060] Each of the first LSB DAC array and the second LSB DAC array alternates between generating output ADC bit values and mismatch error values for the output ADC bit values.
[0061] Embodiment 10 is the method of embodiment 9, further comprising generating the sample values using data weighted averaging by the MSB DAC array.
[0062] Embodiment 11 is the method of any of embodiments 9-10, wherein generating the corresponding sample values by the first LSB DAC array and the second LSB DAC array comprises generating the sample values using backplane sampling.
[0063] Embodiment 12 is the method of embodiment 11, wherein generating the corresponding sample values by the first LSB DAC array and the second LSB DAC array comprises using mismatch error shaping with backplane sampling to generate the sample values.
[0064] Embodiment 13 is the method of embodiment 11, wherein the MSB DAC array includes a plurality of capacitors having substantially the same value, each of the plurality of capacitors representing half of a maximum value generated by the analog-to-digital converter.
[0065] Embodiment 14 is the method of any one of embodiments 9 to 13, wherein the first LSB DAC array comprises a plurality of capacitors having substantially different values, each of the plurality of capacitors having a value smaller than a most significant bit of the output ADC value.
[0066] Embodiment 15 is the method of any one of embodiments 9 to 14, wherein each of the plurality of capacitors in the first LSB DAC array follows a multiplication sequence.
[0067] Embodiment 16 is the method of any one of embodiments 9 to 15, wherein the first LSB DAC array includes a plurality of capacitors, and the second LSB DAC array includes a plurality of capacitors substantially the same as the capacitors of the first LSB DAC array.
[0068] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but should be interpreted as descriptions of features that may be specific to a particular embodiment of a particular invention. Certain features described in the context of a separate embodiment in this specification may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may involve a variant of a sub-combination or a sub-combination.
[0069] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order, or that all illustrated operations be performed to achieve the desired results. In some contexts, multitasking and parallel processing can be advantageous. In addition, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.
[0070] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. For example, the actions set forth in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some cases, multitasking and parallel processing can be advantageous.
Claims
1. An analog-to-digital converter ADC, comprising: a most significant bit (MSB) digital audio converter (DAC) array, the MSB DAC array being configured to generate corresponding sample values for one or more most significant bits of the output modulus value; a first least significant bit (LSB) DAC array configured to generate corresponding sample values for one or more least significant bits of the output ADC value; a second LSB DAC array configured to generate corresponding sample values for the one or more least significant bits of the output ADC value, Each of the first LSB DAC array and the second LSB DAC array is configured to alternate between generating an output ADC bit value and a mismatch error value for the output ADC bit value.
2. The ADC of claim 1, wherein the MSB DAC array is configured to generate the sample values using data-weighted averaging.
3. The ADC of any one of claims 1 to 3, wherein the first LSB DAC array and the second LSB DAC array are configured to generate the respective sample values using backplane sampling.
4. The ADC of claim 3, wherein the first LSB DAC array and the second LSB DAC array are configured to use mismatch error shaping together with backplane sampling to generate corresponding sample values.
5. The ADC of claim 3, wherein the MSB DAC array comprises a plurality of capacitors having substantially the same value, each of the plurality of capacitors representing half of a maximum value generated by the analog-to-digital converter.
6. The ADC of any one of claims 1 to 5, wherein the first LSB DAC array comprises a plurality of capacitors having substantially different values, each of the plurality of capacitors having a value smaller than a most significant bit of the output ADC value.
7. The ADC of any one of claims 1 to 6, wherein each of the plurality of capacitors in the first LSB DAC array follows a multiplication sequence.
8. The ADC of any one of claims 1 to 7, wherein the first LSB DAC array comprises a plurality of capacitors, and the second LSB DAC array comprises a plurality of capacitors substantially identical to the capacitors of the first LSB DAC array.
9. A method performed by an analog-to-digital converter (ADC), the method comprising: Generate corresponding sample values for one or more most significant bits of the output analog value by a most significant bit (MSB) digital audio converter (DAC) array of the ADC; generating corresponding sample values for one or more least significant bits of the output ADC value by a first LSB DAC array of the ADC; generating, by a second LSB DAC array of the ADC, corresponding sample values for the one or more least significant bits of the output ADC value; as well as Each of the first LSB DAC array and the second LSB DAC array alternates between generating output ADC bit values and mismatch error values for the output ADC bit values.
10. The method of claim 9, further comprising generating the sample values using data weighted averaging by the MSB DAC array.
11. The method of any one of claims 9 to 10, wherein generating the respective sample values by the first LSB DAC array and the second LSB DAC array comprises generating the sample values using backplane sampling.
12. The method of claim 11, wherein generating the corresponding sample values by the first LSB DAC array and the second LSB DAC array comprises using mismatch error shaping with backplane sampling to generate the sample values.
13. The method of claim 11, wherein the MSB DAC array comprises a plurality of capacitors having substantially the same value, each of the plurality of capacitors representing half of a maximum value generated by the analog-to-digital converter.
14. The method of any one of claims 9 to 13, wherein the first LSB DAC array comprises a plurality of capacitors having substantially different values, each of the plurality of capacitors having a value smaller than a most significant bit of the output ADC value.
15. The method of any one of claims 9 to 14, wherein each of the plurality of capacitors in the first LSB DAC array follows a multiplication sequence.
16. The method of any one of claims 9 to 15, wherein the first LSB DAC array comprises a plurality of capacitors, and the second LSB DAC array comprises a plurality of capacitors substantially identical to the capacitors of the first LSB DAC array.