Wiring board and mounting structure using same

Abstract

A wiring substrate according to the present disclosure includes: a first insulating layer having a first surface; a land conductor located on the first surface; a second insulating layer covering the first surface and the land conductor, the second insulating layer having a second surface on a side opposite to the first insulating layer; a via penetrating from the second surface of the second insulating layer to the land conductor; and the through hole conductor is positioned in the through hole and is connected with the connecting disc conductor. The via conductor has: a base metal layer on the surface of the land conductor, the wall surface of the via, and the second surface; and an electrolytic plating layer on the base metal layer. The plurality of voids are located in at least a portion of the base metal layer.

Description

Technical Field

[0001] The present disclosure relates to a wiring substrate and a mounting structure using the wiring substrate. Background Art

[0002] In a wiring substrate, in order to electrically connect the conductor layers located on the upper and lower surfaces of the insulating layer, as shown in Patent Document 1, a conductor (through-hole conductor) is filled in a via (through hole) formed in the insulating layer. The through-hole conductor is usually connected to the via land at the bottom of the via. Due to the difference in thermal expansion coefficient between the through-hole conductor such as copper and the resin forming the insulating layer, stress is easily concentrated on the connection portion between the bottom of the via and the via land. Therefore, when exposed to high temperature conditions, for example, it is easy to break.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2007-27341 Summary of the invention

[0006] -Technical means to solve the problem-

[0007] The wiring substrate involved in the present disclosure includes: a first insulating layer having a first surface; a connecting plate conductor located on the first surface; a second insulating layer covering the first surface and the connecting plate conductor, and having a second surface on the side opposite to the first insulating layer; a through hole penetrating from the second surface of the second insulating layer to the connecting plate conductor; and a through-hole conductor located in the through hole and connected to the connecting plate conductor. The through-hole conductor has: a base metal layer located on the surface of the connecting plate conductor, the wall surface of the through hole, and the second surface; and an electrolytic plating layer located on the base metal layer. A plurality of gaps are located in at least a portion of the base metal layer.

[0008] Furthermore, a mounting structure according to the present disclosure includes the above-mentioned wiring substrate and an electronic component located in a mounting region of the wiring substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is an explanatory diagram for explaining a wiring substrate according to one embodiment of the present disclosure.

[0010] Figure 2 It is used to illustrate Figure 1 An enlarged cross-sectional view of region X is shown.

[0011] Figure 3 It is used to illustrate Figure 2 An enlarged cross-sectional view of region Y is shown.

[0012] Figure 4This is an explanatory diagram for explaining an example of a method of forming a through-hole conductor in a wiring substrate according to an embodiment of the present disclosure.

[0013] Figure 5 This is an explanatory diagram for explaining an example of a method of forming a through-hole conductor in a wiring substrate according to another embodiment of the present disclosure.

[0014] Figure 6 This is an explanatory diagram for explaining an example of a method of forming a through-hole conductor in a wiring substrate according to another embodiment of the present disclosure.

[0015] Figure 7 This is an explanatory diagram for explaining an example of a method of forming a through-hole conductor in a wiring substrate according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] As described above, due to the difference in thermal expansion coefficient between the through-hole conductor and the resin forming the insulating layer, stress is easily concentrated on the connection portion between the bottom of the through-hole and the through-hole land. Therefore, when exposed to high temperature conditions, for example, it is easy to break. Therefore, a wiring substrate with excellent connection reliability of through-hole conductors and a mounting structure using the wiring substrate are required.

[0017] The wiring board and the mounting structure according to the present disclosure have the structures described in the section of means for solving the above-mentioned problems, and thus have excellent connection reliability of the through-hole conductors.

[0018] based on Figure 1 as well as Figure 2 A wiring board according to an embodiment of the present disclosure will be described. Figure 1 1 is an explanatory diagram for explaining a wiring substrate 1 according to an embodiment of the present disclosure. Figure 1 As shown, a wiring board 1 according to one embodiment includes an insulating layer 2 , a conductive layer 3 , and a solder resist 4 .

[0019] The insulating layer 2 includes an insulating layer 20 for the core, a first insulating layer 21 and a second insulating layer 22. The insulating layer 20 for the core is not particularly limited as long as it is a raw material with insulating properties. As the raw material with insulating properties, for example, resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin and polyphenylene ether resin can be cited. These resins can also be used in a mixture of two or more. The thickness of the insulating layer 20 for the core is not particularly limited, for example, it is greater than 20μm and less than 10mm. The insulating layer 20 for the core is not required. For example, in a substrate called a coreless substrate or a 2.3D substrate, the insulating layer 20 for the core is not used. For example, like a motherboard, the thickness of the insulating layer 20 for the core sometimes exceeds 10mm.

[0020] The core insulating layer 20 may include a reinforcing material. Examples of the reinforcing material include insulating fabrics such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more reinforcing materials may be used in combination. Furthermore, inorganic insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide may be dispersed in the core insulating layer 20.

[0021] In order to electrically connect the upper and lower surfaces of the core insulating layer 20, the through-hole conductor 20a is located in the core insulating layer 20. The through-hole conductor 20a is located in a through hole that passes from the upper surface to the lower surface of the core insulating layer 20. The through-hole conductor 20a is formed of a metal plating layer such as a copper plating layer, for example. The through-hole conductor 20a is connected to the conductor layer 3 formed on both surfaces of the core insulating layer 20. The through-hole conductor 20a may be located only on the inner wall surface of the through-hole, or may be filled in the through-hole.

[0022] The conductor layer 3 is not limited as long as it is a conductor such as a metal such as copper, nickel, chromium or an alloy thereof (e.g., nickel-chromium). Specifically, the conductor layer 3 is formed of a metal foil such as copper foil, a metal plating layer such as a copper plating layer, or a sputtered metal layer. The thickness of the conductor layer 3 is not particularly limited, and is, for example, not less than 1 μm and not more than 30 μm. The conductor layer 3 tends to become thinner as the wiring becomes finer.

[0023] The build-up layers formed by alternately stacking the conductor layers 3 and the insulating layers 2 are located on both sides of the core insulating layer 20. The build-up layers have a structure in which the conductor layers 3 and the insulating layers 2 are alternately stacked. In the wiring substrate 1 involved in one embodiment, when focusing on any two insulating layers 2 in contact with each other among the insulating layers 2 constituting the build-up layers, the insulating layer 2 on the side close to the core insulating layer 20 is equivalent to the first insulating layer 21, and the other insulating layer 2 is equivalent to the second insulating layer 22.

[0024] Specifically, when there are three insulating layers 2 constituting the build-up layer, focusing on the insulating layer 2 located on the surface of the core insulating layer 20 (the first insulating layer 2) and the insulating layer 2 located on the surface of the first insulating layer 2 (the second insulating layer 2), the first insulating layer 2 on the side close to the core insulating layer 20 corresponds to the first insulating layer 21, and the second insulating layer 2 corresponds to the second insulating layer 22. Focusing on the second insulating layer 2 and the insulating layer 2 located on the surface of the second insulating layer 2 (the third insulating layer 2), the second insulating layer 2 on the side close to the core insulating layer 20 corresponds to the first insulating layer 21, and the third insulating layer 2 corresponds to the second insulating layer 22.

[0025] The insulating layer 2 (the first insulating layer 21 and the second insulating layer 22) constituting the build-up layer is the same as the insulating layer 20 for the core, and is not particularly limited as long as it is a material with insulating properties. As mentioned above, resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin and polyphenylene ether resin can be listed. These resins can also be mixed and used in two or more. The insulating layers 2 constituting the build-up layer can also be the same resin or different resins. The insulating layer 2 constituting the build-up layer and the insulating layer 20 for the core can also be the same resin or different resins. The thickness of the insulating layer 2 constituting the build-up layer is not particularly limited, for example, it is greater than 1μm and less than 60μm. The insulating layers 2 constituting the build-up layer can also have the same thickness or different thicknesses.

[0026] The insulating layer 2 constituting the build-up layer may also include a reinforcing material. Examples of the reinforcing material include insulating fabrics such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more reinforcing materials may also be used in combination. Furthermore, inorganic insulating fillers such as silica, alumina, aluminum oxide, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide may be dispersed in the insulating layer 2 constituting the build-up layer. Usually, in substrates for the purpose of fine wiring, inorganic insulating fillers such as silica and alumina that are chemically not corroded by acids or alkalis are mostly used. As a result, insulation degradation such as ion migration is reduced under high temperature and high humidity and applied conditions.

[0027] like Figure 1 As shown, the solder resist 4 may also be located on the surface of the build-up layer. The solder resist 4 is formed of a resin, and as the resin, for example, an acrylic modified epoxy resin or the like can be cited. An opening is provided in the solder resist 4 to electrically connect the conductor layer 3 to the electrode of the component via the solder 5. As the component, for example, a semiconductor integrated circuit component and an optoelectronic component can be cited.

[0028] A through-hole conductor 3b is formed on the insulating layer 2 constituting the build-up layer to electrically connect the upper and lower surfaces of the insulating layer 2 constituting the build-up layer. The through-hole conductor 3b is located in a through hole 31 formed to penetrate the insulating layer 2 constituting the build-up layer. Figure 2 As shown, the through-hole conductor 3 b is located in the through-hole 31 penetrating from the second surface 222 of the second insulating layer 22 to the land conductor 3 a. Figure 2 It is used to illustrate Figure 1 The second insulating layer 22 covers the first surface 211 of the first insulating layer 21 and the land conductor 3 a located on the first surface 211 . The second surface 222 of the second insulating layer 22 is the surface on the opposite side to the first insulating layer 21 .

[0029] like Figure 2As shown, the through-hole conductor 3b is filled in the through-hole 31 formed in the second insulating layer 22, and the bottom (the bottom surface close to the first surface 211) is in contact with the land conductor 3a. The land conductor 3a and the through-hole conductor 3b are part of the conductor layer 3 and are formed of metal such as copper.

[0030] The through-hole conductor 3b has a base metal layer located on the surface of the land conductor 3a, the wall surface of the through hole 31, and the second surface 222, and an electrolytic plating layer 3b2 located on the base metal layer. In other words, the base metal layer is located between the surface of the land conductor 3a, the wall surface of the through hole 31, and the second surface 222, and the electrolytic plating layer 3b2. Thus, the electrolytic plating layer 3b2 can be firmly and closely attached to the surface of the land conductor 3a, the wall surface of the through hole 31, and the second surface 222 via the base metal layer.

[0031] The base metal layer is formed of, for example, copper, nickel, chromium, or an alloy thereof (e.g., nickel-chromium). The base metal layer may be either an electroless plating layer 3b1 or a sputtered metal layer 8. When the base metal layer is a sputtered metal layer 8, the base metal layer may be a multilayer structure in which, for example, a sputtered metal layer 8 formed of nickel-chromium is located on a sputtered metal layer 8 formed of copper.

[0032] exist Figure 3 In FIG. 1 , an example in which the base metal layer is an electroless plating layer 3b1 is shown. Figure 3 As shown, the through-hole conductor 3b has an electroless plating layer 3b1 and an electrolytic plating layer 3b2. Figure 3 It is used to illustrate Figure 2 2 is an enlarged cross-sectional view of the region Y shown in FIG. The electroless plating layer 3b1 is located on the surface of the land conductor 3a, the wall surface of the through hole 31, and the second surface 222. The thickness of the electroless plating layer 3b1 is not particularly limited, and is, for example, 100 nm or more and 3 μm or less. The electrolytic plating layer 3b2 is located on the electroless plating layer 3b1. The electroless plating layer 3b1 and the electrolytic plating layer 3b2 are formed of a metal such as copper.

[0033] In a wiring substrate 1 according to an embodiment, Figure 3 As shown, a plurality of voids 32 are located in at least a portion of the electroless plating layer 3b1. By providing such voids 32, the wiring substrate 1 according to one embodiment can relieve stress applied to the bottom of the through-hole conductor 3b. As a result, the breakage of the through-hole conductor 3b is reduced, and the connection reliability of the through-hole conductor 3b is improved.

[0034] The voids 32 are preferably arranged irregularly rather than regularly. If the voids 32 are arranged irregularly, the stress applied to the bottom of the through-hole conductor 3b in various directions can be more easily relieved. The size of the voids 32 can be, for example, 1 nm or more and 300 nm or less at the largest diameter portion.

[0035] like Figure 2 As shown in FIG. 1 , the land conductor 3a may have an inclined portion at the periphery that is inclined relative to the first surface 211 of the first insulating layer 21. In a cross-sectional view, the thickness of the inclined portion may increase from the periphery of the land conductor 3a to the side surface of the through-hole conductor 3b. For example, in a cross section including the center of the land conductor 3a when viewed from above, the thickness increases from the periphery of the land conductor 3a to the side surface of the through-hole conductor 3b. By having such a structure, the stress applied from the insulating layer 2 to the through-hole conductor 3b can be further dispersed.

[0036] like Figure 2 As shown, in the case of cross-section, the land conductor 3a may also have a concave portion 3a1 that is concave in a curved shape. The through-hole conductor 3b may also be in contact with the concave portion 3a1. The concave portion 3a1 is, for example, a concave shape that is concave from the second surface 222 side to the first surface 211 side. By having such a structure, the stress applied to the through-hole conductor 3b can be further reduced compared to the case where the through-hole conductor 3b and the land conductor 3a are in contact with each other in a planar shape.

[0037] The through-hole conductor 3b may also have a constricted portion 3bK having the smallest width in the horizontal direction along the first surface 211. Alternatively, the plurality of voids 32 may be located at least in the through-hole conductor 3b at a position closer to the land conductor 3a than the constricted portion 3bK in the vertical direction relative to the first surface 211. The constricted portion 3bK may be defined as, for example, a portion of the through-hole conductor 3b having the smallest length in the horizontal direction along the first surface 211. With such a structure, the point at which the density of the voids 32 changes can be offset from the boundary between the constricted portion 3bK and the insulating layer 2 (the second insulating layer 22) where the stress is most concentrated. As a result, the breakage of the through-hole conductor 3b can be further reduced.

[0038] In the electroless plating layer 3b1, the density of the plurality of voids 32 included in the first region 3b11 may be greater than the density of the plurality of voids 32 included in the second region 3b12. The first region 3b11 is a region located between the electrolytic plating layer 3b2 and the land conductor 3a. The second region 3b12 is a region located between the electrolytic plating layer 3b2 and the second insulating layer 22. The density of the plurality of voids 32 included in the first region 3b11 may be greater than 100% and less than 150% of the density of the plurality of voids 32 included in the second region 3b12. By having such a structure, the stress applied between the through-hole conductor 3b and the land conductor 3a, which are subjected to greater stress, can be further reduced.

[0039] For example, in the case of cross-section, the first region 3b11 in the base metal layer has a thickness of 1,000,000 nm. 2 The number of gaps 32 may be more than 1 and less than 40. Figure 3As shown, for example, when the base metal layer is an electroless plating layer 3b1, every 1000000nm 2 The number of voids 32 may be 1 or more and 40 or less. When the base metal layer is a sputtered metal layer 8, the number of voids 32 per 1,000,000 nm may be 1 or more and 40 or less. 2 The number of gaps 32 may be greater than 1 and less than 10.

[0040] In the case of a multilayer structure in which the base metal layer is a sputtered metal layer 8 formed of, for example, nickel-chromium and is located on a sputtered metal layer 8 formed of copper, if the number of voids 32 of the sputtered metal layer 8 formed of copper with a low Young's modulus is greater than the number of voids 32 of the sputtered metal layer 8 formed of nickel-chromium, the buffering effect is large and the stress relaxation effect is more easily obtained. Furthermore, in the case where the sputtered layer formed of nickel-chromium with a higher Young's modulus than copper is located at the bottom of the via hole where stress is easily concentrated, the stress relaxation effect brought about by the configuration of the voids 32 is high. Since the sputtered layer at the bottom of the via hole is formed close to the interface between the electrolytic plating layer 3b2 and the connecting plate conductor 3a, the stress relaxation effect brought about by the configuration of the voids 32 is high. The number of multiple voids 32 can be confirmed, for example, by photographing and observing in a FE-SEM at a magnification of about 35,000 times. In order to achieve a reduction in cracks when stress is applied to the wiring substrate 1, it can also be more than 1 and less than 5.

[0041] The distance between the electrolytic plating layer 3b2 and the land conductor 3a is defined as, for example, the distance between the imaginary lines connecting the electrolytic plating layer 3b2 and the land conductor 3a at the shortest distance in parallel with respect to the first surface 211. Similarly, the distance between the electrolytic plating layer 3b2 and the second insulating layer 22 is defined as, for example, the distance between the imaginary lines connecting the electrolytic plating layer 3b2 and the second insulating layer 22 at the shortest distance in parallel with respect to the first surface 211.

[0042] Next, based on Figure 4 One embodiment of a method of forming the through-hole conductor 3 b in the through-hole 31 will be described. Figure 4 This is an explanatory diagram for explaining an example of a method of forming the through-hole conductor 3 b in the wiring substrate 1 according to the embodiment of the present disclosure.

[0043] First, if Figure 4 As shown in A, a land conductor 3a is formed on the first surface 211 of the first insulating layer 21. As described above, the land conductor 3a is a part of the conductor layer 3 and is formed of a metal such as copper. Figure 4As shown in FIG. 1B , a through hole 31 is formed in the second insulating layer 22. The through hole 31 is formed to penetrate from the second surface 222 of the second insulating layer 22 to the land conductor 3a. The through hole 31 is formed, for example, by laser processing, photolithography of a photosensitive insulating resin, or the like. Laser processing uses a carbon dioxide laser, a YAG laser, or an excimer laser. The photosensitive insulating resin is generally an epoxy resin, a polyimide, or the like, but other resins may also be used.

[0044] After forming the through hole 31, as Figure 4 As shown in FIG. 3C, a concave portion 3a1 that is concave in a curved shape is formed at the bottom of the through hole 31, that is, at the surface of the land conductor 3a. The concave portion 3a1 is formed by, for example, etching.

[0045] Next, if Figure 4 As shown in D, the electroless plating layer 3b1 is formed on the second surface 222 of the second insulating layer 22, the inner wall surface of the through hole 31, and the bottom surface of the through hole 31 (the recessed portion 3a1 of the land conductor 3a). As described above, the electroless plating layer 3b1 is formed of a metal such as copper. As described above, the thickness of the electroless plating layer 3b1 is, for example, not less than 100 nm and not more than 3 μm.

[0046] After the electroless plating layer 3b1 is formed, the electroless plating layer 3b1 is subjected to heat treatment. Specifically, the substrate on which the electroless plating layer 3b1 is formed is heated at a temperature of, for example, 150°C or higher. The upper limit of the heating temperature is about 180°C. The heating time is, for example, more than 30 minutes, and the longest is about 120 minutes. By subjecting the electroless plating layer 3b1 to heat treatment, it is easy to form the void 32 in the electroless plating layer 3b1.

[0047] Specifically, when heat treatment is performed at a relatively high temperature of 150°C or higher, hydrogen (hydrogen from the plating solution) present in the electroless plating layer 3b1 gathers. As a result, fine voids 32 having a diameter of 100 nm or less are formed. Furthermore, an oxide film is formed on the surface of the electroless plating layer 3b1, and when copper atoms are combined with oxygen atoms at this time, the copper atoms move to generate voids. As a result, voids 32 having a diameter of 50 nm or more and 200 nm or less are formed.

[0048] Next, if Figure 4 As shown in FIG. 1 , an electrolytic plating layer 3b2 is formed on the surface of the electroless plating layer 3b1, and the through hole 31 is filled with the electrolytic plating layer 3b2. As described above, the electrolytic plating layer 3b2 is formed of a metal such as copper. Next, the electroless plating layer 3b1 exposed from the electrolytic plating layer 3b2 is subjected to flash etching and removed, and then subjected to a second heat treatment. The second heat treatment can be heated at a temperature of, for example, 190°C or higher. The upper limit of the heating temperature is about 250°C. The heating time is, for example, more than 20 minutes, and the longest is about 120 minutes.

[0049] By performing the second heat treatment, the size and position of the voids 32 can be easily randomized. Specifically, when the electroless plating layer 3b1 is formed of copper, the metal other than copper contained as an impurity diffuses to form the voids 32. Therefore, the voids 32 formed are dispersed, and the voids 32 can be randomly arranged. In this way, in the wiring substrate 1 involved in one embodiment, Figure 2 As shown, a through-hole conductor 3 b is formed in the through-hole 31 .

[0050] Next, based on Figure 5 to Figure 7 An embodiment in which the base metal layer is a sputtered metal layer 8 will be described. Figure 5 to Figure 7 This is an explanatory diagram for explaining an example of a method of forming a through-hole conductor 3b in a wiring substrate according to another embodiment of the present disclosure. In the wiring substrate according to another embodiment, the same reference numerals are given to the same components as those of the wiring substrate 1 according to one embodiment, and detailed descriptions thereof are omitted.

[0051] In the wiring substrate 1 according to the above-mentioned embodiment, the base metal layer is the electroless plating layer 3b1. On the other hand, in the wiring substrate according to other embodiments, Figure 7 As shown in C, the base metal layer is a sputtered metal layer 8. In a wiring board according to another embodiment, the through-hole conductor 3b is formed, for example, as follows.

[0052] like Figure 5 As shown in FIG. 1A , a seed layer 6 is formed on the surface of the first insulating layer 21. Figure 5 In A, the seed layer 6 has a double-layer structure of a first seed layer 61 and a second seed layer 62. First, the first seed layer 61 is formed on the surface of the first insulating layer 21. The method for forming the first seed layer 61 is not limited, for example, it is formed by sputtering. The first seed layer 61 is formed, for example, of at least one metal selected from the group including the fourth group elements, the fifth group elements, the sixth group elements and the tenth group elements. As such a metal, specifically, nickel, chromium, titanium, tantalum, molybdenum, tungsten, palladium or alloys including these metals can be listed. The first seed layer 61 can also be, for example, a nickel-chromium layer formed by sputtering. The first seed layer 61 can, for example, have a thickness of more than 0.5 nm and less than 100 nm.

[0053] Next, the second seed layer 62 is formed on the surface of the first seed layer 61. The method of forming the second seed layer 62 is not limited, and it is formed by sputtering, for example. The second seed layer 62 is formed of copper. The second seed layer 62 can have a thickness of, for example, 100 nm or more and 1000 nm or less.

[0054] Next, if Figure 5 As shown in FIG. 1B, a resist 7 is formed on the surface of the seed layer 6. The resist 7 has an opening, such as Figure 5 As shown in FIG. 1B, an electrolytic plating layer 63 is formed in the opening. The electrolytic plating layer 63 is, for example, an electrolytic copper plating layer. After the electrolytic plating layer 63 is formed, Figure 5 As shown in FIG. 3C, the resist 7 and the seed layer 6 covered by the resist 7 are removed. The resist 7 is removed by a sodium hydroxide aqueous solution or an amine-based resist stripping solution.

[0055] When the second seed layer 62 in the seed layer 6 is copper, it is etched with a sulfuric acid-hydrogen peroxide aqueous solution, and then the first seed layer 61 is etched with an etchant suitable for etching the metal of the first seed layer 61. For example, if it is nickel chromium, it is removed by etching with a mixed aqueous solution of sulfuric acid and hydrochloric acid.

[0056] Next, if Figure 5 As shown in D, a recess 631 is formed on the surface of the electrolytic plating layer 63. The recess 631 is formed by, for example, performing an annealing treatment at a temperature of 150° C. to 250° C. for 20 minutes to 90 minutes. At this time, the recess 631 has, for example, a diameter of 50 nm to 1000 nm and a depth of 50 nm to 300 nm.

[0057] Next, if Figure 6 As shown in A of FIG. 1 , the surface of the electrolytic plating layer 63 is subjected to a soft etching process, for example, so that the diameter of the recess 631 is greater than 10 nm and less than 500 nm, and the depth is greater than 5 nm and less than 50 nm. After the soft etching process, as shown in FIG. Figure 6 As shown in FIG. 1B , the surface of the electrolytic plating layer 63 is subjected to a silane coupling treatment. Specifically, the surface of the electrolytic plating layer 63 is subjected to a tin plating treatment, and then treated with nitric acid to perform a silane coupling treatment. In this way, the land conductor 3 a is formed on the surface of the first insulating layer 21 .

[0058] Next, if Figure 6 As shown in FIG. 3 , a second insulating layer 22 is formed on the surface of the first insulating layer 21 so as to cover the connection pad conductor 3a. After the second insulating layer 22 is formed, Figure 6 As shown in D, a through hole 31 is formed so as to penetrate from the second surface 222 of the second insulating layer 22 to the land conductor 3a. After the through hole 31 is formed, a concave portion 3a1 that is concave in a curved shape is formed at the bottom of the through hole 31, i.e., the surface of the land conductor 3a. The concave portion 3a1 is formed, for example, by etching. At this time, the silane coupling layer and the tin plating layer formed on the surface of the land conductor 3a are removed. The etching amount is adjusted so that the concave amount of the concave portion 3a1 is less than that in the case of chemical plating.

[0059] Next, if Figure 7As shown in A, a first sputtered metal layer 81 is formed on the second surface 222 of the second insulating layer 22, the inner wall surface of the through hole 31, and the bottom surface of the through hole 31 (the surface of the connecting plate conductor 3a). The first sputtered metal layer 81 is formed, for example, of at least one metal selected from the group including the fourth group elements, the fifth group elements, the sixth group elements, and the tenth group elements. As such a metal, specifically, nickel, chromium, titanium, tantalum, molybdenum, tungsten, palladium, or alloys including these metals can be cited. The first sputtered metal layer 81 can also be, for example, a nickel-chromium layer formed by sputtering. The first sputtered metal layer 81 can have a thickness of, for example, not less than 0.5 nm and not more than 100 nm.

[0060] If sputtering is performed on the surface of the land conductor 3a having the recess 631, the entrance of the recess 631 is blocked before the recess 631 is filled with metal. Figure 7 As shown in A, it is easy to form a gap 32 in the recessed portion 631.

[0061] Next, if Figure 7 As shown in FIG. 1B , a second sputtered metal layer 82 is formed on the surface of the first sputtered metal layer 81. The second sputtered metal layer 82 is formed of, for example, copper. The second sputtered metal layer 82 may be, for example, a copper layer formed by sputtering. The second sputtered metal layer 82 may have, for example, a thickness of 50 nm or more and 1000 nm or less. The sputtered metal layer 8 may have, for example, a thickness of 50 nm or more and 1100 nm or less.

[0062] When forming the second sputtered metal layer 82, for example, by adjusting the settings of the sputtering device by reducing the swing amount of the magnet of the sputtering device, unevenness is likely to occur in the second sputtered metal layer 82. As a result, Figure 7 As shown in FIG. 8B , the voids 32 are also easily formed in the second sputtered metal layer 82 .

[0063] Next, if Figure 7 As shown in FIG. 3C, an electrolytic plating layer 3b2 is formed on the surface of the second sputtered metal layer 82 (sputtered metal layer 8), and the through hole 31 is filled with the electrolytic plating layer 3b2. As described above, the electrolytic plating layer 3b2 is formed of a metal such as copper. Through such steps, the through-hole conductor 3b is formed in the wiring substrate involved in other embodiments.

[0064] Next, the mounting structure involved in the present disclosure is described. The mounting structure involved in one embodiment includes a wiring substrate 1 involved in one embodiment and an element located on the surface of the wiring substrate 1. The conductor layer 3 in the opening of the solder resist layer 4 is connected to the electrode of the element via the solder 5. As the element, as described above, semiconductor integrated circuit elements and optoelectronic elements can be listed. The element can be located on both sides of the wiring substrate 1, or the element can be located on one surface, such as a motherboard, etc., which is located on the other surface.

[0065] The wiring substrate involved in the present disclosure is not limited to the wiring substrate 1 involved in the above-mentioned one embodiment and the wiring substrate involved in other embodiments. In the wiring substrate 1 involved in one embodiment, the insulating layer 2 constituting the build-up layer has a two-layer structure. However, in the wiring substrate involved in the present disclosure, the insulating layer constituting the build-up layer is not limited to a two-layer structure, and may also have a stacked structure of more than three layers.

[0066] In the wiring substrate 1 according to one embodiment and the wiring substrate according to another embodiment, the surface of the land conductor 3a is inclined toward the periphery in cross-sectional view. However, in the wiring substrate according to the present disclosure, the surface of the land conductor may be substantially parallel to the first surface of the first insulating layer.

[0067] In the wiring substrate 1 according to one embodiment, the land conductor 3a has a curved recessed portion 3a1 in cross-sectional view. However, in the wiring substrate according to the present disclosure, the land conductor may not have a recessed portion, and even if it has a recessed portion, it may not be a curved recessed portion.

[0068] In the wiring substrate according to another embodiment, the sputtered metal layer 8 is formed of two layers, namely, the first sputtered metal layer 81 and the second sputtered metal layer 82. However, in the wiring substrate according to the present disclosure, the sputtered metal layer 8 may have a single layer structure or a multilayer structure.

[0069] Furthermore, the invention according to the present disclosure is not limited to the above-described embodiment, and various changes and improvements can be made within the scope of the present disclosure as shown in the following (1) and (12).

[0070] (1) The wiring substrate involved in the present disclosure includes: a first insulating layer having a first surface; a connecting pad conductor located on the first surface; a second insulating layer covering the first surface and the connecting pad conductor and having a second surface on the side opposite to the first insulating layer; a through hole penetrating from the second surface of the second insulating layer to the connecting pad conductor; and a through-hole conductor located in the through hole and connected to the connecting pad conductor. The through-hole conductor includes: a base metal layer located on the surface of the connecting pad conductor, the wall surface of the through hole, and the second surface; and an electrolytic plating layer located on the base metal layer. A plurality of gaps are located in at least a portion of the base metal layer.

[0071] Regarding the embodiments of the present disclosure, the following embodiments (2) to (11) are further disclosed.

[0072] (2) In the wiring board described in (1) above, the base metal layer is an electroless plating layer.

[0073] (3) In the wiring board described in (1) above, the base metal layer is a sputtered metal layer.

[0074] (4) In the wiring substrate described in (3) above, the sputtered metal layer has a multilayer structure.

[0075] (5) In the wiring board described in any one of (1) to (4), the land conductor has an inclined portion at the periphery of the land conductor. In a cross-sectional view, the thickness of the inclined portion increases from the periphery of the land conductor to the side surface of the through-hole conductor.

[0076] (6) In the wiring board described in any one of (1) to (5) above, the land conductor has a recessed portion that is recessed in a curved shape when viewed in cross section, and the through-hole conductor is in contact with the recessed portion.

[0077] (7) In the wiring substrate described in any one of (1) to (6), the through-hole conductor has a constricted portion having the smallest width in a horizontal direction along the first surface, and the plurality of voids are located closer to the land conductor than the constricted portion in at least the vertical direction relative to the first surface of the through-hole conductor.

[0078] (8) In the wiring board described in any one of (1) to (7) above, the base metal layer includes a first region located between the electrolytic plating layer and the land conductor and a second region located between the electrolytic plating layer and the second insulating layer. The density of the plurality of voids included in the first region is greater than the density of the plurality of voids included in the second region.

[0079] (9) In the wiring substrate described in (8) above, the first region has a cross-sectional view of 2 The plurality of gaps includes at least one and no more than 40 gaps.

[0080] (10) In the wiring board described in (9) above, the base metal layer is an electroless plating layer, and the first region has a thickness of 1,000,000 nm when viewed in cross section. 2 The plurality of gaps includes at least one and no more than 40 gaps.

[0081] (11) In the wiring substrate described in (9) above, the base metal layer is a sputtered metal layer, and the first region has a thickness of 1,000,000 nm when viewed in cross section. 2 The plurality of gaps includes one or more and ten or less.

[0082] (12) A mounting structure according to the present disclosure includes: the wiring substrate according to any one of (1) to (11) above; and an electronic component located in a mounting region of the wiring substrate.

[0083] -Explanation of symbols-

[0084] 1 Wiring board

[0085] 2 Insulation layer

[0086] 20 Insulation layer for fiber core

[0087] 20a Through-hole conductor

[0088] 21 First insulation layer

[0089] 211 Page 1

[0090] 22 Second insulation layer

[0091] 222 Second side

[0092] 3 Conductor layer

[0093] 31 Through Holes

[0094] 3a Connecting plate conductor

[0095] 3a1 recess

[0096] 3b Through-hole conductor

[0097] 3b1 Electroless plating

[0098] 3b11 First Area

[0099] 3b12 Second Area

[0100] 3b2 Electrolytic plating

[0101] 3bK Neck reduction

[0102] 32 Gap

[0103] 4. Solder Resist

[0104] 5. Solder

[0105] 6 Seed layer

[0106] 61 First seed layer

[0107] 62 Second seed layer

[0108] 63 Electrolytic plating

[0109] 631 concavity

[0110] 7. Resist

[0111] 8 Sputtered metal layer

[0112] 81 First sputtered metal layer

[0113] 82 Second sputtered metal layer.

Claims

1. A wiring substrate, comprising: A first insulating layer having a first surface; A connecting plate conductor, located on the first surface; a second insulating layer covering the first surface and the connection plate conductor and having a second surface on a side opposite to the first insulating layer; a through hole extending from the second surface of the second insulating layer to the connection plate conductor; as well as a through-hole conductor, located in the through-hole and connected to the connection plate conductor, The through-hole conductor comprises: a base metal layer located on the surface of the land conductor, the wall surface of the through-hole and the second surface; and an electrolytic plating layer located on the base metal layer. A plurality of voids are located in at least a portion of the base metal layer.

2. The wiring substrate according to claim 1, wherein: The base metal layer is an electroless plating layer.

3. The wiring substrate according to claim 1, wherein The base metal layer is a sputtered metal layer.

4. The wiring substrate according to claim 3, wherein: The sputtered metal layer has a multi-layer structure.

5. The wiring substrate according to any one of claims 1 to 4, wherein: The land conductor has an inclined portion at the periphery of the land conductor. In a cross-sectional view, the thickness of the inclined portion is greater from the peripheral edge of the land conductor to the side surface of the through-hole conductor.

6. The wiring substrate according to any one of claims 1 to 5, wherein: In a cross-sectional view, the land conductor has a concave portion that is concave in a curved shape. The through-hole conductor is in contact with the recessed portion.

7. The wiring substrate according to any one of claims 1 to 6, wherein: The through-hole conductor has a constricted portion having the smallest width along the horizontal direction of the first surface, The plurality of voids are located closer to the land conductor than the constricted portion in at least the through-hole conductor in a direction perpendicular to the first surface.

8. The wiring substrate according to any one of claims 1 to 7, wherein: The base metal layer includes a first region between the electrolytic plating layer and the land conductor and a second region between the electrolytic plating layer and the second insulating layer. The density of the plurality of voids included in the first region is greater than the density of the plurality of voids included in the second region.

9. The wiring substrate according to claim 8, wherein: In the case of cross-section, the first region has a 2 The plurality of gaps includes at least one and no more than 40 gaps.

10. The wiring substrate according to claim 9, wherein: The base metal layer is the electroless plating layer, and the first region has a cross-sectional view of every 1000000nm 2 The plurality of gaps includes at least one and no more than 40 gaps.

11. The wiring substrate according to claim 9, wherein: The base metal layer is the sputtered metal layer, and the first region has a thickness of 1,000,000 nm when viewed in cross section. 2 The plurality of gaps includes one or more and ten or less.

12. A mounting structure, comprising: The wiring substrate according to any one of claims 1 to 11; as well as The electronic components are located in the mounting area of ​​the wiring substrate.

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