Heterogeneous all-around gate dielectric thickness

Abstract

The semiconductor includes a first GAA FET (303) and a second GAA FET (305). The second GAA FET includes a first gate dielectric (391) and a second gate dielectric (472) within its gate structure. The first GAA FET includes only a first gate dielectric within its gate structure. The gate dielectric structure of the first GAA FET provides a nominal or less effective gate dielectric or gate dielectric resistance relative to the effective gate dielectric structure of the second GAA FET. The first GAA FET further includes a first gate conductor (392) within its gate structure, and the second GAA FET further includes first and second gate conductors (395) within its gate structure. The first gate conductor and the second gate conductor are separated by a second gate dielectric.

Description

Background Art

[0001] Various embodiments of the present application generally relate to semiconductor device fabrication operations and the resulting devices. More specifically, various embodiments relate to all-around gate transistors including relatively heterogeneous gate dielectric thicknesses.

[0002] Conventional semiconductor devices, such as integrated circuits (ICs) or the like, incorporate planar field effect transistors (FETs) in which current flows through a semiconductor channel between a source and a drain in response to a voltage applied to a control gate. The semiconductor industry strives to adhere to Moore's Law, which states that each generation of IC devices shrinks to half their size and runs at twice the speed. However, as device sizes shrink, conventional silicon device geometries and materials have difficulty maintaining switching speeds without causing failures, such as leakage current from the device into the semiconductor substrate. Several new technologies have emerged that allow chip designers to continue to shrink the size of transistors.

[0003] One particularly radical technology change requires redesigning the structure of the FET from a planar device to a three-dimensional (3D) device, in which the semiconductor channel is replaced by a fin extending from the plane of the substrate. In this device (commonly referred to as a FinFET), the control gate wraps around three sides of the fin to affect the current from three surfaces instead of one. The improved control achieved by the 3D design results in faster switching performance and reduced current leakage. Building taller devices also allows for increased device density within the same footprint previously occupied by planar FETs.

[0004] The FinFET concept was further extended by developing gate all-around FETs or GAA FETs, where the gate completely surrounds one or more channels to maximize control of the current therein. In GAA FETs, the channel can take the form of (nanowire(s)), sheet(s) isolated from the substrate. In GAA FETs, the respective channel surfaces that are not in contact with the source and drain are in contact with and surrounded by the gate.

[0005] One challenge in GAA FET fabrication is forming thick gate dielectric transistors (also referred to as EG FETs). This challenge arises due to the limited and confined space (e.g., 10 nm or less) between vertical nanosheet channels, where such small spacing cannot accommodate thick gate dielectrics. For example, after depositing a thick gate dielectric composed of a gate oxide (e.g., ~3 nm thick) and a high-k dielectric (e.g., ~2 nm thick), the thick gate dielectric can pinch off the space between vertically adjacent nanosheet channels, leaving insufficient space for gate work functions or other gate conductor materials in between. Summary of the invention

[0006] In an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a substrate; a first all-around gate field effect transistor (GAA FET) and a second GAA FET. The first GAA FET is on the substrate and includes a plurality of first nanostructure channels and a first gate structure. The first gate structure includes a first gate dielectric surrounding the plurality of first nanostructure channels and a first gate conductor above the first gate. The second GAA FET is also on the substrate and includes a plurality of second nanostructure channels and a second gate structure. The second gate structure includes a first gate dielectric surrounding the plurality of first nanostructure channels, a first gate conductor above the first gate dielectric, a second gate conductor above the first gate conductor, and a second gate dielectric between the first gate conductor and the second gate conductor.

[0007] The first GAA FET may further include a first gate spacer surrounding the first gate structure, and the second GAA FET may further include a second spacer surrounding the second gate structure. The first gate dielectric may be located between the first gate conductor and the first gate spacer within the first GAA FET. Within the second GAA FET, the first gate dielectric may be between the first gate conductor and the second gate spacer, and the second gate dielectric may be between the second gate conductor and the second gate spacer.

[0008] The first gate structure may further include a first work function conductor between the first gate dielectric and the first gate conductor. The second gate structure may further include a first work function conductor between the first gate dielectric and the first gate conductor. The second gate dielectric may be located between the first gate dielectric and the second gate conductor within the second GAA FET.

[0009] The first gate conductor may be configured to receive a first voltage, and the gate conductor may be configured to receive a second voltage greater than the first voltage. The first gate structure may include a first current impedance from the second gate conductor to the plurality of second nanostructure channels, and the second gate structure may include a second current impedance from the first gate conductor to the plurality of first nanostructure channels, the second current impedance being greater than the first current impedance.

[0010] The plurality of first nanostructure channels may each have a first channel length, and the plurality of second nanostructure channels may each have a second channel length greater than the first channel length.

[0011] In an embodiment of the present disclosure, another semiconductor device is proposed. The semiconductor device includes a substrate, a low voltage all-around gate field effect transistor (SG GAA FET) and a high voltage all-around gate field effect transistor (EG GAA FET). The SG GAA FET is on the substrate and includes a plurality of first nanostructure channels and a first gate structure. The first gate structure includes a first gate dielectric surrounding the plurality of first nanostructure channels and a first gate conductor above the first gate. The EGGAA FET is also on the substrate and includes a plurality of second nanostructure channels and a second gate structure. The second gate structure includes a first gate dielectric surrounding the plurality of first nanostructure channels, a first gate conductor above the first gate dielectric, a second gate conductor above the first gate conductor, and a second gate dielectric between the first gate conductor and the second gate conductor.

[0012] The SG GAA FET may further include a first gate spacer surrounding the first gate structure, and the EG GAA FET may further include a second spacer surrounding the second gate structure. The first gate dielectric may be located between the first gate conductor and the first gate spacer in the SG GAA FET. In the EG GAA FET, the first gate dielectric may be between the first gate conductor and the second gate spacer, and the second gate dielectric may be between the second gate conductor and the second gate spacer.

[0013] The first gate structure may further include a first work function conductor between the first gate dielectric and the first gate conductor. The second gate structure may further include a first work function conductor between the first gate dielectric and the first gate conductor. The second gate dielectric may be located between the first gate dielectric and the second gate conductor within the EG GAA FET.

[0014] The first gate structure may have a first current impedance from the second gate conductor to the plurality of second nanostructure channels, and the second gate structure may have a second current impedance from the first gate conductor to the plurality of first nanostructure channels that is greater than the first current impedance.

[0015] In another embodiment of the present invention, a method for manufacturing a semiconductor device is provided. The method includes forming a plurality of first nanostructure channels between a first source and a drain of a first all-around gate field effect transistor (GAA FET). The method also includes forming a plurality of second nanostructure channels between a second source and a drain of a second GAA FET. The method also includes forming a first gate dielectric around the plurality of first nanostructure channels of the first GAA FET and around the plurality of second nanostructure channels of the second GAA FET. The method also includes forming a first gate conductor on top of the first gate dielectric of the first GAA FET and on top of the first gate dielectric of the second GAA FET. The method also includes partially recessing the first gate conductor of the second GAA FET and forming a second gate dielectric on top of the partially recessed first gate conductor of the second GAA FET. The method also includes forming a second gate conductor on top of the second gate dielectric of the second GAA FET.

[0016] According to an embodiment of the present disclosure, the second GAA FET or EG GAA FET includes a first gate dielectric and a second gate dielectric, while the first GAA FET or SG GAA FET does not include the second gate dielectric. The second gate dielectric can be selected to achieve a predetermined or desired voltage drop across the gate conductor above the nanolayer channel of the second GAA FET or EG GAA FET. In such an embodiment, the current flowing from the gate conductor into the nanolayer channel is sequentially (i.e., in series) blocked by the second gate dielectric and the first gate dielectric. The impedance of the current and the total resistance effect of the second gate dielectric and the first gate dielectric are greater than the total resistance effect of only the first gate dielectric of the first GAA FET or SG GAA FET. In this way, embodiments of the present disclosure provide a nominal or lower effective gate dielectric or gate dielectric resistance in the first GAA FET or SG GAA FET, and provide an increased or higher effective gate dielectric or gate dielectric resistance in the second GAA FET or EG GAA FET. Thus, embodiments of the present disclosure provide a manufacturing method and associated semiconductor structure in which both a first GAA FET or SG GAA FET and a second GAA FET or EG GAA FET are on the same substrate, wafer or device layer.

[0017]

[0011] These and other embodiments, features, aspects and advantages will become better understood with reference to the following description, appended claims and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figures 1 to 8Depicted are respective cross-sectional views of a semiconductor device including a gate-all-around transistor shown after sequential fabrication operations in accordance with one or more embodiments of the present disclosure.

[0019] Figures 9 to 14 Depicted are respective cross-sectional views of a semiconductor device including a gate-all-around transistor with a heterogeneous gate dielectric thickness according to one or more embodiments of the present disclosure.

[0020] Fig.15 is a flowchart illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0021] Embodiments of the present disclosure recognize that not all GAA FETs within the same semiconductor device benefit from the same thickness of the gate dielectric between the GAA channel and the conductive gate material (one or more). Therefore, the present disclosure provides a manufacturing method for forming a semiconductor device that includes at least two GAA FETs with relatively different gate dielectric thicknesses. For example, the semiconductor device is formed to include a thick gate dielectric GAA FET (e.g., EG GAA FET) and to include a thin gate dielectric GAA FET (e.g., SG GAA FET).

[0022] The manufacturing method may include recessing a first conductor (one or more) of a first replacement gate structure of a first GAA FET and masking a second replacement gate structure of a second GAA FET. For example, the gate conductor and work function material of the replacement gate structure of the EG GAA FET are recessed, and the replacement gate structure of the SG GAA FET is masked. The first gate dielectric of the first replacement gate structure may be retained or may be recessed along with the first conductor (one or more).

[0023] The manufacturing method may also include forming a second gate dielectric on the first conductor(s) and on the first gate dielectric. The manufacturing method may also include forming a second conductor(s) on the second gate dielectric. The manufacturing method may also include removing the mask of the second replacement gate structure of the second GAA FET.

[0024] The manufacturing method can form a first GAA FET and a second GAA FET, the first GAA FET including a first replacement gate structure having an effective thick gate dielectric, and the second GAA FET including a second replacement gate structure having an effective thin gate dielectric. The effective thick gate dielectric of the first GAA FET can allow high voltage operation of the first GAA FET with relatively improved gate dielectric reliability. In addition, according to an embodiment, forming the effective thick gate dielectric of the first GAA FET does not require forming the thick gate dielectric directly on the nanosheet channel, which may cause the gate dielectric to pinch off the space between vertically adjacent nanosheet channels. Therefore, according to an embodiment, forming the effective thick gate dielectric of the first GAA FET can allow sufficient gate work function or other gate conductor material (one or more) to be formed between vertically adjacent nanosheet channels.

[0025] Although the detailed description includes examples of how embodiments of the present disclosure may be implemented to form exemplary semiconductor devices having various GAA FETs, implementation of the teachings described herein is not limited to the specific types of GAA FET structures or material combinations depicted or described. Rather, embodiments of the present disclosure can be implemented in conjunction with other transistor types or materials now known or later developed where it is desired to provide transistors having heterogeneous gate dielectric thicknesses.

[0026] For the sake of brevity, conventional techniques associated with semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. In addition, the various tasks and process steps described herein may be incorporated into a more comprehensive program or process having additional steps or functions not described in detail herein. The various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps will only be briefly mentioned herein, or will be omitted entirely, without providing well-known process details.

[0027] Generally, the various processes for forming semiconductor devices to be packaged into ICs are divided into four major categories, i.e., film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process of growing, coating, or otherwise transferring materials onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD), etc. Removal / etching is any process of removing materials from a wafer. Examples include etching processes (wet or dry) and chemical mechanical planarization (CMP), etc. Semiconductor doping is to modify electrical properties by doping (e.g., transistor source and drain) usually by diffusion and / or by ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing is used to activate the implanted dopant. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to change as voltage is applied. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the formation of a three-dimensional (3D) relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern to a substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called a photoresist. In order to build the complex structure of transistors and the many wires that connect the millions of transistors of the circuit, the lithography and etching pattern transfer steps are repeated many times. Each pattern printed on the wafer is aligned with the previously formed pattern, and conductors, insulators, and selectively doped regions are slowly built to form the final device.

[0028] Turning now to the generalities associated with the embodiments, transistors are semiconductor devices commonly found in a wide variety of ICs. Typical semiconductor devices are formed using active regions of a wafer. The active region is defined by an insulating region for separating and electrically insulating adjacent semiconductor devices. For example, in an IC having multiple GAA FETs, each GAA FET has a source and a drain formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the corresponding source and drain materials. Disposed between the source and drain is a channel (or body) region. A gate is disposed around the channel. The gate and the channel are separated by a dielectric layer.

[0029] GAA FETs can be manufactured using so-called complementary metal oxide semiconductor (CMOS) manufacturing technology. Generally, CMOS is a technology that uses complementary and symmetrical pairs of p-type MOSFETs and n-type MOSFETs to implement logic functions. A channel region connects the source and the drain, and current flows from the source to the drain through the channel region. Current flow is induced in the channel region by a voltage applied at the gate electrode.

[0030] The wafer footprint of a GAA FET is related to the conductivity of the channel material. If the channel material has a relatively high conductivity, a GAA FET can be manufactured with a correspondingly smaller wafer footprint. A known method of increasing channel conductivity and reducing the size of a GAA FET is to form the channel into nanostructures, such as nanowires or nanosheets. These GAA FETs provide a relatively small FET footprint by forming the channel into a series of vertical nanostructures.

[0031] In a known GAA configuration, a nanostructure-based FET includes a source region, a drain region, and a stacked nanostructure channel between the source region and the drain region. The gate surrounds the stacked nanostructure channel and regulates the flow of electrons through the nanostructure channel between the source region and the drain region. GAA FETs can be manufactured by forming alternating layers of channel nanostructure layers and sacrificial nanostructure layers. The sacrificial nanostructure layer is released from the channel nanostructure before the GAA FET device is completed. For n-type GAAFETs, the channel nanostructure layer can be silicon (Si), and the sacrificial nanostructure layer can be silicon germanium (SiGe). For p-type GAA FETs, in some embodiments, the channel nanostructure layer can be SiGe, and the sacrificial nanostructure layer can be Si, and in other embodiments, the channel nanostructure can be Si, and the sacrificial nanostructure can be SiGe.

[0032] Forming a GAA nanostructure with alternating layers of channel nanostructure layers formed of a first type of semiconductor material (e.g., Si for n-type FET and SiGe for p-type FET) and sacrificial nanostructure layers formed of a second type of semiconductor material (e.g., SiGe for n-type FET and Si for p-type FET) can provide excellent channel electrostatic control, which is beneficial to the continuous scaling of CMOS technology.

[0033] Turning now to a more detailed description of fabrication operations and resulting structures according to embodiments of the present disclosure, Figure 1-8 The semiconductor device 100 is depicted after various manufacturing operations. For ease of illustration, the semiconductor device 100 will be described in the context of forming one or more GAAFETs. Figure 1-8 The fabrication operations described herein are equally applicable to the fabrication of any number and / or logically positioned FET types.

[0034] Although the cross-sectional structural diagrams depicted in the accompanying drawings are two-dimensional (2D), it should be understood that the depicted diagrams represent 3D devices. Figure 1 The top-down reference diagram shown in Figure 1-8The various cross-sectional views (X view, Y view) shown in FIG. 1 provide reference. The X view is a side cross-sectional view taken along the channel stack 125 across three (3) gates 135, and the Y view is another side cross-sectional view taken along one of the gates 135 across two of the channel stacks 125. For clarity, the gate 135 is depicted as a common gate or gate structure, and can be, for example, a sacrificial gate or sacrificial gate structure, a replacement gate conductor or replacement gate structure, etc.

[0035] Figure 1 A cross-sectional view of a semiconductor device 100 after initial manufacturing operations according to an embodiment of the present disclosure is depicted. In this manufacturing stage, one or more channel stacks 125 are formed on a substrate 102. Additionally, in this manufacturing stage, shallow trench isolation (STI) regions 130 may be formed on the substrate 102 alongside the channel stacks 125.

[0036] Non-limiting examples of suitable materials for the substrate 102 include Si (silicon), strained Si, SiC (silicon carbide), Ge (germanium), SiGe (silicon germanium), SiGe:C (silicon-germanium-carbon), Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any combination thereof. Other non-limiting examples of semiconductor materials include III-V materials, such as indium phosphide (InP), gallium arsenide (GaAs), aluminum arsenide (AlAs), or any combination thereof. The III-V material may include at least one "III element", such as aluminum (Al), boron (B), gallium (Ga), indium (In), and at least one "V element", such as nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb). The substrate 102 may be a bulk semiconductor material including Si, a multilayer substrate such as a silicon-on-insulator (SOI) substrate, or the like.

[0037] A bottom sacrificial layer 108 may be formed on the substrate 102. Subsequently, an alternating nanostructure layer may be formed on the bottom sacrificial layer 108. The bottom sacrificial layer 108 may be initially formed above the substrate 102. The bottom sacrificial layer 108 may include an epitaxial SiGe layer with a high Ge% (ranging from 50% to 70%). In some embodiments of the present disclosure, the bottom sacrificial layer 108 is SiGe with a Ge percentage that is sufficiently different from the Ge percentage in the sacrificial nanolayer, so that the bottom sacrificial layer 108 can be selectively removed without also removing the SiGe sacrificial nanolayer. The bottom sacrificial layer 108 may have a thickness of, for example, about 4 to about 15 nm.

[0038] In some embodiments, the bottom sacrificial layer 108 may be omitted, and the channel stack 125 may be formed directly on the top surface of the substrate 102 .

[0039] The channel stack 125 may include portions formed of alternating series of sacrificial nanolayers (such as SiGe sacrificial nanolayers) and portions of nanolayers (such as Si nanolayers). The sacrificial SiGe nanolayers may have a lower Ge% ranging from 20% to 45%. The sacrificial portions 110, 114, 118, and 122 of each of the channel stacks 125 may be formed by associated sacrificial nanolayers, and the nanostructure channels 112, 116, and 120 of each of the channel stacks 125 may be formed by associated nanolayers.

[0040] According to an embodiment of the present disclosure, the bottom sacrificial layer 108 may be epitaxially grown from the substrate 102, and the alternating nanolayers may be formed by epitaxially growing one layer and then the next layer until the desired number of layers and the desired thickness are achieved. Any number of alternating layers may be provided. The epitaxial material may be grown from a gaseous or liquid precursor. The epitaxial material may be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. Depending on the type of transistor, epitaxial silicon, silicon germanium, and / or carbon-doped silicon (Si:C) silicon may be doped during deposition (in-situ doping) by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium).

[0041] The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" mean the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), wherein the grown semiconductor material (crystalline capping layer) has substantially the same crystalline characteristics as the semiconductor material (seed material) of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface so that the deposited atoms orient themselves to the crystal arrangement of the atoms of the deposition surface. As a result, the epitaxially grown semiconductor material has substantially the same crystalline characteristics as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a (100) oriented crystalline surface will exhibit a (100) orientation. In some embodiments, the epitaxial growth and / or deposition process is selective for formation on semiconductor surfaces and generally does not deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

[0042] In some embodiments of the present disclosure, the nanolayer is formed of silicon (Si), and may include, for example, single crystal Si. The nanolayer may have, for example, a thickness of about 4 to about 12 nm. In embodiments where the sacrificial nanolayer includes SiGe, the sacrificial nanolayer may have, for example, a thickness of about 4 to about 12 nm. Subsequently, a mask layer (not shown) may be formed on top of the uppermost sacrificial nanolayer.

[0043] At the current manufacturing stage, each of the channel stacks 125 may include a bottom sacrificial portion 108, a sacrificial nanolayer portion 110, a nanostructure channel 112, a sacrificial nanolayer portion 114, a nanostructure channel 116, a sacrificial nanolayer portion 118, a nanostructure channel 120, and a sacrificial nanolayer portion 122. The channel stacks 125 may be formed by patterning the associated layers or portions thereof.

[0044] One or more channel stacks 125 may be patterned by removing corresponding undesirable portions (one or more) or segments (one or more) of the aforementioned layers while retaining corresponding desired portions. Removal of the bottom sacrificial layer and the undesirable portions of the alternating sacrificial nanolayers and nanolayers may be accomplished using, for example, conventional photolithography and etching processes. Removal of such undesirable portions may further remove undesirable portions of the substrate 102, as depicted. The bottom sacrificial layer and the desired portions of the alternating sacrificial nanolayers and nanolayers may be retained, thereby forming one or more channel stacks 125.

[0045] Subsequently, STI regions 130 may be formed over the substrate 102 and adjacent to the one or more channel stacks 125. The STI regions 130 may be formed by depositing an STI dielectric material on the substrate 102 and adjacent to the channel stacks 125, followed by etching back the STI dielectric material, making recesses, etc. The STI regions 130 may electrically insulate components or features of adjacent GAA FETs, etc. In the depicted embodiment, the top surface of the one or more STI regions 130 may be coplanar with the bottom surface of the bottom sacrificial portion 108 (one or more) of the one or more channel stacks 125.

[0046] Figure 2 A cross-sectional view of a semiconductor device 100 is depicted after exemplary manufacturing operation(s) according to one or more embodiments. In the depicted manufacturing stage, one or more sacrificial gate structures 144 are formed on and around one or more channel stacks 125 and on STI regions 130. The sacrificial gate structures 144 may include a sacrificial gate liner (not shown), a sacrificial gate 140, and a sacrificial gate cap 142.

[0047] The sacrificial gate structure 144 may be formed by forming a sacrificial gate liner layer (e.g., a dielectric, an oxide, etc.) on the STI region 130 and on and around the channel stack 125. For example, the sacrificial gate liner layer may be deposited on the upper surface of the STI region 130, the sidewalls of the bottom sacrificial portion 108, the sidewalls of the sacrificial nanolayer portion 110, the sidewalls of the nanostructure channel 112, the sidewalls of the sacrificial nanolayer portion 114, the sidewalls of the nanostructure channel 116, the sidewalls of the sacrificial nanolayer portion 118, the sidewalls of the nanostructure channel 120, and the sidewalls and upper surface of the sacrificial nanolayer portion 122.

[0048] The sacrificial gate structure 144 may be further formed by subsequently forming a sacrificial gate layer (eg, amorphous silicon, etc.) on the sacrificial gate liner. The thickness of the sacrificial gate layer may be greater than the height of the one or more channel stacks 125.

[0049] It may also be formed by subsequently forming a gate capping layer on the sacrificial gate layer. The gate capping layer may be formed by depositing a mask material (such as a hard mask material) to form a sacrificial gate structure 144. The gate capping layer may be composed of one or more layers of masking material to protect the sacrificial gate layer and / or other underlying materials during subsequent processing of the semiconductor device 100. The gate capping layer may be formed of known gate mask materials, such as silicon nitride, silicon oxide, combinations thereof, and the like.

[0050] Conventional photolithography and etching processes may be used to pattern the gate cap layer, the sacrificial gate layer, and the sacrificial gate liner to remove undesirable portions and retain desired portions (one or more), respectively. The retained desired portions (one or more) of the gate cap layer, the sacrificial gate layer, and the sacrificial gate liner may form a sacrificial gate liner (not shown), a sacrificial gate 140, and a sacrificial gate cap 142 of each of the one or more sacrificial gate structures 144, respectively.

[0051] Each sacrificial gate structure 144 can be formed on a target area or portion of the semiconductor device 100 to define the length of one or more GAA FETs, one or more GAA FET channels, etc., and provide sacrificial material for producing a target GAA FET structure (one or more) in subsequent processing. According to an example, each sacrificial gate structure 144 can have a height between about 50nm and about 200nm and a length between about 15nm and about 200nm.

[0052] Figure 3 A cross-sectional view of a semiconductor device 100 is depicted, shown after exemplary manufacturing operation(s) according to one or more embodiments. In the depicted manufacturing stage, the bottom sacrificial portion 108 may be selectively removed, a bottom dielectric insulation (BDI) region 152 may be formed in its place, and one or more gate spacers 154 may be formed.

[0053] The bottom sacrificial portion 108 can be selectively removed and can thus form an associated BDI cavity between the substrate 102 and the sacrificial nanolayer portion 110, respectively. Instead of removing the bottom sacrificial portion 108, a BDI region 152 can be formed between the substrate 102 and the sacrificial nanolayer portion 110 within each of the channel stacks 125.

[0054] Furthermore, in the depicted manufacturing stage, gate spacers 154 may be formed around each of the one or more sacrificial gate structures 144. Each gate spacer 154 may also be formed on at least a portion of a sidewall of the one or more channel stacks 125 and on a top surface of a portion of the STI regions 130.

[0055] The BDI region 152 and the gate spacer 154 may be formed simultaneously by conformally depositing a dielectric material (e.g., silicon nitride, SiBCN, SiNC, SiN, SiCO, SiNOC, or a combination thereof, etc.) within the BDI cavity(ies) and on the STI region 130 and around each of the one or more sacrificial gate structures 144. Undesirable portions(s) of the dielectric material may be removed by etching or other subtractive removal processes. Desired portions(s) of the dielectric material may remain within the BDI cavity and the BDI region(s) 152 may be formed. Additional desired portions(s) of the additional dielectric material(s) may remain on the top surface of the STI region 130, adjacent to and on the sidewalls of the sacrificial gate structure 144, and around the one or more channel stacks 125.

[0056] Figure 4 A cross-sectional view of a semiconductor device 100 is depicted after exemplary manufacturing operation(s) according to one or more embodiments. In the depicted manufacturing stage, one or more source / drain (S / D) recesses 160 and one or more nanostructure stacks 170 are formed.

[0057] One or more S / D recesses 160 and one or more nanostructure stacks 170 can be formed by making a recess or otherwise removing at least one corresponding portion of one or more channel stacks 125 that is not protected by the sacrificial gate structure 144 and / or the gate spacer 154. For example, unprotected and / or undesirable portions of each of the channel stacks 125 can be etched or otherwise removed. The etching can use the top surface of the BDI region 152 as an etch stop. The retained one or more portions of the channel stacks 125 can effectively form one or more nanostructure stacks 170.

[0058] At the current stage of manufacturing, the nanostructure stack 170 may include a sacrificial nanolayer portion 180 formed from the sacrificial nanolayer portion 110 (see Figure 3 ), nanostructured channel 182 formed by nanostructured channel 112 (see Figure 2 ), the sacrificial nano-layer portion 184 formed by the sacrificial nano-layer portion 114 (see Figure 2 ), nanostructured channel 186 formed by nanostructured channel 116 (see Figure 2 ), the sacrificial nano-layer portion 188 formed by the sacrificial nano-layer portion 118 (see Figure 2 ), nanostructure channel 190 formed by nanostructure channel 120 (see Figure 2 ), and a sacrificial nano-layer portion 192 formed by the sacrificial nano-layer portion 122 (see Figure 2 ).

[0059] One or more nanostructure stacks 170 may be further modified or fabricated by selectively recessing the length of sacrificial nanolayer portions 180, 184, 188, 192, etc. or otherwise recessing the sacrificial nanolayer portions 180, 184, 188, 192, etc. laterally. Such lateral recessing of the sacrificial nanolayer portions 180, 184, 188, 192 may be provided, for example, by a vapor phase process, which leaves other structures (e.g., substrate 102, BDI region 152, gate spacer 154, nanostructure channels 182, 186, 190, etc.) substantially intact.

[0060] The inner spacer 196 may be formed within an indentation or lateral recess of the sacrificial nanolayer portion 180, 184, 188, 192. The inner spacer 196 may be formed by depositing an electrically insulating material (e.g., a dielectric) to pinch off a previously formed recess to produce an inner spacer 196 positioned therein (e.g., above and below each of the nanostructure channels 182, 186, 190 within the nanosheet stack 170). For example, one inner spacer 196 may be formed on the sidewalls of the sacrificial nanolayer portion 180 and between the BDI region 152 and the nanostructure channel 182, one inner spacer 196 may be formed on the sidewalls of the sacrificial nanolayer portion 184 and between the nanostructure channel 182 and the nanostructure channel 186, one inner spacer 196 may be formed on the sidewalls of the sacrificial nanolayer portion 188 and between the nanostructure channel 186 and the nanostructure channel 190, and one inner spacer 196 may be formed on the sidewalls of the sacrificial nanolayer portion 192 and between the nanostructure channel 190 and the gate spacer 154. At the current manufacturing stage, the nanostructure stack 170 may also include the inner spacer 196.

[0061] Figure 5 A cross-sectional view of a semiconductor device 100 is depicted after exemplary manufacturing operation(s) according to one or more embodiments. In the depicted manufacturing stage, S / D regions 240 are formed in one or more S / D recesses 160, respectively, and S / D caps 252 are formed on one or more S / D regions 240, respectively.

[0062] The S / D region 240 can be formed by epitaxially growing a source / drain epitaxial region in the S / D recess 160, for example, from the exposed inner sidewalls in the S / D recess 160. In some embodiments, the S / D region 240 is formed by in-situ doping epitaxial growth. In some embodiments, the epitaxial growth and / or deposition process can be selective for formation on a semiconductor surface and may not deposit material on a dielectric surface, such as a silicon dioxide or silicon nitride surface. In some embodiments, the epitaxial growth of the S / D region 240 can overgrow above the upper surface of the semiconductor device 100.

[0063] Suitable n-type dopants include, but are not limited to, phosphorus (P), and suitable p-type dopants include, but are not limited to, boron (B). The use of an in-situ doping process is merely an example. For example, an ex-situ process may be used instead to introduce dopants into the source and drain. Other doping techniques may be used to incorporate dopants into the bottom source / drain region. Dopant techniques include, but are not limited to, ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implant doping, liquid phase doping, solid phase doping, in-situ epitaxial growth, or any suitable combination of these techniques. In a preferred embodiment, the S / D epitaxial growth conditions promote in-situ boron doped SiGe for p-type transistors and phosphorus or arsenic doped silicon or Si:C for n-type transistors. The doping concentration in the S / D region 240 may be between 1×10 19 cm -3 Up to 2×10 21 cm -3 , or preferably 2×10 20 cm -3 Up to 7×10 20 cm -3 .

[0064] In some embodiments, the S / D regions 240 can be partially recessed such that an upper portion of the S / D regions 240 is removed. For example, an upper portion of one or more S / D regions 240 can be etched or otherwise removed. The etching can be timed or otherwise controlled to stop removing one or more S / D regions 240 such that a top surface of the remaining one or more S / D regions 240 is above an upper surface of the nanostructure channel 190. The partial removal of the upper portion of the S / D region 240 can at least partially reform the S / D recess 160.

[0065] The S / D cap 252 may be formed on one or more S / D regions 240 within the partially reformed S / D recess 160, respectively. The S / D cap 252 may be formed by depositing a dielectric material (e.g., silicon nitride, SiBCN, SiNC, SiN, SiCO, SiNOC, or a combination thereof, etc.) within the partially reformed S / D recess 160 and on the S / D region 240. In one embodiment, the S / D cap 252 may be formed to a thickness above the top surface of the semiconductor device 100 and then etched back so that the top surface of the S / D cap 252 is coplanar with the top surface of the sacrificial gate structure 144 and / or the top surface of the gate spacer 152. The S / D cap 252 may also be referred to herein as an S / D insulator. In some embodiments, the S / D cap 252 may also be referred to as an interlayer dielectric (ILD).

[0066] Figure 6 Depicted is a cross-sectional view of a semiconductor device 100 shown after exemplary manufacturing operation(s) in accordance with one or more embodiments. In the depicted manufacturing stage, a gate opening 250 is formed.

[0067] The gate opening 250 can be formed by removing the sacrificial gate structure 144, and as depicted in the Y cross-sectional view, can expose at least corresponding segments of the upper surface of the STI region 130, corresponding sidewall surface segments of the BDI region 152, corresponding sidewall surface segments of the sacrificial nanolayer portions 180, 184 and 188 and 192, and corresponding sidewall surface segments of the nanolayer channels 182, 186 and 190.

[0068] Figure 7 Depicted is a cross-sectional view of a semiconductor device 100 shown after exemplary fabrication operation(s) in accordance with one or more embodiments. In the depicted fabrication stage, the nanostructure stack 170 is modified by selectively removing sacrificial nanolayer portions 180 , 184 , 188 , and 192 .

[0069] Various techniques may be utilized to process the nanostructure stack 170. For example, the gate opening 250 may laterally or otherwise expose the nanostructure stack 170. Subsequently, the exposed sacrificial nanolayer portions 180, 184, 188, and 192 may be removed to expose the nanolayer channels 182, 186, and 190 within the nanostructure stack 170. As shown in the X cross-section, the upper and lower surfaces of the nanolayer channels 182, 186, and 190 may be exposed inside or within the adjacent inner spacers 196 associated with the adjacent nanostructure stack 170. As depicted in the Y cross-section, the perimeters of the nanolayer channels 182, 186, and 190 may be exposed inside or within the adjacent inner spacers 196 associated with the adjacent nanostructure stack 170.

[0070] Figure 8 Depicted is a cross-sectional view of semiconductor device 100 shown after exemplary manufacturing operation(s) according to one or more embodiments. In the depicted manufacturing stage, a replacement gate structure 289 is formed within gate opening 250 around nanolayer channels 182 , 186 , and 190 .

[0071] The replacement gate structure 289 may include a gate dielectric 290 and a gate conductor 292. The gate dielectric 290 may include any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or any combination of these materials. The gate dielectric 290 may be formed by any suitable deposition process, etc. In some embodiments, the gate dielectric 290 has a thickness ranging from 1 nm to 5 nm, although lesser thicknesses and greater thicknesses are also contemplated.

[0072] Gate conductor 292 may include any suitable conductive material, including but not limited to doped polysilicon or amorphous silicon, germanium, silicon germanium, metal (eg, silicon), metal (eg, silicon), and the like. For example, tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au), conductive metal compound materials (e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide (CoSi), nickel silicide (NiSi)), transition metal aluminides (e.g., Ti3Al, ZrAl), TaC, TaMgC, carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials.

[0073] The gate conductor 292 may also include dopants incorporated during or after deposition. In some embodiments, the gate conductor 292 may also include a work function setting layer (not shown) between the gate dielectric 290 and the gate conductor 292. The work function setting layer may be a work function metal (WFM). The gate conductor 292 and the WFM may be formed by any suitable process or any suitable combination of processes, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electroplating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, etc.

[0074] The replacement gate structure 289 may be formed by initially forming a gate dielectric layer within the gate opening 250 around the nanolayer channels 182, 186, and 190, on the sidewalls of the inner spacer 196, on the gate spacer 154, and on the top surface of the BDI region 152. The replacement gate structure 289 may be further formed by subsequently forming a gate conductor layer on the gate dielectric layer. For clarity, the replacement gate structure 289 may be a wraparound gate structure, a gate all around structure, because the gate conductor 292 wraps around the nanolayer channels 182, 186, and 190, as shown in the Y cross section.

[0075] The gate conductor layer and the gate dielectric layer can be patterned using conventional photolithography and etching processes to remove undesirable portions and retain desired portions (one or more), respectively. The retained desired portions (one or more) of the gate conductor layer and the gate dielectric layer can form the gate dielectric layer 290 and the gate conductor 292 of the replacement gate structure 292. The etching process or another subtractive removal technique can remove the undesirable portions of the replacement gate structure 289 so that the top surface of the replacement gate structure 289 is coplanar with the top surface of the semiconductor device 100.

[0076] In some embodiments, the gate conductor 292 can be recessed below the top surface of the semiconductor device 100 , and a dielectric gate cap (not shown) can be formed on the recessed gate conductor 292 .

[0077] Figure 9-14 The semiconductor device 300 is depicted after various manufacturing operations. For example, Fig. 9 The semiconductor device 300 depicted in FIG. 3 may have previously undergone Figure 1-5 The manufacturing operations are similar to those depicted in FIG. Fig. 9 As shown, semiconductor device 300 may include substrate 302, BDI region 352, nanostructure stack 370, S / D 340, S / D cap 452, sacrificial gate structure and / or gate spacer 354. Nanostructure stack 370 may include sacrificial nanolayer portions 380, 384, 388, and 392. Nanostructure stack 370 may also include nanolayer channels 382, ​​386, and 390. Nanostructure stack 370 may also include inner spacer 396.

[0078] For clarity, substrate 302 , BDI region 352 , nanostructure stack 370 , S / D 340 , S / D cap 452 , sacrificial gate structure and / or gate spacer 354 may be formed of similar materials and by similar fabrication techniques as described with reference to related features of semiconductor device 100 .

[0079] Semiconductor device 300 may include SG GAA FET 303 and EG GAA FET 305. According to an embodiment of the present disclosure, SG GAA FET 303 is fabricated to include a relatively thin gate dielectric, and EG GA FET 305 is fabricated to include an effectively thick gate dielectric. As depicted, EG GAFET 305 may include a channel having a greater channel length relative to an associated channel length within SG GAA FET 303.

[0080] The SG GAA FET 303 and the EG GAA FET 305 may be formed on the same substrate 302 and / or BDI region 352. For clarity, the SG GAA FET 303 and the EG GAA FET 305 may be formed in the same type of region (e.g., a p-type region or an n-type region), but may be formed in the same regional location or different regional locations of the semiconductor device 300, as depicted.

[0081] When the SG GAA FET 303 and the EG GAA FET 305 are of the same type (e.g., p-type or n-type), the SG GAA FET 303 and the EG GAA FET 305 may utilize appropriate, similar, or identical material(s), dopant(s), etc. to form their respective S / D 340, replacement gate structures. When the SG GAA FET 303 and the EG GAA FET 305 are of different types (e.g., p-type or n-type), the SG GAA FET 303 and the EG GAA FET 305 may utilize appropriate or different material(s), dopant(s), etc. to form their respective S / D 340, replacement gate structures.

[0082] Fig. 9 Depicted is a cross-sectional view of a semiconductor device 300 shown after exemplary manufacturing operation(s) in accordance with one or more embodiments. In the depicted manufacturing stage, a gate opening 450 is formed.

[0083] The gate opening 450 may be formed by removing the sacrificial gate structure, and may expose at least a corresponding portion of the upper surface of the STI region, a corresponding sidewall surface portion of the BDI region 352, a corresponding sidewall surface portion of the sacrificial nanolayer portions 380, 384, 388, and 392, and a corresponding sidewall surface portion of the nanolayer channels 382, ​​386, and 390. In other words, the gate opening 450 may expose the side surfaces of the BDI 352, the sacrificial nanolayer portions 380, 384, 388, and 392, and the nanolayer channels 382, ​​386, and 390. The gate opening 450 may further expose the top surface of the sacrificial nanolayer portion 392. The gate opening 450 may further expose at least an inner portion or an inner-facing portion of the gate spacer 354.

[0084] Fig.10 A cross-sectional view of semiconductor device 300 is depicted after exemplary manufacturing operations according to one or more embodiments. In the depicted manufacturing stage, nanostructure stack 370 of SG GAA FET 303 and nanostructure stack 370 of EG GAA FET 305 are processed by selectively removing sacrificial nanolayer portions 380, 384, 388, and 392 therein. Subsequently, in the depicted manufacturing stage, replacement gate structure 489 is formed around nanolayer channels 382, ​​386, and 390 within gate opening 450 of SG GAA FET 303, and replacement gate structure 491 is formed around nanolayer channels 382, ​​386, and 390 within gate opening 450 of EG GAA FET 305.

[0085] Various techniques may be utilized to process the nanostructure stack 370 of the SG GAA FET 303 and the nanostructure stack 370 of the EG GAA FET 305 to selectively remove the respective sacrificial nanolayer portions 380, 384, 388, and 392 therein. For example, the first gate opening 450 may laterally or otherwise expose the nanostructure stack 370 of the SG GAA FET 303, and the second gate opening 450 may laterally or otherwise expose the nanostructure stack 370 of the EG GAA FET 305. Subsequently, the exposed sacrificial nanolayer portions 380, 384, 388, and 392 may be removed to expose the associated nanolayer channels 382, ​​386, and 390. As shown, the upper, lower, and side surfaces of the nanolayer channels 382, ​​386, and 390 may be exposed inside or within the adjacent inner spacer 396.

[0086] In some embodiments, nanolayer channels 382, ​​386, and 390 can be trimmed, for example, by etching or other selective removal processes. Nanolayer channels 382, ​​386, and 390 can be trimmed to increase the vertical space between vertically adjacent nanolayer channels 382, ​​386, and 390 to prevent undesired merging of vertically adjacent nanolayer channels. Trimming of nanolayer channels 382, ​​386, and 390 can be accomplished by a vapor phase etching process, controlled etching cycles, and the like.

[0087] The replacement gate structures 489, 491 include a gate dielectric 391 and a gate conductor 392. The gate dielectric 391 may include any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or any combination of these materials. The gate dielectric 391 may be formed by any suitable deposition process, etc. In some embodiments, the gate dielectric 391 has a thickness ranging from 1 nm to 5 nm, although smaller thicknesses and greater thicknesses are also contemplated.

[0088] The gate conductor 392 may include any suitable conductive material, including but not limited to doped polysilicon or amorphous silicon, germanium, silicon germanium, metal (eg, silicon), metal (eg, silicon), and the like. For example, tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au), conductive metal compound materials (such as tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide (CoSi), nickel silicide (NiSi)), transition metal aluminides (such as Ti3Al, ZrAl), TaC, TaMgC, carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials. The gate conductor 392 may further include dopants incorporated during or after deposition, as may be suitable for inclusion within the SG GAA FET 303 (eg, GAA FET 305), respectively.

[0089] In some embodiments, the replacement gate structures 489, 491 may further include a work function conductor 394 between the gate dielectric 391 and the gate conductor 392. The work function conductor 394 may be a work function metal (WFM). The gate conductor 392 and the work function conductor 394 may be sequentially formed by any suitable process or any suitable combination of processes, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electroplating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, etc.

[0090] Replacement gate structures 489, 491 may be formed by forming a gate dielectric layer within gate opening 450 around nanolayer channels 382, ​​386, and 390, on the sidewalls of inner spacer 396, on gate spacer 354, and on the top surface of BDI 352, respectively. Replacement gate structures 489, 491 may be further formed by subsequently forming a work function conductor layer on the gate dielectric layer. The work function conductor layer may fill the remaining space between BDI 352 and nanolayer channel 382, ​​may fill the remaining space between nanolayer channel 382 and nanolayer channel 386, and may fill the remaining space between nanolayer channel 386 and nanolayer channel 390, as shown. Replacement gate structures 489, 491 may be further formed by forming a gate conductor layer on the work function conductor layer filling the remaining gate opening 450. For clarity, the replacement gate structures 489, 491 may be wrap-around gate structures, gate-all-around structures, because the conductor(s) of the replacement gate structures 489, 491 wrap around the corresponding nanolayer channels 382, ​​386, and 390, respectively.

[0091] Conventional photolithography and etching processes may be used to pattern the gate conductor layer, the work function conductor layer, and the gate dielectric layer to remove undesirable portions and retain desired portions (one or more), respectively. The retained desired portions (one or more) of the gate conductor layer, the work function conductor layer, and the gate dielectric layer may form the gate dielectric layer 390, the work function conductor 394, and the gate conductor 392 of the replacement gate structures 489, 491, respectively. An etching process or another subtractive removal technique may remove undesirable portions of the replacement gate structures 489, 491 such that the top surfaces of the replacement gate structures 489, 491 are coplanar with the top surface of the semiconductor device 300.

[0092] Fig.11A cross-sectional view of semiconductor device 300 is depicted after exemplary manufacturing operation(s) according to one or more embodiments. In the depicted manufacturing stage, mask 460 is formed over SG GAA FET 303 and / or replacement gate structure 491 is partially recessed, which forms second gate opening 462 .

[0093] The mask 460 may be a dielectric material, an organic planarization material, or a mask material, and may be formed by deposition of a mask material over at least the SG GAA FET 303. The mask 460 material may be further deposited on the S / D caps 452, gate spacers 354, etc. associated with the SG GAA FET 303. The mask 460 may be formed by depositing a blanket mask material over the semiconductor device 300 and removing the blanket mask material over the EG GAA FET 305 while retaining the blanket mask material over the SG GAA FET 303. The mask 460 may protect the SG GAA FET 303 from subsequent processing of the replacement gate structure 491.

[0094] The replacement gate structure 491 may be partially recessed using conventional photolithography and etching processes. For example, the thickness or height of the work function conductor 394 and the gate conductor 392 of the replacement gate structure 491 is reduced by partially recessing them, as depicted. After the replacement gate structure 491 is partially recessed, the respective top surfaces of the work function conductor 394 and the gate conductor 392 may be coplanar. In a particular embodiment, as depicted, the top surfaces of the work function conductor 394 and the gate conductor 392 may be located between the top and bottom surfaces of the surrounding gate spacer 454. The gate dielectric layer 390 may be retained or otherwise maintained when formed so that the top surface of the gate dielectric layer 390 is coplanar with the surrounding gate spacer 454. Alternatively, the gate dielectric layer 390 may be partially recessed along with the other replacement gate structure 491 materials. In this embodiment, the respective top surfaces of each material of the replacement gate structure 491 may be coplanar.

[0095] Recessing the replacement gate structure 491 generally reduces the thickness of the replacement gate structure 491 such that one or more top surfaces of the material of the replacement gate structure 491 (e.g., work function conductor 394 and gate conductor 392) are lower than the top surface of the surrounding semiconductor device 300 material (such as gate structure 454). In this manner, a second gate opening 462 is formed between the top surface of the recessed replacement gate structure 491 and the top surface of the surrounding semiconductor device 300 material. In some embodiments, the thickness of the replacement gate structure 491 is reduced by 10 nm to 30 nm, although greater or lesser reductions are also contemplated.

[0096] Fig.12 A cross-sectional view of a semiconductor device 300 is depicted after exemplary manufacturing operation(s) according to one or more embodiments. In the depicted manufacturing stage, the mask 460 is removed and a gate dielectric layer 470 is formed over the replacement gate structure 491 of the EG GAA FET 305 within the second gate opening 462. In some embodiments, as depicted, the gate dielectric layer 470 is formed over the EG GAA FET 305 and the SG GAA FET 303.

[0097] The gate dielectric layer 470 may be formed by depositing a blanket dielectric layer over the EG GAA FET 305 within the second gate opening 462 and over the SG GAA FET 303. For example, the gate dielectric layer 470 may be deposited over the SGGAA FET 303 on the respective top surfaces of the S / D cap 452, the gate spacer 354, and the replacement gate structure 489, and the gate dielectric layer 470 may be deposited over the EGGAA FET 305 on the top surfaces of the S / D cap 452 and the gate spacer 354, on the portions of the gate dielectric layer 390 exposed during the formation of the second gate opening 462, and on the top surface(s) of the recessed replacement gate structure 491. In a particular embodiment, the thickness of the gate dielectric layer 470 is selected to achieve a dielectric layer having a thickness of 0.040 mm / s from the gate conductor 395 (e.g., Fig.13 ) and a predetermined or desired voltage drop of a work function conductor 394 surrounding nanolayer channels 382, ​​386 and 390.

[0098] The gate dielectric layer 470 may include any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, high-k material, or any combination of these materials. The gate dielectric layer 470 may be formed by any suitable deposition process, etc. In some embodiments, the gate dielectric 290 has a thickness ranging from 1nm to 20nm, but smaller thicknesses and larger thicknesses may also be envisioned. In an embodiment, the gate dielectric layer 470 is formed of the same material as the gate dielectric 391. For example, the gate dielectric layer 470 and the gate dielectric 391 are formed of the same first high-k dielectric material (i.e., a dielectric material having a greater dielectric constant relative to silicon dioxide). In another embodiment, the gate dielectric layer 470 is formed of a relatively different dielectric material relative to the gate dielectric 391. For example, the gate dielectric 391 is formed of a first high-k dielectric material, and the gate dielectric layer 470 is formed of a different second high-k dielectric material.

[0099] For clarity, at the current manufacturing stage, after the gate dielectric layer 470 is formed, the second gate opening 462 remains or otherwise exists.

[0100] Fig.13 A cross-sectional view of a semiconductor device 300 is depicted after exemplary manufacturing operation(s) according to one or more embodiments. In the depicted manufacturing stage, a gate conductor 395 is formed on the gate dielectric layer 470 of the replacement gate structure 491 within the second gate opening 462, and excess or undesirable gate dielectric layer 470 is removed.

[0101] The gate conductor 395 may include any suitable conductive material, including but not limited to doped polycrystalline or amorphous silicon, germanium, silicon germanium, metal (eg, silicon), metal (eg, silicon), and the like. For example, tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au), conductive metal compound materials (e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide (CoSi), nickel silicide (NiSi)), transition metal aluminides (e.g., Ti3Al, ZrAl), TaC, TaMgC, carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials.

[0102] The gate conductor 395 may further include dopants incorporated during or after deposition, as suitable for inclusion in, for example, the GAA FET 305. The gate conductor 395 may be formed by any suitable process or any suitable combination of processes, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electroplating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, etc.

[0103] In the replacement gate structure 491 of the EG GAA FET 305, a gate conductor 395 can be formed by depositing a gate conductor layer on the gate dielectric layer 470, generally filling the second gate opening 462. In some embodiments, the gate conductor layer can be over deposited to fill the second gate opening 462, so that the top surface of the gate conductor 395 is higher than the top surface of the other semiconductor 300 materials. Subsequently, a chemical mechanical polishing (CMP) or other planarization process can remove excess gate conductor 395 material and / or excess gate dielectric layer 470 material, and can generally planarize the gate conductor 395 material relative to the top surface of the other semiconductor device 300. For example, the respective top surfaces of the S / D cap 452, the gate spacer 354, the replacement gate structure 489, and the replacement gate structure 491 can be coplanar. After CMP, the remaining gate dielectric layer 470 can effectively form the second gate dielectric 472 in the replacement gate structure 491.

[0104] In a particular embodiment, the material, thickness, etc. of the second gate dielectric 472 is selected to achieve a predetermined or desired voltage drop across the gate conductor 395 and the work function conductor 394 that surround the nanolayer channels 382, ​​386, and 390 of the replacement gate structure 491. In such an embodiment, the flow of current from the gate conductor 395 into the nanolayer channels 382, ​​386, and 390 is sequentially (i.e., in series) blocked by both the gate dielectric 472 and the gate dielectric 391. The resistance to this current and the total resistance effect of the gate dielectric (e.g., GAA FET 305) are effectively equal to the sum of the resistances of the gate dielectric 472 and the gate dielectric 391. In this manner, embodiments of the present disclosure provide a nominal or lower effective gate dielectric or gate dielectric resistance within the SG GAA FET 303 and an increased or higher effective gate dielectric or gate dielectric resistance within the EG GAA FET 305.

[0105] Fig.14 A cross-sectional view of semiconductor device 300 is depicted after exemplary manufacturing operation(s) according to one or more embodiments. In the depicted manufacturing stage, ILD 492 is formed on S / D cap 452, on gate spacer 354, on replacement gate structure 489, and on replacement gate structure 491, corresponding S / D contacts 494 are formed on replacement gate structure 489 and on replacement gate structure 491, and corresponding gate contacts 496 are formed on replacement gate structure 489 and on replacement gate structure 491.

[0106] ILD 492 may be any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, high-k material, or any combination of these materials. ILD 492 may be formed by any suitable process or any suitable combination of multiple processes, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0107] ILD 492 may be formed on respective top surfaces of S / D caps 452 associated with replacement gate structure 489 and associated with replacement gate structure 491. ILD 492 may be further formed on respective top surfaces of gate spacers 354 associated with replacement gate structure 489 and associated with replacement gate structure 491. ILD 492 may be further formed on respective top surfaces of gate dielectric 391, gate conductor 392, and / or work function conductor 394 of replacement gate structure 489. Similarly, ILD 492 may be further formed on respective top surfaces of gate dielectric 391, gate dielectric 472, and gate conductor 395 of replacement gate structure 491.

[0108] In the SG GAA FET 303 and the EG GAA FET 305, the S / D contact 494 can be formed by initially forming an S / D contact trench within the ILD 492 and the S / D cap 452. The S / D contact trench can expose the sidewalls of the gate spacer 354, can expose a portion of the sidewalls of the upper inner spacer 396, and can further expose a portion of the corresponding top surface of the S / D 340. Similarly, in the SG GAA FET 303, the gate contact 496 can be formed by initially forming a gate contact trench within the ILD 492. The gate contact trench can expose a portion or the entire top surface of the replacement gate structure 489. For example, the gate contact trench can expose the top surface of the gate conductor 392 and the top surface of the work function conductor 394 of the replacement gate structure 489.

[0109] In EG GAA FET 305, gate contact 496 may be formed by initially forming a gate contact trench within ILD 492. The gate contact trench may expose a portion or the entire top surface of replacement gate structure 491. For example, the gate contact trench may expose a portion of the top surface of gate conductor 395.

[0110] Subsequently, one S / D contact 494 may be formed in each S / D contact trench by depositing a conductive material in each S / D contact trench, and one gate contact 496 may be formed in each gate contact trench by depositing a conductive material in each gate contact trench.

[0111] The S / D contact 494 and the gate contact 492 may be formed by depositing conductive material on the replacement gate structure 489 and the replacement gate structure 491 to fill the corresponding contact trench(es). CMP or other grinding techniques may remove excess conductive material of the S / D contact 494 and the gate contact 492. The planarization may result in the upper surfaces of the S / D contact 494 and the gate contact 492 being coplanar with the upper surface of the ILD 492. The S / D contact 494 and the gate contact 492 conductive material may be any common conductive material used as an electrode, such as tungsten, platinum, titanium nitride, tantalum nitride, titanium aluminum nitride, alloys thereof, and the like.

[0112] In some embodiments, the S / D contact 494 and / or the gate contact 492 include an inner conductive region and a conductive barrier layer (one or more, not shown) lining the sidewalls and bottom surface of the inner conductive region. The conductive barrier layer (one or more) can be formed of titanium, titanium nitride, tantalum, tantalum nitride, cobalt, combinations thereof, etc. The inner conductive region can be formed of metals such as copper, aluminum, tungsten, cobalt, tungsten, platinum, titanium nitride, tantalum nitride, titanium aluminum nitride, alloys thereof, etc.

[0113] The formation of the S / D contact 494 and / or the gate contact 492 may include forming a blanket conductive barrier layer extending into the corresponding S / D contact trench and extending into the corresponding gate contact trench, depositing metal over the blanket conductive barrier layer, and performing a planarization process, such as a CMP process grinding process, to remove excess portions of the blanket conductive barrier layer and excess portions of the internal conductive region so that the top surface of the S / D contact 494 and / or the gate contact 492 is coplanar with the ILD 492.

[0114] For clarity, semiconductor device 300 includes EG GAA FET 305 and SG GAA FET 303, the EG GAA FET 305 including a first gate dielectric 391 and a second gate dielectric 472, and the SG GAA FET 303 including only the first gate dielectric 391. In EG GAA FET 305, the first gate dielectric 391 and the second gate dielectric 472 can be the same or different materials, such as the same or different high-k dielectric materials. The second gate dielectric 472 can be selected to achieve a predetermined or desired voltage drop across the gate conductor 395 and the work function conductor 394, which surrounds the nanolayer channels 382, ​​386, and 390 of the replacement gate structure 491. In such embodiments, current flow from the gate conductor 395 into the nanolayer channels 382, ​​386, and 390 is sequentially (i.e., in series) blocked by both the gate dielectric 472 and the gate dielectric 391. The resistance of this current and the total resistance effect of the gate dielectric (e.g., GAA FET 305) is effectively equal to the sum of the resistances of gate dielectric 472 and gate dielectric 391. In this manner, embodiments of the present disclosure provide a nominal or lower effective gate dielectric or gate dielectric resistance in the SG GAA FET 303 and an increased or higher effective gate dielectric or gate dielectric resistance in the EG GAA FET 305.

[0115] Additionally, gate conductor 395 and gate conductor 392 may be referred to herein as upper and lower gate conductors, first and second gate conductors, etc. These descriptions of gate conductor 395 and gate conductor 392 generally define two electrically separated (separated by a resistor) entities or nodes of gate conductor material, such as gate dielectric 472, at which there are (e.g., current impedances to gate conductor 395 and gate conductor 392).

[0116] Fig.15 A flowchart illustrating a method 500 of manufacturing a semiconductor device 300 according to one or more embodiments of the present disclosure is depicted. Figures 9 to 14 One or more of the diagrams and descriptions of the manufacturing operations of the depicted method 500. Referring to the method 500, the semiconductor device 300 may have previously undergone a process similar to Figures 1 to 8 The method 500 described herein is exemplary. Many variations of the diagrams or operations described therein may exist without departing from the spirit of the embodiments. For example, the operations may be performed in a different order, or operations may be added, deleted, or modified.

[0117] Method 500 may include forming a first replacement gate structure around a first nanostructure stack (block 502) and forming a second replacement gate structure around a second nanostructure stack (block 504). The first replacement gate structure includes a first gate dielectric, a work function conductor, and a first gate conductor, and the second replacement gate structure includes a first gate dielectric, a work function conductor, and a first gate conductor. For example, replacement gate structure 489 and replacement gate structure 491 are formed. At the current manufacturing stage, each replacement gate structure 489 and replacement gate structure 491 may include a first gate dielectric 391, a work function conductor 394, and a first gate conductor 392.

[0118] At block 506, method 500 may include forming a mask over the first replacement gate structure. For example, mask 460 is formed over replacement gate structure 489. At block 508, partially recessing the work function conductor and the first gate conductor of the second replacement structure to form a second replacement gate structure gate trench while maintaining the first gate dielectric of the second replacement structure. For example, the thickness of the first gate conductor 392 and the work function conductor 394 of replacement gate structure 491 is reduced by partially removing them, and retaining the first gate conductor 392 to form a gate opening 462. At block 510, method 500 may include removing the mask over the first replacement gate structure. For example, mask 460 is removed over replacement gate structure 489.

[0119] At block 512 and block 514, method 500 may include forming a second gate dielectric layer over the first replacement gate structure and over the second replacement gate structure within the gate opening. For example, second gate dielectric layer 470 may be formed on first gate dielectric 390, first gate conductor 392, and work function conductor 394 of replacement gate structure 489, and may be further formed on first gate dielectric 390, recessed first gate conductor 392, and recessed work function conductor 394 within gate opening 462 of replacement gate structure 491.

[0120] At block 516, method 500 may include forming a second gate conductor on the second gate dielectric layer within the second gate opening of the second replacement gate structure. For example, second gate conductor 395 is located on second gate dielectric layer 470 within gate opening 462 of replacement gate structure 491. In some embodiments, CMP or other planarization processes may remove excess second gate dielectric layer material over the first replacement gate structure and over the second replacement gate structure while retaining the second gate dielectric layer material previously formed within the gate opening.

[0121] At block 518 and block 520, method 500 may include forming gate contacts and forming corresponding source / drain contacts for a first replacement gate structure, and forming gate contacts and forming corresponding source / drain contacts for a second replacement gate structure. For example, forming corresponding S / D contacts 494 and each S / D contact 494 is in direct contact with a corresponding S / D 340 of replacement gate structures 489, 491, forming gate contact 496 and gate contact 496 is in direct contact with a conductor (gate conductor 392, work function conductor 394, etc.) of replacement gate structure 489, and forming another gate contact 496 and another gate contact 496 is in direct contact with a conductor (gate conductor 395, etc.) of replacement gate structure 491.

[0122] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the described embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present disclosure. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments described herein.

Claims

1. A semiconductor device comprising: substrate; a first gate-all-around field effect transistor (GAA FET) on the substrate and comprising a plurality of first nanostructure channels and a first gate structure, the first gate structure comprising a first gate dielectric surrounding the plurality of first nanostructure channels and a first gate conductor over the first gate; and a second GAA FET on the substrate and comprising a plurality of second nanostructure channels and a second gate structure, wherein the second gate structure comprises the first gate dielectric surrounding the plurality of first nanostructure channels, the first gate conductor above the first gate dielectric, a second gate conductor above the first gate conductor, and a second gate dielectric between the first gate conductor and the second gate conductor. 2 . The semiconductor device of claim 1 , wherein the first GAA FET further comprises a first gate spacer surrounding the first gate structure, and wherein the second GAA FET further comprises a second spacer surrounding the second gate structure. 3 . The semiconductor device of claim 2 , wherein the first gate dielectric is located between the first gate conductor and the first gate spacer within the first GAA FET. 4 . The semiconductor device of claim 2 , wherein in the second GAA FET, the first gate dielectric is between the first gate conductor and the second gate spacer, and the second gate dielectric is between the second gate conductor and the second gate spacer. 5 . The semiconductor device of claim 2 , wherein the first gate structure further comprises a first work function conductor between the first gate dielectric and the first gate conductor. 6 . The semiconductor device of claim 5 , wherein the second gate structure further comprises the first work function conductor between the first gate dielectric and the first gate conductor. 7 . The semiconductor device of claim 6 , wherein the second gate dielectric is located between the first gate dielectric and the second gate conductor in the second GAA FET.

8. The semiconductor device according to claim 1, wherein The first gate conductor is configured to receive a first voltage, and the gate conductor is configured to receive a second voltage, wherein the second voltage is greater than the first voltage.

9. The semiconductor device of claim 1 , wherein the first gate structure comprises a first current impedance from the second gate conductor to the plurality of second nanostructure channels, wherein the second gate structure comprises a second current impedance from the first gate conductor to the plurality of first nanostructure channels, and wherein the second current impedance is greater than the first current impedance.

10. The semiconductor device according to claim 1, wherein The plurality of first nanostructure channels and the plurality of second nanostructure channels are formed of a same material. 11 . The semiconductor device of claim 1 , wherein the plurality of first nanostructure channels each have a first channel length, and wherein the plurality of second nanostructure channels each have a second channel length, wherein the second channel length is greater than the first channel length.

12. A semiconductor device comprising: substrate; a low voltage all-around gate field effect transistor (SG GAA FET) disposed on the substrate and comprising a plurality of first nanostructure channels and a first gate structure, the first gate structure comprising a first gate dielectric surrounding the plurality of first nanostructure channels and a first gate conductor over the first gate; and A high voltage all-around gate field effect transistor (e.g., GAA FET) is on the substrate and includes a plurality of second nanostructure channels and a second gate structure, the second gate structure including the first gate dielectric surrounding the plurality of first nanostructure channels, the first gate conductor above the first gate dielectric, a second gate conductor above the first gate conductor, and a second gate dielectric between the first gate conductor and the second gate conductor. 13 . The semiconductor device of claim 12 , wherein the SG GAA FET further comprises a first gate spacer surrounding the first gate structure, and wherein the EG GAA FET further comprises a second spacer surrounding the second gate structure. 14 . The semiconductor device of claim 13 , wherein the first gate dielectric is located between the first gate conductor and the first gate spacer within the SG GAA FET. 15 . The semiconductor device of claim 13 , wherein in the EG GAA FET, the first gate dielectric is located between the first gate conductor and the second gate spacer, and the second gate dielectric is located between the second gate conductor and the second gate spacer. 16 . The semiconductor device of claim 13 , wherein the first gate structure further comprises a first work function conductor between the first gate dielectric and the first gate conductor. 17 . The semiconductor device of claim 16 , wherein the second gate structure further comprises the first work function conductor between the first gate dielectric and the first gate conductor. 18 . The semiconductor device of claim 17 , wherein in the EG GAA FET, the second gate dielectric is located between the first gate dielectric and the second gate conductor.

19. The semiconductor device of claim 12, wherein the first gate structure comprises a first current impedance from the second gate conductor to the plurality of second nanostructure channels, wherein the second gate structure comprises a second current impedance from the first gate conductor to the plurality of first nanostructure channels, and wherein the second current impedance is greater than the first current impedance.

20. A method for manufacturing a semiconductor device, comprising: forming a plurality of first nanostructure channels between a first source and a drain of a first gate all around field effect transistor (GAA FET); forming a plurality of second nanostructure channels between a second source and a drain of a second GAA FET; forming a first gate dielectric around the plurality of first nanostructure channels of the first GAA FET and around the plurality of second nanostructure channels of the second GAA FET; forming a first gate conductor over the first gate dielectric of the first GAA FET and over the first gate dielectric of the second GAA FET; recessing the first gate conductor portion of the second GAA FET; forming a second gate dielectric over the partially recessed first gate conductor of the second GAA FET; and A second gate conductor is formed over the second gate dielectric of the second GAA FET.

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