Sorting control method and device for chip testing

Abstract

The invention discloses a sorting control method and device for chip testing, and relates to the technical field of article sorting, and the sorting control method comprises the following steps: setting a carrier for chip testing; placing a plurality of to-be-tested chips on a plurality of test positions on a carrier, wherein pins of each to-be-tested chip comprise a scanning register and a test access port; connecting a chip test system, and reading test scripts corresponding to the plurality of chips to be tested; controlling the boundary scanning tester to perform boundary scanning testing according to the testing script, and outputting chip response data; and analyzing the chip response data, identifying an abnormal chip and a test position of the abnormal chip, and controlling a sorting mechanism to carry out abnormal sorting according to the test position of the abnormal chip. The technical problems that in the prior art, the sorting speed is low, sorting line planning is unreasonable, and the combination degree of chip testing and sorting control is not tight enough are solved, and the technical effects that the sorting speed is increased, sorting lines are reasonably planned, and the combination degree of chip testing and sorting control is increased are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of object sorting, and in particular to a sorting control method and device for chip testing. Background Art

[0002] With the rapid development of the semiconductor industry, chip testing technology has been widely used in the electronics manufacturing industry. Existing chip testing and sorting methods have achieved a certain degree of automation, which can play an important role in improving efficiency and reducing human errors. However, with the continuous expansion of production scale and the increasing complexity of process flow, in the chip testing process, the sorting and management of normal and abnormal chips still have problems such as insufficient sorting speed, unreasonable path planning, and insufficient integration of chip testing and sorting control. Summary of the invention

[0003] The present application provides a sorting control method and device for chip testing, which are used to solve the technical problems of slow sorting speed, unreasonable sorting line planning, and insufficient integration of chip testing and sorting control in the prior art.

[0004] In view of the above problems, the present application provides a sorting control method and device for chip testing.

[0005] In a first aspect of the present application, a sorting control method for chip testing is provided, the method comprising: A carrier for chip testing is provided, wherein a plurality of test positions are provided on the carrier; a plurality of chips to be tested are placed in the plurality of test positions on the carrier, wherein the pins of each chip to be tested include a scan register and a test access port, and the test single-channel scan chains corresponding to each chip to be tested are interconnected; a chip testing system is connected to read the test scripts corresponding to the plurality of chips to be tested; a boundary scan tester is controlled to perform boundary scan tests on the plurality of chips to be tested according to the test scripts, and chip response data is output; the chip response data is analyzed to identify abnormal chips and the test positions of the abnormal chips, and a sorting mechanism is controlled to perform abnormal sorting according to the test positions of the abnormal chips.

[0006] In a second aspect of the present application, a sorting control device for chip testing is provided, the device comprising: A carrier setting unit, wherein the carrier setting unit sets a carrier for chip testing, and a plurality of test positions are set on the carrier; a chip to be tested placement unit, wherein the chip to be tested placement unit places a plurality of chips to be tested in a plurality of test positions on the carrier, wherein the pins of each chip to be tested include a scan register and a test access port, and the test single-channel scan chains corresponding to each chip to be tested are interconnected; a script reading unit, wherein the script reading unit is connected to a chip testing system and reads test scripts corresponding to the plurality of chips to be tested; a boundary scan test unit, wherein the boundary scan test unit controls a boundary scan tester to perform boundary scan tests on the plurality of chips to be tested according to the test script and outputs chip response data; an abnormality sorting unit, wherein the abnormality sorting unit analyzes the chip response data, identifies abnormal chips and the test positions of the abnormal chips, and controls a sorting mechanism to perform abnormality sorting according to the test positions of the abnormal chips.

[0007] One or more technical solutions provided in this application have at least the following technical effects or advantages: The present application sets a carrier for chip testing, and a plurality of test positions are set on the carrier; a plurality of chips to be tested are placed in the plurality of test positions on the carrier, wherein the pins of each chip to be tested include a scan register and a test access port, and the test single-channel scan chains corresponding to each chip to be tested are interconnected; a chip test system is connected to read the test scripts corresponding to the plurality of chips to be tested; a boundary scan tester is controlled according to the test script to perform boundary scan tests on the plurality of chips to be tested, and chip response data is output; the chip response data is analyzed to identify abnormal chips and the test positions of the abnormal chips, and a sorting mechanism is controlled to perform abnormal sorting according to the test positions of the abnormal chips. The present invention solves the technical problems of slow sorting speed, unreasonable sorting line planning, and insufficient integration of chip testing and sorting control in the prior art, and achieves the technical effects of improving sorting speed, rationally planning sorting lines, and improving the integration of chip testing and sorting control by integrating path planning algorithms, conflict detection algorithms, and real-time optimization technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 A schematic flow chart of a sorting control method for chip testing provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of a sorting control device for chip testing provided in an embodiment of the present application.

[0010] Explanation of the reference numerals: carrier setting unit 11 , chip to be tested placement unit 12 , script reading unit 13 , boundary scan test unit 14 , abnormality sorting unit 15 . DETAILED DESCRIPTION

[0011] The present application provides a sorting control method and device for chip testing, aiming to solve the technical problems in the prior art such as slow sorting speed, unreasonable sorting line planning, and insufficient integration of chip testing and sorting control. By integrating path planning algorithms, conflict detection algorithms and real-time optimization technologies, the present application achieves the technical effects of improving sorting speed, reasonably planning sorting lines, and improving the integration of chip testing and sorting control.

[0012] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0013] It should be noted that any variations of the terms "include" and "have" are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product or server that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or modules that are not explicitly listed or inherent to these processes, methods, products or devices.

[0014] Embodiment 1, as Figure 1 As shown, the present application provides a sorting control method for chip testing, the method comprising: Step S100: Setting a carrier for chip testing, wherein a plurality of test sites are set on the carrier.

[0015] In an embodiment of the present application, during the chip testing process, a carrier for chip testing is first set up. When setting the carrier, the size, shape and pin layout of the chip to be tested are compared with the preset carrier structure, and a carrier that matches the size, shape and pin layout of the chip to be tested is selected as the carrier for chip testing. The carrier is a specially designed physical device for fixing and accommodating multiple chips to be tested. Multiple test positions are set on the carrier, and each test position is a predefined position for placing and fixing the chip to be tested. The test positions include needle beds or slots, which are precisely docked with the pins of the chip to achieve stable transmission of signals.

[0016] Step S200: placing a plurality of chips to be tested in a plurality of test positions on the carrier, wherein the pin of each chip to be tested includes a scan register and a test access port, and the test single-channel scan chains corresponding to each chip to be tested are interconnected.

[0017] In an embodiment of the present application, the placement of the chip to be tested is performed by an automated chip placement system. The automated chip placement system includes a robotic arm and a visual recognition system. The robotic arm picks up a chip to be tested from a chip tray and uses a visual recognition system to locate the pin position of the chip. The robotic arm accurately places the chip in a test position on the carrier, ensuring that the pins of the chip are aligned with the connection points on the test position. These connection points are designed to correspond to the scan registers and test access ports of the chip. The scan register is used to store and transmit test data, and the test access port is a standardized interface for external test equipment to communicate with the chip. After each chip is placed in the test position, other chips to be tested continue to be placed, and the placement process of each chip follows the same steps, i.e., picking up the chip from the tray, accurately positioning it, and placing it in the test position.

[0018] When placing the chip in the test position, the pins of each chip are accurately connected to the connection points on the carrier. These connection points electrically connect the chip to the test system, allowing the test signal to be transmitted to the chip and returned from the chip to the test system. Furthermore, the test single-path scan chains of each chip to be tested are interconnected to form a continuous test chain. A test single-path scan chain refers to a path for transmitting test signals, which starts from the output end of the test system, enters the chip through the input pin of a chip, passes through the scan register, and then comes out of the output pin and is transmitted to the next chip. In this way, the scan chain of each chip is connected to the scan chain of the adjacent chip to form a long test chain.

[0019] Through the above process, multiple chips to be tested are placed in multiple test positions on the carrier, and it is ensured that the pins of each chip, including the scan register and the test access port, are connected to the carrier and are connected to each other to form a test single-channel scan chain.

[0020] Step S300: connecting to a chip testing system and reading test scripts corresponding to the plurality of chips to be tested.

[0021] In an embodiment of the present application, the carrier is first physically connected to the chip test system. The chip test system is a specially designed device for performing complex chip test tasks. It includes multiple interfaces and connection points that match the test bits on the carrier to ensure seamless transmission of signals. Once the physical connection is completed, the chip test system communicates with each chip through a test access port. The test access port is a standardized interface that allows external test equipment to access the test functions inside the chip. Through TAP, the test system sends commands to the chip and receives response signals from the chip. After the communication connection is established, the chip test system begins to read the test scripts stored in the system. The test script is a set of predefined instruction sets that instruct the test system on how to test each chip. These scripts include various test modes, signal transmission paths, expected response data, and error handling mechanisms.

[0022] Step S400: Controlling a boundary scan tester to perform boundary scan tests on the plurality of chips to be tested according to the test script, and outputting chip response data.

[0023] In an embodiment of the present application, first, the chip test system configures the boundary scan tester according to the instructions in the test script, including setting the initial state of the scan register, determining the sequence and frequency of the test signal, and specifying the order of the test steps. These configuration parameters are transmitted to the boundary scan tester through a high-speed serial interface, such as JTAG. After the configuration is completed, the chip test system issues a start instruction, and the boundary scan tester starts to perform the test. The tester sends a test signal to the input pin of each chip through the test access port. These signals are sent according to a predetermined sequence and frequency to ensure that all functions and connections of the chip are covered. After the test signal enters the chip, it is transmitted through the internal scan register. The signal is transmitted along a predetermined path inside the chip, passes through the connection between each functional module and the pin, and finally returns to the boundary scan tester from the output pin. The boundary scan tester transmits the received response signal data back to the chip test system. Through the above process, the chip response data is obtained.

[0024] Step S500: analyzing the chip response data, identifying abnormal chips and test bits of the abnormal chips, and controlling a sorting mechanism to perform abnormal sorting according to the test bits of the abnormal chips.

[0025] In the embodiment of the present application, first, the chip test system uses data analysis software to perform detailed analysis on the chip response data collected from the boundary scan tester, compares the actual response data with the expected response mode, and looks for any abnormalities such as signal loss, delay, or wrong connection. Through this comparative analysis, it is possible to identify which chips exhibit abnormalities during the test and determine the specific test positions where these abnormal chips are located.

[0026] Once the abnormal chip and its test position are identified, the chip test system controls the sorting mechanism to perform abnormal sorting. The sorting mechanism consists of multiple robotic arms equipped with precise moving and grabbing devices. After receiving the sorting instruction, the robotic arm moves to the test position of the identified abnormal chip along a predetermined path, accurately grabs the abnormal chip, and completes the abnormal sorting.

[0027] Furthermore, in the method provided in the embodiment of the application, a single-path scan chain is planned in the carrier, and planning the single-path scan chain includes: Acquire the position information and layout structure information of the multiple test bits; plan a single-channel scan chain according to the layout structure information until the preset scan chain planning indicators are met, and output the single-channel scan chain of the carrier, including the starting point, end point and intermediate nodes of the single-channel scan chain; the boundary scan tester performs boundary scan testing on the multiple chips to be tested through the single-channel scan chain.

[0028] In an embodiment of the present application, the location information and layout structure information of multiple test bits are first obtained through the design document. The test bit is a predefined position on the carrier for fixing and connecting the chip to be tested; the layout structure information includes the arrangement of the test bits on the carrier and the connection relationship between them. Next, the single-channel scan chain is planned according to these location information and layout structure information. The single-channel scan chain is a path for transmitting test signals, which must pass through the test bits of all the chips to be tested on the carrier. The planning process uses a path optimization algorithm, such as the shortest path algorithm or the Dijkstra algorithm in graph theory, to ensure that the length and complexity of the scan chain meet the preset scan chain planning indicators. The preset indicators include the shortest path, the least transit nodes, and the maximum test coverage. In the planning process, the starting point and the end point of the single-channel scan chain are determined using EDA software. The starting point is the first chip position where the test signal enters, and the end point is the last position where the signal leaves after passing through all chips. The intermediate nodes are other test bits passed by the single-channel scan chain, and these nodes are arranged in the best order calculated by the optimization algorithm. Through repeated iterations and optimization, using optimization methods such as Monte Carlo simulation, the path of the single-path scan chain is gradually adjusted until all preset planning indicators are met. Once the planning is completed, the single-path scan chain of the vehicle is output, detailing the starting point, end point, and location and order of all intermediate nodes of the link.

[0029] After the single-channel scan chain planning is completed, the boundary scan tester performs boundary scan tests on multiple chips under test through the planned single-channel scan chain. The boundary scan tester sends a test signal to the starting point of the scan chain through the test access port. The signal passes through each intermediate node in turn and finally reaches the end point. Each node is a test bit, and the signal is processed and transmitted by the scan register inside the chip at these nodes.

[0030] Furthermore, in the method provided in the embodiment of the application, single-path scan chain planning is performed according to the layout structure information, including: Initialize a single-path scan chain and evaluate the initialized single-path scan chain, wherein evaluation indicators include test bit coverage, scan chain length, and scan chain transfer nodes; obtain scan chain planning indicators according to the test bit coverage, the length of the single-path scan chain, and the scan chain transfer nodes; compare the scan chain planning indicators with preset scan chain planning indicators, optimize the initialized single-path scan chain, and output the single-path scan chain of the carrier.

[0031] In an embodiment of the present application, first, a single-path scan chain is initialized using electronic design automation software, and a preliminary scan chain path is generated by reading the position information and layout structure information of the test bits on the carrier. The initial path planning uses a standard path generation algorithm, such as the shortest path algorithm, to ensure that all test bits are included in the link. Next, the initialized single-path scan chain is evaluated, and the evaluation indicators include test bit coverage, scan chain length, and scan chain transfer nodes. The test bit coverage evaluation is completed using a coverage algorithm, which calculates whether the scan chain covers all test bits. The scan chain length is calculated using a geometric distance algorithm to count the total length of all path segments in the link. The number of transfer nodes is counted using a simple counting algorithm to calculate all transfer points passed during signal transmission.

[0032] After the evaluation is completed, the test bit coverage, the length of the single-path scan chain, and the scan chain transfer nodes are used as scan chain planning indicators. The scan chain planning indicators are compared with the preset scan planning indicators. The preset indicators are standard values ​​set according to best practices and specific test requirements, including minimum path length, highest coverage, and minimum transfer nodes. During the comparison process, the actual evaluation results are compared with the preset standards item by item to determine which indicators need to be optimized.

[0033] To optimize the single-path scan chain, advanced optimization algorithms, such as genetic algorithms or Monte Carlo simulations, are used to adjust the link path. The optimization process is repeated, and the link indicators are recalculated and evaluated after each adjustment, gradually approaching the preset standards. In this way, the path length is shortened, the coverage is improved, and the number of transfer nodes is reduced. Finally, after multiple iterations and optimizations, the single-path scan chain of the vehicle is output.

[0034] Furthermore, the method provided in the application embodiment includes: A multi-channel scan chain is also planned in the carrier, wherein the multi-channel scan chain corresponds to the multiple test bits; and independent boundary scan tests are performed on the multiple chips to be tested according to the multi-channel scan chain.

[0035] In the embodiment of the present application, the multi-channel scan chain is first planned using electronic design automation software, and the preliminary multi-channel scan chain layout is generated by reading the position information and layout structure information of all test bits on the carrier. Each scan chain corresponds to a group of test bits, ensuring that all chips under test can receive independent boundary scan tests through these links.

[0036] After planning is completed, each scan chain starts from a starting point, passes through a series of intermediate nodes, and finally reaches the end point. The design of the multi-channel scan chain enables each link to work independently without interfering with each other. According to the planned multi-channel scan chain, multiple chips to be tested are subjected to independent boundary scan tests. During the test, the signal transmission and data acquisition of each scan chain are carried out independently. The tester records the response data of each chip and transmits the data back to the chip test system. Through the planning and use of multi-channel scan chains, the impact of single point failures is reduced. If a scan chain fails, other links can still continue to work, ensuring the reliability and stability of the overall test process.

[0037] Furthermore, the method provided in the application embodiment includes: The chip testing system also includes a mode switching control module; wherein the mode switching control module is provided with a chip response health sample; the mode switching control module identifies abnormalities in the chip response data according to the chip response health sample, and if the chip response data is abnormal, activates a mode switching instruction, wherein the chip response data is acquired through a mode test of a single-channel scan chain; according to the mode switching instruction, the mode of the single-channel scan chain is switched to the mode of a multi-channel scan chain, a plurality of chip response data are acquired, and abnormal chips are identified according to the plurality of chip response data.

[0038] In an embodiment of the present application, in addition to the conventional test module, a mode switching control module is also included in the chip test system. The design purpose of this module is to enhance the flexibility of the test system and its ability to cope with abnormal situations. The mode switching control module is provided with a chip response health sample for comparing and identifying abnormal situations that may occur during the chip test process. The chip response health sample refers to predetermined response data representing the normal working state of the chip.

[0039] When identifying anomalies in chip response data based on chip response healthy samples, a statistical anomaly detection algorithm is used to calculate the difference between the chip response data and the healthy samples. For example, the Z-score is used to calculate the Z score of each test point to measure its degree of deviation from the mean of the healthy sample. Based on the calculated difference index, it is determined whether the chip response data is abnormal. Specifically, a threshold is first set by a technical expert. For example, if the absolute value of the Z-score exceeds 3, the calculated difference index is compared with the threshold. If the difference index exceeds the threshold, the chip response data is considered abnormal.

[0040] When an abnormal situation is detected, the mode switching control module sends a mode switching instruction through the system bus. After receiving the instruction, the chip test system starts the multi-channel scan chain mode, and the boundary scan tester uses multiple independent scan chains to perform parallel testing on the chip under test. The test system collects the response data of each chip through each independent scan chain, and the test data is transmitted to the test system through the parallel interface.

[0041] After the parallel test is completed, the response data from different scan chains are integrated together for comprehensive evaluation using data fusion technology. First, data fusion technology, such as Kalman filtering or Bayesian reasoning, is used to integrate the response data of multiple scan chains to form a comprehensive data set. Then, statistical analysis tools are used to evaluate the comprehensive data set to determine the specific location and cause of the abnormality. Specifically, based on the chip response healthy samples, a statistical model under normal working conditions is constructed, including calculating the mean and standard deviation. Then, the Z-score is used to calculate the difference between each test point in the comprehensive data set and the healthy sample. The calculated difference index is compared with the preset threshold to determine which test points are abnormal. Through this process, the identification of abnormal chips is completed, the abnormal chips and qualified chips are identified, and the test bits of each chip are recorded.

[0042] Furthermore, in the method provided in the embodiment of the application, the abnormality sorting is performed according to the test bit control sorting mechanism of the abnormal chip, including: The sorting mechanism includes a first sorting arm and a second sorting arm; the first sorting arm performs abnormal sorting according to the test position of the abnormal chip and places it in an unqualified container, and the second sorting arm sorts the remaining test chips into a qualified container.

[0043] In an embodiment of the present application, the sorting mechanism includes a first sorting arm and a second sorting arm, the first sorting arm is responsible for sorting abnormal chips, and the second sorting arm is responsible for sorting qualified chips.

[0044] The first sorting arm moves to the test position where the abnormal chip is located through a pre-planned path. The robotic arm uses a vacuum suction cup or a mechanical clamp to grab the abnormal chip from the test position. Then the first sorting arm moves the grabbed abnormal chip to the unqualified container and places it in the designated position.

[0045] The second sorting arm also moves along the pre-planned path to the test position where the qualified chip is located, and the robotic arm also uses a vacuum suction cup or mechanical clamp to grab the qualified chip from the test position. Then the second sorting arm moves the grabbed qualified chip to the qualified container and places it in the specified position.

[0046] Furthermore, in the method provided in the embodiment of the application, the abnormality sorting is performed according to the test bit control sorting mechanism of the abnormal chip, including: Plan the sorting route of the first sorting arm; plan the sorting route of the second sorting arm; predict the conflict between the sorting route of the first sorting arm and the sorting route of the second sorting arm, and obtain the conflict index; optimize the sorting route of the first sorting arm and the sorting route of the second sorting arm according to the conflict index, and output the optimized sorting route of the first sorting arm and the optimized sorting route of the second sorting arm.

[0047] In the embodiment of the present application, for the first sorting arm, by reading the information of the chip test bit and combining the current position of the sorting arm, the A* algorithm is used to plan the optimal path and determine the sorting line of the first sorting arm. Similarly, the same path planning algorithm is used for the second sorting arm, by reading the test bit information of the qualified chip and combining the current position of the sorting arm, the optimal path is planned and the sorting line of the second sorting arm is determined.

[0048] After planning the initial sorting route, conflicts are predicted between the sorting route of the first sorting arm and the sorting route of the second sorting arm. A conflict detection algorithm, such as the RRT algorithm, is used to predict conflicts. By simulating the motion trajectories of the two robotic arms, the RRT algorithm identifies the location and time where conflicts may occur and generates conflict indicators.

[0049] Once the conflict index is obtained, the sorting routes of the first sorting arm and the second sorting arm are optimized respectively according to the conflict index. Specifically, the priority scheduling algorithm is first used to rearrange the task order of the robot arm. The priority scheduling algorithm assigns priorities and arranges the execution order of tasks according to the importance and urgency of each robot arm's task. By adjusting the movement order, the robot arms are prevented from occupying the same space in the same time period. In this application, the priority of the first sorting arm is greater than that of the second sorting arm. If adjusting the movement order cannot completely avoid the conflict, the path optimization algorithm is used to recalculate the path of the robot arm. Based on the adjustment of the path and the movement order, the speed planning algorithm is used to optimize the movement speed of the robot arm. The gradient descent method iteratively optimizes the speed curve so that the robot arms are staggered in time to avoid conflicts.

[0050] Through the above process, the optimization of the sorting circuit of the first sorting arm and the sorting circuit of the second sorting arm is completed, and the optimized sorting circuit of the first sorting arm and the optimized sorting circuit of the second sorting arm are output.

[0051] In the embodiments of the present application, in summary, the embodiments of the present application have at least the following technical effects: The present application sets a carrier for chip testing, and a plurality of test positions are set on the carrier; a plurality of chips to be tested are placed in the plurality of test positions on the carrier, wherein the pins of each chip to be tested include a scan register and a test access port, and the test single-channel scan chains corresponding to each chip to be tested are interconnected; a chip test system is connected to read the test scripts corresponding to the plurality of chips to be tested; a boundary scan tester is controlled according to the test script to perform boundary scan tests on the plurality of chips to be tested, and chip response data is output; the chip response data is analyzed to identify abnormal chips and the test positions of the abnormal chips, and a sorting mechanism is controlled to perform abnormal sorting according to the test positions of the abnormal chips. The present invention solves the technical problems of slow sorting speed, unreasonable sorting line planning, and insufficient integration of chip testing and sorting control in the prior art, and achieves the technical effects of improving sorting speed, rationally planning sorting lines, and improving the integration of chip testing and sorting control by integrating path planning algorithms, conflict detection algorithms, and real-time optimization technologies.

[0052] Embodiment 2, based on the same inventive concept as the sorting control method for chip testing in the above embodiment, Figure 2 As shown, the present application provides a sorting control device for chip testing, and the device and method embodiments in the present application are based on the same inventive concept. The device includes: A carrier setting unit 11, wherein the carrier setting unit 11 sets a carrier for chip testing, and a plurality of test positions are set on the carrier; a chip to be tested placement unit 12, wherein the chip to be tested placement unit 12 places a plurality of chips to be tested in a plurality of test positions on the carrier, wherein the pins of each chip to be tested include a scan register and a test access port, and the test single-channel scan chains corresponding to each chip to be tested are interconnected; a script reading unit 13, wherein the script reading unit 13 is connected to a chip testing system and reads the test scripts corresponding to the plurality of chips to be tested; a boundary scan test unit 14, wherein the boundary scan test unit 14 controls a boundary scan tester to perform boundary scan tests on the plurality of chips to be tested according to the test script and outputs chip response data; an abnormal sorting unit 15, wherein the abnormal sorting unit 15 analyzes the chip response data, identifies abnormal chips and the test positions of the abnormal chips, and controls a sorting mechanism to perform abnormal sorting according to the test positions of the abnormal chips.

[0053] Furthermore, the device is also used to achieve the following functions: Acquire the position information and layout structure information of the multiple test bits; plan a single-channel scan chain according to the layout structure information until the preset scan chain planning indicators are met, and output the single-channel scan chain of the carrier, including the starting point, end point and intermediate nodes of the single-channel scan chain; the boundary scan tester performs boundary scan testing on the multiple chips to be tested through the single-channel scan chain.

[0054] Furthermore, the device is also used to achieve the following functions: Initialize a single-path scan chain and evaluate the initialized single-path scan chain, wherein evaluation indicators include test bit coverage, scan chain length, and scan chain transfer nodes; obtain scan chain planning indicators according to the test bit coverage, the length of the single-path scan chain, and the scan chain transfer nodes; compare the scan chain planning indicators with preset scan chain planning indicators, optimize the initialized single-path scan chain, and output the single-path scan chain of the carrier.

[0055] Furthermore, the device is also used to achieve the following functions: A multi-channel scan chain is also planned in the carrier, wherein the multi-channel scan chain corresponds to the multiple test bits; and independent boundary scan tests are performed on the multiple chips to be tested according to the multi-channel scan chain.

[0056] Furthermore, the device is also used to achieve the following functions: The chip testing system also includes a mode switching control module; wherein the mode switching control module is provided with a chip response health sample; the mode switching control module identifies abnormalities in the chip response data according to the chip response health sample, and if the chip response data is abnormal, activates a mode switching instruction, wherein the chip response data is acquired through a mode test of a single-channel scan chain; according to the mode switching instruction, the mode of the single-channel scan chain is switched to the mode of a multi-channel scan chain, a plurality of chip response data are acquired, and abnormal chips are identified according to the plurality of chip response data.

[0057] Furthermore, the device is also used to achieve the following functions: The sorting mechanism includes a first sorting arm and a second sorting arm; the first sorting arm performs abnormal sorting according to the test position of the abnormal chip and places it in an unqualified container, and the second sorting arm sorts the remaining test chips into a qualified container.

[0058] Furthermore, the device is also used to achieve the following functions: Plan the sorting route of the first sorting arm; plan the sorting route of the second sorting arm; predict the conflict between the sorting route of the first sorting arm and the sorting route of the second sorting arm, and obtain the conflict index; optimize the sorting route of the first sorting arm and the sorting route of the second sorting arm according to the conflict index, and output the optimized sorting route of the first sorting arm and the optimized sorting route of the second sorting arm.

[0059] It should be noted that the above-mentioned sequence of the embodiments of the present application is only for description and does not represent the advantages and disadvantages of the embodiments. And the above-mentioned specific embodiments of this specification are described. The processes depicted in the accompanying drawings do not necessarily require the specific order and continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0060] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

[0061] This specification and drawings are merely exemplary illustrations of the present application and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, a person skilled in the art may make various modifications and variations to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present application and its equivalents, the present application intends to include these modifications and variations.

Claims

1. A sorting control method for chip testing, characterized in that: The method comprises: A carrier for chip testing is provided, wherein a plurality of test positions are provided on the carrier; Placing a plurality of chips to be tested in a plurality of test positions on the carrier, wherein the pins of each chip to be tested include a scan register and a test access port, and the test single-channel scan chains corresponding to each chip to be tested are connected to each other; Connecting to a chip testing system to read test scripts corresponding to the plurality of chips to be tested; Controlling the boundary scan tester to perform boundary scan tests on the plurality of chips to be tested according to the test script, and outputting chip response data; The chip response data is analyzed to identify abnormal chips and test bits of the abnormal chips, and a sorting mechanism is controlled to perform abnormal sorting according to the test bits of the abnormal chips.

2. The sorting control method for chip testing according to claim 1, characterized in that: A single-channel scanning chain is planned in the carrier, and planning the single-channel scanning chain includes: Acquire location information and layout structure information of the plurality of test bits; Perform single-channel scan chain planning according to the layout structure information until the preset scan chain planning index is met, and output the single-channel scan chain of the carrier, including the single-channel scan chain starting point, end point and intermediate node; The boundary scan tester performs boundary scan testing on the multiple chips to be tested through the single-path scan chain.

3. The method according to claim 2, characterized in that The single-path scan chain planning is performed according to the layout structure information, and the method includes: Initializing a single-path scan chain, and evaluating the initialized single-path scan chain, wherein the evaluation indicators include test bit coverage, scan chain length, and scan chain transfer nodes; Obtaining a scan chain planning indicator according to the test bit coverage, the length of the single-path scan chain, and the scan chain transfer node; The scan chain planning index is compared with a preset scan chain planning index, the initialized single-channel scan chain is optimized, and the single-channel scan chain of the carrier is output.

4. The method according to claim 2, characterized in that The carrier is also planned to have multiple scan chains, wherein the multiple scan chains correspond to the multiple test bits; Independent boundary scan tests are performed on the multiple chips to be tested according to the multi-path scan chain.

5. The method according to claim 4, characterized in that The chip testing system also includes a mode switching control module; Wherein, the mode switching control module is provided with a chip response health sample; The mode switching control module identifies abnormalities in the chip response data according to the chip response healthy sample, and activates a mode switching instruction if the chip response data is abnormal, wherein the chip response data is obtained through a mode test of a single-channel scan chain; The mode of the single-channel scan chain is switched to the mode of the multi-channel scan chain according to the mode switching instruction, a plurality of chip response data are acquired, and an abnormal chip is identified according to the plurality of chip response data.

6. The method according to claim 1, characterized in that According to the test bit of the abnormal chip, the control sorting mechanism performs abnormal sorting, and the method include: Wherein, the sorting mechanism comprises a first sorting arm and a second sorting arm; The first sorting arm sorts the abnormal chips according to the test positions of the abnormal chips and places them in unqualified containers, and the second sorting arm sorts the remaining test chips into qualified containers.

7. The method according to claim 6, characterized in that The method further comprises: controlling the sorting mechanism to perform abnormal sorting according to the test bit of the abnormal chip; Planning a sorting route of the first sorting arm; Planning a sorting route of the second sorting arm; Predicting conflicts between the sorting lines of the first sorting arm and the sorting lines of the second sorting arm to obtain conflict indicators; The sorting lines of the first sorting arm and the sorting lines of the second sorting arm are optimized respectively according to the conflict index, and the optimized sorting lines of the first sorting arm and the optimized sorting lines of the second sorting arm are output.

8. A sorting control device for chip testing, characterized in that: The device comprises: A carrier setting unit, wherein the carrier setting unit sets a carrier for chip testing, and a plurality of test positions are set on the carrier; A chip-to-be-tested placement unit, which places a plurality of chips-to-be-tested in a plurality of test positions on the carrier, wherein the pins of each chip-to-be-tested include a scan register and a test access port, and the test single-channel scan chains corresponding to each chip-to-be-tested are connected to each other; A script reading unit, the script reading unit is connected to the chip testing system and reads the test scripts corresponding to the plurality of chips to be tested; A boundary scan test unit, wherein the boundary scan test unit controls a boundary scan tester to perform boundary scan tests on the plurality of chips to be tested according to the test script, and outputs chip response data; An abnormality sorting unit analyzes the chip response data, identifies abnormal chips and test bits of the abnormal chips, and controls a sorting mechanism to perform abnormality sorting according to the test bits of the abnormal chips.

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