Chip internal logic analyzer and analysis method

Abstract

The invention belongs to the field of testing and analysis of chip systems, and particularly relates to a chip internal logic analyzer and an analysis method.The chip internal logic analyzer comprises a register module and a trigger sampling module, the register module is connected with the trigger sampling module, an OBS pin is arranged on the logic analyzer, and the logic analyzer is mounted under an on-chip system; the register module is used for receiving a control signal of the system on chip to generate a corresponding register signal and transmitting the register signal to the trigger sampling module; the OBS pin is used for transmitting an internal signal in the system on chip to the trigger sampling module; the trigger sampling module is used for receiving the register signal and the internal signal and generating a trigger signal according to the register signal, and the trigger sampling module samples the internal signal through the trigger signal to obtain a sampling result and writes the sampling result back to the system on chip.

Description

Technical Field

[0001] The present invention belongs to the field of chip system testing and analysis, and more specifically, relates to a chip internal logic analyzer and an analysis method. Background Art

[0002] System on Chip (SoC) is a complex circuit system composed of multiple IP (Intellectual Property) cores, usually including processors, analog IP cores, digital IP cores, storage media or interfaces, interconnection IP and interfaces, peripheral protocol interfaces, etc., with extremely high complexity and debugging difficulty. Among them, IP cores are reusable hardware or software components that have specific functions or characteristics and can be integrated into SoC to achieve specific application requirements. IP cores can include processor cores, storage controllers, peripheral interfaces, communication interfaces, etc.

[0003] In order to facilitate the return test of SoC chips, some debugging mechanisms are generally built into the chip. The commonly used debugging methods for SoC in the industry include reserving debugging registers to observe internal status signals; reserving on-board signal (OBS) pins to lead the internal signals of the chip to general-purpose input / output (GPIO) and then observe them through a logic analyzer.

[0004] Existing debugging methods can help testers locate problems to a great extent during the wafer return test. The method of reserving debug registers can observe a large number of internal chip signals with low resource consumption. Reserving OBS pins can observe internal signals for a long time and accurately see the value of each cycle of the internal signal, which is very helpful for debugging.

[0005] However, the above methods still have great limitations during use. Although the method of reserving debug registers takes up less resources and can observe a large number of signals, it is impossible to observe the value of each cycle continuously and without interruption. Although the method of reserving OBS pins can see the value of each cycle of the signal, it is limited by the GPIO rate, the required signal frequency is low, and the number of GPIOs is limited, so it is impossible to observe a large amount of data. Therefore, there is a need for a debugging method in the existing SoC debugging method that can continuously and without intervals observe a large number of internal signals. Summary of the invention

[0006] The technical problem to be solved by the present invention is: how to achieve continuous and uninterrupted observation of the Cycle value of each signal while observing a large number of signals.

[0007] The present invention achieves the above object through the following technical solutions:

[0008] In a first aspect, a chip internal logic analyzer is provided, comprising: a register module and a trigger sampling module, wherein the register module is connected to the trigger sampling module, an OBS pin is provided on the logic analyzer, and the logic analyzer is mounted under a system on chip;

[0009] The register module is used to receive the control signal of the system on chip to generate a corresponding register signal, and transmit the register signal to the trigger sampling module;

[0010] The OBS pin is used to transmit the internal signal of the system on chip to the trigger sampling module;

[0011] The trigger sampling module is used to receive the register signal and the internal signal, and generate a trigger signal according to the register signal. The trigger sampling module samples the internal signal through the trigger signal to obtain a sampling result, and writes the sampling result back to the on-chip system.

[0012] Preferably, the system on chip includes a control unit and an AHB (Advanced High-performance Bus) bus unit, and the control unit is connected to the AHB bus unit;

[0013] The control unit is used to control the operation of the entire system on chip and send the control signal through the AHB bus unit;

[0014] The interrupt pin of the control unit is connected to the interrupt pin of the logic analyzer, and is used to receive and execute the interrupt signal of the logic analyzer.

[0015] Preferably, the system on chip further includes an APB (Advanced Peripheral Bus) bridge unit, the logic analyzer further includes an APB interface, the APB bridge unit includes an input interface and an output interface, and the APB interface includes an input end and an output end;

[0016] The input interface of the APB bridge unit is connected to the AHB bus unit, and the output interface of the APB bridge unit is connected to the input end of the APB interface;

[0017] The output end of the APB interface is connected to the register module;

[0018] The APB bridge unit is used to send the control signal from the AHB bus unit to the logic analyzer.

[0019] Preferably, the AHB bus unit is used to convert the control signal of the system on chip into a protocol specification signal of the AHB bus unit;

[0020] The protocol specification signal of the AHB bus unit is converted into a format recognizable by the register module through the APB bridge unit and the APB interface, so as to ensure normal communication between the register module and the system on chip.

[0021] Preferably, the trigger sampling module includes a trigger generation module, a sampling module and a FIFO module, the register module is connected to the trigger generation module, the sampling module and the FIFO module respectively, the trigger generation module is connected to the sampling module, and the sampling module is connected to the FIFO module;

[0022] The register module is used to receive the control signal of the system on chip to generate a corresponding register signal, and transmit the register signal to the trigger generation module, the sampling module and the first-in-first-out queue (First-In-First-Out, abbreviated as FIFO) module respectively;

[0023] Wherein, the register signal includes: a configuration signal, a sampling signal and a write-back signal;

[0024] The trigger generation module is used to configure the corresponding trigger condition according to the configuration signal, and when the trigger condition is met, the trigger generation module generates a trigger signal;

[0025] The sampling module is used to sample the internal signal according to the trigger signal to obtain the sampling result, and write the sampling result back to the memory in real time according to the sampling signal;

[0026] The FIFO module is used for processing the sampling result in the sampling module to obtain a FIFO signal, and writing the FIFO signal back to the DDR of the system on chip according to the write-back signal.

[0027] Preferably, the trigger sampling module further includes a data channel module, and the data channel module is connected to the sampling module;

[0028] The data channel module is used to receive the internal signal of the system on chip through the OBS pin and transmit the internal signal to the sampling module.

[0029] In a second aspect, an analysis method is provided, comprising:

[0030] The register module receives the control signal of the system on chip to generate a corresponding register signal, and transmits the register signal to the trigger sampling module;

[0031] The OBS pin transmits the internal signal of the system on chip to the trigger sampling module;

[0032] The trigger sampling module receives the register signal and the internal signal, and generates a trigger signal according to the register signal. The trigger sampling module samples the internal signal through the trigger signal to obtain a sampling result, and writes the sampling result back to the on-chip system.

[0033] Preferably, the register module receives the control signal of the system on chip to generate a corresponding register signal, and transmits the register signal to the trigger sampling module, including:

[0034] The trigger sampling module includes a trigger generation module, a sampling module and a FIFO module, the register module is connected to the trigger generation module, the sampling module and the FIFO module respectively, the trigger generation module is connected to the sampling module, and the sampling module is connected to the FIFO module;

[0035] The register module receives the control signal of the system on chip to generate a corresponding register signal, and transmits the register signal to the trigger generation module, the sampling module and the FIFO module respectively.

[0036] Preferably, the OBS pin transmits the internal signal in the system on chip to the trigger sampling module, including:

[0037] The trigger sampling module also includes a data channel module, and the data channel module is connected to the sampling module;

[0038] The data channel module receives an internal signal in the system on chip through the OBS pin, and transmits the internal signal to the sampling module.

[0039] Preferably, the trigger sampling module receives the register signal and the internal signal, and generates a trigger signal according to the register signal, the trigger sampling module samples the internal signal through the trigger signal to obtain a sampling result, and writes the sampling result back to the on-chip system, including:

[0040] The register signals include: configuration signals, sampling signals and write-back signals;

[0041] The trigger generation module configures a corresponding trigger condition according to the configuration signal, and when the trigger condition is met, the trigger generation module generates a trigger signal;

[0042] The sampling module samples the internal signal according to the trigger signal to obtain the sampling result, and writes the sampling result back to the memory in real time according to the sampling signal;

[0043] The FIFO module processes the sampling result in the sampling module to obtain a FIFO signal, and writes the FIFO signal back to the DDR of the system on chip according to the write-back signal.

[0044] The beneficial effects of the present invention are:

[0045] The present invention sets an OBS pin on a logic analyzer and sets a register module inside the logic analyzer; transmits an internal signal in a system on chip to the logic analyzer through the OBS pin, and then observes the internal signal through the logic analyzer, so that the cycle value of each internal signal can be observed through the logic analyzer; the logic analyzer is controlled by the register module, the register module can store the cycle values ​​of multiple internal signals, and the cycle values ​​of these internal signals can be obtained or modified through a read or write operation, so that the debugging efficiency can be improved, resource consumption can be reduced, and a large number of internal signals can be observed. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. The drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific implementation methods, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:

[0047] Figure 1 It is a schematic diagram of the structure of a chip internal logic analyzer provided by an embodiment of the present invention;

[0048] Figure 2 It is a schematic diagram of the structure of a system on chip of an internal logic analyzer of a chip provided by an embodiment of the present invention;

[0049] Figure 3 is a more specific structural schematic diagram of an internal chip logic analyzer provided by an embodiment of the present invention;

[0050] Figure 4 It is a structural schematic diagram of a trigger sampling module of a chip internal logic analyzer provided by an embodiment of the present invention;

[0051] Figure 5 It is a schematic diagram of the pin structure of a chip internal logic analyzer provided by an embodiment of the present invention;

[0052] Figure 6 It is a schematic diagram of a flow chart of an analysis method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0054] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0055] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0056] In order to solve the problem of how to continuously and uninterruptedly observe the Cycle value of each signal while observing a large number of signals, in an embodiment of the present invention, Figure 1 As shown, a chip internal logic analyzer is provided, including: a register module and a trigger sampling module, the register module is connected to the trigger sampling module, an OBS pin is provided on the logic analyzer, and the logic analyzer is mounted under the system on chip; the register module is used to receive the control signal of the system on chip to generate a corresponding register signal, and transmit the register signal to the trigger sampling module; the OBS pin is used to transmit the internal signal in the system on chip to the trigger sampling module; the trigger sampling module is used to receive the register signal and the internal signal, and generate a trigger signal according to the register signal, the trigger sampling module samples the internal signal through the trigger signal to obtain a sampling result, and writes the sampling result back to the system on chip.

[0057] The register module receives the control signal of the system on chip and generates corresponding register signals according to the control signal. The control signal of the system on chip may be an instruction for setting trigger conditions, sampling rate, sampling depth or other related parameters. The register module parses these instructions and generates corresponding register signals according to the content and format of the instructions; the generated register signals may include register addresses, write enable signals, data signals, etc., which will be transmitted to the trigger sampling module to configure the working mode and parameters of the logic analyzer; the trigger sampling module performs corresponding operations according to these register signals, such as setting trigger conditions, configuring sampling rate or sampling depth, etc. The specific signals included in the register signals will be described below.

[0058] The OBS pin is used to transmit internal signals of the system on chip to the trigger sampling module. These internal signals may be signals that need to be logically analyzed, such as clock signals, data signals, and other signals.

[0059] In the process of designing and debugging the system on chip, the logical analysis of the internal signals of the system on chip is very important for discovering problems, verifying design and debugging errors. By transmitting these internal signals to the trigger sampling module, continuous sampling and analysis of these internal signals can be achieved; for example, the clock signal is usually an important signal in the system on chip, which is critical for determining timing problems and verifying the correctness of the clock domain; the data signal includes the data transmission and processing process inside the system on chip. By performing logical analysis on the data signal, it can help detect data transmission errors and logic problems.

[0060] In some implementations, the system on chip is specifically a SoC chip. The design scheme for the OBS pin is as follows:

[0061] In the design of the SoC chip, a GPIO pin is reserved as the OBS pin on the SoC chip to ensure that the OBS pin can be accessed externally and can receive corresponding internal signals; the internal signal of the SoC chip is led out to the OBS pin on the SoC chip by making a wire connection in the SoC chip layout or by other appropriate methods, which are not specifically limited here. The OBS pin on the SoC chip is connected to the OBS pin on the logic analyzer, and then the sampling rate and trigger conditions of the logic analyzer are ensured to be set correctly; the logic analyzer is configured to capture and analyze the internal signal received through the OBS pin on the logic analyzer.

[0062] Through the above solution, the internal signals of the SoC chip can be brought out to the GPIO pins and observed through a logic analyzer. This makes it easy to analyze, debug and verify the internal signals of the SoC chip, helping to solve problems and optimize chip design.

[0063] The trigger sampling module receives the register signal transmitted by the register module and the internal signal of the on-chip system. The trigger sampling module generates a trigger signal according to the register signal. The trigger signal is used to control the sampling of the internal signal to obtain a sampling result. The sampling result is written back to the on-chip system for further analysis and debugging. The specific structure of the trigger sampling module will be described below.

[0064] In order to facilitate the operation of the logic analyzer, the system on chip will be introduced below. Figure 2 As shown, the system on chip includes a control unit and an AHB bus unit, and the control unit is connected to the AHB bus unit; the control unit is used to control the operation of the entire system on chip and send the control signal through the AHB bus unit; the interrupt pin of the control unit is connected to the interrupt pin of the logic analyzer, and is used to receive and execute the interrupt signal of the logic analyzer.

[0065] The system on chip also includes an APB bridge unit, and the logic analyzer also includes an APB interface. The APB bridge unit includes an input interface and an output interface, and the APB interface includes an input end and an output end; the input interface of the APB bridge unit is connected to the AHB bus unit, and the output interface of the APB bridge unit is connected to the input end of the APB interface; the output end of the APB interface is connected to the register module; the APB bridge unit is used to send a control signal from the AHB bus unit to the logic analyzer.

[0066] The control unit is specifically a central processing unit (CPU), which is responsible for the operation control of the entire system on chip. It is directly connected to the AHB bus unit and obtains and sends the control signal through the AHB bus unit. In addition, the interrupt pin in the control unit is also directly connected to the interrupt pin on the logic analyzer to receive and execute the interrupt signal of the logic analyzer. When it is necessary to stop or pause execution in the system on chip, the logic analyzer sends the corresponding debugging instruction to the system on chip to implement the interrupt operation. The system on chip will perform corresponding operations according to the requirements of the instructions, such as entering the debugging mode, pausing execution, reading register values, etc.

[0067] The control unit is the core part of the entire system on chip, and usually includes components such as an instruction decoding unit, an execution unit and a status register. The instruction decoding unit parses instructions, the execution unit performs the operation of instructions, and the status register is used to store and manage the operating status of the processor; the control unit is connected to the AHB bus unit, and obtains and sends control signals through the AHB bus unit to control the data transmission and operation between the system on chip and each IP.

[0068] The AHB bus unit is a bus unit used to connect various modules inside the system on chip. It is connected to the control unit and the APB bridge unit. The AHB bus unit is responsible for transmitting data and control signals inside the system on chip, providing high-performance and high-bandwidth data transmission capabilities; the AHB bus unit provides high-bandwidth and low-latency data transmission capabilities, and realizes efficient data exchange inside the system on chip; the AHB bus is usually divided into a master bus and a slave bus. The master bus is used to connect the core modules of the system on chip, and the slave bus is used to connect the peripheral modules. The AHB bus unit is responsible for processing data transmission, address mapping, priority control and other functions to realize communication between the internal modules of the system on chip.

[0069] The APB bridge unit is used to connect the AHB bus unit and the logic analyzer. Its main function is to convert and transmit data and signals between the AHB bus unit and the logic analyzer to realize communication and control between the system on chip and the logic analyzer. APB is a low-power, low-speed peripheral bus, which is often used to connect slower peripheral modules. It can provide relevant data and signals to the logic analyzer according to the needs of the logic analyzer for debugging, verification and subsequent analysis.

[0070] In some embodiments, continue to refer to Figure 2 The AHB bus unit is used to convert the control signal of the system on chip into the protocol specification signal of the AHB bus unit; through the APB bridge unit and the APB interface, the protocol specification signal of the AHB bus unit is converted into a format recognizable by the register module to ensure normal communication between the register module and the system on chip.

[0071] Among them, the APB interface specifically uses an asynchronous peripheral bus protocol (APB Async), which is mainly used for low-power, low-speed peripheral modules. Unlike the traditional APB bus, APB Async uses an asynchronous method for data transmission and does not rely on a clock signal. This means that in APB Async, no clock signal is required to drive the initiation and reception of data transmission. On the contrary, APB Async uses a handshake protocol to coordinate the sending and receiving of data; in APB Async, data transmission is based on a request-response method. When the logic analyzer needs to send a data request to the on-chip system, it will send a request signal to the on-chip system. After receiving the request signal, the on-chip system will send a response signal to confirm the reception request and perform signal transmission. After the signal transmission is completed, the on-chip system will send a completion signal to the peripheral, indicating that the data has been successfully transmitted.

[0072] APB Async has the following advantages over the traditional APB bus: Asynchronous transmission: It does not rely on clock signals, which can reduce power consumption and transmission delay; Flexibility: It can adapt to the operating frequency and transmission rate of different peripherals; Simplified design: Since no clock signal is required, it can reduce design complexity and clock management overhead.

[0073] After introducing the structure of the system on chip, the trigger sampling module will be described in detail. In some implementations, Figure 3 and Figure 4 As shown, the trigger sampling module includes a trigger generation module, a sampling module and a FIFO module, the register module is connected to the trigger generation module, the sampling module and the FIFO module respectively, the trigger generation module is connected to the sampling module, and the sampling module is connected to the FIFO module; the register module is used to receive the control signal of the system on chip to generate a corresponding register signal, and transmit the register signal to the trigger generation module, the sampling module and the FIFO module respectively; wherein the register signal includes: a configuration signal, a sampling signal and a write-back signal; the trigger generation module is used to configure the corresponding trigger condition according to the configuration signal, and when the trigger condition is met, the trigger generation module generates a trigger signal; the sampling module is used to sample the internal signal according to the trigger signal to obtain the sampling result, and write the sampling result back to the memory in real time according to the sampling signal; the FIFO module is used to process the sampling result in the sampling module to obtain a FIFO signal, and write the FIFO signal back to the DDR of the system on chip according to the write-back signal.

[0074] Among them, when the on-chip system needs to perform a trigger sampling operation, the corresponding control signal is sent by controlling the register module. After receiving the control signal, the register module generates a corresponding register signal according to the control signal, and transmits the register signal to the trigger generation module, the sampling module and the FIFO module respectively. The register signal includes a configuration signal, a sampling signal and a write-back signal; the configuration signal is a signal used by the register module to configure the trigger generation module, which is used to trigger data acquisition or other specific events; the sampling signal is a signal used by the register module to control the sampling module to work normally; the write-back signal is a signal used by the register module to control the FIFO module to write data from the FIFO buffer back to the main memory or other target locations.

[0075] In the register module, the trigger conditions of the trigger generation module can also be configured. These conditions include specific signal states, signal edges, timing relationships, etc. When the trigger generation module detects that the trigger conditions are met, it generates a trigger signal and sends it to the sampling module.

[0076] The sampling module samples the internal signal according to the trigger signal. It can sample the internal signal or the signal generated by other modules. The sampling module will write the sampling result back to its own memory in real time to ensure the timeliness and accuracy of the data.

[0077] In order to facilitate data transmission and storage, a FIFO module is introduced into the logic analyzer. The sampling module passes the sampling result to the FIFO module, and then the FIFO module writes the sampling result back to the DDR of the on-chip system. DDR is a high-speed memory that can provide larger storage capacity and faster data reading and writing speed to meet the needs of high-speed data transmission.

[0078] Next, the transmission process of the internal signal will be described. In a preferred embodiment, continue to refer to Figure 4 The trigger sampling module also includes a data channel module, which is connected to the sampling module; the data channel module is used to receive the internal signal in the on-chip system through the OBS pin and transmit the internal signal to the sampling module.

[0079] The data channel module is an important component of the logic analyzer. It is responsible for transmitting the internal signals of the system on chip to the sampling module. It receives the internal signals of the system on chip through the OBS pin on the logic analyzer and transmits these internal signals to the sampling module. It is worth noting that the data channel module can be designed according to system requirements to meet different data transmission requirements. It may include functions such as data caching, data forwarding and data scheduling to ensure stable transmission and effective sampling of the internal signals.

[0080] So far, the specific structure of the logic analyzer has been described. Since there are many different types of signals received and output on the logic analyzer, a plurality of ports are provided on the logic analyzer to receive or output these signals. The port list of the logic analyzer is as follows: Figure 5 As shown, the directions of the arrows represent the transmission directions of different types of signals, and the function of each port and its specific connection method are not described in detail in this embodiment.

[0081] The present invention sets an OBS pin on a logic analyzer and sets a register module inside the logic analyzer; transmits an internal signal in a system on chip to the logic analyzer through the OBS pin, and then observes the internal signal through the logic analyzer, so that the cycle value of each internal signal can be observed through the logic analyzer; the logic analyzer is controlled by the register module, the register module can store the cycle values ​​of multiple internal signals, and the cycle values ​​of these internal signals can be obtained or modified through a read or write operation, so that the debugging efficiency can be improved, resource consumption can be reduced, and a large number of internal signals can be observed.

[0082] In the embodiment of the present invention, a chip internal logic analyzer is proposed. In order to further illustrate the logic analyzer, an analysis method will be proposed in this embodiment. Figure 6 As shown, including:

[0083] Step 101: The register module receives a control signal of the system on chip to generate a corresponding register signal, and transmits the register signal to the trigger sampling module.

[0084] The trigger sampling module includes a trigger generation module, a sampling module and a FIFO module. The register module is connected to the trigger generation module, the sampling module and the FIFO module respectively. The trigger generation module is connected to the sampling module, and the sampling module is connected to the FIFO module. The register module receives the control signal of the system on chip to generate a corresponding register signal, and transmits the register signal to the trigger generation module, the sampling module and the FIFO module respectively.

[0085] Step 102: The OBS pin transmits the internal signal in the system on chip to the trigger sampling module.

[0086] The trigger sampling module also includes a data channel module, which is connected to the sampling module; the data channel module receives an internal signal of the system on chip through the OBS pin, and transmits the internal signal to the sampling module.

[0087] Step 103: The trigger sampling module receives the register signal and the internal signal, and generates a trigger signal according to the register signal. The trigger sampling module samples the internal signal through the trigger signal to obtain a sampling result, and writes the sampling result back to the on-chip system.

[0088] The register signal includes: a configuration signal, a sampling signal and a write-back signal; the trigger generation module configures the corresponding trigger condition according to the configuration signal, and when the trigger condition is met, the trigger generation module generates a trigger signal; the sampling module samples the internal signal according to the trigger signal to obtain the sampling result, and writes the sampling result back to the memory in real time according to the sampling signal; the FIFO module processes the sampling result in the sampling module to obtain a FIFO signal, and writes the FIFO signal back to the DDR of the on-chip system according to the write-back signal.

[0089] Among them, the specific implementation process and implementation basis of each step have been correspondingly explained in the above embodiments, and will not be repeated in this embodiment. The specific structure of the internal logic analyzer of the chip can be found in the above embodiments, and will not be explained in detail in this embodiment.

[0090] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip internal logic analyzer, characterized in that: include: A register module and a trigger sampling module, wherein the register module is connected to the trigger sampling module, an OBS pin is provided on the logic analyzer, and the logic analyzer is mounted under the system on chip; The register module is used to receive the control signal of the system on chip to generate a corresponding register signal, and transmit the register signal to the trigger sampling module; The OBS pin is used to transmit the internal signal of the system on chip to the trigger sampling module; The trigger sampling module is used to receive the register signal and the internal signal, and generate a trigger signal according to the register signal. The trigger sampling module samples the internal signal through the trigger signal to obtain a sampling result, and writes the sampling result back to the on-chip system.

2. The internal chip logic analyzer according to claim 1, characterized in that: The system on chip comprises a control unit and an AHB bus unit, wherein the control unit is connected to the AHB bus unit; The control unit is used to control the operation of the entire system on chip and send the control signal through the AHB bus unit; The interrupt pin of the control unit is connected to the interrupt pin of the logic analyzer, and is used to receive and execute the interrupt signal of the logic analyzer.

3. The chip internal logic analyzer according to claim 2, characterized in that: The system on chip further includes an APB bridge unit, the logic analyzer further includes an APB interface, the APB bridge unit includes an input interface and an output interface, and the APB interface includes an input end and an output end; The input interface of the APB bridge unit is connected to the AHB bus unit, and the output interface of the APB bridge unit is connected to the input end of the APB interface; The output end of the APB interface is connected to the register module; The APB bridge unit is used to send the control signal from the AHB bus unit to the logic analyzer.

4. The internal chip logic analyzer according to claim 3, characterized in that: The AHB bus unit is used to convert the control signal of the system on chip into a protocol specification signal of the AHB bus unit; The protocol specification signal of the AHB bus unit is converted into a format recognizable by the register module through the APB bridge unit and the APB interface, so as to ensure normal communication between the register module and the system on chip.

5. The chip internal logic analyzer according to claim 1, characterized in that: The trigger sampling module includes a trigger generation module, a sampling module and a FIFO module, the register module is connected to the trigger generation module, the sampling module and the FIFO module respectively, the trigger generation module is connected to the sampling module, and the sampling module is connected to the FIFO module; The register module is used to receive the control signal of the system on chip to generate a corresponding register signal, and transmit the register signal to the trigger generation module, the sampling module and the FIFO module respectively; Wherein, the register signal includes: a configuration signal, a sampling signal and a write-back signal; The trigger generation module is used to configure the corresponding trigger condition according to the configuration signal, and when the trigger condition is met, the trigger generation module generates a trigger signal; The sampling module is used to sample the internal signal according to the trigger signal to obtain the sampling result, and write the sampling result back to the memory in real time according to the sampling signal; The FIFO module is used to process the sampling result in the sampling module to obtain a FIFO signal, and write the FIFO signal back to the DDR of the system on chip according to the write-back signal.

6. The internal chip logic analyzer according to claim 5, characterized in that: The trigger sampling module also includes a data channel module, and the data channel module is connected to the sampling module; The data channel module is used to receive the internal signal of the system on chip through the OBS pin and transmit the internal signal to the sampling module.

7. An analysis method, characterized in that The analysis method is applicable to the chip internal logic analyzer according to any one of claims 1 to 6, comprising: The register module receives the control signal of the system on chip to generate a corresponding register signal, and transmits the register signal to the trigger sampling module; The OBS pin transmits the internal signal of the system on chip to the trigger sampling module; The trigger sampling module receives the register signal and the internal signal, and generates a trigger signal according to the register signal. The trigger sampling module samples the internal signal through the trigger signal to obtain a sampling result, and writes the sampling result back to the on-chip system.

8. The analysis method according to claim 7, characterized in that The register module receives the control signal of the system on chip to generate a corresponding register signal, and transmits the register signal to the trigger sampling module, including: The trigger sampling module includes a trigger generation module, a sampling module and a FIFO module, the register module is connected to the trigger generation module, the sampling module and the FIFO module respectively, the trigger generation module is connected to the sampling module, and the sampling module is connected to the FIFO module; The register module receives the control signal of the system on chip to generate a corresponding register signal, and transmits the register signal to the trigger generation module, the sampling module and the FIFO module respectively.

9. The analysis method according to claim 7, characterized in that The OBS pin transmits the internal signal of the system on chip to the trigger sampling module, including: The trigger sampling module also includes a data channel module, and the data channel module is connected to the sampling module; The data channel module receives an internal signal in the system on chip through the OBS pin, and transmits the internal signal to the sampling module.

10. The analysis method according to claim 8, characterized in that The trigger sampling module receives the register signal and the internal signal, and generates a trigger signal according to the register signal, the trigger sampling module samples the internal signal through the trigger signal to obtain a sampling result, and writes the sampling result back to the on-chip system, including: The register signals include: configuration signals, sampling signals and write-back signals; The trigger generation module configures a corresponding trigger condition according to the configuration signal, and when the trigger condition is met, the trigger generation module generates a trigger signal; The sampling module samples the internal signal according to the trigger signal to obtain the sampling result, and writes the sampling result back to the memory in real time according to the sampling signal; The FIFO module processes the sampling result in the sampling module to obtain a FIFO signal, and writes the FIFO signal back to the DDR of the system on chip according to the write-back signal.

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