A flip-flop resource detection method, device, equipment and medium

Abstract

The present application relates to the technical field of chip testing, and discloses a flip-flop resource detection method, device, equipment and medium, the method is applied to an FPGA chip, the FPGA chip includes a plurality of flip-flops;The method comprises the following steps: obtaining a to-be-detected flip-flop in the FPGA chip, and dividing the to-be-detected flip-flop into a plurality of target test groups;The target test group includes at least one to-be-detected flip-flop;Cascade link is constructed, and the cascade link is connected with each target test group;A test signal is sent to the inlet end of the cascade link, and an output signal of the cascade link is received;The test signal and the output signal are compared, and based on the comparison result, the detection information of the to-be-detected flip-flop is generated.The present application can improve the efficiency of flip-flop resource detection.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, and in particular to a flip-flop resource detection method, device, equipment and medium. BACKGROUND

[0002] A field programmable gate array (FPGA) is a programmable hardware platform with the characteristics of general flexibility, reconfigurability and parallel computing, and is widely used in many important fields such as national defense, medical treatment, computing acceleration and communication signal processing. The hardware logic circuit can be reconfigured by programming, so that it can adapt to different application scenarios. A flip-flop (FF) is one of the most basic logic resources in an FPGA (Field-Programmable Gate Array), which is used for storing data and state. In the production process of the FPGA, the flip-flop resources need to be tested.

[0003] In the related art, all flip-flops on the routing of the input pin and the output pin of the FPGA chip are usually connected in series. However, when the area of the FPGA chip is large, the test time of the chip is long, and the test cost is increased.

[0004] Therefore, there is a need for an efficient flip-flop resource detection method. SUMMARY

[0005] Therefore, the present application provides a flip-flop resource detection method, which can improve the efficiency of flip-flop resource detection.

[0006] In a first aspect, the present application provides a flip-flop resource detection method, which is applied to an FPGA chip, and the FPGA chip includes a plurality of flip-flops. The method includes: obtaining flip-flops to be detected in the FPGA chip, and dividing the flip-flops to be detected into a plurality of target test groups; each target test group includes at least one flip-flop to be detected; a cascade link is constructed, and the cascade link connects each target test group; a test signal is sent to an entrance end of the cascade link, and an output signal of the cascade link is received; the test signal and the output signal are compared, and based on the comparison result, detection information of the flip-flops to be detected is generated.

[0007] In this embodiment, the flip-flops to be detected in the FPGA chip are divided into a plurality of target test groups, and each target test group is connected to construct a cascade link. By sending a test signal to the entrance end of the cascade link and receiving the output signal of the cascade link, the detection information of the flip-flops is obtained. The time delay from the input end to the output end can be reduced, the simulation time of the flip-flop resources can be reduced, and the efficiency of flip-flop resource detection can be improved.

[0008] In an optional implementation, the dividing the to-be-detected flip-flops into the target test groups comprises: obtaining routing resources of the FPGA chip, and determining a target number based on the routing resources; and dividing the to-be-detected flip-flops into the target test groups, each of which includes the target number of to-be-detected flip-flops.

[0009] In the embodiment, the target number is determined according to the routing resources of the FPGA chip, so as to determine the number of to-be-detected flip-flops in each target test group. The adaptability and flexibility of the method can be improved.

[0010] In an optional implementation, the number of input terminals of the target test group corresponds to the number of to-be-detected flip-flops in the target test group, and the number of output terminals of the target test group is the same as the number of input terminals of the target test group.

[0011] In the embodiment, the number of input terminals of the target test group corresponds to the number of to-be-detected flip-flops in the target test group, and the number of output terminals of the target test group is the same as the number of input terminals of the target test group. The to-be-detected flip-flops in the target test group can be detected simultaneously during the flip-flop resource test, and the efficiency of the flip-flop resource detection can be improved.

[0012] In an optional implementation, the constructing the cascade link comprises: determining a connection order of the cascade link; and connecting, according to the connection order, an output terminal of a first target test group with an input terminal of a second target test group, the second target test group being a next target test group of the first target test group in the connection order.

[0013] In the embodiment, the connection order of the cascade link is obtained, and the target test groups are connected according to the connection order, so that the signal transmission of the cascade link is more regular, and the convenience of the flip-flop resource detection is improved.

[0014] In an optional implementation, the constructing the cascade link comprises: determining a distribution state of each target test group on the FPGA chip; and based on the distribution state, serially cascading target test groups in a same column and parallelly cascading target test groups between different columns.

[0015] In the embodiment, the distribution state of the target test groups on the FPGA chip is obtained, and the target test groups in the same column are serially cascaded and the target test groups between different columns are parallelly cascaded. The test delay from the input terminal to the output terminal of the cascade link can be reduced.

[0016] In an optional implementation, the FPGA chip further comprises a lookup table module in a target column; the lookup table module is configured to obtain an output of a terminal target test group of a previous column of the target column and an output of a previous target test group of a terminal target test group of the target column, and generate a corresponding control signal to be transmitted to an input terminal of the terminal target test group of the target column.

[0017] In the embodiment, the lookup table module is configured to obtain the output of the last target test group of the previous column of the target column and the output of the previous target test group of the last target test group of the target column, and generate a corresponding control signal to be transmitted to the input end of the last target test group of the target column, so that the test signals between different columns can be transmitted in parallel, the time delay of the flip-flop resource detection is reduced, and the efficiency of the flip-flop resource detection is improved.

[0018] In an optional embodiment, the detection information of the flip-flop to be detected is generated based on the comparison result of the test signal and the output signal, including: comparing the test signal and the output signal, obtaining the similarity between the test signal and the output signal based on the comparison result; and generating the detection information of the flip-flop to be detected based on the similarity.

[0019] In the embodiment, the flip-flop resource can be quickly detected by comparing the similarity of the test signal and the output signal, and the detection efficiency is improved.

[0020] In a second aspect, the present application provides a flip-flop resource detection device, which comprises: a division module configured to obtain flip-flops to be detected in an FPGA chip and divide the flip-flops to be detected into a plurality of target test groups; each target test group comprises at least one flip-flop to be detected; a construction module configured to construct a cascade link connecting the target test groups; a test module configured to send a test signal to an entrance of the cascade link and receive an output signal of the cascade link; and a generation module configured to compare the test signal and the output signal and generate detection information of the flip-flops to be detected based on the comparison result.

[0021] In a third aspect, the present application provides a computer device, which comprises a memory and a processor, the memory and the processor are in communication connection with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the flip-flop resource detection method of the first aspect or any of the corresponding embodiments thereof.

[0022] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer instructions, and the computer instructions are used to make a computer execute the flip-flop resource detection method of the first aspect or any of the corresponding embodiments thereof. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the specific embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0024] Figure 1 is a flowchart of a trigger resource detection method according to an embodiment of the present application;

[0025] Figure 2 is a schematic diagram of a target test group connection according to an embodiment of the present application;

[0026] Figure 3 is a flowchart of another trigger resource detection method according to an embodiment of the present application;

[0027] Figure 4 is a schematic diagram of a cascaded link according to an embodiment of the present application;

[0028] Figure 5 is a flowchart of another trigger resource detection method according to an embodiment of the present application;

[0029] Figure 6 is a structural block diagram of a trigger resource detection device according to an embodiment of the present application;

[0030] Figure 7 is a hardware structure schematic diagram of a computer device according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0032] In the production process of an FPGA, the FPGA chip is susceptible to process defects, electrostatic discharge, temperature and stress, etc., leading to its not meeting the expectation. Before leaving the factory, the FPGA chip needs to go through a series of production tests, including circuit probe (CP) and final test (FT), etc., to perform detailed fault coverage tests on the key resources in the FPGA.

[0033] Important factors in the production design include coverage and test time, and it is required to cover as many faults as possible with as few detection times as possible, so as to reduce the cost of production test while ensuring the test quality.

[0034] Flip-Flop (FF) is one of the most basic logic resources in FPGA, which is used to store data and state. In mass production design, it is necessary to implement full coverage of FF resources efficiently to ensure the synchronization logic function of FF.

[0035] FF captures the value of the input signal at the rising edge or falling edge of the clock, and updates its output in the next clock cycle, that is, it needs to be tapped every time a FF passes. In the related art, when testing the FF, a cascading method is usually used, and the specific cascading method is to connect all the FFs in the routing from the INPAD (input end) to the OUTPAD (output end) in series, and the time delay from the input to the output is proportional to the number of cascaded FFs in the routing. Therefore, when the area of the FPGA chip is large, it is easy to cause the test time to be too long, increase the test cost, and a method for efficiently implementing FF resource detection is needed.

[0036] The embodiment of the present application provides a flip-flop resource detection method, which divides the flip-flop to be detected of the FPGA chip into a plurality of target test groups, and then connects each target test group to build a cascading link. The detection information of the flip-flop resource is obtained by sending a test signal to the entrance of the cascading link and receiving the output signal of the cascading link. The time delay from the input end to the output end can be reduced, the simulation time of the flip-flop resource can be reduced, and the efficiency of the flip-flop resource detection can be improved.

[0037] According to the embodiment of the present application, a flip-flop resource detection method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a group of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from here.

[0038] In this embodiment, a flip-flop resource detection method is provided, which is applied to an FPGA chip, and the FPGA chip includes a plurality of flip-flops. Figure 1 The flowchart of the flip-flop resource detection method according to the embodiment of the present application is shown in FIG. 1, which includes the following steps: Figure 1 As shown in the figure, the flowchart includes the following steps:

[0039] In step S101, the flip-flop to be detected in the FPGA chip is obtained, and the flip-flop to be detected is divided into a plurality of target test groups; the target test group includes at least one flip-flop to be detected.

[0040] In the detection of the flip-flop, the FPGA chip can be first installed on a suitable development board, and the power supply of the development board is ensured to be stable, and each pin is correctly connected. Then the development tool is configured to enable it to identify the model of the FPGA chip on the development board. After successful identification, the resource viewing function of the development tool is used to view the internal flip-flops and the number and location of the FPGA chip. According to the actual situation, the flip-flop to be detected is determined.

[0041] After the flip-flop to be detected is determined, the flip-flop to be detected can be divided into several target test groups according to the location or function of the flip-flop to be detected. Each target test group contains at least one flip-flop to be detected.

[0042] In specific implementation, the FPGA chip includes several Tiles (tiled modules), and each Tile includes several flip-flops. The flip-flop to be detected can be selected from the flip-flops on the Tile according to the test purpose, and the flip-flop to be detected can be divided into several target test groups.

[0043] In an actual application, all flip-flops in the FPGA chip need to be detected, and the flip-flops can be divided into several test groups according to the type and distribution of the flip-flops. The test groups containing flip-flops of the same type and number can be constructed as target test sequences for subsequent detection. The number of target test sequences can be determined according to the actual situation.

[0044] In each detection, the test groups contained in a target test sequence are used as target test groups for testing. After the test is completed, the test groups contained in the next target test sequence are used as target test groups for the next round of testing, until all target test sequences are tested. The number of target test sequences is the configuration times of covering all flip-flops on the FPGA chip. In subsequent detection, if the detection information is problematic, it means that the flip-flops in the target test groups through which the routing passes have a fault, and if the detection information is normal, it means that the flip-flops in the target test groups through which the routing passes have no fault.

[0045] Step S102, a cascade link is constructed, and the cascade link connects each target test group.

[0046] The cascade link can be constructed according to the distribution state of the target test groups. In some optional embodiments, after a target test group in the cascade link is determined, the target test group closest to the previous target test group in position can be selected from the remaining target test groups as the next connected test group of the cascade link, until all target test groups are connected to obtain a complete cascade link.

[0047] In some optional embodiments, as Figure 2As shown, FFA, FFB, FFC and FFD represent four types of flip-flops respectively. There are several Tiles in the FPGA chip, and each Tile has FFA, FFB, FFC and FFD flip-flops. According to the distribution of the four types of flip-flops, they are combined into several FF Groups, that is, target test groups, and each FF Group includes one FFA, FFB, FFC and FFD flip-flop. It is shown that this detection can cover all FFA, FFB, FFC and FFD flip-flops on the FPGA chip. The connection of the cascade link is as shown in Figure 2 As shown, the output end of the Nth stage FF Group is connected to the input end of the N+1th stage FF Group; FF_IN[0:3] represents the input end of the FF Group, and the input end has four lines respectively connected to the input ends of the four types of flip-flops in the FF Group. BUS[0:3] represents the output end of the FF Group, and the output end has four lines respectively connected to the output ends of the four types of flip-flops in the FF Group. That is, the outputs of the FFA, FFB, FFC and FFD flip-flops in the Nth stage FF Group are connected to the inputs of the FFA, FFB, FFC and FFD flip-flops in the N+1th stage FF Group.

[0048] In step S103, a test signal is sent to the input end of the cascade link, and an output signal of the cascade link is received.

[0049] The test signal can be a fixed frequency rectangular wave. The output signal is the output signal of the last target test group on the cascade link.

[0050] The output signal is directly connected to the last target test group on the cascade link, or an oscilloscope can be connected behind the output end of the cascade link, and the data of the oscilloscope is taken as the output signal.

[0051] In step S104, the test signal and the output signal are compared, and based on the comparison result, the detection information of the flip-flop to be detected is generated.

[0052] The timing, waveform integrity, etc. of the output signal can be checked to obtain the test result of the flip-flop to be detected. After obtaining the detection information of the flip-flop to be detected, the test result of the flip-flop to be detected can be displayed through a screen display device, and if the detection result is abnormal, the staff can be reminded through an alarm device.

[0053] In specific implementation, the test signal can be a certain period excitation signal. If the output signal of the cascade link is the same as the test signal, it means that the flip-flop to be detected does not have a fault, and if the output signal does not meet the expectation, that is, there is a large difference between the test signal, it means that the flip-flop to be detected on the cascade link has a fault.

[0054] In one practical application, there are multiple Tiles on the FPGA chip to be detected, and each Tile has the same type and number of FFs to be detected; the FFs to be detected on each Tile are divided into a plurality of FF Groups, and the division result of each Tile is consistent, that is, each Tile includes the same number of FF Groups, and each FF Group includes the same type and number of FFs to be detected.

[0055] The number of detection configuration times of the FFs to be detected is the same as the number of FF Group types, that is, the first type of FF Group on each Tile is configured and detected in the first time, the second type of FF Group on each Tile is configured and detected in the second time, and so on until the detection of the FF Group of the last type is completed. For each configuration, the corresponding FF Group on each Tile is detected. In each configuration, the corresponding FF Groups on different Tiles are connected by cascading. The cascaded routing can be solved in a local range and replicated in the whole chip range, and is not limited by the size of the chip.

[0056] The flip-flop resource detection method provided in the embodiment divides the flip-flops to be detected of the FPGA chip into a plurality of target test groups, connects each target test group, and constructs a cascaded link. The detection information of the flip-flop resource is obtained by sending a test signal to the entrance of the cascaded link and receiving the output signal of the cascaded link. The time delay from the input end to the output end can be reduced, the simulation time of the flip-flop resource can be reduced, and the efficiency of flip-flop resource detection can be improved.

[0057] A flip-flop resource detection method is provided in the embodiment, and the method is applied to an FPGA chip. The FPGA chip includes a plurality of flip-flops. Figure 3 The flowchart of the flip-flop resource detection method according to the embodiment of the application is shown in FIG. 1, and the flowchart includes the following steps: Figure 3

[0058] In step S201, the flip-flops to be detected in the FPGA chip are obtained, and the flip-flops to be detected are divided into a plurality of target test groups; the target test group includes at least one flip-flop to be detected.

[0059] For details, refer to step S101 of the embodiment shown in FIG. 1, which will not be repeated here. Figure 1

[0060] In some optional embodiments, step S201 includes:

[0061] In step S2011, the routing resources of the FPGA chip are obtained, and the target number is determined based on the routing resources.​​

[0062] The routing resources of the FPGA chip can be obtained according to a data manual of the FPGA chip, or the routing resources of the FPGA chip can be obtained by using an FPGA development tool.

[0063] Under the premise of the routing resources, the number of the to-be-detected flip-flops in each target test group is as large as possible, and the number of the target test groups is as small as possible, so that the multiple flip-flops in the target test group are detected at the same time in each detection configuration, the number of the detection configurations is reduced, and the detection efficiency of the flip-flop resources is improved.

[0064] In step S2012, the to-be-detected flip-flops are divided into a plurality of target test groups, and each target test group includes a target number of to-be-detected flip-flops.

[0065] The to-be-detected flip-flops can be divided according to the positions of the to-be-detected flip-flops on the FPGA chip, so as to reduce unnecessary wiring waste.

[0066] The number of the to-be-detected flip-flops in each target test group is determined according to the routing resources of the FPGA chip, so that the adaptability and flexibility of the method are improved.

[0067] In some optional embodiments, the number of the input ends of the target test group corresponds to the number of the to-be-detected flip-flops in the target test group, and the number of the output ends of the target test group is the same as the number of the input ends of the target test group.

[0068] The number of the input ends of the target test group corresponds to the number of the to-be-detected flip-flops in the target test group, and the number of the output ends of the target test group is the same as the number of the input ends of the target test group. When the number of the to-be-detected flip-flops in the target test group is not 1, multiple detection signals can be input to the to-be-detected flip-flops at the same time, and the output signals of the to-be-detected flip-flops are received, so that the to-be-detected flip-flops in the target test group are detected at the same time, and the detection efficiency of the flip-flop resources is improved.

[0069] In step S202, a cascade link is constructed, and the cascade link connects the target test groups.

[0070] Specifically, the step S202 includes the following steps.

[0071] In step S2021, the distribution state of each target test group on the FPGA chip is determined.

[0072] The distribution state of the target test group on the FPGA chip can be obtained by using the development tool of the FPGA, or can be directly obtained by using the data manual of the FPGA.

[0073] In step S2022, the target test groups in the same column are serially cascaded, and the target test groups between different columns are parallelly cascaded based on the distribution state.

[0074] Wherein, the target test groups can be divided by column according to the distribution state of the target test groups. After the division, adaptive adjustment can be made according to the actual situation. After the adjustment, the target test groups in the same column are serially cascaded, that is, the output end of the previous target test group is connected to the input end of the next target test group. The target test groups between different columns are parallelly cascaded, that is, the input end of the first target test group of each column target test group is connected to the inlet end of the cascade link to receive the test signal.

[0075] In some optional embodiments, the FPGA chip further comprises a lookup table module in the target column; the lookup table module is used to obtain the output of the last target test group of the previous column of the target column and the output of the previous target test group of the last target test group of the target column, and generate a corresponding control signal to be transmitted to the input end of the last target test group of the target column.

[0076] Wherein, the lookup table module has three input signals, which are respectively: the output of the last target test group of the previous column of the target column, the output of the previous target test group of the last target test group of the target column, and a control signal, the three input signals jointly control the lookup table and generate a corresponding data signal to be transmitted to the input end of the last target test group of the target column.

[0077] The function of the control signal is to combine the output of the last target test group of the previous column of the target column and the output of the previous target test group of the last target test group of the target column. When the test data signal is 0, the lookup table module is controlled to perform OR operation by the control signal; when the test data signal is 1, the lookup table module is controlled to perform AND operation by the control signal.

[0078] Wherein, the number and distribution of the lookup table modules can be determined according to the actual situation. In some optional embodiments, the number of the lookup table modules can be determined according to the number of columns of the target test groups. In a specific implementation, if the cascade link has N columns of target test groups, N-1 lookup table modules can be set.

[0079] In an actual application, only one flip-flop is included in each target test group, and the construction result of the cascade link is as follows Figure 4As shown, there are X target test groups, and each target test group has Y rows of target test groups, and each target test group includes only one flip-flop. The target test group is directly represented by FF. Wherein, CLK represents a clock signal, DATA represents a data signal, CTRL represents a control signal, and LUT represents a lookup table module; clk represents a clock input end of the flip-flop, D represents a data input end of the flip-flop, and Q represents a data output end of the flip-flop. The clock signal is connected to the clock input end of each FF to control the sampling time of the FF. The DATA signal from the entrance of the cascade link is transmitted to the FF at the bottom end of each column and is cascaded in series from bottom to top. After the DATA signal of the first column is serially input into the topmost FF, the output of the FF is combined with the DATA signal output by the second last FF of the next column through the LUT, as the input of the topmost FF of the next column. As shown in the connection mode, the time delay of the cascade link from input to output is k*(X+Y-1); if the same number of target test groups each include only one flip-flop, and each flip-flop is connected in series, then the time delay of the cascade link from input to output is k*X*Y, where k is a proportionality coefficient which can be determined according to actual conditions. Figure 4 As shown in the connection mode, the time delay of the cascade link from input to output is k*(X+Y-1); if the same number of target test groups each include only one flip-flop, and each flip-flop is connected in series, then the time delay of the cascade link from input to output is k*X*Y, where k is a proportionality coefficient which can be determined according to actual conditions. Figure 4 As shown in the connection mode, the time delay of the cascade link from input to output is k*(X+Y-1); if the same number of target test groups each include only one flip-flop, and each flip-flop is connected in series, then the time delay of the cascade link from input to output is k*X*Y, where k is a proportionality coefficient which can be determined according to actual conditions.

[0080] The combination of data signals of different columns by the lookup table module can make the DATA signals between columns be transmitted in parallel, and the test signal can reach the output end of the cascade link through fewer flip-flops. The time delay from input to output can be greatly reduced, and the test time and test cost can be reduced.

[0081] In step S203, a test signal is sent to the entrance of the cascade link, and an output signal of the cascade link is received.

[0082] For details, please refer to Figure 1 The step S103 of the embodiment shown will not be repeated here.

[0083] In some optional embodiments, the test signal can be flipped every certain period of time to sufficiently detect all flip-flops on the FPGA chip.

[0084] In step S204, the test signal and the output signal are compared, and based on the comparison result, detection information of the flip-flop to be detected is generated.

[0085] For details, please refer to Figure 1 The step S104 of the embodiment shown will not be repeated here.

[0086] In some optional embodiments, the step S204 includes:

[0087] In step S2041, the test signal and the output signal are compared, and based on the comparison result, the similarity between the test signal and the output signal is obtained.

[0088] The signal features of the test signal and the output signal can be extracted, and the similarity between the output signal and the test signal is obtained by comparing the signal features of the test signal and the output signal. The signal features can be determined according to actual conditions and can include signal frequency, signal amplitude, signal phase, signal oscillation amplitude, etc. By using different signal features, the reliability of the detection result can be improved.

[0089] In some optional embodiments, a plurality of signal features can be extracted and compared. According to actual conditions, the target signal feature type to be compared can be selected, the reference features of the test signal are extracted, and the reference sequence is constructed; the output features corresponding to the output signal are extracted, and the output sequence is constructed. The reference features and the output features correspond to the target signal feature type. The matching feature parameter pairs are determined in the reference sequence and the output sequence, the parameter ratios of the feature parameter pairs are calculated, and then based on the ratio results, the similarity between the reference sequence and the output sequence is obtained.

[0090] The similarity can be obtained by weighting and fusing or averaging the parameter ratios, so as to improve the accuracy of the flip-flop resource detection result.

[0091] In step S2042, based on the similarity, the detection information of the flip-flop to be detected is generated.

[0092] A similarity threshold can be set, and the detection information of the flip-flop to be detected is generated by judging the relationship between the similarity and the similarity threshold. If the similarity is greater than the similarity threshold, it means that the flip-flop resource is normal, and if the similarity is less than the similarity threshold, it means that the flip-flop resource is abnormal. The staff needs to process it.

[0093] By comparing the similarity of the test signal and the output signal, the flip-flop resource can be quickly detected, and the detection efficiency is improved.

[0094] The flip-flop resource detection method provided in this embodiment can obtain the distribution state of the target test group in the cascade link, cascade the target test groups in the same column in series, and cascade the target test groups between different columns in parallel. The test delay from the input end to the output end of the cascade link can be reduced.

[0095] In this embodiment, a flip-flop resource detection method is provided, which is applied to an FPGA chip. The FPGA chip includes a plurality of flip-flops. Figure 5 The flowchart of the flip-flop resource detection method according to the embodiment of the application is shown in FIG. 1, which includes the following steps: Figure 5 ​

[0096] Step S301, obtaining the to-be-detected flip-flops in the FPGA chip, and dividing the to-be-detected flip-flops into a plurality of target test groups; each target test group includes at least one to-be-detected flip-flop.

[0097] For details, please refer to Figure 1 Step S101 of the embodiment shown will not be repeated here.

[0098] Step S302, constructing a cascade link, the cascade link connecting the target test groups.

[0099] Specifically, the above step S302 includes:

[0100] Step S3021, determining the connection order of the cascade link.

[0101] The connection order can be determined according to the distribution state of the target test groups. In some optional embodiments, connecting adjacent target test groups can reduce the waste of wiring resources and improve the efficiency of flip-flop detection.

[0102] Step S3022, connecting the output end of the first target test group to the input end of the second target test group according to the connection order; the second target test group is the next target test group of the first target test group in the connection order.

[0103] The connection of the first target test group and the second target test group can be as shown in Figure 2 .

[0104] Step S303, sending a test signal to the inlet end of the cascade link, and receiving an output signal of the cascade link.

[0105] For details, please refer to Figure 1 Step S103 of the embodiment shown will not be repeated here.

[0106] Step S304, comparing the test signal and the output signal, and generating detection information of the to-be-detected flip-flops based on the comparison result.

[0107] For details, please refer to Figure 1 Step S104 of the embodiment shown will not be repeated here.

[0108] The flip-flop resource detection method provided in the embodiment can make the signal transmission of the cascade link more regular by obtaining the connection order of the cascade link and connecting the target test groups according to the connection order, thereby improving the convenience of flip-flop resource detection.

[0109] A trigger resource detection apparatus is also provided in the embodiments, which is configured to implement the above-described embodiments and preferred embodiments, and details of which have been described above. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0110] The embodiments provide a trigger resource detection apparatus, as shown in Figure 6 The apparatus comprises:

[0111] A division module 401 is configured to obtain a to-be-detected trigger in an FPGA chip, and divide the to-be-detected trigger into a plurality of target test groups, each of which includes at least one to-be-detected trigger.

[0112] A construction module 402 is configured to construct a cascade link connecting the target test groups.

[0113] A test module 403 is configured to send a test signal to an entry end of the cascade link, and receive an output signal of the cascade link.

[0114] A generation module 404 is configured to compare the test signal and the output signal, and generate detection information of the to-be-detected trigger based on a comparison result.

[0115] In some optional embodiments, the division module 401 comprises:

[0116] A quantity determination unit is configured to obtain routing resources of the FPGA chip, and determine a target quantity based on the routing resources.

[0117] A division unit is configured to divide the to-be-detected trigger into a plurality of target test groups, each of which includes the target quantity of to-be-detected triggers.

[0118] In some optional embodiments, the number of input ends of the target test group corresponds to the number of to-be-detected triggers of the target test group, and the number of output ends of the target test group is the same as the number of input ends of the target test group.

[0119] In some optional embodiments, the construction module 402 comprises:

[0120] A sequence determination unit is configured to determine a connection sequence of the cascade link.

[0121] A connection unit is configured to connect an output end of a first target test group to an input end of a second target test group according to the connection sequence, the second target test group being a next target test group of the first target test group in the connection sequence.

[0122] In some optional embodiments, the construction module 402 comprises:

[0123] a distribution determining unit configured to determine a distribution state of the target test groups on the FPGA chip.

[0124] a cascading unit configured to cascade the target test groups in the same column in series and cascade the target test groups between different columns in parallel based on the distribution state.

[0125] In some optional embodiments, the FPGA chip further comprises a lookup table module in the target column; the lookup table module is configured to obtain an output of a terminal target test group of a previous column of the target column and an output of a previous target test group of the terminal target test group of the target column, and generate a corresponding control signal to be transmitted to an input end of the terminal target test group of the target column.

[0126] In some optional embodiments, the generation module 404 comprises:

[0127] a comparison unit configured to compare the test signal and the output signal, and obtain a similarity between the test signal and the output signal based on a comparison result.

[0128] an information generation unit configured to generate detection information of the to-be-detected flip-flop based on the similarity.

[0129] Further function descriptions of the above-mentioned modules and units are the same as those of the corresponding embodiments, and will not be repeated here.

[0130] The flip-flop resource detection apparatus in the embodiment is presented in the form of functional units. The units herein refer to ASIC (Application Specific Integrated Circuit) circuits, processors and memories executing one or more software or fixed programs, and / or other devices that can provide the above functions.

[0131] The embodiment of the application further provides a computer device with the above-described Figure 6 flip-flop resource detection apparatus.

[0132] Please refer to Figure 7 , Figure 7 is a structural schematic diagram of a computer device provided by an optional embodiment of the application, as Figure 7As shown, the computer device includes one or more processors 10, memory 20, and interfaces 50 for external devices such as modems and network interfaces. One or more external devices are present, such as display devices, keyboards, mice, speakers, microphones, printers, joysticks, and the like. The computer device optionally has a storage device, such as a disk drive, a flash drive, or a combination thereof, for storing data and programs. The computer device has sufficient storage available to store the programs and data used to implement the embodiments of the present application. Figure 7 The processor 10 is used in one embodiment as the processor.

[0133] The processor 10 can be a central processing unit, a network processor, or a combination thereof. The processor 10 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic device, a general array logic, or a combination thereof.

[0134] The memory 20 stores instructions that can be executed by the at least one processor 10, such that the at least one processor 10 implements the method shown in the above embodiments.

[0135] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system, application programs, and the like for controlling the computer device. The data storage area can store data such as files stored by the computer device. The memory 20 can include a high speed random access memory, and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid state storage device. In some alternative embodiments, the memory 20 can optionally include a memory that is remotely located from the processor 10, and can be connected to the computer device through a network. Examples of the network include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and a combination thereof.

[0136] The memory 20 can include a volatile memory, such as a random access memory, and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid state storage device. The memory 20 can include a combination of the above-mentioned types of storage.

[0137] The computer device also includes input devices 30 and output devices 40. The input devices 30 are used to input information into the computer device 10, and the output devices 40 are used to output information from the computer device 10. The input devices 30 and output devices 40 can include a combination of input and output devices including, but not limited to, a display, a keyboard, a mouse, a trackpad, a trackball, a microphone, a speaker, a camera, a printer, and the like.Figure 7 The bus connection is taken as an example.

[0138] The input device 30 can receive inputted digital or character information, and generate key signal input related to user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (e.g., an LED), a tactile feedback device (e.g., a vibration motor), etc. The display device includes, but is not limited to, a liquid crystal display, a light-emitting diode, a display, and a plasma display. In some alternative embodiments, the display device can be a touch screen.

[0139] The embodiments of the present application also provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded from a network and stored in a local storage medium, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, which, when accessed and executed by the computer, the processor, or the hardware, implements the method shown in the above embodiments.

[0140] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, the method and / or technical solutions according to the present application can be called or provided. Those skilled in the art should understand that the form of computer program instructions in a computer readable medium includes but is not limited to source files, executable files, installation package files, etc. Correspondingly, the way of computer program instructions executed by a computer includes but is not limited to: the computer directly executes the instructions, or the computer executes the corresponding compiled program after compiling the instructions, or the computer reads and executes the instructions, or the computer executes the corresponding installed program after reading and installing the instructions. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0141] While embodiments of the application have been described in connection with the preferred embodiments of the various figures, those of ordinary skill in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the application, and that such modifications and changes fall within the scope of the appended claims.

Claims

1. A flip-flop resource detection method, characterized in that, The method is applied to an FPGA chip, and the FPGA chip includes a plurality of flip-flops; the method includes: obtaining a to-be-detected flip-flop in the FPGA chip, and dividing the to-be-detected flip-flop into a plurality of target test groups; each target test group includes at least one to-be-detected flip-flop; constructing a cascade link connecting the target test groups; sending a test signal to an entrance of the cascade link, and receiving an output signal of the cascade link; comparing the test signal and the output signal, and generating detection information of the to-be-detected flip-flop based on a comparison result; wherein the dividing of the to-be-detected flip-flop into the target test groups includes: obtaining routing resources of the FPGA chip, and determining a target number based on the routing resources; dividing the to-be-detected flip-flops into the target test groups based on positions of the to-be-detected flip-flops on the FPGA chip; each target test group includes a target number of to-be-detected flip-flops; the constructing of the cascade link includes: determining a distribution state of each target test group on the FPGA chip; based on the distribution state, serially cascading target test groups in a same column, and parallelly cascading target test groups between different columns.

2. The method of claim 1, wherein, A number of input ends of each target test group corresponds to a number of to-be-detected flip-flops in the target test group; a number of output ends of each target test group is the same as a number of input ends of the target test group.

3. The method of claim 1, wherein, The constructing of the cascade link includes: determining a connection order of the cascade link; connecting an output end of a first target test group with an input end of a second target test group according to the connection order; the second target test group is a next target test group of the first target test group in the connection order.

4. The method of claim 1, wherein, The FPGA chip further includes a lookup table module in a target column; the lookup table module is configured to obtain an output of a terminal target test group of a previous column of the target column and an output of a previous target test group of a terminal target test group of the target column, and generate a corresponding control signal to be transmitted to an input end of the terminal target test group of the target column.

5. The method of claim 1, wherein, The comparing of the test signal and the output signal, and the generating of the detection information of the to-be-detected flip-flop based on a comparison result include: comparing the test signal and the output signal, and obtaining a similarity between the test signal and the output signal based on a comparison result; generating the detection information of the to-be-detected flip-flop based on the similarity.

6. A flip-flop resource detection apparatus, characterized by comprising: The apparatus includes: a dividing module configured to obtain to-be-detected flip-flops in an FPGA chip, and divide the to-be-detected flip-flops into a plurality of target test groups; each target test group includes at least one to-be-detected flip-flop; a constructing module configured to construct a cascade link connecting the target test groups; a testing module configured to send a test signal to an entrance of the cascade link, and receive an output signal of the cascade link; a generating module configured to compare the test signal and the output signal, and generate detection information of the to-be-detected flip-flop based on a comparison result; wherein the dividing module is specifically configured to: obtaining routing resources of the FPGA chip, and determining a target number based on the routing resources; based on a position of the to-be-detected flip-flop on the FPGA chip, dividing the to-be-detected flip-flop into a plurality of target test groups, the target test group including a target number of to-be-detected flip-flops; The construction module is specifically configured to: determine the distribution state of each target test group on the FPGA chip; based on the distribution state, serially cascading target test groups in the same column, and parallelly cascading target test groups between different columns.

7. A computer device, comprising: comprising: a memory and a processor, which are in communication connection with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the flip-flop resource detection method in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions, and the computer instructions are used to make the computer execute the flip-flop resource detection method in any one of claims 1 to 5.

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