Array substrate and display device

Abstract

The invention provides an array substrate and a display device. The array substrate comprises a driving module, the driving circuit comprises an input module, an output module and a noise reduction module, the input module transmits a first input signal to a first node under the control of an input signal, and the output module transmits a second input signal to the output end of the driving circuit under the control of the potential of the first node. The noise reduction module transmits a first voltage signal to the first node and / or the output end under the control of the potential of the second node; the driving circuit comprises a plurality of transistors; at least one transistor in the plurality of transistors is electrically connected with a first node through a first via hole, and at least one transistor in the plurality of transistors is electrically connected with a second node through a second via hole; at least one transistor is arranged between the first via hole and the second via hole in a spaced mode. According to the invention, the phenomenon of poor reliability corrosion easily occurring in a narrow-bezel display product is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] In related technologies, with the development of liquid crystal display technology, narrow bezels have become the first requirement for consumer-grade display products. Narrow bezel display products reduce the wrapping of frame sealants on internal wiring and vias, making them more susceptible to reliability corrosion. Summary of the invention

[0003] The main purpose of the present invention is to provide an array substrate and a display device to solve the problem that existing narrow-frame display products are prone to reliability corrosion.

[0004] In one aspect, an embodiment of the present invention provides an array substrate, comprising a substrate and a driving module disposed on the substrate, wherein the driving module comprises a multi-stage driving circuit; the driving circuit comprises an input module, an output module and a noise reduction module, wherein the input module is electrically connected to a first node and is used to transmit a first input signal to the first node under the control of an input signal provided by an input signal terminal, the output module is used to transmit a second input signal to an output terminal of the driving circuit under the control of a potential of the first node, and the noise reduction module is used to transmit a first voltage signal transmitted by a first voltage line to the first node and / or the output terminal under the control of a potential of a second node;

[0005] The driving circuit includes a plurality of transistors;

[0006] At least one transistor among the plurality of transistors is electrically connected to the first node through a first via, and at least one transistor among the plurality of transistors is electrically connected to the second node through a second via;

[0007] At least one transistor is spaced between the first via hole and the second via hole.

[0008] Optionally, a distance between an orthographic projection of the first via hole on the substrate and an orthographic projection of the second via hole on the substrate is greater than or equal to a first distance threshold;

[0009] The first distance threshold is greater than or equal to 100 μm.

[0010] Optionally, the first voltage line is arranged on a side of some transistors included in the driving circuit close to the display area;

[0011] At least one transistor among the plurality of transistors is electrically connected to the first voltage line through a third via.

[0012] Optionally, the noise reduction module includes a first transistor;

[0013] The first transistor is used to reset the potential of the first node under the control of the potential of the second node;

[0014] The first electrode of the first transistor is electrically connected to the first node through a first via.

[0015] Optionally, the driving circuit further includes a second transistor;

[0016] The second transistor is used for resetting the potential of the first node under the control of a frame reset signal provided by a frame reset line;

[0017] The first electrode of the second transistor is electrically connected to the first node through the first via.

[0018] Optionally, the first via hole is arranged on a side of the first transistor close to the display area.

[0019] Optionally, the driving circuit further includes a third transistor and a fourth transistor;

[0020] The third transistor is used to write the second voltage signal provided by the second voltage line into the second node under the control of the potential of the pull-down control node;

[0021] The fourth transistor is used for resetting the potential of the second node under the control of the potential of the first node;

[0022] The second electrode of the third transistor and the first electrode of the fourth transistor are both electrically connected to the second node through the second via.

[0023] Optionally, the second via hole is arranged on a side of the fourth transistor away from the display area.

[0024] Optionally, the driving circuit includes a first transistor;

[0025] The fourth transistor is disposed on a side of the first transistor away from the display area.

[0026] Optionally, the output module includes a driving transistor, and the driving transistor is used to provide a driving signal through an output terminal under the control of the potential of the first node; the array substrate also includes a first voltage line;

[0027] An orthographic projection of the gate of the driving transistor on the substrate and an orthographic projection of the second via hole on the substrate are arranged along a first direction;

[0028] The first direction is substantially the same as an extending direction of the first voltage line.

[0029] Optionally, the driving transistor and the third transistor are arranged along a first direction;

[0030] The driving transistor and the fourth transistor are arranged along a first direction;

[0031] Optionally, the driving circuit further includes a storage capacitor and a fifth transistor;

[0032] The fifth transistor is used to control the output terminal to be connected to the first voltage line under the control of the frame reset signal provided by the frame reset line; the fifth transistor is electrically connected to the first voltage line through the third via hole;

[0033] A notch is provided on one side of the storage capacitor close to the first voltage line, and an orthographic projection of the gate of the fifth transistor on the substrate at least partially overlaps with an orthographic projection of the notch on the substrate.

[0034] Optionally, the driving module includes N-level driving circuits, the first voltage line includes N first voltage line portions, and the n-th level driving circuit corresponds to the n-th first voltage line portion; N is an integer greater than 1, and n is a positive integer less than or equal to N;

[0035] The n-th stage driving circuit includes a fifth transistor electrically connected to the (n-1)th first voltage line portion.

[0036] Optionally, the storage capacitor is adjacent to the first voltage line, and the fifth transistor is adjacent to the first voltage line.

[0037] Optionally, the input module includes a sixth transistor; a gate of the sixth transistor is electrically connected to the input signal terminal, a first electrode of the sixth transistor is electrically connected to the first input signal terminal, and a second electrode of the sixth transistor is electrically connected to the first node;

[0038] The first voltage line is disposed between the storage capacitor and the sixth transistor.

[0039] Optionally, the output module includes a driving transistor;

[0040] The driving transistor is used to provide a driving signal through an output terminal under the control of the potential of the first node;

[0041] The storage capacitor is arranged on a side of the driving transistor close to the display area.

[0042] Optionally, the array substrate further includes a first voltage line; the storage capacitor includes a first electrode plate and a second electrode plate;

[0043] The orthographic projection of the first electrode plate of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the storage capacitor on the substrate;

[0044] The orthographic projection of the first electrode plate of the storage capacitor on the substrate and the orthographic projection of the first via hole on the substrate are arranged along a first direction;

[0045] The first direction is substantially the same as an extending direction of the first voltage line.

[0046] Optionally, the driving circuit includes a first transistor and a second transistor;

[0047] The storage capacitor and the first transistor are arranged along a first direction;

[0048] The storage capacitor and the second transistor are arranged along a first direction.

[0049] In a second aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned array substrate.

[0050] In the embodiment of the present invention, by arranging the first via hole and the second via hole to be separated by at least one transistor, the first via hole can be prevented from being seriously corroded during the reliability process, thereby improving the reliability corrosion problem that is prone to occur in narrow-frame display products. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 is a structural diagram of a related display panel;

[0052] Figure 2 is a structural diagram of at least one embodiment of a pixel circuit;

[0053] Figure 3 is a circuit diagram of at least one embodiment of the pixel circuit;

[0054] Figure 4 yes Figure 3 A layout diagram of at least one embodiment of the driving circuit shown;

[0055] Figure 5 yes Figure 4 A layout diagram of the gate metal layer in FIG.

[0056] Figure 6 yes Figure 4 Layout diagram of source and drain metal layers in FIG.

[0057] Figure 7 yes Figure 4 Layout diagram of the ITO layer in;

[0058] Figure 8 yes Figure 4A layout diagram of a semiconductor layer in FIG.

[0059] Fig. 9 yes Figure 3 A schematic diagram of the positional relationship between at least one embodiment of the driving circuit and the display area A0 shown;

[0060] Fig.10 is a layout diagram of at least one embodiment of a two-stage driving circuit. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0063] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0064] The array substrate described in the embodiment of the present invention comprises a substrate and a driving module arranged on the substrate, wherein the driving module comprises a multi-stage driving circuit; the driving circuit comprises an input module, an output module and a noise reduction module, wherein the input module is electrically connected to a first node and is used to transmit a first input signal to the first node under the control of an input signal provided by an input signal terminal, wherein the output module is used to transmit a second input signal to an output terminal of the driving circuit under the control of a potential of the first node, wherein the noise reduction module is used to transmit a first voltage signal transmitted by a first voltage line to the first node and / or the output terminal under the control of a potential of a second node;

[0065] The driving circuit includes a plurality of transistors;

[0066] At least one transistor among the plurality of transistors is electrically connected to the first node through a first via, and at least one transistor among the plurality of transistors is electrically connected to the second node through a second via;

[0067] At least one transistor is spaced between the first via hole and the second via hole.

[0068] In an embodiment of the present invention, the first via is a via between a first node and at least one transistor included in the driving circuit, and the second via is a via between a second node and at least one transistor included in the driving circuit. By arranging the first via and the second via to be separated by at least one transistor, it is possible to avoid severe corrosion of the first via during the reliability process.

[0069] In the related art, the first via is adjacent to the second via, and during the reliability process, the first via is often severely corroded; when the layout is not changed and only the device spacing is increased, the distance between the first via and the second via is increased very limitedly, and the frame size will be increased, which is not suitable for narrow-frame display products. Based on this, in the array substrate described in the embodiment of the present invention, by making at least one transistor between the first via and the second via, a narrow frame can be achieved while increasing the distance between the first via and the second via.

[0070] In related technologies, with the development of liquid crystal display technology, narrow borders have become the first requirement for consumer display products. Narrow border display products reduce the wrapping of frame sealant on internal wiring and vias, which is more prone to reliability corrosion. High temperature and high humidity operation test is the most stringent environmental condition and also the most prone to reliability corrosion. In high temperature and high humidity environment, such as Figure 1 As shown, water vapor penetrates into the interior of the display screen through the sealing glue and is absorbed by the PI (polyimide) layer into the ITO (indium tin oxide) layer, forming a layer of solution at the PI interface. When the distance between the high and low voltage signals is too close (that is, when the distance between the high voltage via and the low voltage via is too close), an electrolytic cell reaction occurs between the high voltage signal and the low voltage signal. During this process, the low voltage via is easily corroded. When the amount of water absorbed is large, water vapor enters the gap between the ITO layer and the source and drain metal layer, and a primary battery reaction occurs. At this time, the high voltage via will also corrode. Based on this, in the array substrate described in the embodiment of the present invention, by making at least one transistor between the first via and the second via, the distance between the high voltage via and the low voltage via is increased, thereby avoiding the corrosion of the via caused by the high voltage via and the low voltage via being too close.

[0071] exist Figure 1 Among them, numbered 10 is a substrate, numbered 11 is a gate metal layer, numbered 12 is a gate insulating layer, numbered 13 is a source-drain metal layer, numbered 14 is a passivation layer, numbered 15 is an ITO layer, numbered 16 is a PI layer, numbered 17 is a frame sealant, and numbered 18 is an electrolyte (water vapor).

[0072] In at least one embodiment of the present invention, the specific value of the distance is related to PPI (pixel density), and the larger the PPI is, the larger the distance between the first via hole and the second via hole is.

[0073] like Figure 2 As shown, the driving circuit may include an input module 21, an output module 22 and a noise reduction module 23;

[0074] The input module 21 is electrically connected to the first node PU, the input signal terminal I0 and the first input terminal I1 respectively, and is used to transmit the first input signal provided by the first input terminal I1 to the first node PU under the control of the input signal provided by the input signal terminal I0;

[0075] The output module 22 is electrically connected to the first node PU, the second input terminal I2 and the output terminal O1 of the driving circuit respectively, and is used to transmit the second input signal provided by the second input terminal I2 to the output terminal O1 of the driving circuit under the control of the potential of the first node PU;

[0076] The noise reduction module 23 is electrically connected to the second node PD, the first voltage line VL1, the first node PU and the output terminal O1 respectively, and is used to transmit the first voltage signal transmitted by the first voltage line VL1 to the first node PU and / or the output terminal O1 under the control of the potential of the second node PD.

[0077] Optionally, the first input terminal I1 may be a first control voltage line VDS, the second input terminal I2 may be a clock signal line, and the first voltage line VL1 may be a low voltage line, but is not limited thereto.

[0078] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown,

[0079] The noise reduction module includes a first transistor M1, and the driving circuit also includes a second transistor M2, a third transistor M3 and a fourth transistor M4; the output module includes a driving transistor M0; the driving circuit also includes a storage capacitor C1 and a fifth transistor M5; the input module includes a sixth transistor M6; the driving circuit also includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10;

[0080] The gate of M1 is electrically connected to the second node PD, the first electrode of M1 is electrically connected to the first node PU, and the second electrode of M1 is electrically connected to the low voltage line VGL;

[0081] The gate of M2 is electrically connected to the frame reset line STV0, the first electrode of M2 is electrically connected to the first node PU, and the second electrode of M2 is electrically connected to the low voltage line VGL;

[0082] The gate of M3 is electrically connected to the pull-down control node PD_CN, the first electrode of M3 is electrically connected to the high voltage line GCH, and the second electrode of M3 is electrically connected to the second node PD;

[0083] The gate of M4 is electrically connected to the first node PU, the first electrode of M4 is electrically connected to the second node PD, and the second electrode of M4 is electrically connected to the low voltage line VGL;

[0084] The gate of M0 is electrically connected to the first node PU, the first electrode of M0 is electrically connected to the clock signal line CLK, and the second electrode of M0 is electrically connected to the output terminal O1;

[0085] The first electrode plate of C1 is electrically connected to the first node PU, and the second electrode plate of C1 is electrically connected to the output terminal O1;

[0086] The gate of M5 is electrically connected to the frame reset line STV0, the first electrode of M5 is electrically connected to the output terminal O1, and the second electrode of M5 is electrically connected to the low voltage line VGL;

[0087] The gate of M6 is electrically connected to the input signal terminal I0, the first electrode of M6 is electrically connected to the first control voltage line VDS, and the second electrode of M6 is electrically connected to the first node PU;

[0088] The gate of M7 and the first electrode of M7 are electrically connected to the high voltage line GCH, and the second electrode of M7 is electrically connected to the pull-down control node PD_CN;

[0089] The gate of M8 is electrically connected to the first node PU, the first electrode of M8 is electrically connected to the pull-down control node PD_CN, and the second electrode of M8 is electrically connected to the low voltage line VGL;

[0090] The gate of M9 is electrically connected to the reset terminal R1, the first electrode of M9 is electrically connected to the first node PU, and the second electrode of M9 is electrically connected to the second control voltage line VSD;

[0091] A gate of M10 is electrically connected to the second node PD, a first electrode of M10 is electrically connected to the output terminal O1 , and a second electrode of M10 is electrically connected to the low voltage line VGL.

[0092] exist Figure 3 In at least one embodiment shown, all transistors are n-type transistors, but the present invention is not limited thereto.

[0093] exist Figure 3 In at least one embodiment shown, when the driving circuit is in a forward scanning state, VDS provides a high voltage signal and VSD provides a low voltage signal; when the driving circuit is in a reverse scanning state, VDS provides a low voltage signal and VSD provides a high voltage signal.

[0094] In at least one embodiment of the present invention, the potential of the first node PU can be regarded as a low-voltage signal, the potential of the second node PD is controlled by the potential of the first node PU, the potential of the second node PD can be regarded as a high-voltage signal, the first via can be a low-voltage via, the second via can be a high-voltage via, the potential of the first node PU is a high level between the output signal of this stage and the reset signal, and a low level at other times, and the potential of the first node PU can be regarded as a low-voltage signal; the potential of the second node PD is controlled by the PU voltage, when the potential of the first node PU is a low level, the potential of the second node PD is a high level, and the potential of the second node PD can be regarded as a high-voltage signal.

[0095] In at least one embodiment of the present invention, the distance between the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate is greater than or equal to a first distance threshold;

[0096] The first distance threshold is greater than or equal to 100 μm.

[0097] In a specific implementation, the distance between the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate may be greater than or equal to 100 μm. For example, the distance between the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate may be set to be greater than or equal to 150 μm, but is not limited to this.

[0098] In at least one embodiment of the present invention, the first distance threshold may be greater than or equal to 100 μm and less than or equal to 200 μm. For example, the first distance threshold may be 110 μm, 120 μm, 130 μm, 150 μm, 160 μm, 180 μm, 190 μm or 200 μm, but is not limited thereto.

[0099] In a specific implementation, the first via hole may be the outermost low-voltage via hole. According to a more related technical solution, the low-voltage via hole may be moved inward by 230 μm.

[0100] In at least one embodiment of the present invention, the first voltage line is arranged on a side of a portion of transistors included in the driving circuit close to the display area;

[0101] At least one transistor among the plurality of transistors is electrically connected to the first voltage line through a third via.

[0102] In the related art, the first voltage line can be a low voltage line, and the low voltage line is arranged on the side of the driving circuit away from the display area, the low voltage line is close to the edge of the frame sealant, and the connection via between the transistor in the driving circuit and the low voltage line is close to the edge of the frame sealant, and moisture can easily enter the connection via. Based on this, at least one embodiment of the present invention arranges the first voltage line on the side of some transistors included in the driving circuit close to the display area, increases the distance between the third via and the edge of the frame sealant, and prevents moisture from entering the third via.

[0103] In at least one embodiment of the present invention, by setting the first voltage line on the side of some transistors included in the driving circuit close to the display area, the third via can be moved inward, and the first via becomes the outermost low-voltage via. Compared with the related scheme, the low-voltage via is moved inward by 230μm.

[0104] Optionally, the noise reduction module includes a first transistor;

[0105] The first transistor is used to reset the potential of the first node under the control of the potential of the second node;

[0106] The first electrode of the first transistor is electrically connected to the first node through a first via.

[0107] Figure 4 yes Figure 3 A layout diagram of at least one embodiment of a driving circuit shown in FIG. Figure 5 yes Figure 4 The layout diagram of the gate metal layer in Figure 6 yes Figure 4 Layout diagram of source and drain metal layers in Figure 7 yes Figure 4 Layout diagram of the ITO layer in Figure 8 yes Figure 4 Layout diagram of the semiconductor layers in .

[0108] In at least one embodiment of the present invention, the gate metal layer, the semiconductor layer, the source-drain metal layer and the ITO layer may be arranged in sequence along a direction away from the substrate, but the present invention is not limited thereto.

[0109] exist Fig. 9 In the figure, the area labeled A0 is the display area. Fig. 9 As shown, the display area A0 is arranged on the right side of the driving circuit.

[0110] Fig.10 is a layout diagram of at least one embodiment of a two-stage driving circuit.

[0111] In at least one embodiment of the present invention, the gate of the first transistor is electrically connected to the second node, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the low voltage line;

[0112] like Figure 4-Figure 9 As shown, the first electrode S1 of the first transistor M1 is electrically connected to the first node through the first via H1, and the first node is electrically connected to the first electrode plate C1a of the storage capacitor C1.

[0113] like Figure 4-Figure 9 As shown, the first via hole H1 includes a first connection portion H11 formed in the gate metal layer, a second connection portion H12 formed in the source-drain metal layer, and a third connection portion H13 formed in the ITO layer; optionally, the ITO layer can be in the same layer and material as the pixel electrode layer of the display area or in the same layer and material as the common electrode of the display area; through the first via hole H1, the third connection portion H13 formed in the ITO layer is used to realize electrical connection between the connection pattern formed in the gate metal layer and the connection pattern formed in the source-drain metal layer.

[0114] In at least one embodiment of the present invention, the driving circuit further includes a second transistor;

[0115] The second transistor is used for resetting the potential of the first node under the control of a frame reset signal provided by a frame reset line;

[0116] The first electrode of the second transistor is electrically connected to the first node through the first via.

[0117] In a specific implementation, the driving circuit may further include a second transistor, and a first electrode of the second transistor is electrically connected to the first node through a first via hole.

[0118] like Figure 4-Figure 9 As shown, the first electrode S2 of the second transistor is electrically connected to the first node point through the first via hole H1, and the first node is electrically connected to the first electrode plate of the storage capacitor C1.

[0119] like Figure 4-Figure 9 As shown, the first electrode S1 of the first transistor is electrically connected to the first electrode S2 of the second transistor, the first transistor M1 and the second transistor M2 are arranged adjacent to each other, the first electrode S1 of the first transistor M1 and the first electrode S2 of the second transistor M2 are electrically connected to the first node through the same via hole, compared with the related art, one via hole is reduced, and the overall width of the driving circuit is reduced by about 30μm.

[0120] In at least one embodiment of the present invention, the first via hole is disposed on a side of the first transistor close to the display area.

[0121] like Figure 4 and Fig. 9 As shown, the first via hole H1 is disposed on a side of the first transistor M1 close to the display area A0 , the display area A0 is disposed on the right side of the driving circuit, and the edge of the sealing glue is disposed on the left side of the driving circuit.

[0122] Optionally, the driving circuit further includes a third transistor and a fourth transistor;

[0123] The third transistor is used to write the second voltage signal provided by the second voltage line into the second node under the control of the potential of the pull-down control node;

[0124] The fourth transistor is used for resetting the potential of the second node under the control of the potential of the first node;

[0125] The second electrode of the third transistor and the first electrode of the fourth transistor are both electrically connected to the second node through the second via.

[0126] like Figure 4-Figure 9 As shown, the second electrode D3 of the third transistor M3 is electrically connected to the second node through the second via hole H2, and the first electrode S4 of the fourth transistor M4 is electrically connected to the second node through the second via hole H2.

[0127] like Figure 4-Figure 9 As shown, the second via hole H2 includes a fourth connection portion H21 formed in the gate metal layer, a fifth connection portion H22 formed in the source-drain metal layer, and a sixth connection portion H23 formed in the ITO layer; through the second via hole H2, the sixth connection portion H23 formed in the ITO layer is used to realize electrical connection between the connection pattern formed in the gate metal layer and the connection pattern formed in the source-drain metal layer.

[0128] like Figure 4-Figure 9 As shown, the second via hole H2 is the outermost via hole, and the outermost via hole is shifted inward by 32 μm.

[0129] In at least one embodiment of the present invention, the second via hole is disposed on a side of the fourth transistor away from the display area.

[0130] exist Figure 4-Figure 9 In the figure, the line labeled CLK1 is the first clock signal line, the line labeled CLK2 is the second clock signal line, the line labeled CLK3 is the third clock signal line, and the line labeled CLK4 is the fourth clock signal line. It should be noted that the number of specific clock signal lines is not limited;

[0131] The second via H2 is disposed between each clock signal line and the fourth transistor M4.

[0132] like Figure 4 and Fig. 9As shown, the second via hole H2 is disposed on a side of the fourth transistor M4 away from the display area A0.

[0133] like Figure 4 As shown, three transistors are spaced between the second via hole H2 and the first via hole H1.

[0134] Optionally, the driving circuit includes a first transistor;

[0135] The fourth transistor is disposed on a side of the first transistor away from the display area.

[0136] like Figure 4-Figure 9 As shown, the driving circuit includes a first transistor M1;

[0137] The fourth transistor M4 is arranged on the side of the first transistor M1 away from the display area A0. In the present case, the extension direction of the source and drain of the fourth transistor M4 is different from that of the source and drain of the first transistor M1. Optionally, the extension directions of the two are intersecting. Optionally, the extension directions of the two are perpendicular. The extension direction of the source and drain of the fourth transistor M4 is the row direction, and the extension direction of the source and drain of the first transistor M1 is the column direction. The purpose of such arrangement is to further realize the utilization of the non-display area and further reduce the narrow frame by reasonably placing the transistors. Optionally, the GOA circuit may include multiple transistors with different extension directions. Figure 4 For example, the transistors whose source and drain extend in the row direction include M0, M7, M8, M3, and M4, and the source and drain of other transistors extend in the column direction.

[0138] In at least one embodiment of the present invention, the output module includes a driving transistor; the driving transistor is used to provide a driving signal through an output terminal under the control of the potential of the first node; the array substrate also includes a first voltage line;

[0139] An orthographic projection of the gate of the driving transistor on the substrate and an orthographic projection of the second via hole on the substrate are arranged along a first direction;

[0140] The first direction is substantially the same as an extending direction of the first voltage line.

[0141] Optionally, the first voltage line may be a low voltage line, and the first direction may be a vertical direction.

[0142] like Figure 4-Figure 9 As shown, the output module includes a driving transistor M0; the array substrate also includes a low voltage line VGL;

[0143] The orthographic projection of the gate G0 of the driving transistor M0 on the substrate and the orthographic projection of the second via H2 on the substrate are arranged in a vertical direction. The second via H2 can be set in the space under the gate of the driving transistor M0 to achieve a narrow frame.

[0144] Optionally, the driving transistor and the third transistor are arranged along a first direction;

[0145] The driving transistor and the fourth transistor are arranged along a first direction;

[0146] like Figure 4-Figure 9 As shown, the driving transistor M0 and the third transistor M3 are arranged in a vertical direction, and the driving transistor M0 and the fourth transistor M4 are arranged in a vertical direction;

[0147] In at least one embodiment of the present invention, M3 and M4 are disposed below M0 to facilitate the realization of a narrow frame.

[0148] In at least one embodiment of the present invention, the driving circuit further includes a storage capacitor and a fifth transistor;

[0149] The fifth transistor is used to control the output terminal to be connected to the first voltage line under the control of the frame reset signal provided by the frame reset line; the fifth transistor is electrically connected to the first voltage line through the third via hole;

[0150] A notch is provided on one side of the storage capacitor close to the first voltage line, and an orthographic projection of the gate of the fifth transistor on the substrate at least partially overlaps with an orthographic projection of the notch on the substrate.

[0151] like Figure 4-Figure 10 As shown, the driving circuit further includes a storage capacitor C1 and a fifth transistor M5;

[0152] The fifth transistor M5 is electrically connected to the low voltage line VGL through the third via hole H3;

[0153] A notch is provided on one side of the storage capacitor C1 close to the low voltage line VGL;

[0154] The orthographic projection of the gate G5 of the fifth transistor M5 on the substrate at least partially overlaps with the orthographic projection of the recess on the substrate, so as to set the fifth transistor M5 in the recess of the storage capacitor C1, and set the fifth transistor M5 between the storage capacitor C1 and the low voltage line VGL, which is beneficial for the fifth transistor M5 to pass through the third via H3 and the low voltage line VGL.

[0155] like Figure 4-Figure 10As shown, the third via hole H3 includes a seventh connection portion H31 formed in the gate metal layer, an eighth connection portion H32 formed in the source-drain metal layer, and a ninth connection portion H33 formed in the ITO layer; through the third via hole H3, the ninth connection portion H33 formed in the ITO layer is used to realize electrical connection between the connection pattern formed in the gate metal layer and the connection pattern formed in the source-drain metal layer.

[0156] In at least one embodiment of the present invention, the driving module includes an N-level driving circuit, the first voltage line includes N first voltage line portions, and the n-th level driving circuit corresponds to the n-th first voltage line portion; N is an integer greater than 1, and n is a positive integer less than or equal to N;

[0157] The n-th stage driving circuit includes a fifth transistor electrically connected to the (n-1)th first voltage line portion.

[0158] exist Fig.10 Among them, the one labeled GAn-1 is the n-1th level driving circuit, and the one labeled GAn is the nth level driving circuit;

[0159] The n-1th low voltage line portion is labeled VGLn-1, and the n-1th low voltage line portion VGLn-1 corresponds to the low voltage line portion of the n-1th level driving circuit GAn-1. The n-th low voltage line portion is labeled VGLn, and the n-th low voltage line portion VGLn corresponds to the low voltage line portion of the n-1th level driving circuit GAn.

[0160] The fifth transistor M5 included in the n-th stage driving circuit is electrically connected to the (n-1)th low voltage line portion VGLn through the third via hole H3.

[0161] Optionally, the storage capacitor is adjacent to the first voltage line, and the fifth transistor is adjacent to the first voltage line.

[0162] like Figure 4-Figure 9 As shown, the storage capacitor C1 is adjacent to the low voltage line VGL, and the fifth transistor M5 is adjacent to the low voltage line VGL, so as to facilitate the electrical connection between M5 and VGL. Such a wiring design can further reduce the frame.

[0163] In at least one embodiment of the present invention, the input module includes a sixth transistor; a gate of the sixth transistor is electrically connected to the input signal terminal, a first electrode of the sixth transistor is electrically connected to the first input signal terminal, and a second electrode of the sixth transistor is electrically connected to the first node;

[0164] The first voltage line is disposed between the storage capacitor and the sixth transistor.

[0165] like Figure 4-Figure 9 As shown, the input module includes a sixth transistor M6;

[0166] The low voltage line VGL is disposed between the storage capacitor C1 and the sixth transistor M6 .

[0167] Optionally, the output module includes a driving transistor;

[0168] The driving transistor is used to provide a driving signal through an output terminal under the control of the potential of the first node;

[0169] The storage capacitor is arranged on a side of the driving transistor close to the display area.

[0170] like Figure 4-Figure 9 As shown, the output module includes a driving transistor M0;

[0171] The storage capacitor C1 is disposed on a side of the driving transistor M0 close to the display area A0;

[0172] The storage capacitor C1 and the driving transistor M0 may be arranged in a horizontal direction.

[0173] In at least one embodiment of the present invention, the array substrate further includes a first voltage line; the storage capacitor includes a first electrode plate and a second electrode plate;

[0174] The orthographic projection of the first electrode plate of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the storage capacitor on the substrate;

[0175] The orthographic projection of the first electrode plate of the storage capacitor on the substrate and the orthographic projection of the first via hole on the substrate are arranged along a first direction;

[0176] The first direction is substantially the same as an extending direction of the first voltage line.

[0177] like Figure 4-Figure 9 As shown, the array substrate further includes a low voltage line VGL; the storage capacitor C1 includes a first plate C1a and a second plate C1b;

[0178] The orthographic projection of the first electrode plate C1a of the storage capacitor C1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C1b of the storage capacitor C1 on the substrate;

[0179] The orthographic projection of the first electrode plate C1a of the storage capacitor C1 on the substrate and the orthographic projection of the first via hole H1 on the substrate are arranged in a vertical direction, so that the first via hole H1 is provided through the space below the storage capacitor C1, which is conducive to achieving a narrow frame.

[0180] Optionally, the driving circuit includes a first transistor and a second transistor;

[0181] The storage capacitor and the first transistor are arranged along a first direction;

[0182] The storage capacitor and the second transistor are arranged along a first direction.

[0183] like Figure 4-Figure 9 As shown, the storage capacitor C1 and the first transistor M1 are arranged in the vertical direction, and the storage capacitor C1 and the second transistor M2 are arranged in the vertical direction, so that the first transistor M1 and the second transistor M2 can be arranged in the space below the storage capacitor C1, which is conducive to achieving a narrow frame.

[0184] exist Figure 8 , labeled A0 is the active graphic of M0, labeled A1 is the active graphic of M1, labeled A2 is the active graphic of M2, labeled A3 is the active graphic of M3, labeled A4 is the active graphic of M4, labeled A5 is the active graphic of M5, labeled A6 is the active graphic of M6, labeled A7 is the active graphic of M7, labeled A8 is the active graphic of M8, labeled A9 is the active graphic of M9, and labeled A10 is the active graphic of M10.

[0185] exist Figure 4 and Figure 5 middle,

[0186] The line labeled GCH is a high voltage line, the line labeled VDS is a first control voltage line, and the line labeled VSD is a second control voltage line; the line labeled CLK1 is a first clock signal line, the line labeled CLK2 is a second clock signal line, the line labeled CLK3 is a third clock signal line, and the line labeled CLK4 is a fourth clock signal line;

[0187] The line labeled STV0 is a frame reset line, the line labeled VGL is a low voltage line, the line labeled VCOM1 is a first common electrode voltage line, the line labeled VCOM2 is a second common electrode voltage line, the line labeled GND is a ground line, the line labeled STV1 is a first starting voltage line, and the line labeled STV2 is a second starting voltage line.

[0188] The display device described in the embodiment of the present invention includes the above-mentioned array substrate.

[0189] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that: A device comprising a substrate and a driving module disposed on the substrate, wherein the driving module comprises a multi-stage driving circuit; the driving circuit comprises an input module, an output module and a noise reduction module, wherein the input module is electrically connected to a first node and is used to transmit a first input signal to the first node under the control of an input signal provided by an input signal terminal, the output module is used to transmit a second input signal to an output terminal of the driving circuit under the control of a potential of the first node, and the noise reduction module is used to transmit a first voltage signal transmitted by a first voltage line to the first node and / or the output terminal under the control of a potential of a second node; The driving circuit includes a plurality of transistors; At least one transistor among the plurality of transistors is electrically connected to the first node through a first via, and at least one transistor among the plurality of transistors is electrically connected to the second node through a second via; At least one transistor is spaced between the first via hole and the second via hole.

2. The array substrate according to claim 1, characterized in that: The distance between the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate is greater than or equal to a first distance threshold; The first distance threshold is greater than or equal to 100 μm.

3. The array substrate according to claim 1, characterized in that: The first voltage line is arranged on a side of a part of transistors included in the driving circuit close to the display area; At least one transistor among the plurality of transistors is electrically connected to the first voltage line through a third via.

4. The array substrate according to claim 1, wherein: The noise reduction module includes a first transistor; The first transistor is used to reset the potential of the first node under the control of the potential of the second node; The first electrode of the first transistor is electrically connected to the first node through a first via.

5. The array substrate according to claim 4, characterized in that: The driving circuit further includes a second transistor; The second transistor is used for resetting the potential of the first node under the control of a frame reset signal provided by a frame reset line; The first electrode of the second transistor is electrically connected to the first node through the first via.

6. The array substrate according to claim 4, characterized in that: The first via hole is disposed on a side of the first transistor close to the display area.

7. The array substrate according to any one of claims 1 to 6, characterized in that: The driving circuit further includes a third transistor and a fourth transistor; The third transistor is used to write the second voltage signal provided by the second voltage line into the second node under the control of the potential of the pull-down control node; The fourth transistor is used for resetting the potential of the second node under the control of the potential of the first node; The second electrode of the third transistor and the first electrode of the fourth transistor are both electrically connected to the second node through the second via.

8. The array substrate according to claim 7, characterized in that: The second via hole is disposed on a side of the fourth transistor away from the display area.

9. The array substrate according to claim 8, characterized in that: The driving circuit includes a first transistor; The fourth transistor is disposed on a side of the first transistor away from the display area.

10. The array substrate according to claim 7, wherein: The output module includes a driving transistor, and the driving transistor is used to provide a driving signal through an output terminal under the control of the potential of the first node; the array substrate also includes a first voltage line; An orthographic projection of the gate of the driving transistor on the substrate and an orthographic projection of the second via hole on the substrate are arranged along a first direction; The first direction is substantially the same as an extending direction of the first voltage line.

11. The array substrate according to claim 10, characterized in that: The driving transistor and the third transistor are arranged along a first direction; The driving transistor and the fourth transistor are arranged along a first direction.

12. The array substrate according to claim 3, characterized in that: The driving circuit also includes a storage capacitor and a fifth transistor; The fifth transistor is used to control the output terminal to be connected to the first voltage line under the control of the frame reset signal provided by the frame reset line; the fifth transistor is electrically connected to the first voltage line through the third via hole; A notch is provided on one side of the storage capacitor close to the first voltage line, and an orthographic projection of the gate of the fifth transistor on the substrate at least partially overlaps with an orthographic projection of the notch on the substrate.

13. The array substrate according to claim 12, wherein: The driving module includes an N-level driving circuit, the first voltage line includes N first voltage line parts, and the n-th level driving circuit corresponds to the n-th first voltage line part; N is an integer greater than 1, and n is a positive integer less than or equal to N; The n-th stage driving circuit includes a fifth transistor electrically connected to the (n-1)th first voltage line portion.

14. The array substrate according to claim 12, wherein: The storage capacitor is adjacent to the first voltage line, and the fifth transistor is adjacent to the first voltage line.

15. The array substrate according to claim 12, wherein: The input module includes a sixth transistor; a gate of the sixth transistor is electrically connected to the input signal terminal, a first electrode of the sixth transistor is electrically connected to the first input signal terminal, and a second electrode of the sixth transistor is electrically connected to the first node; The first voltage line is disposed between the storage capacitor and the sixth transistor.

16. The array substrate according to claim 12, wherein: The output module includes a driving transistor; The driving transistor is used to provide a driving signal through an output terminal under the control of the potential of the first node; The storage capacitor is arranged on a side of the driving transistor close to the display area.

17. The array substrate according to claim 16, wherein: The array substrate further comprises a first voltage line; the storage capacitor comprises a first electrode plate and a second electrode plate; The orthographic projection of the first electrode plate of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the storage capacitor on the substrate; The orthographic projection of the first electrode plate of the storage capacitor on the substrate and the orthographic projection of the first via hole on the substrate are arranged along a first direction; The first direction is substantially the same as an extending direction of the first voltage line.

18. The array substrate according to claim 17, wherein: The driving circuit includes a first transistor and a second transistor; The storage capacitor and the first transistor are arranged along a first direction; The storage capacitor and the second transistor are arranged along a first direction.

19. A display device, characterized in that: The invention comprises an array substrate as claimed in any one of claims 1 to 18.

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