Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel, and relates to the technical field of display, the array substrate comprises a substrate, a plurality of sub-pixels, a first metal wire and a second metal wire; the sub-pixels are arranged on the surface of the substrate at intervals, a non-display area is arranged between every two adjacent sub-pixels, each sub-pixel comprises a main area and a secondary area, the main area comprises a first pixel electrode, and the secondary area comprises a second pixel electrode; the first metal wire is electrically connected with the first pixel electrode and the second pixel electrode and is used for providing a first voltage signal for the first pixel electrode and the second pixel electrode; the second metal wire is electrically connected with the first pixel electrode or the second pixel electrode and is used for providing a second voltage signal for the first pixel electrode or the second pixel electrode; wherein the first metal wire and the second metal wire are both located in the non-display area. The problem that the reflectivity of the display panel is high due to the fact that an existing metal wire is arranged in a display area is solved, and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] With the development of liquid crystal display technology and the improvement of users' requirements for the display effect of liquid crystal display panels, more and more users require that the display panels can also provide a better visual experience in strong light environments. Therefore, it is necessary to reduce the reflection of the display panel in strong light environments to make it have higher contrast and brightness.

[0003] In order to improve the display quality of the display panel, the existing display panel changes the traditional 4-domain design to an 8-domain design. In the traditional 4-domain design, each sub-pixel of the display panel is divided into a main / sub (primary / secondary) area, and the main area and the sub area each contain two sub-pixel electrodes, each of which can be used to control the arrangement direction of the liquid crystal molecules separately. The 8-domain design is based on the 4-domain design, and the pixel electrodes of the main area and the sub area are divided into 4 sub-pixel electrodes respectively, that is, each sub-pixel has 8 domains.

[0004] By setting a gate line and a plurality of thin film transistors between the main area and the sub area, and electrically connecting the thin film transistors to the data lines set on one side of the main area and the sub area, the data lines provide the sub-pixel electrodes of the main area and the sub area with a first operating voltage of the same voltage value. At the same time, metal wiring is set in the main area and the sub area, and the metal wiring is electrically connected to the sub-pixel electrodes of the sub area through the thin film transistors, and provides the sub-pixel electrodes of the sub area with a second operating voltage. Therefore, the voltage values ​​of the sub-pixel electrodes of the main area and the sub area can be different, and then the independent display control of the 8 domains of each sub-pixel is realized, thereby reducing the brightness and contrast changes caused by the change of the viewing angle, and improving the display effect.

[0005] However, since the main area and the sub area are provided with metal wiring, the material of the metal wiring is generally Al, Ti, Mo or Cu and other metals, which have a high reflectivity, resulting in a corresponding increase in the reflectivity of the panel, affecting the display effect of the display panel. Summary of the invention

[0006] The main purpose of the present invention is to provide an array substrate and a display panel, aiming to solve the problem of high reflectivity of the existing display panel.

[0007] To achieve the above-mentioned purpose, the present invention proposes an array substrate, which includes a substrate, a plurality of sub-pixels, a first metal routing and a second metal routing; the plurality of sub-pixels are arranged at intervals on the surface of the substrate, and a non-display area is between two adjacent sub-pixels, each of the sub-pixels includes a main area and a secondary area, the main area includes a first pixel electrode, and the secondary area includes a second pixel electrode; the first metal routing is electrically connected to both the first pixel electrode and the second pixel electrode, and is used to provide a first voltage signal to the first pixel electrode and the second pixel electrode; the second metal routing is electrically connected to the first pixel electrode or the second pixel electrode, and is used to provide a second voltage signal to the first pixel electrode or the second pixel electrode; wherein the first metal routing and the second metal routing are both located in the non-display area.

[0008] In an embodiment of the present invention, each of the non-display areas is provided with the first metal wiring and the second metal wiring, and the first metal wiring and the second metal wiring in each of the non-display areas are electrically connected to two adjacent sub-pixels respectively.

[0009] In one embodiment of the present invention, each of the non-display areas is provided with two of the first metal wirings or two of the second metal wirings, and the first metal wirings and the second metal wirings electrically connected to each of the sub-pixels are respectively located in two adjacent non-display areas.

[0010] In an embodiment of the present invention, the main area and the secondary area are both arranged at intervals along a first direction, and the extension direction of the first metal wiring and the second metal wiring is parallel to the first direction.

[0011] In one embodiment of the present invention, the first metal wiring and the second metal wiring are respectively disposed close to two sub-pixels adjacent to the non-display area.

[0012] In one embodiment of the present invention, the array substrate also includes a plurality of common electrodes, each of the main areas and each of the sub-areas is provided with a common electrode, the common electrode of each of the main areas and the first pixel electrode form a first storage capacitor, the common electrode of each of the sub-areas and the second pixel electrode form a second storage capacitor, and the first storage capacitor and the second storage capacitor are respectively used to stabilize the voltages of the first pixel electrode and the second pixel electrode.

[0013] In an embodiment of the present invention, the common electrode is in the shape of a closed rectangular frame.

[0014] In an embodiment of the present invention, the common electrode includes a first segment, a second segment and a third segment connected in sequence, and the first segment, the second segment and the third segment are surrounded to form a rectangular frame with an opening.

[0015] In one embodiment of the present invention, the sub-pixel includes a first metal layer, a second metal layer, a color resist layer and an electrode layer sequentially stacked on the surface of the substrate;

[0016] The first metal layer is disposed on the surface of the substrate, the first metal layer includes the common electrode, the second metal layer includes the first metal wiring and the second metal wiring, and the electrode layer includes the first pixel electrode and the second pixel electrode;

[0017] Among them, a first via hole and a second via hole penetrating the electrode layer and the color resist layer are opened on the side of each non-display area facing away from the substrate, the inner walls of the first via hole and the second via hole are plated with a conductive layer, the first metal routing is electrically connected to the first pixel electrode through the conductive layer, and the second metal routing is electrically connected to the second pixel electrode through the conductive layer.

[0018] The present invention further provides a display panel, comprising a color filter substrate, a liquid crystal layer and any one of the above array substrates; the liquid crystal layer is sandwiched between the color filter substrate and the array substrate.

[0019] The array substrate proposed by the present invention includes a substrate, a plurality of sub-pixels, a first metal wiring and a second metal wiring. The plurality of sub-pixels are arranged on the surface of the substrate at intervals in a direction parallel to the substrate, and the area between two adjacent sub-pixels is a non-display area. Each sub-pixel includes a main area and a secondary area, the main area includes a first pixel electrode, the secondary area includes a second pixel electrode, and the first pixel electrode and the second pixel electrode are respectively used to cooperate with the color film electrode to form an electric field to adjust the arrangement of the liquid crystal molecule layer. The first metal wiring is electrically connected to the first pixel electrode and the second pixel electrode, and provides a first voltage signal to the first pixel electrode and the second pixel electrode. The second metal wiring is electrically connected to the first pixel electrode or the second pixel electrode, and provides a second voltage signal to the first pixel electrode or the second pixel electrode. Therefore, the voltage of the first pixel electrode in the main area can be different from the voltage of the second sub-pixel in the secondary area, thereby realizing independent display control of the main area and the secondary area.

[0020] The first metal routing and the second metal routing are both arranged in the non-display area. Since a black matrix is ​​arranged in the non-display area of ​​the display panel, that is, the first metal routing and the second metal routing are arranged in the positive projection area of ​​the black matrix on the substrate, the black matrix can absorb light, thereby solving the problem of high reflectivity of the display panel caused by the existing metal routing being arranged in the display area, thereby improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0022] Figure 1 A schematic structural diagram of an embodiment of an array substrate provided by the present invention;

[0023] Figure 2 A schematic structural diagram of another embodiment of an array substrate provided by the present invention;

[0024] Figure 3 A schematic structural diagram of another embodiment of an array substrate provided by the present invention;

[0025] Figure 4 for Figure 3 A cross-sectional view at AA;

[0026] Figure 5 for Figure 3 A cross-sectional view at BB;

[0027] Figure 6 This is a schematic structural diagram of another embodiment of the array substrate provided by the present invention.

[0028] Description of Figure Numbers:

[0029] 10. Substrate; 20. Sub-pixel; 21. Main area; 22. Sub-area; 23. Non-display area; 201. First pixel electrode; 202. Second pixel electrode; 210. First metal layer; 220. Second metal layer; 230. Insulating layer; 240. Color resist layer; 250. Electrode layer; 260. Conductive layer; 270. First via hole; 280. Second via hole; 30. First metal wiring; 40. Second metal wiring; 50. Common electrode; 60. Liquid crystal layer; 70. Transparent conductive film layer; 80. Glass substrate.

[0030] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0033] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of the features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or solutions that satisfy both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0034] The invention provides an array substrate.

[0035] Combination Figures 1 to 6 As shown, in one embodiment of the present invention, the array substrate includes a substrate 10, a plurality of sub-pixels 20, a first metal wiring 30 and a second metal wiring 40; the plurality of sub-pixels 20 are arranged at intervals on the surface of the substrate 10, and a non-display area 23 is between two adjacent sub-pixels 20, each sub-pixel 20 includes a main area 21 and a secondary area 22, the main area 21 includes a first pixel electrode 201, and the secondary area 22 includes a second pixel electrode 202; the first metal wiring 30 is electrically connected to both the first pixel electrode 201 and the second pixel electrode 202, and is used to provide a first voltage signal to the first pixel electrode 201 and the second pixel electrode 202; the second metal wiring 40 is electrically connected to the first pixel electrode 201 or the second pixel electrode 202, and is used to provide a second voltage signal to the first pixel electrode 201 or the second pixel electrode 202; wherein the first metal wiring 30 and the second metal wiring 40 are both located in the non-display area 23.

[0036] In this embodiment, the substrate 10 may be a glass substrate 10 or other transparent substrate 10 materials, such as a plastic substrate. Glass has good transparency and mechanical strength, and is suitable for TFT-LCD display panels. Plastic substrates are light and flexible, and are suitable for flexible display panels.

[0037] A plurality of sub-pixels 20 are arranged in a direction parallel to the substrate 10 and are spaced in an array on the surface of the substrate 10. The plurality of sub-pixels 20 constitute the display area of ​​the display panel. The size of each sub-pixel 20 can be adjusted according to the resolution and pixel density of the display panel. The width of the non-display area 23 between two adjacent sub-pixels 20 can be adjusted according to actual needs, usually between 10-20 microns. The display panel is also provided with a light shielding layer (ie, a black matrix) in the non-display area 23 to prevent the light of the two adjacent sub-pixels 20 from interfering with each other, thereby improving the contrast of the display panel. At the same time, other auxiliary film layers, such as an insulating layer 230, a protective layer, etc., are also provided in the non-display area 23 to enhance the stability and reliability of the structure.

[0038] Each sub-pixel 20 is divided into a main area 21 and a sub-area 22, and the main area 21 and the sub-area 22 respectively include a first pixel electrode 201 and a second pixel electrode 202. The first pixel electrode 201 and the second pixel electrode 202 are made of ITO (indium tin oxide) and have good conductivity and transparency. The main area 21 and the sub-area 22 can be respectively provided with a plurality of pixel electrodes. For example, in one embodiment, the main area 21 includes four first pixel electrodes 201, and the sub-area 22 includes four second pixel electrodes 202, that is, each sub-pixel 20 has eight domains. Each pixel electrode is composed of a plurality of electrode lines arranged at intervals, and the extension directions of the electrode lines in the four pixel electrodes of the main area 21 and the sub-area 22 are set to be different. For example, the electrode lines of the four first pixel electrodes 201 of the main area 21 can be extended in the horizontal direction, the vertical direction, the left oblique direction and the right oblique direction, respectively, and the electrode lines of the four second pixel electrodes 202 of the sub-area 22 can also be extended in these four directions respectively, but the directions can be different to achieve different electric field distributions. Each pixel electrode cooperates with the color film electrode to adjust the arrangement of liquid crystal molecules. Through the above arrangement, the first pixel electrode 201 and the second pixel electrode 202 can adjust the display effect separately.

[0039] Gate lines, thin film transistors, etc. are arranged between the main area 21 and the sub-area 22. Specifically, a main area 21 thin film transistor, a sub-area 22 thin film transistor, and a third thin film transistor are arranged between each main area 21 and the sub-area 22, wherein the source of the thin film transistor in the main area 21 is electrically connected to the first metal wiring 30, the drain of the thin film transistor in the main area 21 is electrically connected to the first pixel electrode 201, and the gate of the thin film transistor in the main area 21 is electrically connected to the gate line. Driven by the signal of the gate line, the thin film transistor in the main area 21 is turned on, and the first voltage signal of the first metal wiring 30 is transmitted to the first pixel electrode 201, so that the first pixel electrode 201 has a first voltage. The source of the thin film transistor in the sub-area 22 is electrically connected to the first metal wiring 30, the drain of the thin film transistor in the sub-area 22 is electrically connected to the second pixel electrode 202, and the gate of the thin film transistor in the sub-area 22 is electrically connected to the gate line. Driven by the signal of the gate line, the thin film transistor of the sub-region 22 is turned on, and the first voltage signal of the first metal wiring 30 is transmitted to the second pixel electrode 202, so that the second pixel electrode 202 has the first voltage. The source of the third thin film transistor is electrically connected to the second metal wiring 40, the drain of the third thin film transistor is electrically connected to the second pixel electrode 202, and the gate of the third thin film transistor is electrically connected to the gate line. Driven by the signal of the gate line, the third thin film transistor is turned on, and the second voltage signal of the second metal wiring 40 is transmitted to the second pixel electrode 202, so that the second pixel electrode 202 has the second voltage. Therefore, the voltage value of the first pixel electrode 201 depends on the first voltage, and the voltage of the second pixel electrode 202 depends on the sum of the first voltage and the second voltage. Therefore, by changing the value of the second voltage, the rotation angle of the liquid crystal molecules corresponding to the first pixel electrode 201 relative to the liquid crystal molecules corresponding to the second pixel electrode 202 can be adjusted.

[0040] Therefore, the function of the first metal wiring 30 (also known as the data line) is to provide a first voltage signal to the first pixel electrode 201 and the second pixel electrode 202 to ensure the normal operation of each sub-pixel 20. The function of the second metal wiring 40 (also known as the share bar line) is to achieve different voltages in the main area 21 and the secondary area 22, thereby achieving different voltages for multiple pixel electrodes in the main area 21 and the secondary area 22, and then controlling the different arrangements of liquid crystal molecules. In this way, independent display control of the eight domains of each sub-pixel 20 can be achieved, reducing the brightness and contrast changes caused by changes in viewing angles, and improving the display effect.

[0041] The first metal wiring 30 and the second metal wiring 40 can be made of metals such as aluminum (Al), titanium (Ti), molybdenum (Mo) or copper (Cu), and have good electrical conductivity and mechanical strength. The width and thickness of the wiring can be adjusted according to actual needs, usually between 2-5 microns. The first metal wiring 30 and the second metal wiring 40 are arranged on the same layer to improve processing efficiency and reduce processing costs. The first metal wiring 30 and the second metal wiring 40 are connected to the first pixel electrode 201 and the second pixel electrode 202 through vias. The material of the via can be the same material as the metal wiring to ensure good electrical conductivity and reliability. An insulating layer 230 can be arranged between the first metal wiring 30 and the second metal wiring 40 to prevent short circuit. The material of the insulating layer 230 can be silicon dioxide (SiO2), silicon nitride (SiN), etc.

[0042] The first metal trace 30 and the second metal trace 40 are both arranged in the non-display area 23. Since the non-display area 23 of the display panel is provided with a light shielding layer, the light shielding layer can absorb light and has a low reflectivity to external light, the first metal trace 30 and the second metal trace 40 are arranged in the positive projection area of ​​the black matrix on the substrate 10, thereby solving the problem of the existing metal trace being arranged in the display area leading to a high reflectivity of the display panel and improving the display effect. At the same time, it also avoids the metal trace arranged in the display area from blocking the light emitted by the backlight source penetrating the display area, thereby also improving the aperture ratio of the display panel.

[0043] Combination Figure 3 As shown, in one embodiment of the present invention, each non-display area 23 is provided with a first metal wiring 30 and a second metal wiring 40, and the first metal wiring 30 and the second metal wiring 40 of each non-display area 23 are electrically connected to two adjacent sub-pixels 20 respectively.

[0044] In the present embodiment, since the first metal wiring 30 and the second metal wiring 40 are both arranged in the same metal layer, and the thin film transistors in the main area 21, the thin film transistors in the secondary area 22, and the third thin film transistors are all arranged between the main area 21 and the secondary area 22, the first metal wiring 30 and the second metal wiring 40 both need to extend the electrical connection line to between the main area 21 and the secondary area 22, so the first metal wiring 30 and the second metal wiring 40 of each non-display area 23 are respectively electrically connected to two adjacent sub-pixels 20, which can avoid the intersection of the first metal wiring 30 and the second metal wiring 40 to avoid the problem of short circuit. In addition, since the first metal wiring 30 and the second metal wiring 40 of each non-display area 23 are respectively connected to different sub-pixels 20, it is also convenient to respectively arrange the first metal wiring 30 and the second metal wiring 40 near the electrically connected sub-pixels 20 to increase the first metal wiring 30 and the second metal wiring 40, and further reduce the problem of short circuit.

[0045] Combination Figure 1 and Figure 2 As shown, in one embodiment of the present invention, each non-display area 23 is provided with two first metal wirings 30 or two second metal wirings 40, and the first metal wirings 30 and the second metal wirings 40 electrically connected to each sub-pixel 20 are respectively located in two adjacent non-display areas 23.

[0046] In this embodiment, two metal traces of the same type are arranged in each non-display area 23. Figure 1 and Figure 2 As shown, two first metal wirings 30 in a non-display area 23 are electrically connected to the second pixel electrodes 202 of the two sub-pixels 20 on the left and right sides, respectively, and two second metal wirings 40 in another adjacent non-display area 23 are electrically connected to the first pixel electrode 201 and the second pixel electrode 202 of the two sub-pixels 20 on the left and right sides, respectively, and multiple metal wirings in the non-display area 23 are arranged in sequence according to the arrangement method of the above-mentioned two non-display areas 23.

[0047] Combination Figures 1 to 3 As shown, in one embodiment of the present invention, the main area 21 and the secondary area 22 are both arranged in a first direction with intervals, and the extension direction of the first metal wiring 30 and the second metal wiring 40 is parallel to the first direction.

[0048] In this embodiment, the first direction is Figure 1 In the vertical direction of the structure shown, the first metal wiring 30 and the second metal wiring 40 are both arranged in the non-display area 23 parallel to the first direction, and the first metal wiring 30 and the second metal wiring 40 are both parallel to the first direction. This design is more convenient for the layout of the first metal wiring 30 and the second metal wiring 40 in the non-display area 23, simplifies the wiring design, reduces the complexity of the wiring and the signal interference between different metal wirings. In addition, since the thin film transistor and the gate line are arranged between the main area 21 and the secondary area 22, the first metal wiring 30 and the second metal wiring 40 are parallel to the first direction and arranged on one side of the sub-pixel 20, so as to facilitate the connection between the first metal wiring 30 and the second metal wiring 40 and each thin film transistor.

[0049] Combination Figures 1 to 3 As shown, in one embodiment of the present invention, the first metal wiring 30 and the second metal wiring 40 are respectively disposed close to two sub-pixels 20 adjacent to the non-display area 23 .

[0050] In this embodiment, the width of the non-display area 23 is generally about 15um, and the width of the first metal wiring 30 and the second metal wiring 40 is generally 2-5um. The first metal wiring 30 and the second metal wiring 40 are respectively arranged close to the two sub-pixels 20 adjacent to the non-display area 23, that is, the spacing between the two metal wirings in the non-display area 23 is set as large as possible, so as to deposit two metal wirings in the same non-display area 23 and avoid short circuit of the two metal wirings. At the same time, the signal interference between the two metal wirings can also be reduced, especially in high-resolution and high-refresh rate application scenarios, the integrity and stability of the signal can be better maintained. In addition, the first metal wiring 30 and the second metal wiring 40 are respectively arranged close to the two sub-pixels 20 adjacent to the non-display area 23, and the spacing between the metal wiring and the sub-pixel 20 can also be reduced, thereby reducing the path length of the signal transmission, reducing signal attenuation and noise interference, and improving the transmission efficiency and stability of the signal.

[0051] Combination Figures 1 to 3 As shown, in one embodiment of the present invention, the array substrate also includes a plurality of common electrodes 50, each main area 21 and each sub-area 22 is provided with a common electrode 50, the common electrode 50 of each main area 21 and the first pixel electrode 201 form a first storage capacitor, the common electrode 50 of each sub-area 22 and the second pixel electrode 202 form a second storage capacitor, and the first storage capacitor and the second storage capacitor are respectively used to stabilize the voltages of the first pixel electrode 201 and the second pixel electrode 202.

[0052] In this embodiment, in actual application of the display panel, due to factors such as voltage signal transmission delay and noise interference of the first metal wiring 30 and the second metal wiring 40, the voltage on the first pixel electrode 201 and the second pixel electrode 202 may fluctuate. At the same time, when the display panel is displaying, the pixel electrode is not always in an electrically conductive state, but according to the requirements of the screen display, multiple pixel electrodes are frequently turned on or off. The common electrode 50 arranged in the main area 21 and the secondary area 22 respectively forms a first storage capacitor and a second storage capacitor with the first pixel electrode 201 and the second pixel electrode 202. The main function of the first storage capacitor and the second storage capacitor is to keep the voltage of the first pixel electrode 201 and the second pixel electrode 202 stable.

[0053] Specifically, when the first metal wiring 30 provides the first voltage signal to the first pixel electrode 201 and the second pixel electrode 202, the first voltage signal will be stored in the corresponding first storage capacitor and the second storage capacitor at the same time. Even if the first metal wiring 30 stops providing the first voltage signal, the charges in the first storage capacitor and the second storage capacitor will continue to maintain the voltage on the first pixel electrode 201 and the second pixel electrode 202, thereby keeping the deflection state of the corresponding liquid crystal molecules unchanged, thereby improving the image display quality of the display panel. Especially in high-resolution and high-refresh rate applications, this optimized layout can better maintain display integrity and stability.

[0054] Furthermore, the common electrode 50 is electrically connected to the color film electrode so that the voltages of the two are the same, so that no electric field is formed between the common electrode 50 and the color film electrode, thereby avoiding affecting the angle of the liquid crystal molecules between the common electrode 50 and the color film electrode.

[0055] Combination Figure 1 As shown, in one embodiment of the present invention, the common electrode 50 is in the shape of a closed rectangular frame, and the positive projections of the common electrode 50 in the main area 21 and the secondary area 22 on the surface of the substrate 10 are respectively located at the outer edges of the first pixel electrode 201 and the second pixel electrode 202.

[0056] In this embodiment, the shape of the common electrode 50 is designed to be a closed rectangular frame. When multiple pixel electrodes are provided in the main area 21 and the secondary area 22, the common electrode 50 can form a first storage capacitor with the multiple pixel electrodes to keep the deflection state of the liquid crystal molecules between different pixel electrodes and the color film electrodes unchanged. At the same time, since the common electrode 50 is a metal material, the common electrodes 50 of the main area 21 and the secondary area 22 are respectively arranged at the outer edges of the first pixel electrode 201 and the second pixel electrode 202 to reduce the influence of the common electrode 50 on the reflectivity of the central display area of ​​the main area 21 and the secondary area 22.

[0057] Combination Figure 2 and Figure 3 As shown, in one embodiment of the present invention, the common electrode 50 includes a first segment, a second segment and a third segment connected in sequence, the first segment, the second segment and the third segment enclose a rectangular frame with an opening, and the positive projections of the common electrode 50 of the main area 21 and the secondary area 22 on the surface of the substrate 10 are respectively located at the periphery of the first pixel electrode 201 and the second pixel electrode 202.

[0058] In this embodiment, the common electrode 50 is designed as a rectangular frame with an opening to further reduce the area of ​​the common electrode 50, thereby further reducing the influence of the common electrode 50 on the reflectivity of the central display area of ​​the main area 21 and the sub-area 22. The opening of the common electrode 50 in the shape of a rectangular frame can be oriented toward another main area 21 or sub-area 22 of the same sub-pixel 20, or toward the non-display area 23 or toward another main area 21 or sub-area 22 away from the same sub-pixel 20. Figure 2 and Figure 3 As shown, in one embodiment, the opening of the rectangular frame of the common electrode 50 of the main area 21 is designed to face the side away from the secondary area 22, and the opening of the rectangular frame of the common electrode 50 of the secondary area 22 is designed to face the side away from the main area 21. This design can make the common electrode 50 as close as possible to the central area of ​​the same sub-pixel 20 to ensure that the common electrode 50 in the central area maintains the deflection state of the liquid crystal molecules.

[0059] Combination Figure 4 and Figure 5 As shown, in one embodiment of the present invention, the sub-pixel 20 includes a first metal layer 210, a second metal layer 220, a color resist layer 240 and an electrode layer 250 sequentially stacked on the surface of the substrate 10;

[0060] The first metal layer 210 is disposed on the surface of the substrate 10 , the first metal layer 210 includes a common electrode 50 , the second metal layer 220 includes a first metal wiring 30 and a second metal wiring 40 , and the electrode layer 250 includes a first pixel electrode 201 and a second pixel electrode 202 ;

[0061] Among them, a first via hole 270 and a second via hole 280 penetrating the electrode layer 250 and the color resist layer 240 are provided on the side of each non-display area 23 facing away from the substrate 10, and the first metal trace 30 and the second metal trace 40 are respectively exposed in the first via hole 270 and the second via hole 280, and the inner walls of the first via hole 270 and the second via hole 280 are plated with a conductive layer 260, the first metal trace 30 is electrically connected to the first pixel electrode 201 through the conductive layer 260, and the second metal trace 40 is electrically connected to the second pixel electrode 202 through the conductive layer 260.

[0062] In this embodiment, the array substrate is a multi-layer structure, wherein the first metal layer 210 is provided with a common electrode 50, a gate line, etc. The common electrode 50 and the gate line can be made of the same metal to improve the convenience of processing. The second metal layer 220 includes a first metal trace 30 and a second metal trace 40 arranged at intervals. Since the two are also in the same layer, the first metal trace 30 and the second metal trace 40 can also be made of the same metal to improve the convenience of processing. The color resist layer 240 is used to achieve color display, and the color resist layer 240 includes three colors of red, green and blue. The first pixel electrode 201 and the second pixel electrode 202 are arranged on the electrode layer 250 to control the deflection of the liquid crystal molecules.

[0063] An insulating layer 230 is provided between the first metal layer 210 and the second metal layer 220, between the second metal layer 220 and the color resist layer 240, between the color resist layer 240 and the electrode layer 250, and between the metal lines in the first metal layer 210 and the second metal layer 220. The insulating layer 230 is used to isolate the electrical connections between the layers to prevent short circuits and ensure stable signal transmission.

[0064] By setting the first via hole 270 and the second via hole 280 in the non-display area 23, and electroplating or depositing the conductive layer 260 in the first via hole 270 and the second via hole 280, the electrical connection between the first metal wiring 30 and the second metal wiring 40 and the pixel electrode is realized. The shape of the first via hole 270 and the second via hole 280 is an inverted trapezoid. During the etching process, the inverted trapezoid structure is easier to form, which reduces the problem of uneven etching and improves the production yield. At the same time, the inverted trapezoidal via design can increase the contact area between the hole wall of the via hole and the conductive layer 260, and reduce the inclination angle of the conductive layer 260, thereby improving the reliability of the conductive layer 260 attached to the hole wall of the via hole. The material of the conductive layer 260 can be the same material as the first metal wiring 30 and the second metal wiring 40, so as to improve the reliability of the connection between the conductive layer 260 and the first metal wiring 30 and the second metal wiring 40.

[0065] The present invention also proposes a display panel, which includes a color film substrate, a liquid crystal layer and an array substrate. The specific structure of the array substrate refers to the above-mentioned embodiment. Since the display panel adopts all the technical solutions of all the above-mentioned embodiments of the array substrate, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here one by one.

[0066] Among them, the liquid crystal layer 60 is sandwiched between the color filter substrate and the array substrate. The color filter substrate includes a glass substrate 80 and a transparent conductive film layer 70 arranged on the side of the glass substrate 80 facing the liquid crystal layer 60, and the liquid crystal layer 60 is sandwiched between the color filter substrate and the array substrate. The liquid crystal layer 60 is composed of liquid crystal molecules. The deflection of the liquid crystal molecules is controlled by the transparent conductive film side 70 and the electrode layer 250 under the action of the electric field, thereby adjusting the light passing through the liquid crystal layer 60 to realize the display of the image. Since the second metal wiring 40 in the array substrate is arranged in the non-display area 23 in the present application, and the shape of the common electrode 50 is optimized, the reflectivity of the display panel is reduced to improve the display effect of the display panel.

[0067] The above description is only an exemplary embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the technical concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate comprises: substrate; A plurality of sub-pixels, wherein the plurality of sub-pixels are arranged at intervals on the surface of the substrate, a non-display area is formed between two adjacent sub-pixels, each of the sub-pixels comprises a main area and a secondary area, the main area comprises a first pixel electrode, and the secondary area comprises a second pixel electrode; a first metal wiring, the first metal wiring being electrically connected to the first pixel electrode and the second pixel electrode and being used to provide a first voltage signal to the first pixel electrode and the second pixel electrode; and a second metal wiring, the second metal wiring being electrically connected to the first pixel electrode or the second pixel electrode and being used to provide a second voltage signal to the first pixel electrode or the second pixel electrode; Wherein, the first metal wiring and the second metal wiring are both located in the non-display area.

2. The array substrate according to claim 1, characterized in that: Each of the non-display areas is provided with the first metal wiring and the second metal wiring, and the first metal wiring and the second metal wiring in each of the non-display areas are electrically connected to two adjacent sub-pixels respectively.

3. The array substrate according to claim 1, characterized in that: Each of the non-display areas is provided with two of the first metal wirings or two of the second metal wirings, and the first metal wirings and the second metal wirings electrically connected to each of the sub-pixels are respectively located in two adjacent non-display areas.

4. The array substrate according to any one of claims 1 to 3, characterized in that: The main area and the secondary area are both arranged at intervals along a first direction, and the extension directions of the first metal wiring and the second metal wiring are parallel to the first direction.

5. The array substrate according to any one of claims 1 to 3, characterized in that: The first metal wiring and the second metal wiring are respectively arranged close to the two sub-pixels adjacent to the non-display area.

6. The array substrate according to any one of claims 1 to 3, characterized in that: The array substrate also includes a plurality of common electrodes, each of the main areas and each of the sub-areas is provided with a common electrode, the common electrode of each of the main areas and the first pixel electrode form a first storage capacitor, the common electrode of each of the sub-areas and the second pixel electrode form a second storage capacitor, and the first storage capacitor and the second storage capacitor are respectively used to stabilize the voltages of the first pixel electrode and the second pixel electrode.

7. The array substrate according to claim 6, characterized in that: The common electrode is in the shape of a closed rectangular frame.

8. The array substrate according to claim 6, wherein: The common electrode includes a first segment, a second segment and a third segment connected in sequence, and the first segment, the second segment and the third segment are surrounded to form a rectangular frame with an opening.

9. The array substrate according to claim 6, wherein: The sub-pixel comprises a first metal layer, a second metal layer, a color resist layer and an electrode layer sequentially stacked on the surface of the substrate; The first metal layer is disposed on the surface of the substrate, the first metal layer includes the common electrode, the second metal layer includes the first metal wiring and the second metal wiring, and the electrode layer includes the first pixel electrode and the second pixel electrode; Among them, a first via hole and a second via hole penetrating the electrode layer and the color resist layer are opened on the side of each non-display area facing away from the substrate, the inner walls of the first via hole and the second via hole are plated with a conductive layer, the first metal routing is electrically connected to the first pixel electrode through the conductive layer, and the second metal routing is electrically connected to the second pixel electrode through the conductive layer.

10. A display panel, characterized in that: The display panel comprises a color filter substrate, a liquid crystal layer and an array substrate according to any one of claims 1 to 9; the liquid crystal layer is sandwiched between the color filter substrate and the array substrate.

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