Memory controller, operating method thereof, and
By designing logical address feature mapping and preprocessing devices in the memory controller, the problems of large amount of host resource utilization and data movement in the prior art are solved, and efficient data processing and performance improvement are achieved.
Patent Information
- Application Number
- CN202411294053.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-27
- Filing Date
- 2024-09-14
- Publication Date
- 2025-04-29
AI Technical Summary
When existing computing systems process large amounts of data, the amount of host resource utilization and data movement is large, making it difficult to achieve efficient data processing.
A memory controller is designed to generate a logical address feature map by receiving system configuration setting information from an external device, and processing write data based on the mapping to reduce the computing load of the main system.
By preprocessing data in memory devices, the calculation load and power consumption of the main system are reduced, and the efficiency and performance of data processing are improved.
Smart Images
Figure CN119902700A_ABST
Abstract
Description
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS
[0002] This application claims priority to Korean Patent Application No. 10-2023-0145600, filed on October 27, 2023, which is incorporated herein by reference in its entirety. Technical Field
[0003] Various embodiments of the present disclosure generally relate to a computing apparatus, and more particularly, to a memory controller, a computing memory device, an operation method for processing input data, and a data processing system including the computing memory device. Background Art
[0004] As the interest and importance of artificial intelligence applications and big data analytics grows, so too does the need for computing systems that can efficiently process large amounts of data.
[0005] As the capacity of memory devices increases and computing speed improves, research into in-memory computing technology and near-memory data processing (NDP) technology that performs not only data storage but also data computing in or near the memory is underway.
[0006] In-memory computing technology has attracted much attention as a technology for processing artificial intelligence applications because it can reduce the use of host (i.e., main system) resources and reduce the amount of data movement by performing calculations inside the storage device and sending only the result data to the host. Therefore, various methods for processing data more accurately and at a higher speed are currently being studied. Summary of the invention
[0007] A memory controller according to an embodiment of the present disclosure may include: an external device interface, configured to receive system configuration setting information from a first external device; a logical address feature map storage circuit, configured to generate a logical address feature map by extracting logical address feature data from the system configuration setting information, the logical address feature data defining a calculation type for each logical address range specified by the first external device; a computing core, configured to process data requested to be written with a corresponding calculation type in response to a write request for a logical address included in the logical address feature map; and a memory interface, configured to send the processed requested write data to a second external device.
[0008] A memory controller according to an embodiment of the present disclosure may be configured to: receive a set feature command defining a calculation type for each logical address range from an external device, store the set feature command, process write data based on the calculation type of the logical address corresponding to the write data requested to be written by the external device, and store the processed write data in a non-volatile memory device.
[0009] A computing memory device according to an embodiment of the present disclosure may include: a memory controller configured to receive system configuration setting information defining a computing type for each logical address range from an external device, extract logical address characteristic data defining the computing type for each logical address range specified by the external device, and process write data based on the computing type of the logical address corresponding to the write data requested to be written by the external device; and a non-volatile memory device configured to store the processed write data.
[0010] An operating method of a memory controller according to an embodiment of the present disclosure is an operating method of a memory controller that communicates with a first external device, and may include: receiving system configuration setting information from the first external device; generating a logical address feature map by extracting logical address feature data from the system configuration setting information, the logical address feature data defining a calculation type for each logical address range specified by the first external device; in response to a write request for a logical address included in the logical address feature map, processing the data requested to be written with a corresponding calculation type; and sending the processed requested write data to a second external device.
[0011] A data processing system according to an embodiment of the present disclosure may include: an external device, configured to send system configuration setting information including logical address characteristic data, which defines a calculation type for each logical address range; and a computing memory device, configured to extract the logical address characteristic data from the system configuration setting information, and process and store the write data based on the calculation type of the logical address corresponding to the write data requested to be written by the external device.
[0012] By pre-processing the data to be processed within the memory device, the computational load of the host system can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 is a diagram showing a configuration of a data processing system according to an embodiment of the present disclosure;
[0014] Figure 2 is a diagram showing a detailed configuration of a memory controller according to an embodiment of the present disclosure;
[0015] Figure 3is a diagram showing a detailed configuration of a preprocessing device according to an embodiment of the present disclosure;
[0016] Figure 4 is a diagram for describing the structure of logical address feature data according to an embodiment of the present disclosure;
[0017] Figure 5 is a diagram for describing the structure of a logical address feature map according to an embodiment of the present disclosure;
[0018] Figure 6 is a diagram for describing a type of preprocessing of input data according to an embodiment of the present disclosure;
[0019] Figure 7 is a sequence diagram of a method for setting and confirming a configuration of a computing memory device according to an embodiment of the present disclosure;
[0020] Figure 8 is a sequence diagram of a data writing method according to an embodiment of the present disclosure;
[0021] Fig. 9 is a sequence diagram of a data reading method according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0022] Hereinafter, embodiments of the present disclosure are described in more detail with reference to the accompanying drawings.
[0023] Figure 1 is a diagram showing a configuration of a data processing system 10 according to an embodiment of the present disclosure.
[0024] Reference Figure 1 , the data processing system 10 may include an external device 100 and a computing memory device 200 .
[0025] The external device 100 may be, for example, a high performance computing (HPC) device capable of processing neural network or artificial intelligence tasks, but is not limited thereto.
[0026] The external device 100 may include a host controller 110 , any number of processors 120 , an interface (IF) 130 , and a main memory 140 .
[0027] The host controller 110 may control the overall operation of the external device 100 and may be configured as a combination of software and hardware executing the software. In an embodiment, the host controller 110 may manage each hardware component and resource by running an operating system (OS) and running a program installed therein.
[0028] The processor 120 may operate by running firmware or software provided for various operations of the external device 100 on hardware. In an embodiment, the processor 120 may be hardware or a hardware accelerator capable of processing a neural network operation.
[0029] The interface 130 may provide an environment in which the external device 100 may communicate with the computing memory apparatus 200 .
[0030] The main memory 140 may store a program executed by the host controller 110 or the processor 120 , data, or a result processed by the host controller 110 or the processor 120 .
[0031] The computing memory device 200 may include a memory controller 210 and a non-volatile memory device (NVM) 220 that may be located outside the memory controller 210. In an embodiment, the external device 100 may be referred to as a first external device, and the NVM 220 may be referred to as a second external device.
[0032] The memory controller 210 may store data provided from the external device 100 in the NVM 220 in response to a write request from the external device 100 , and provide data stored in the NVM 220 to the external device 100 in response to a read request from the external device 100 .
[0033] The memory controller 210 may include a pre-processing device 300 .
[0034] The preprocessing device 300 can extract logical address characteristic data (i.e., logical block address (LBA) range type data, also referred to as "LRT data") from the system configuration setting information provided by the external device 100, and generate a logical address characteristic map (i.e., LBA range type map, also referred to as "LRTM").
[0035] In an embodiment, the LRT data may be data of a preprocessing type defined for preprocessing data corresponding to a specific logical address in a format that can be processed by a neural network, which will be referred to below. Figures 4 to 6 Give a description.
[0036] When the logical address of the data requested to be written by the external device 100 is included in the LRTM, the pre-processing device 300 may process the write data according to the pre-processing type set in the LRTM and store the pre-processed data in the NVM 220 .
[0037] The external device 100 may receive the pre-processed data from the computing memory device 200 and perform a neural network operation, such as learning.
[0038] Figure 2is a diagram illustrating a detailed configuration of the memory controller 210 according to an embodiment of the present disclosure.
[0039] Reference Figure 2 , the memory controller 210 may include a processor 211, an external device interface (IF) 213, a memory interface (IF) 215, a first memory device 217, a second memory device 219, and a pre-processing device 300. According to the configuration, the pre-processing device 300 may be integrated with the external device IF 213 (see 213-1).
[0040] The processor 211 may be implemented as a combination of hardware and firmware / software running on the hardware to operate by running firmware or software provided for various operations of the computing memory device 200 on the hardware. In an embodiment, the processor 211 may perform a flash translation layer (FTL) function for managing the computing memory device 200, such as address mapping, block management, garbage collection, and wear leveling.
[0041] The external device IF 213 may receive a command and a clock signal from the external device 100 and provide a communication channel for controlling input and output of data under the control of the processor 211. The external device IF 213 may provide a physical connection between the external device 100 and the computing memory apparatus 200.
[0042] The external device IF 213 may include a direct memory access (DMA) engine 2131 and an input / output (IO) buffer 2133 .
[0043] The IO buffer 2133 may store data transmitted and received between the external device 100 and the external device IF 213 .
[0044] In response to a system configuration setting request from the external device 100, the DMA engine 2131 may acquire system configuration setting information stored in the main memory 140 of the external device 100, and store the acquired system configuration setting information in the IO buffer 2133. In an embodiment, the system configuration setting information may include logical address feature data (i.e., LRT data). The LRT data may be data defining a pre-processing type for a logical address within a specific range.
[0045] In response to a write request from the external device 100, the DMA engine 2131 may acquire write data stored in the main memory 140 of the external device 100 and store the acquired write data in the IO buffer 2133. In response to a read request from the external device 100, the DMA engine 2131 may store read data to be provided to the external device 100 in the IO buffer 2133.
[0046] In an embodiment, the external device IF 213 can communicate with the external device based on an interface utilizing at least one of the various communication interfaces or standards such as: Universal Serial Bus (USB) protocol, MultiMediaCard (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial-ATA (SATA) protocol, Parallel-ATA (PATA) protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced MiniDisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, proprietary protocol, System Management Bus (SMBus) protocol, Inter-Integrated Circuit (I2C) protocol, Improved Inter-Integrated Circuit (I3C) protocol, etc.
[0047] The memory interface 215 may provide a communication channel for transmitting and receiving signals between the memory controller 210 and the NVM 220. The memory interface 215 may write data temporarily stored in the buffer memory (i.e., the first memory device 217 or the second memory device 219) to the NVM 220 under the control of the processor 211. The memory interface 215 may transmit read data read from the NVM 220 to the buffer memory (the first memory device 217 or the second memory device 219) under the control of the processor 211 and temporarily store the data.
[0048] The buffer memory may be implemented as at least one of the first memory device 217 and the second memory device 219. In an embodiment, the first memory device 217 may be disposed inside the memory controller 210, and the second memory device 219 may be disposed outside the memory controller 210.
[0049] The preprocessing device 300 may perform various types of preprocessing to convert data provided from the external device 100 into a format that can be processed by the neural network.
[0050] Figure 3 is a diagram illustrating a detailed configuration of the preprocessing device 300 according to an embodiment of the present disclosure.
[0051] Reference Figure 3 The pre-processing device 300 may include an LRTM storage circuit 310 , a determination circuit 320 , a computational core 330 , and any number of computational circuits 340 .
[0052] The LRTM storage circuit 310 may generate a logical address feature map (LRTM) based on logical address feature data (LRT data) included in the system configuration setting information transmitted from the external device 100 .
[0053] In an embodiment, the external device 100 may set the system configuration of the computing memory device 200 by sending a set feature command to the computing memory device 200 .
[0054] The feature identifier included in the set feature command may include an entry defining logical address feature data (LRT data), and a preprocessing type of each logical address may be defined by the entry.
[0055] Figure 4 is a diagram for describing the structure of logical address feature data according to an embodiment of the present disclosure.
[0056] Reference Figure 4 ,The LRT data includes a feature field (type, 00), an attribute field (attribute, 01), a first reserved field (reserved, 15:02), a starting logical address field (starting LBA (SLBA), 23:16), a logical address (LBA) number field (number of logical blocks (NLB), 31:24), a logical region identifier field (unique identifier (GUID), 47:32), and a second reserved field (reserved, 63:48).
[0057] Among the data values that can be specified in the characteristic field (type), a vendor-specific value (80h to FFh) can be used to define the type of preprocessing for the corresponding logical address.
[0058] That is, the preprocessing type of data of the number of LBAs (number of logical blocks (NLB), 31: 24) specified from the starting logical address (starting LBA (SLBA), 23:16) of the logical area indicated by the logical area identifier (unique identifier (GUID), 47:32) can be defined by the data value (80h to FFh) of the characteristic field (Type).
[0059] Figure 5 is a diagram for describing the structure of a logical address feature map according to an embodiment of the present disclosure.
[0060] The LRTM storage circuit 310 of the pre-processing device 300 may receive the LRT data (eg, Figure 4 LRT data in the format shown in the figure), extract the value included in each field in the LRT data, and generate and store Figure 5 The Logical Address Feature Map (LRTM) is shown.
[0061] Reference Figure 5 , Index 0 of LRTM is defined as: in the logical area whose logical area identifier (GUID) is 0, data from the starting logical address (SLBA) 0×0 to the number of LBAs (NLB) 0×10000 is pre-processed with type 80h.
[0062] Index 1 definition: In the logical area whose logical area identifier (GUID) is 1, data from the start logical address (SLBA) 0×10000 to the number of LBAs (NLB) 0×10000 is pre-processed with type 81h.
[0063] Index 2 definition: In the logical area whose logical area identifier (GUID) is 2, data from the start logical address (SLBA) 0×20000 to the number of LBAs (NLB) 0×10000 is pre-processed with type 82h.
[0064] Preprocessing types 80h to 82h may be data alignment, outlier (noise) removal, structure (dimension) conversion, etc., but are not limited thereto. Preprocessing types may include, for example, duplicate value removal, missing value correction, data linking / integration, data vectorization, outlier detection, feature engineering, etc.
[0065] Computation core 330 may be implemented as a combination of hardware and software running on the hardware to support various pre-processing types by utilizing computation circuitry 340 .
[0066] Figure 6 is a diagram for describing types of preprocessing of input data according to an embodiment of the present disclosure.
[0067] After the LRTM is generated and stored, a write request may be received from the external device 100 .
[0068] The determination circuit 320 of the pre-processing apparatus 300 may determine whether a logical address (LBA) included in the write request is included in the LRTM.
[0069] When the logical address (LBA) of the data requested to be written is included in the LRTM, the computing core 330 may process the write data WT DATA according to the preprocessing type set in the LRTM by using the computing circuit 340. The computing core 330 may store the preprocessed data PP DATA in the NVM 220.
[0070] When a neural network operation is required, the external device 100 may receive the preprocessed data PP DATA from the computing memory device 200 and process the preprocessed data PP DATA without a preprocessing process.
[0071] Figure 7 is a sequence diagram for describing a method for setting and confirming a configuration of a computing memory device 200 according to an embodiment of the present disclosure.
[0072] Reference Figure 7 , the external device 100 may, for example, send a set feature command to the computing memory device 200 and request to set the system configuration of the computing memory device 200 ( S101 ).
[0073] The external device IF 213 of the memory controller 210 included in the computing memory apparatus 200 may acquire logical address characteristic data (LRT data) stored in the external device 100 in response to the system configuration setting request ( S103 ).
[0074] The pre-processing device 300 of the memory controller 210 may receive the logical address feature data (LRT data), extract the value included in each field of the logical address feature data (LRT data), and generate and store, for example Figure 5 The logical address feature map (LRTM) shown (S105).
[0075] The pre-processing device 300 may request the NVM 220 to program the logical address feature map (LRTM) ( S107 ), so that the logical address feature map (LRTM) is programmed into the NVM 220 .
[0076] The memory controller 210 may update mapping data associated with the logical address feature map (LRTM) programmed into the NVM 220 ( S109 ), and respond to the external device 100 that the storage of the system configuration setting information has been completed ( S111 ).
[0077] Through such a procedure, the logical address feature map (LRTM) stored in the NVM 220 may be loaded into the memory controller 210 during the booting process of the computing memory device 200 ( S201 ).
[0078] When the external apparatus 100 wants to check previously set system configuration setting information, the external apparatus 100 may transmit, for example, a get feature command to the computing memory device 200 ( S301 ).
[0079] The pre-processing device 300 of the memory controller 210 included in the computing memory device 200 may generate logical address feature data (LRT data) based on the logical address feature map (LRTM) ( S303 ).
[0080] The memory controller 210 may transmit the logical address feature data (LRT data) generated by the pre-processing device 300 to the external device 100 ( S305 ), and respond to the external device 100 that the output of the system configuration setting information has been completed ( S307 ).
[0081] The external device 100 may check the pre-processing type set for each logical address range by checking the logical address feature data (LRT data) ( S309 ).
[0082] By setting the data preprocessing type, for example, using a set feature command, the preprocessing type can be specified for each logical address range. In addition, the preprocessing type for each logical address range can be easily managed according to the type and purpose of the neural network operation.
[0083] When data preprocessing is not required, since the logical address characteristic data can be initialized, the data processing system can be applied to various purposes and environments.
[0084] Figure 8 is a sequence diagram for describing a data writing method according to an embodiment of the present disclosure.
[0085] The external device 100 may transmit a data write request including a logical address (LBA) to the computing memory device 200 ( S401 ).
[0086] The write data requested to be written by the external device 100 may be transmitted from the external device 100 to the memory controller 210 and buffered in, for example, the IO buffer 2133 within the external device IF 213 ( S403 ).
[0087] The preprocessing device 300 of the memory controller 210 included in the computing memory device 200 may check whether a logical address (LBA) included in the write request is included in a logical address feature map (LRTM), and determine whether preprocessing of write-requested data is required ( S405 ).
[0088] When the data requested to be written does not need to be preprocessed ("No" in S405), the memory controller 210 may request to program the write data into the NVM 220 (S407). In this case, it is obvious that a process of converting the write-requested logical address (LBA) to a physical address must be performed first. The NVM 220 may program the write data into the corresponding physical address area (S409) and update the mapping data associated with the write data (S419).
[0089] When the data requested to be written needs to be preprocessed (“Yes” in S405 ), the preprocessing device 300 of the memory controller 210 may preprocess the write data according to the preprocessing type included in the logical address feature map (LRTM) ( S411 ).
[0090] After the preprocessing is completed, the memory controller 210 may convert the logical address (LBA) requested to be written into a physical address and request to write the write data into the NVM 220 (S413). The NVM 220 may program the preprocessed write data into the corresponding physical address area (S415).
[0091] The memory controller 210 may transmit a response signal indicating success or failure of processing of the write request to the external device 100 ( S417 ), and update mapping data associated with the write data ( S419 ).
[0092] Fig. 9 is a sequence diagram for describing a data reading method according to an embodiment of the present disclosure.
[0093] The external device 100 may transmit a data read request including a logical address (LBA) to the computing memory device 200 ( S501 ).
[0094] The memory controller 210 of the computing memory device 200 may convert a read-requested logical address into a physical address ( S503 ), and send a read request to the NVM 220 ( S505 ).
[0095] The NVM 220 may read data from the area corresponding to the physical address (S507), and transmit the read data to the memory controller 210 (S509). The memory controller 210 may provide the read data to the external device 100 (S511).
[0096] The data requested to be read by the external device 100 may be data pre-processed for the neural network operation, and the external device 100 may process the neural network operation by using the read data provided from the computing memory device 200 ( S513 ).
[0097] Since the data required for the neural network operation of the external device 100 is pre-processed in the computing memory device 200, the computing load and power consumption of the external device 100 can be reduced.
[0098] It will be appreciated by those skilled in the art that the present disclosure may be implemented in other specific forms without changing its technical spirit or basic features. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims rather than by specific embodiments, and it should be understood that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included within the scope of the present disclosure. In addition, the embodiments may also be combined to form other embodiments.
Claims
1. A memory controller, comprising: an external device interface to receive system configuration setting information from a first external device; a logical address feature map storage circuit that generates a logical address feature map by extracting logical address feature data from the system configuration setting information, the logical address feature data defining a calculation type for each logical address range specified by the first external device; a computing core, in response to a write request for a logical address included in the logical address feature map, processing the data requested to be written with a corresponding computing type; as well as The memory interface sends the processed write-requested data to the second external device.
2. The memory controller according to claim 1, wherein: The computing core pre-processes the write-requested data provided by the first external device into a format for neural network processing.
3. The memory controller according to claim 1, wherein: The system configuration setting information is included in a set feature command.
4. The memory controller according to claim 3, wherein: The logical address feature map storage circuit generates the logical address feature map by extracting at least a feature field, an attribute field, a start logical address field, a logical address quantity field and a logical area identification field from the logical address feature data of the set feature command.
5. The memory controller according to claim 4, wherein: The logical address feature map storage circuit extracts the calculation type from the vendor specific value of the feature field.
6. The memory controller according to claim 1, wherein: The first external device includes a host, and the second external device includes a non-volatile memory device.
7. A computing memory device comprising: Memory Controller: receiving system configuration setting information defining a calculation type for each logical address range from an external device, extracting logical address characteristic data defining a calculation type for each logical address range specified by the external device, and processing the write data based on a calculation type corresponding to a logical address of the write data requested to be written by the external device; as well as A non-volatile memory device that stores processed write data.
8. The computing memory device of claim 7, wherein: The memory controller pre-processes the write data provided by the external device into a format for neural network processing.
9. The computing memory device of claim 7, wherein: The system configuration setting information is included in a set feature command.
10. The computing memory device of claim 9, wherein: The memory controller generates a logical address feature map by extracting at least a feature field, an attribute field, a start logical address field, a logical address quantity field, and a logical region identification field from the logical address feature data of the set feature command.
11. The computing memory device of claim 10, wherein: The memory controller extracts the computation type from a vendor specific value of the characteristic field.
12. A method for operating a memory controller communicating with a first external device, comprising: receiving system configuration setting information from the first external device; generating a logical address characteristics map by extracting logical address characteristics data from the system configuration setting information, the logical address characteristics data defining a calculation type for each logical address range specified by the first external device; In response to a write request for a logical address included in the logical address feature map, processing the data requested to be written with a corresponding calculation type; and The processed write-requested data is sent to the second external device.
13. The operating method according to claim 12, wherein: Processing the data requested to be written includes: The write-requested data provided by the first external device is pre-processed into a format for neural network processing.
14. The operating method according to claim 12, wherein: Receiving the system configuration setting information includes receiving a set feature command.
15. The operating method according to claim 14, wherein: Generating the logical address feature map includes generating the logical address feature map by extracting at least a feature field, an attribute field, a start logical address field, a logical address quantity field, and a logical area identification field from the logical address feature data of the set feature command.
16. The operating method according to claim 15, wherein: Generating the logical address feature map further includes extracting the calculation type from a vendor specific value of the feature field.
17. The operating method according to claim 12, wherein: The first external device includes a host, and the second external device includes a non-volatile memory device.