Storage device performing copy operation in background and operating method thereof

Abstract

An operating method of a memory device including a non-volatile memory device and a controller controlling the non-volatile memory device, the operating method includes: receiving, by a controller from a host device, a first logical address of a source range entry, a second logical address of a destination range entry, and a first copy command including a first flag indicating that a background copy is set; mapping, at the controller, the first physical address to a second logical address; mapping, at the controller, the second physical address to the second logical address and / or the first physical address; sending, by the controller, a first notification to the host device to complete the first copy command; and after the controller transmits the first notification, reading, at the non-volatile memory device, the first data stored at the first physical address, and writing the first data at the second physical address.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0146044 filed on October 27, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The device, apparatus and method according to the present disclosure relate to a storage device that executes a copy command in the background. Background Art

[0004] A nonvolatile memory device, which is a type of semiconductor memory device, includes a flash memory device. A nonvolatile memory device can be used as a non-temporary storage device.

[0005] Non-Volatile Memory Express (NVMe), which is one of the interface protocols, supports various command sets, and a copy command is supported as one of the command sets. Summary of the invention

[0006] One aspect is to provide a storage device that efficiently executes a copy command by performing read and write operations associated with the copy command in the background after notifying a host device that the copy command is fully executed.

[0007] According to one aspect of one or more embodiments, a method for operating a storage device is provided, the storage device including a non-volatile memory device and a controller for controlling the non-volatile memory device, the method including: receiving, by the controller, from a host device, a first logical address of at least one source range entry, a second logical address of a destination range entry, and a first copy command including a first flag indicating that background copy is set; based on the first flag indicating that background copy is set, mapping, at the controller, a first physical address to a second logical address; mapping, at the controller, the second physical address to at least one of the second logical address and the first physical address; sending, by the controller, a first notification of completion of the first copy command to the host device; and after the controller sends the first notification, reading, at the non-volatile memory device, first data stored at the first physical address and writing the first data at the second physical address.

[0008] According to another aspect of one or more embodiments, a storage device is provided, comprising: at least one non-volatile memory device configured to store or read data; and a controller configured to control at least one non-volatile memory device and execute a command provided from a host device. The controller is also configured to receive from the host device a first logical address of at least one source range entry, a second logical address of a destination range entry, and a first copy command including a first flag indicating that background copying is set; based on the first copy command, map a first physical address to a second logical address; map the second physical address to at least one of the second logical address and the first physical address; send a first notification of completion of the first copy command to the host device; after sending the first notification, read the first data stored at the first physical address; and write the first data at the second physical address.

[0009] According to another aspect of one or more embodiments, there is provided a storage device, comprising: at least one non-volatile storage device configured to store or read data; and a controller configured to control the at least one non-volatile storage device and execute a command provided from a host device. The controller is further configured to receive a copy command including a flag indicating that background copy is set from the host device; based on the copy command, update a mapping table in which a logical address and a physical address are mapped in a one-to-one correspondence; after updating the mapping table, send a completion notification of the copy command to the host device; and after sending the completion notification, control the at least one non-volatile storage device to perform a data read operation or a data write operation corresponding to the copy command. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects will become apparent by describing in detail embodiments thereof with reference to the accompanying drawings, in which:

[0011] Figure 1 is a diagram showing a storage device according to an embodiment;

[0012] Figure 2 is a diagram showing a configuration of a controller of a storage device according to an embodiment;

[0013] Figure 3 is a diagram showing a configuration of a submission queue entry used in a copy command supporting background copy according to an embodiment;

[0014] Figure 4 is a diagram showing a method according to an embodiment of the present invention. Figure 3 A diagram of the configuration of source range entries used in the copy command;

[0015] Figure 5is a diagram showing a configuration of a copy descriptor inserted into a copy queue of a controller according to an embodiment;

[0016] FIG. 6A to FIG. 6C is a diagram showing the Figure 1 A diagram showing how the mapping table changes when a storage device executes a copy command;

[0017] Figure 7 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A diagram of a configuration of a storage device;

[0018] Figure 8 is a diagram describing an operation of notifying a host device whether a background copy function is supported in a method of operating a storage device according to an embodiment;

[0019] Fig. 9 is a diagram describing an operation of executing a copy command in a method of operating a storage device according to an embodiment;

[0020] Fig.10 is a diagram describing a copy command execution operation in a method for operating a storage device according to an embodiment; and

[0021] Fig.11 is a diagram illustrating an operation of handling an exception while executing a copy command in an operating method of a storage device according to an embodiment. DETAILED DESCRIPTION

[0022] To access the nonvolatile memory device, the host device follows an interface protocol to communicate with a controller of the memory interface.

[0023] The controller of the related art storage device supporting the copy command of NVMe performs a read operation on the source range entry targeted by the copy command and writes the result of the read operation at the target address. After completing the operations associated with all source range entries targeted by the copy command, the related art storage device notifies the host device to fully execute the copy command. Therefore, compared with the case where the host device directly performs the above-mentioned operations with the non-volatile storage device through read commands and write commands, the communication overhead is reduced. However, the following method is not efficient: after completing the internal read and write operations of the storage device associated with the copy command, the host device is notified to fully execute the copy command.

[0024] Various embodiments will be described below in detail and clearly to such an extent that those skilled in the art can easily implement the various embodiments.

[0025] Figure 1is a diagram showing a storage device 20 according to an embodiment. The storage device 20 may complete the update of the mapping table associated with the copy command, and then may notify the host device 10 to fully execute the copy command. After the storage device 20 notifies the host device 10 to fully execute the copy command, the storage device 20 may internally perform operations of reading and writing data, so that the execution of the copy command is completed internally. That is, the storage device 20 may perform data read and write operations associated with the copy command in the background (that is, without the intervention of the host device 10). In other words, the host device 10 may not control the specific data read and write operations associated with the copy command.

[0026] refer to Figure 1 , the storage device 20 may be electrically connected to the host device 10, and may include a controller 100 and at least one nonvolatile memory device 200. In the following description, reference to "nonvolatile memory device 200" or "the nonvolatile memory device 200" includes a plurality of nonvolatile memory devices 200 within its scope.

[0027] The storage device 20 may be implemented to be physically separated from the host device 10 , or may be implemented in the same package as the host device 10 .

[0028] The storage device 20 may be coupled to the host device 10 so that it can communicate with any other components of the host device 10 through a storage interface bus. For example, the storage interface bus may be a Peripheral Component Interconnect Express (PCIe) bus. The host device 10 may exchange data with the storage device 20 via the storage interface bus using a storage interface protocol. In an embodiment, for example, the storage interface protocol may be Non-Volatile Memory Express (NVMe).

[0029] The host device 10 may include a data center server, a cloud server, a personal computer, a laptop computer, etc. The host device 10 may be a computing device including a processor 11 configured to process data. The processor 11 of the host device 10 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or any other type of processing device implemented by software commands, microcode, and / or firmware. Figure 1 One processor 11 is shown in FIG. 1 , but in some embodiments, the processor 11 may include multiple processors.

[0030] The processor 11 of the host device 10 is connected to the memory device 12. The memory device 12 may include a static random access memory (SRAM), a dynamic random access memory (DRAM), or the like.

[0031] The storage device 20 may be used as a nonvolatile storage device that stores data regardless of whether power is supplied or not, and may provide a relatively large storage capacity compared to the storage device 12 of the host device 10 .

[0032] The controller 100 may control the nonvolatile memory device 200 to process or execute a workload. The nonvolatile memory device 200 may write (or otherwise referred to as “store” or “program”), erase, and / or read data under the control of the controller 100 .

[0033] The non-volatile memory device 200 may include a flash memory of a two-dimensional (2D) structure or a three-dimensional (3D) structure. The flash memory may include different types of non-volatile memories, for example, NAND flash memory, vertical NAND (V-NAND) flash memory, NOR flash memory, magnetic RAM (MRAM), phase change RAM (PRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM) and / or resistive RAM (RRAM).

[0034] When the host device 10 and the storage device 20 communicate with each other based on NVMe, the storage device 12 may include at least one submission queue SQ and at least one completion queue CQ. The host device 10 may send a command to the storage device 20 by using the submission queue SQ. That is, in an embodiment, the host device 10 may record a command (or an entry corresponding to a command) at a submission queue SQ that the storage device 20 can access. After the host device 10 records the command, the host device 10 may notify the storage device 20 of the presence of a new command by using the submission queue tail doorbell register of the controller 100 of the storage device 20. The storage device 20 can obtain the command from the submission queue SQ and can process the command. When the processing of the command is completed, the storage device 20 may record an entry at the completion queue CQ and may generate an interrupt. The host device 10 may process the necessary tasks and may record information indicating the completion of the processing of the command at the completion queue head doorbell register of the controller 100 of the storage device 20.

[0035] In an embodiment, some commands sent from the host device 10 may be decomposed and executed as at least one internal command executable by the storage device 20. For example, a copy command may be decomposed into a read command and a write command and then may be executed internally.

[0036] After the related art storage device completes execution of all internal operations for processing a command, the related art storage device notifies the host device of completion of processing the command by recording a completion queue entry at the completion queue CQ. For example, when the related art storage device executes a read command and a write command as internal commands obtained by decomposing a copy command, the related art storage device completes all operations corresponding to the read command and the write command, and then notifies the host device of completion of execution of the copy command.

[0037] Contrary to the related art, the storage device 20 may perform an update of the mapping table MAP_TAB associated with the copy command, and then may notify the host device 10 of the completion of the execution of the copy command. In other words, in an embodiment, the storage device 20 may only perform an update of the mapping table MAP_TAB before notifying the host device 10 of the completion of the execution of the copy command. That is, the storage device 20 may record an entry at the completion queue CQ. Therefore, the efficiency of processing the copy command of the host device 10 may be improved.

[0038] Reference Figure 1 How the storage device 20 processes the copy command is described in detail.

[0039] The host device 10 may send a copy command to the storage device 20 by using the submission queue SQ. For example, the host device 10 may record a submission queue entry SQE (refer to Figure 2 ). The submission queue entry SQE may be implemented to include a first logical address as a logical address of at least one source range entry, a second logical address as a logical address of a destination range entry, and a first flag indicating background copying. For example, in an embodiment, the first flag may be regarded as a background copy flag that informs the storage device 20 to use a background copy process for executing a copy command, and therefore, when the background copy flag is set, it may be indicated that the background copy process will be implemented on the storage device 20, and when the background copy flag is not set, it may be indicated that the background copy process will not be implemented (i.e., a related art process will be implemented, in which all operations corresponding to a read command and a write command as an internal command obtained by decomposing the copy command will be completed before notifying the host device to complete the execution of the copy command). The logical address may be a logical block address (LBA) as a logical block unit. In the present specification, the first logical address as a logical address of a source range entry may be referred to as a "source LBA (SLBA)". In the present specification, the second logical address as a logical address of a destination range entry may be referred to as a "destination LBA (DLBA)".

[0040] The storage device 20 may parse the copy command and may perform processing based on the parsed copy command. For example, the copy command may request to copy data stored at a source LBA including at least one or more non-contiguous LBAs at a destination LBA (DLBA) including contiguous LBAs. The copy command may be used for garbage collection specified by the host device 10, but the embodiment is not limited thereto.

[0041] The storage device 20 may perform an update of a mapping table MAP_TAB corresponding to a copy command by using a flash translation layer (FTL). The mapping table MAP_TAB may store information about a mapping relationship between a logical address of the host device 10 and a physical address of the storage device 20. The storage device 20 may map a first physical address (first PA) to a destination LBA (DLBA), and may map a second physical address (second PA) to at least one of the destination LBA (DLBA) or the first physical address (first PA). That is, information about a correlation between the destination LBA (DLBA), the first physical address (first PA), and the second physical address (second PA) may be stored in the mapping table MAP_TAB.

[0042] The first physical address (first PA) may be a physical address mapped to the source LBA (SLBA). Therefore, the first physical address (first PA) may be non-continuous. In this specification, logical addresses will be described by using numbers, and physical addresses will be described by using lowercase English letters. In the description of this specification, non-continuous numbers represent non-continuous logical addresses, and continuous numbers represent continuous logical addresses. Non-continuous lowercase English letters represent non-continuous physical addresses, and continuous lowercase English letters represent continuous physical addresses. Reference Figure 1 , a description will be given when the first physical address (first PA) is PA a, PA b, PA e, or PA f. That is, the first physical address (first PA) mapped to the source LBA (SLBA) before executing the copy command may be a non-continuous physical address. The second physical address (second PA) is the physical address to which the data of the first physical address (first PA) will be written when the copy command is executed. That is, according to the definition of the copy command, the second physical address (second PA) is a continuous physical address. Reference Figure 1 The second physical address (second PA) refers to a physical address represented by consecutive lowercase English letters PAi, PAj, PAk and PAl.

[0043] The storage device 20 performs an update of the mapping table MAP_TAB corresponding to the copy command, and then notifies the host device 10 that the execution of the copy command is completed. For example, the storage device 20 may record (also referred to as "publish") a completion queue entry CQE associated with the copy command at the completion queue CQ (see Figure 2 ), and an interrupt can be issued to the host device 10.

[0044] After the storage device 20 notifies the host device 10 of the completion of the copy command, the storage device 20 may control the nonvolatile memory device 200 to execute the internal read command and the internal write command obtained by decomposing the copy command. That is, unlike the related art storage device that notifies the completion of the copy command after completing the operations of updating the mapping table and executing the internal read command and the internal write command, the storage device 20 according to the embodiment immediately notifies the host device 10 of the completion of the copy command after performing the update of the mapping table MAP_TAB corresponding to the copy command. After the storage device 20 notifies the host device 10 of the completion of the copy command, the storage device 20 may execute the operations corresponding to the internal read command and the internal write command.

[0045] After notifying the completion of the copy command, the controller 100 of the storage device 20 can read the data stored at the first physical address (first PA). The storage device 20 can provide the internal read and write command MEM_CMD and the related physical address ADDR to the nonvolatile memory device 200 so that the read data is written at the second physical address (second PA).

[0046] Therefore, the storage device 20 can execute the internal read command and the internal write command in the background (that is, without the intervention of the host device 10), which require time during the processing operation of the copy command after the completion notification of the copy command, so the copy command can be processed efficiently. In this specification, unlike the related art operation of processing the copy command, the operation of processing the copy command by executing the operations corresponding to the internal read and write commands associated with the copy command after the completion notification of the copy command is referred to as "background copy", and will be described in more detail below.

[0047] Figure 2 2 is a diagram showing an example configuration of a storage device 20 according to an embodiment. Figure 2 , the storage device 20 may include a controller 100 and at least one non-volatile memory device (NVM) 200 .

[0048] The controller 100 may include a host interface (I / F) 110, a command queue (CMQ) 121, a command decoder 122, a copy manager 123, a copy queue (CPQ) 124, a flash translation layer (FTL) 125, a mapping table (MAP_TAB) 126, a copy circuit 127, a read circuit 128, a write circuit 129, and a non-volatile memory interface (I / F) 130. In some embodiments, the controller 100 may further include a working memory (not shown) loaded with firmware.

[0049] The host interface (I / F) 110 of the controller 100 may receive a submission queue entry SQE associated with a copy command from the host device 10. Receiving the submission queue entry SQE of the host interface 110 may be implemented by acquiring the submission queue entry SQE from the submission queue SQ. A background copy flag of the submission queue entry SQE associated with the copy command may be set. That is, an address corresponding to the background copy flag of the submission queue entry SQE may be set to "1h". The submission queue entry SQE with the background copy flag set may allow the storage device 20 to execute internal read and write commands of the copy command in the background (that is, without intervention of the host device 10).

[0050] The host interface (I / F) 110 may be implemented with various interfaces, for example, an Advanced Technology Attachment (ATA) interface, a Serial ATA (SATA) interface, an External SATA (e-SATA) interface, a Small Computer Small Interface (SCSI), a Serial Attached SCSI (SAS), a Peripheral Component Interconnect (PCI) interface, a PCI Express (PCIe) interface, an IEEE 1394 interface, a Universal Serial Bus (USB) interface, and a Non-Volatile Memory Express (NVMe) interface. For example, in some embodiments, the controller 100 may receive a command that complies with the NVMe standard protocol, and may send a response to the host device 10.

[0051] The command queue (CMQ) 121 may manage the received submission queue entry SQE according to the queue structure. The command decoder 122 may parse the submission queue entry SQE stored in the command queue 121, and may generate a copy descriptor based on the information of the copy command parsed from the submission queue entry SQE. The command decoder 122 may generate a copy descriptor based on the source LBA (SLBA) and the destination LBA (DLBA) included in the submission queue entry SQE associated with the copy command. The command decoder 122 may provide the copy descriptor to the copy manager 123.

[0052] The replication manager 123 may insert the replication descriptor into the replication queue 124 and manage the replication descriptor. The command decoder 122 may generate replication descriptors for corresponding submission queue entries SQE of a plurality of different replication commands stored in the command queue 121 at different time points. The replication manager 123 may sequentially insert the plurality of replication descriptors thus generated into the replication queue 124 (CPQ).

[0053] According to an embodiment, the copy queue (CPQ) 124 may include a plurality of copy queues. In an embodiment, a copy descriptor generated according to a copy command associated with background copy and a copy descriptor generated according to a copy command not associated with background copy may be inserted into different copy queues 124. In this case, a copy command associated with background copy may be processed in the background without intervention of the host device 10. A copy command not associated with background copy may be processed in the foreground by intervention of the host device 10.

[0054] According to an embodiment, the copy queue (CPQ) 124 may include only one type of copy descriptor, that is, a copy descriptor generated according to a copy command associated with background copy or a copy descriptor generated according to a copy command not associated with background copy. For example, while performing operations corresponding to internal read commands and internal write commands based on copy descriptors generated according to copy commands associated with background copy, a copy command not associated with background copy may be received. In this case, the copy manager 123 may perform operations corresponding to internal read commands and internal write commands in the foreground by refreshing all copy descriptors associated with background copy stored in the copy queue 124.

[0055] The copy manager 123 may refer to the copy descriptor of the copy queue 124 , transfer the source LBA (SLBA) and the destination LBA (DLBA) to the flash translation layer (FTL) 125 , and may direct the update of the mapping table 126 .

[0056] The flash translation layer (FTL) 125 may perform various functions (or operations) such as address mapping, wear leveling, and garbage collection. The address mapping operation refers to an operation of converting a logical address received from a host into a physical address to be used to actually store data in the nonvolatile memory device 200. For example, wear leveling, which is a technique for allowing blocks of the nonvolatile memory device 200 to be used evenly so as to prevent excessive degradation of a specific block, may be implemented by a firmware technique for balancing erase counts of physical blocks. Garbage collection refers to a technique for ensuring the available capacity of the nonvolatile memory device 200 by copying valid data of an existing block to a new block and erasing the existing block.

[0057] The flash translation layer (FTL) 125 may update the mapping table 126 by mapping the first physical address (first PA) mapped to the source LBA (SLBA) to the destination LBA (DLBA). The flash translation layer 125 may allocate a second physical address (second PA) as a new physical address to which data is to be copied so as to correspond to the destination LBA (DLBA), and may update the mapping table 126 by mapping the second physical address (second PA) to the destination LBA (DLBA) and / or the first physical address (first PA).

[0058] The copy manager 123 may receive a notification indicating that the mapping table 126 is updated by the flash translation layer 125, and may control the host interface 110 so that the mapping table 126 is updated to the host device (eg, Figure 1 The host device 10 of the host interface 110 sends a completion queue entry CQE associated with the copy command. Sending the completion queue entry CQE of the host interface 110 may be posting the completion queue entry CQE to the completion queue CQ and issuing an interrupt to the host device.

[0059] After sending the completion queue entry CQE associated with the copy command to the host device, the copy manager 123 may control the copy circuit 127 based on the copy descriptor stored in the copy queue 124 and may execute the internal read command and the internal write command.

[0060] The replica circuit 127 may control the read circuit 128 so that data is read from the first physical address (first PA), and may control the write circuit 129 so that the read data is stored at the second physical address (second PA). The read circuit 128 may read data by controlling the nonvolatile memory device 200 via the nonvolatile memory interface 130, and the write circuit 129 may write data by controlling the nonvolatile memory device 200 via the nonvolatile memory interface 130.

[0061] Figure 3 1 is a diagram showing a configuration of a submission queue entry SQE used in a copy command supporting background copy according to an embodiment. Figure 1 , Figure 2 and Figure 3 To describe the submission queue entry SQE.

[0062] The storage device 20 may receive a copy command from the host device 10 indicating that a background copy is to be performed. In an embodiment, the copy command may be Figure 3 The submission queue entry SQE is shown.

[0063] The submission queue entry SQE may include a first word (double word 0) DWORD 0 storing a command identifier (command ID) and an OPCODE indicating a copy command. The command identifier (command ID) may be an identifier for identifying a relevant submission queue entry SQE from among a plurality of submission queue entries SQE included in the submission queue SQ.

[0064] The submission queue entry SQE may include data (eg, such as Figure 4 The second word (double word 1) DWORD 1 of the data pointer DPTR of the location of the source range entry SRE (e.g., the memory of the host device 10). In an embodiment, the data pointer DPTR may be a reference Figure 1 The first logical address described.

[0065] The submission queue entry SQE may include a third word (double word 2) DWORD 2 and a fourth word (double word 3) DWORD 3. A starting destination LBA (SDLBA) indicating a starting address of a destination LBA (DLBA) serving as a destination location to which data read from at least one source LBA (SLBA) is to be written may be stored in the third word (double word 2) DWORD 2 and the fourth word (double word 3) DWORD 3. In an embodiment, the destination LBA (DLBA) may be a reference Figure 1 Describes the second logical address.

[0066] The submission queue entry SQE may include a fifth word (double word 4) DWORD 4. A range number NR indicating the number of source range entries SRE capable of providing information about data location and data capacity may be stored in the fifth word (double word 4) DWORD 4. The data may be used for one or more read operations of the copy command.

[0067] The submission queue entry SQE may include a sixth word (double word 5) DWORD 5. A background copy flag BGCF indicating whether a background copy-based copy command is performed may be stored in the sixth word (double word 5) DWORD 5.

[0068] For example, in an embodiment, when the host device 10 requests to execute a copy command based on background copy, the sixth word DWORD 5 of the submission queue entry SQE may be set to "1h". When the host device 10 requests to execute a copy command not based on background copy, the sixth word DWORD 5 of the submission queue entry SQE may be set (or cleared) to "0h".

[0069] According to an embodiment, the command decoder 122 may set the background copy flag BGCF of the copy descriptor with reference to the background copy flag BGCF stored in the sixth word DWORD 5 of the submission queue entry SQE.

[0070] The first logical address indicated by the data pointer DPTR of the submission queue entry SQE may be associated with a first logical space identified by a first identifier. The second logical address, which is a destination LBA (DLBA) of the submission queue entry SQE, may be associated with a second logical space identified by a second identifier. The first logical space and the second logical space may be located at the same location of the storage device 20. That is, in some embodiments, background copy operations may be performed between different namespaces as well as the same namespace.

[0071] In some embodiments, the submission queue entry SQE may include one or more additional words or fields associated with characteristics such as retries, protection information, indicator type, and reference tags.

[0072] Figure 4 is a diagram showing a method according to an embodiment of the present invention. Figure 3 FIG. 400 is a diagram of the configuration of the source range entry used in the copy command. Figure 2 and Figure 4 4. The source range entry 400 used in the copy command is described.

[0073] refer to Figure 4 , the source range entry 400 may include one or more source range entries 410 and 420. The source range entry 410 may include a start address (StLBA) 411 of a source LBA (SLBA) and a number of logical blocks (NLB) 412 to be copied, and the source range entry 420 may include a start address (StLBA) 421 of a source LBA (SLBA) and a number of logical blocks (NLB) 422 to be copied. That is, a read operation may be performed on a logical block corresponding to the number of logical blocks 412 to be copied from the start address 411 of the source LBA (SLBA) of the first source range entry (SRE 0) 410 and a logical block corresponding to the number of logical blocks 422 to be copied from the start address 421 of the source LBA (SLBA) of the second source range entry (SRE 1) 420, and data read by the read operation may be written at the destination LBA (DLBA). Writing data at the destination LBA (DLBA) may be writing data at a second physical address (second PA) mapped to the destination LBA (DLBA).

[0074] In an embodiment, the logical block indicated by the first source range entry (SRE 0) 410 and the logical block indicated by the second source range entry (SRE 1) 420 may not be located at consecutive logical block addresses. For example, in the first source range entry (SRE 0) 410, the start address StLBA of the source LBA (SLBA) may indicate LBA 01, and the number of logical blocks (NLB) 412 may indicate 2. In this case, the first source range entry (SRE 0) 410 may indicate LBA 01 and LBA 02. In the second source range entry (SRE 1) 420, the start address StLBA of the source LBA (SLBA) may indicate LBA 05, and the number of logical blocks (NLB) 422 may indicate 2. In this case, the second source range entry (SRE 1) 420 may indicate LBA 05 and LBA 06.

[0075] The command decoder 122 may generate a copy descriptor based on one or more source range entries 410 and 420. Figure 5 To describe the copy descriptor.

[0076] Figure 5 1 is a diagram showing a copy descriptor 500 inserted into the copy queue 124 of the controller 100 according to an embodiment. Figure 2 , Figure 3 , Figure 4 and Figure 5 The copy descriptor 500 is described below.

[0077] refer to Figure 5 In an embodiment, the copy queue 124 may include a plurality of cells, and information indicating each copy descriptor 500 may be stored in each cell. For example, the information indicating each copy descriptor 500 may be an address where each copy descriptor 500 is stored. Alternatively, each copy descriptor 500 itself may be stored in each cell of the copy queue 124. For example, in an embodiment, one of the copy descriptors 500 may be stored in the cell 124a of the copy queue 124, such as Figure 5 As shown in reference Figure 2 As described, the copy descriptor 500 may be generated based on a submission queue entry SQE associated with the copy command.

[0078] In an embodiment, the copy queue 124 may be a circular queue of a given size. In some embodiments, the copy queue 124 may be a linked queue. When the copy queue 124 is a queue of a given size, a copy command received when all cells of the copy queue 124 are full may be blocked. That is, when there is insufficient available space in the copy queue 124 for storing copy descriptors, the storage device 20 may issue a completion queue entry CQE with a completion flag cleared to the completion queue CQ of the host device 10 in response to receiving a copy command.

[0079] The copy descriptor 500 may include a source (Src) entry count 520, a source (Src) entry 530, and a destination LBA (DLBA) 540. According to an embodiment, a copy descriptor generated according to a copy command associated with a background copy and a copy descriptor generated according to a copy command not associated with a background copy may be managed by using different copy queues 124. In this case, the copy descriptor 500 generated according to the copy command associated with the background copy may selectively include a background copy flag 510.

[0080] The source (Src) entry count 520 may indicate the number of source range entries SRE included in the submission queue entry SQE of the replication command. The source range entries SRE included in the submission queue entry SQE may constitute a source entry. Figure 4 In each source range entry SRE described, the start address StLBA of the source LBA and the number NLB of logical blocks to be copied may constitute the source entry 531 / 532.

[0081] The destination LBA 540 may include the starting address (starting DLBA) SDLBA of the destination LBA and the sum of the number of logical blocks NLB to be copied of the source entry. Figure 3 The destination LBA 540 is set using the third word (DWORD 2) DWORD 2 and the fourth word (DWORD 3) DWORD 3 of the SDLBA of the described submission queue entry (SQE) 300 and the fifth word (DWORD 4) DWORD 4 storing the source range number NR indicating the number of source range entries SRE.

[0082] According to the reference Figure 4The source (Src) entry 530 is generated by describing the first source range entry (SRE0) 410 indicating LBA 01 and LBA 02 and the second source range entry (SRE1) 420 indicating LBA 05 and LBA 06. For example, the start address SDLBA of the destination LBA (DLBA) 540 may indicate LBA 09, and the number of logical blocks to be copied NLB of the source entry may be 4. Therefore, the logical addresses indicated by the destination LBA (DLBA) 540 may be LBA 09, LBA 10, LBA 11, and LBA 12.

[0083] FIG. 6A to FIG. 6C is a diagram showing the Figure 1 FIG. 20 is a diagram showing how the mapping table MAP_TAB changes when the storage device 20 executes a copy command. Figure 1 , Figure 2 , Figure 4 , Figure 5 as well as FIG. 6A to FIG. 6C The update of the mapping table (MAP_TAB) 126 will be described below. The following reference will be made to the assumption that the source LBA (SLBA) indicates LBA 01, LBA 02, LBA 05, and LBA 06 and the destination LBA (DLBA) indicates LBA 09, LBA 10, LBA 11, and LBA 12. Fig. 6A and Figure 6C The copy command is described as an example.

[0084] Fig. 6A The mapping table (MAP_TAB) 126 that has not been updated by the flash translation layer 125 of the storage device 20 that has not received the copy command is shown.

[0085] Fig. 6A An example of a mapping table (MAP_TAB) 126 in which source LBAs (SLBAs) LBA 01, LBA 02, LBA 05, and LBA 06 are mapped to first physical addresses PA a, PA b, PA e, and PA f is shown. As described above, whether the numbers of the logical addresses are continuous indicates whether the logical addresses are continuous, and whether the lowercase English letters of the physical addresses are continuous indicates whether the physical addresses are continuous. Since the mapping table (MAP_TAB) 126 has not been updated, the physical address may not be mapped to the destination LBA (DLBA). At the first physical addresses PA a, PA b, PA e, and PA f of the nonvolatile memory device 200 mapped to the source LBAs (SLBAs) LBA 01, LBA 02, LBA 05, and LBA 06, there are previously stored data DT a, DT b, DT e, and DT f.

[0086] Figure 6BThe mapping table (MAP_TAB) 126 updated by the flash translation layer 125 of the storage device 20 that received the copy command is shown.

[0087] refer to Figure 6B , the flash translation layer 125 updates the mapping table (MAP_TAB) 126 by mapping the first physical addresses PA a, PA b, PA e, and PA f mapped to the source LBA (SLBA) to the destination LBAs LBA 09, LBA 10, LBA 11, and LBA 12. The flash translation layer 125 updates the mapping table (MAP_TAB) 126 by mapping the second physical addresses PA i, PA j, PA k, and PA l to the destination LBAs LBA 09, LBA 10, LBA 11, and LBA 12 and / or the physical addresses PA a, PA b, PA e, and PA f. Some of the first physical addresses PA a, PA b, PA e, and PA f are non-contiguous physical addresses, and all of the second physical addresses PA i, PA j, PA k, and PA l are consecutive physical addresses. Since operations corresponding to the internal read command and the internal write command obtained by decomposing the copy command are not performed, data has not been written at the second physical addresses PAi, PAj, PAk, and PA1 of the nonvolatile memory device 200.

[0088] The storage device 20 may be Figure 6B The mapping table (MAP_TAB) 126 is shown updated, and the host device 10 may then be notified that the execution of the copy command is completed.

[0089] After the storage device 20 notifies the host device 10 of the completion of the execution of the copy command, the storage device 20 executes the internal read command and the internal write command obtained by decomposing the copy command in the background without the intervention of the host device 10 .

[0090] Figure 6C The mapping table (MAP_TAB) 126 is shown after the storage device 20 executes an internal read command and an internal write command in the background without intervention of the host device 10 .

[0091] refer to Figure 6C , the flash translation layer 125 releases the first physical addresses PAa, PAb, PAe and PAf mapped to the destination LBAs LBA09, LBA10, LBA11 and LBA12. The second physical addresses PAi, PAj, PAk and PA1 are mapped to the destination LBAs LBA09, LBA10, LBA11 and LBA12.

[0092] The replica circuit 127 of the controller 100 controls the read circuit 128 to read the data DT a, DT b, DT e, and DT f of the first physical addresses PA a, PA b, PA e, and PA f of the nonvolatile memory device 200. The replica circuit 127 controls the write circuit 129 to write the read data DT a, DT b, DT e, and DT f at the second physical addresses PA i, PA j, PA k, and PA l of the nonvolatile memory device 200.

[0093] Under the following assumptions FIG. 6A to FIG. 6C A description is given: even after the background copy is completed, the first physical addresses PA a, PA b, PA e, and PA f are mapped to the source LBA (SLBA), and data still exists at the first physical addresses PA a, PA b, PA e, and PA f of the nonvolatile memory device 200. According to an embodiment, after the background copy is completed, the first physical addresses PA a, PA b, PA e, and PA f mapped to the source LBA (SLBA) may be released, and the first physical addresses PA a, PA b, PA e, and PA f of the nonvolatile memory device 200 may be set to "unavailable".

[0094] Figure 7 is a diagram showing a configuration of a nonvolatile memory device 200 of a storage apparatus 20 according to an embodiment.

[0095] The nonvolatile memory device 200 may include a control logic circuit 210, a memory block 220, a page buffer 230, a voltage generator 240, and a row decoder 250. Figure 7 Not shown, but in some embodiments, the nonvolatile memory device 200 may include components of a memory device of a solid state drive, for example, a memory interface circuit, a column logic, a pre-decoder, a temperature sensor, a command decoder, and an address decoder.

[0096] The control logic circuit 210 may control various operations of the nonvolatile memory device 200 as a whole. The control logic circuit 210 may output various control signals in response to a command CMD and / or a physical address ADDR from a memory interface circuit. For example, the control signal may include a voltage control signal CTRL_vol, a row address X_ADDR, and a column address Y_ADDR.

[0097] The command CMD may include an internal read command and / or an internal write command obtained by decomposing the copy command. The address ADDR corresponding to the command CMD may be a reference FIG. 6A to FIG. 6CThe control logic circuit 210 reads a plurality of pieces of data at the first physical address in response to the internal read command. The control logic circuit 210 writes the read data at the second physical address in response to the internal write command.

[0098] The memory block 220 may include a plurality of memory blocks BLK1 to BLKz (z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. The memory block 220 may be connected to the page buffer 230 through the bit lines BL1 to BLn, and may be connected to the row decoder 250 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL.

[0099] The page buffer 230 may include a plurality of page buffers PB1 to PBn (n is an integer of 3 or more), and the plurality of page buffers PB1 to PBn may be connected to the memory cells through the bit lines BL1 to BLn, respectively. The page buffer 230 may select at least one bit line among the bit lines BL1 to BLn in response to the column address Y_ADDR. The page buffer 230 may operate as a write driver or a sense amplifier according to the operation mode. For example, in a programming (or writing) operation, the page buffer 230 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. In a reading operation, the page buffer 230 may sense the current or voltage of the selected bit line to read the data stored in the memory cell.

[0100] The voltage generator 240 may generate various voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol.

[0101] In response to the row address X_ADDR, the row decoder 250 may select one of a plurality of word lines WL and may select one of a plurality of string selection lines SSL.

[0102] Figure 8 is a diagram describing an operation of notifying a host device whether a background copy function is supported in a method of operating a storage device according to an embodiment.

[0103] In operation S110, the host device may request the capabilities supported by the controller of the storage device from the storage device. In an embodiment, the request for the capabilities supported by the controller may be completed by sending an identification command of NVMe to the storage device. That is, the host device may publish a submission queue entry SQE to the submission queue SQ in response to the identification command, and may notify the storage device of the presence of the identification command by using the submission queue tail doorbell register. The submission queue entry SQE of the identification command may include a data pointer indicating the starting address of the data buffer.

[0104] In operation S120, the storage device may generate a controller data structure in response to the identification command. One field of the controller data structure may include a code indicating whether the copy command is supported and whether the background copy operation is supported. For example, the storage device may set a bit of the field indicating whether the copy command is supported (e.g., a copy command flag) to "1h", and may set a bit of the field indicating whether the background copy operation is supported (e.g., a background copy flag) to "1h". In this case, the storage device may provide a response to the host device indicating that both the copy command and the background copy operation are supported.

[0105] In operation S130, the storage device may send a response including the controller data structure to the host device. For example, in some embodiments, the storage device may store the address of the generated controller data structure in a data buffer, publish a completion queue entry CQE to a completion queue CQ, and issue an interrupt to the host device.

[0106] Therefore, after the host device parses and checks the received controller data structure, the host device can send a copy command with the background copy flag set (e.g., set to "1h") to the storage device so that the storage command processes the copy command in the background without intervention by the host device.

[0107] Fig. 9 is a diagram describing an operation of executing a copy command in a method for operating a storage device according to an embodiment. Figures 1 to 7 To avoid redundancy and for the sake of brevity, the reference to Figures 1 to 7 The same additional description is given as the description.

[0108] In operation S210, the host device may send a copy command with a background copy flag set (e.g., set to "1h") to the storage device. That is, the host device may publish a submission queue entry SQE with a background copy flag set (e.g., set to "1h") in association with the copy command to the submission queue SQ. The host device may notify the storage device of the presence of the copy command by using the submission queue tail bell register.

[0109] In operation S220, the storage device may update a mapping table that maps logical addresses and physical addresses in a one-to-one correspondence based on a submission queue entry SQE of a copy command by using a flash translation layer (FTL). For example, the storage device may map a first physical address mapped to a first logical address as an address of a source range entry to a second logical address as a destination LBA. The storage device may allocate a second physical address to which data of the first physical address will be written. The storage device may map the second physical address to a second logical address or the first physical address.

[0110] When the mapping table is successfully updated, the storage device may notify the host device that the copy is complete in operation S230. For example, the storage device may publish a completion queue entry CQE with a flag set indicating that the execution of the copy command is complete to the completion queue CQ.

[0111] In some embodiments, when the storage device cannot support execution of a copy command for a range of all blocks of a source range entry and a range of all blocks of a destination LBA, the storage device may publish a completion queue entry CQE with a flag set indicating failure to execute the copy command to the completion queue CQ.

[0112] In operation S240, the storage device may perform operations corresponding to the internal read command and the internal write command based on the updated mapping table. The storage device may read data stored at a first physical address of the nonvolatile memory device and may write the read data at a second physical address of the nonvolatile memory device.

[0113] In some embodiments, in operation S250, the storage device may notify the host device of the completion of the execution of the internal read command and the internal write command by using an asynchronous event request (AER). In some embodiments, operation S250 may be omitted.

[0114] Fig.10 FIG. 1 is a diagram describing a copy command execution operation according to an embodiment in an operation method of a storage device according to an embodiment. Fig. 9 The same additional description is given as the description.

[0115] In operation S310 , the host device may send a copy command with a background copy flag set (eg, set to “1h”) to the storage device.

[0116] In operation S320, the storage device may check the copy queue (CPQ) 124. For example, the storage device may check whether the copy queue (CPQ) 124 has available space for storing the copy descriptor. That is, the storage device may check whether there is free space in the copy queue (CPQ) 124 that can store the copy descriptor.

[0117] In operation S330a, the storage device may determine whether the CPQ is full. When the result of checking whether the copy queue (CPQ) 124 is available indicates that the copy queue (CPQ) 124 is full due to copy descriptors generated by a previous copy command (e.g., a copy command with a background copy flag set) (operation S330a, "Yes"), the storage device may post a completion queue entry CQE with a completion flag set indicating that execution of the copy command failed (e.g., set to "0h") to the completion queue CQ in operation S330b.

[0118] When the result of checking whether the copy queue (CPQ) 124 is available indicates that the copy queue (CPQ) 124 is not full and has available space to store the copy descriptor generated by the previous copy command (e.g., the copy command with the background copy flag set) (operation S330a, no), the storage device may generate the copy descriptor in operation S340. For example, the storage device may generate the copy descriptor. The copy descriptor may be generated based on the submission queue entry SQE corresponding to the copy command of the host device.

[0119] In operation S350, the storage device may insert the generated copy descriptor into the copy queue (CPQ) 124. When the copy queue (CPQ) 124 is a circular queue, the storage device may update the positions of the queue head and the queue tail based on the position of the newly inserted copy descriptor.

[0120] In operation S360, the storage device may update the mapping table.

[0121] In operation S370, the storage device may notify the host device that the copy is complete. For example, the storage device may publish a completion queue entry CQE in which a flag indicating that the execution of the copy command is completed is set to the completion queue CQ.

[0122] In operation S380 , the storage device may perform operations corresponding to the internal read command and the internal write command based on the updated mapping table.

[0123] The copy command execution operation of the storage device may include setting the copy queue (CPQ) 124 to a degree that can be executed in the background according to the resources of the storage device, and when the copy queue (CPQ) 124 is full, the copy command with the background copy flag set may be prevented / blocked. Therefore, the copy command with the background copy flag set may be prevented from being excessively executed. This configuration may mean preventing the storage device from falling into an inoperable state or preventing overload.

[0124] Fig.11 FIG. 1 is a diagram showing an operation of handling an exception while executing a copy command in an operation method of a storage device according to an embodiment. Figures 8 to 10 The same additional description is given as the description.

[0125] In operation S410, the host device may send a copy command with a background copy flag set (e.g., set to "1h") to the storage device. The copy command may include a source LBA (SLBA) indicating a source range entry and a destination LBA (DLBA) as a logical address to which data is to be copied. That is, a background copy flag of a submission queue entry SQE corresponding to the copy command may be set, and the submission queue entry SQE may include a source LBA (SLBA) and a destination LBA (DLBA).

[0126] In operation S420, the storage device may update the mapping table.

[0127] In operation S430, the storage device may notify the host device that the copy is complete. For example, the storage device may publish a completion queue entry CQE in which a flag indicating that the execution of the copy command is completed is set to the completion queue CQ.

[0128] In operation S440 , the storage device may receive a read command for reading data from a destination LBA (DLBA) before executing internal read and write commands corresponding to the copy command.

[0129] In operation S450 , the storage device may check the physical address PA mapped to the source LBA (SLBA) with reference to the updated mapping table, and may read data from the physical address PA of the nonvolatile memory device.

[0130] In operation S460 , the storage device may transmit data read from a physical address PA mapped to a source LBA (SLBA) of the nonvolatile memory device to the host device.

[0131] In operation S470 , the storage device may perform operations corresponding to the internal read command and the internal write command based on the updated mapping table.

[0132] That is, after the storage device notifies the host device that the copy command is fully executed, the storage device may receive a read command at a different time point (i.e., before and / or after the operation corresponding to the internal read command and the internal write command is executed). The read commands received at different time points may indicate a read operation on data at the same logical address. In this case, the storage device may read data stored at different physical addresses in response to the read command, and may send the read data to the host device.

[0133] According to an embodiment, handling an abnormal operation while executing a copy command can safely handle an abnormal operation that can occur by notifying the host device of completion of the copy command before executing an internal read command and an internal write command.

[0134] A storage device according to various embodiments may efficiently execute a copy command.

[0135] While the present disclosure has been described with reference to various embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims.

Claims

1. A method for operating a storage device, the storage device comprising a non-volatile storage device and a controller for controlling the non-volatile storage device, the method comprising: receiving, by the controller, from a host device, a first logical address of at least one source range entry, a second logical address of a destination range entry, and a first copy command including a first flag indicating that background copy is set; Based on the first flag indicating that the background copy is set, mapping, at the controller, a first physical address to the second logical address; at the controller, mapping a second physical address to at least one of the second logical address and the first physical address; The controller sends a first notification of completing the first copy command to the host device; as well as After the controller sends the first notification, at the nonvolatile memory device, first data stored at the first physical address is read, and the first data is written at the second physical address.

2. The operating method according to claim 1, wherein: The sending includes: A completion queue entry associated with the first copy command is posted, by the controller, to a completion queue of the host device.

3. The operating method according to claim 1, wherein: Mapping the first physical address to the second logical address comprises: At the controller, the first physical address mapped to the first logical address is mapped to the second logical address.

4. The operating method according to claim 3, wherein: At least a portion of the first physical address includes a plurality of non-contiguous physical addresses, and The second physical address includes a plurality of consecutive physical addresses.

5. The operating method according to claim 3, further comprising: receiving, by the controller, a read command for the second logical address from the host device after sending the first notification and before writing the first data at the second physical address; Based on the read command, reading the first data stored at the first physical address at the nonvolatile memory device under the control of the controller; as well as The controller sends the first data to the host device.

6. The operating method according to claim 3, further comprising: After sending the first notification, receiving, by the controller, a first read command for the second logical address from the host device at a first time point, and receiving a second read command for the second logical address at a second time point different from the first time point; Based on the first read command and the second read command, reading data respectively stored at different physical addresses at the non-volatile memory device; as well as The controller sends the read data to the host device.

7. The operating method according to claim 1, further comprising: Before receiving the first copy command: receiving, by the controller, from the host device, an identification command requesting a controller data structure; Based on the identification command, the controller sends the controller data structure to the host device, in which the first flag is set to the background copy and a second flag associated with whether a copy command is supported is set; as well as A completion queue entry associated with the identify command is posted, by the controller, to a completion queue of the host device.

8. The operating method according to claim 1, further comprising: generating, at the controller, a first copy descriptor associated with and based on the first copy command; receiving, by the controller, a second copy command; generating, at the controller, a second copy descriptor associated with the second copy command; as well as At the controller, inserting the first copy descriptor and the second copy descriptor into a background copy queue in the order in which the first copy command and the second copy command are received, Each of the first copy command and the second copy command includes the first flag indicating that the background copy is set.

9. The operating method according to claim 8, wherein: Each of the first copy descriptor and the second copy descriptor includes the first logical address and the second logical address.

10. The operating method according to claim 8, further comprising: receiving, by the controller, a third copy command from the host device; At the controller, checking available space of the background copy queue; as well as When the available space of the background copy queue is insufficient to store the first copy descriptor and the second copy descriptor, the controller publishes a completion queue entry with a completion flag cleared to a completion queue of the host device, The third copy command includes the first flag indicating that the background copy is set.

11. The operating method according to claim 1, further comprising: Based on the first data being completely written at the second physical address, the controller sends an asynchronous event request to the host device to notify the host device that the first data is completely written.

12. The operating method according to claim 1, wherein: The first logical address is associated with a first logical space identified by a first identifier, the second logical address is associated with a second logical space identified by a second identifier, and the first logical space and the second logical space are located at a same location of the storage device.

13. A storage device, comprising: at least one non-volatile memory device configured to: store or read data; as well as a controller configured to: control the at least one nonvolatile memory device and execute a command provided from a host device, Wherein, the controller is at least further configured to: receiving from the host device a first logical address of at least one source range entry, a second logical address of a destination range entry, and a first copy command including a first flag indicating that a background copy is set; Based on the first copy command, mapping the first physical address to the second logical address; mapping a second physical address to at least one of the second logical address and the first physical address; Sending a first notification of completing the first copy command to the host device; After sending the first notification, reading first data stored at the first physical address; and The first data is written at the second physical address.

14. The storage device according to claim 13, wherein: The controller is configured to: generating a first copy descriptor associated with the first copy command; generating, based on receiving a second copy command, a second copy descriptor associated with the second copy command; as well as inserting the first copy descriptor and the second copy descriptor into a background copy queue in the order in which the first copy command and the second copy command are received, Each of the first copy command and the second copy command includes the first flag indicating that the background copy is set.

15. The storage device according to claim 14, wherein: Each of the first copy descriptor and the second copy descriptor includes the first logical address and the second logical address.

16. The storage device according to claim 14, wherein: The controller is configured to: Based on receiving the third copy command, checking the available space of the background copy queue; as well as When the available space is insufficient to store the first copy descriptor and the second copy descriptor, a completion queue entry with a completion flag cleared is posted to the completion queue of the host device, and The third copy command includes the first flag indicating that the background copy is set.

17. The storage device according to claim 13, wherein: The controller is configured to: Based on the first data being completely written at the second physical address, an asynchronous event request is sent to the host device to notify the host device that the first data is completely written.

18. The storage device according to claim 13, wherein: The first logical address is associated with a first logical space identified by a first identifier, the second logical address is associated with a second logical space identified by a second identifier, and the first logical space and the second logical space are located at a same location of the storage device.

19. The storage device according to claim 13, wherein: The controller complies with the Non-Volatile Memory Express (NVMe) protocol.

20. A storage device comprising: at least one non-volatile memory device configured to: store or read data; as well as a controller configured to: control the at least one nonvolatile memory device and execute a command provided from a host device, Wherein, the controller is at least further configured to: receiving, from the host device, a copy command including a flag indicating that background copying is set; Based on the copy command, updating a mapping table, in which logical addresses and physical addresses are mapped according to a one-to-one correspondence; After updating the mapping table, sending a completion notification of the copy command to the host device; and After sending the completion notification, the at least one nonvolatile memory device is controlled to perform a data read operation or a data write operation corresponding to the copy command.

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