Processor, method and system for dynamically switching RISC-V and X86 instruction sets

Abstract

The invention discloses a processor, method and system for dynamically switching RISC-V and X86 instruction sets. The processor comprises an instruction reading unit, a translation unit and an instruction processing unit. The instruction reading unit comprises a state machine and a trigger circuit, the instruction reading unit receives an instruction stream and transmits the instruction stream to the state machine, and a target instruction sequence is arranged between any adjacent X86 instruction sequence and RISC-V instruction sequence in the instruction stream; the state machine sends a trigger signal to the trigger circuit when receiving the target instruction sequence, otherwise, the trigger signal is not sent; when the trigger circuit receives the trigger signal, the current state of connecting one of the translation unit and the instruction processing unit is switched to the state of connecting the other one of the translation unit and the instruction processing unit; the translation unit is used for translating the X86 instruction sequence into an RISC-V instruction sequence; the instruction processing unit is used for processing the RISC-V instruction sequence. According to the invention, the RISC-V instruction and the X86 instruction can be dynamically switched and processed.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a processor, method and system for dynamically switching between RISC-V and X86 instruction sets. Background Art

[0002] With the continuous development of computer technology, instruction set architecture is also evolving. There are differences in instruction sets between different processor architectures, which may lead to compatibility issues when applications under the same operating system run on processors with different instruction set architectures. Since traditional general-purpose processors usually use a fixed instruction set architecture, existing processors usually cannot meet the needs of running different instruction sets, and have problems such as insufficient flexibility and difficulty in meeting different application scenarios.

[0003] At present, the compatibility issues between different instruction set architectures are mainly solved by software translation and hardware translation. Software translation technology can achieve compatibility across instruction sets, but the translation process is time-consuming, which affects the real-time response capability of the system; hardware translation attempts to achieve instant conversion of different instruction sets at the hardware level, but due to the high complexity of hardware design and the difficulty in supporting the efficient operation of multiple instruction sets at the same time, it also has certain limitations.

[0004] Existing technologies generally face problems such as low efficiency and high cost when solving compatibility issues of different instruction set architectures. Although software translation can solve compatibility issues, it introduces additional processing time and reduces the overall performance of the system; while hardware translation can improve compatibility to a certain extent, it is limited by the complexity and cost of hardware design and is difficult to be widely used in various embedded systems.

[0005] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0006] The purpose of the present invention is to provide a processor, method and system for dynamically switching RISC-V and X86 instruction sets, which can dynamically switch and process RISC-V instructions and X86 instructions, and realize fast and efficient processing of instruction streams including RISC-V instructions and X86 instructions.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows: A processor for dynamically switching between RISC-V and X86 instruction sets, comprising an instruction reading unit, a translation unit and an instruction processing unit; The instruction reading unit includes a state machine and a trigger circuit, and the instruction reading unit is configured to receive an instruction stream to be processed and transmit it to the state machine, the instruction stream includes an X86 instruction sequence and a RISC-V instruction sequence, and a target instruction sequence is configured between any adjacent X86 instruction sequence and RISC-V instruction sequence; The state machine is configured to send a trigger signal to the trigger circuit in response to receiving the target instruction sequence, and otherwise not send a trigger signal to the trigger circuit; The trigger circuit is configured to be electrically connected to one of the translation unit and the instruction processing unit, and in response to receiving the trigger signal, the trigger circuit switches from a state of currently connecting to one of the translation unit and the instruction processing unit to a state of connecting to the other of the translation unit and the instruction processing unit; The translation unit is configured to translate the X86 instruction sequence into a RISC-V instruction sequence; The instruction processing unit is configured to process the RISC-V instruction sequence.

[0008] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the instruction reading unit is also configured to transmit the received instruction stream to the state machine and the trigger circuit at the same time.

[0009] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the state machine includes a counter, and the counter is configured to count according to the target instruction sequence to obtain a target count value, and the target count value is unique; In response to the count of the counter being the target count value, the state machine sends a trigger signal to the trigger circuit.

[0010] Further, based on any of the above-mentioned technical solutions or a combination of multiple technical solutions, the size of the target instruction sequence is not less than the size of the cache line of the processor. Preferably, the size of the target instruction sequence is equal to the size of the cache line of the processor, or the size of the target instruction sequence is several times the size of the cache line of the processor. The cache line of the processor is a basic unit in the processor cache system, which is used to transfer and store data between the processor and the memory. The cache line is the smallest unit for storing data in the processor cache.

[0011] Further, based on any of the above-mentioned technical solutions or a combination of multiple technical solutions, the number of single instructions included in the target instruction sequence is not less than the number of pipeline stages of the processor. Preferably, the number of single instructions included in the target instruction sequence is equal to the number of pipeline stages of the processor, or the number of single instructions included in the target instruction sequence is several times the number of pipeline stages of the processor. Pipeline architecture means that the processor decomposes the execution process of an instruction into several consecutive steps or stages, and each stage in the processor is performed by a dedicated hardware unit corresponding to the task.

[0012] Further, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes: for adjacent X86 instruction sequences and RISC-V instruction sequences, determining that an instruction set corresponding to the previous instruction sequence is a target instruction set, wherein the instruction set includes a RISC-V instruction set and an X86 instruction set; The target instruction sequence is configured as the corresponding instruction sequence in the target instruction set, that is, if in adjacent different instruction sequences, if the previous instruction sequence is a RISC-V instruction sequence, then the target instruction sequence is the instruction in the RISC-V instruction set; if the previous instruction sequence is an X86 instruction sequence, then the target instruction sequence is the instruction in the X86 instruction set.

[0013] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the target instruction sequence includes a plurality of consecutive empty instructions; The counter is incremented by one in response to receiving a null instruction, otherwise the counter is reset.

[0014] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, if the instruction sequence first received by the state machine is an X86 instruction sequence, the state machine sends a first signal to the trigger circuit, and the trigger circuit is electrically connected to the translation unit in response to receiving the first signal; If the instruction sequence first received by the state machine is a RISC-V instruction sequence, the state machine sends a second signal to the trigger circuit, and the trigger circuit is electrically connected to the instruction processing unit in response to receiving the second signal.

[0015] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, after the processor starts working each time, the first group of instruction sequences in the instruction stream are all X86 instruction sequences; After the processor starts working each time, the initial state of the trigger circuit is configured to be electrically connected to the translation unit.

[0016] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, after the processor starts working each time, the first group of instruction sequences in the instruction stream are all RISC-V instruction sequences; After the processor starts working each time, the initial state of the trigger circuit is configured to be electrically connected to the instruction processing unit.

[0017] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the translation unit is configured as a hardware translator, and the hardware translator is configured to translate the X86 instruction sequence into a RISC-V instruction sequence by calling an instruction processing result pre-stored in a hardware device; The instruction processing result includes a mapping relationship between the X86 instruction sequence and the RISC-V instruction sequence.

[0018] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the instruction processing result is obtained by the following method: For any X86 instruction sequence in the target X86 instruction set; Determine whether there is an equivalent RISC-V standard instruction sequence that replaces the X86 instruction sequence, the function of the equivalent RISC-V standard instruction sequence is consistent with the function of the X86 instruction sequence and the difference in execution efficiency between the two is within a preset range, and if so, determine that the X86 instruction sequence is the first instruction sequence, and determine that the equivalent RISC-V standard instruction sequence is the second instruction sequence; If not, determining whether there is a non-equivalent RISC-V standard instruction sequence that replaces the X86 instruction sequence; if so, determining whether the execution efficiency of the non-equivalent RISC-V standard instruction sequence meets a preset requirement; if so, determining that the X86 instruction sequence is the third instruction sequence, and determining that the non-equivalent RISC-V standard instruction sequence is the fourth instruction sequence; If not satisfied, determining a RISC-V custom instruction sequence to replace the X86 instruction sequence, determining the X86 instruction sequence to be the fifth instruction sequence, and determining the RISC-V custom instruction sequence to be the sixth instruction sequence; Based on the above steps, the instruction sequence processing result is obtained and stored in a hardware device, and the instruction sequence processing result includes: Taking the first instruction sequence as input, the second instruction sequence as output; Taking the third instruction sequence as input, the fourth instruction sequence as output; The fifth instruction sequence is taken as input, and the sixth instruction sequence is taken as output.

[0019] Further, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes obtaining the instruction processing result by the following method: For any X86 instruction sequence in the target X86 instruction set; If there is no equivalent RISC-V standard instruction sequence to replace the X86 instruction sequence, and there is no non-equivalent RISC-V standard instruction sequence to replace the X86 instruction sequence; Then a RISC-V custom instruction sequence is determined to replace the X86 instruction sequence, and the X86 instruction sequence is determined to be the fifth instruction sequence, and the RISC-V custom instruction sequence is determined to be the sixth instruction sequence.

[0020] According to another aspect of the present invention, a processing method for dynamically switching between RISC-V and X86 instruction sets is provided, wherein the instruction stream to be processed includes an X86 instruction sequence and a RISC-V instruction sequence, and the method includes the following steps: A trigger circuit is pre-configured, the trigger circuit includes an input end and two output ends, the input end is selectively electrically connected to the two output ends, one of the output ends is electrically connected to the translation unit, and the other output end is electrically connected to the instruction processing unit; wherein the translation unit is configured to translate the X86 instruction sequence into a RISC-V instruction sequence, and the instruction processing unit is configured to process the RISC-V instruction sequence; in this way, the trigger circuit can selectively control the instruction stream to pass through one of two transmission paths, wherein one transmission path is that the instruction stream is translated by the translation unit and then input into the instruction processing unit, and the other transmission path is that the instruction stream is directly input into the instruction processing unit; Configure a target instruction sequence between any adjacent X86 instruction sequence and RISC-V instruction sequence in the instruction stream to be processed; The state machine is used to monitor the instruction stream to be processed, and if the state machine detects the target instruction sequence, a trigger signal is generated and transmitted to the trigger circuit; In response to receiving the trigger signal, the trigger circuit switches the input terminal currently connected to one of the output terminals to be connected to another of the output terminals, thereby switching the transmission / processing path of the instruction stream.

[0021] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the processing method for dynamically switching RISC-V and X86 instruction sets further includes the following steps: The state machine is configured to detect the target instruction sequence using a counter, and the counter is configured to count according to the target instruction sequence to obtain a target count value, and the target count value is unique; In response to the count value of the counter being the target count value, the state machine sends a trigger signal to the trigger circuit.

[0022] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, the processing method for dynamically switching RISC-V and X86 instruction sets also includes: the size of the target instruction sequence is equal to the size of the cache line of the processor.

[0023] According to another aspect of the present invention, the present invention provides a computer system, comprising a processor for dynamically switching RISC-V and X86 instruction sets as described in any one of the above technical solutions or a combination of multiple technical solutions.

[0024] The beneficial effects brought by the technical solution provided by the present invention are as follows: a. The present invention realizes dynamic switching of corresponding instruction stream processing circuits according to changes of RISC-V and X86 instructions in the instruction stream by adding a state machine for monitoring the input instruction stream and a trigger circuit for controlling the transmission direction of the instruction stream in the processor, and quickly dynamically switches the processed instruction set architecture through hardware, thereby increasing the processor's efficient compatibility with different instruction set architectures and the portability and versatility of the program, and also reducing the development and maintenance costs of products such as programs and processors; b. The technical solution provided by the present invention can realize instruction set switching through the hardware interface by introducing a state machine and a trigger circuit, thereby simplifying the hardware design, reducing the hardware complexity and cost, making the technology more easily and widely used, more suitable for embedded systems and IoT devices with limited resources, and having a wide range of applications; c. The present invention sets the size of the target instruction sequence to be the same as the size of the processor's cache line, and the number of single instructions included in the target instruction sequence is equal to the number of pipeline stages of the processor, thereby ensuring that the data in the registers and arithmetic logic units on the processor pipeline are executed and stored in the memory, and can ensure that the instruction set switching will not interrupt the workflow of the processor, thereby improving the real-time response capability and overall performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1A flowchart of a processor for dynamically switching between RISC-V and X86 instruction sets provided for an exemplary embodiment of the present invention; Figure 2 A schematic diagram of a processor architecture for dynamically switching between RISC-V and X86 instruction sets provided for an exemplary embodiment of the present invention; Figure 3 A schematic diagram of a transmission path of an instruction stream in a processor is provided for an exemplary embodiment of the present invention; Figure 4 A schematic diagram of the working principle of a state machine provided for an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0029] In one embodiment of the present invention, a processor for dynamically switching between RISC-V and X86 instruction sets is provided, wherein the processor is configured to dynamically switch between running a RISC-V instruction sequence and an X86 instruction sequence without interrupting the workflow. Based on this, when the computer is running, the instruction set architecture to be processed can be dynamically switched quickly through hardware to process different instruction sets.

[0030] See also Figure 1 and Figure 2 , the processor includes an instruction reading unit, a translation unit and an instruction processing unit; The instruction reading unit includes a state machine and a trigger circuit, and the instruction reading unit is configured to receive an instruction stream to be processed and transmit it to the state machine, the instruction stream includes an X86 instruction sequence and a RISC-V instruction sequence, and a target instruction sequence is configured between any adjacent X86 instruction sequence and RISC-V instruction sequence; The state machine is configured to send a trigger signal to the trigger circuit in response to receiving the target instruction sequence, and otherwise not send a trigger signal to the trigger circuit; The trigger circuit is configured to be electrically connected to one of the translation unit and the instruction processing unit, and in response to receiving the trigger signal, the trigger circuit switches from a state of currently connecting to one of the translation unit and the instruction processing unit to a state of connecting to the other of the translation unit and the instruction processing unit; The translation unit is configured to translate the X86 instruction sequence into a RISC-V instruction sequence; The instruction processing unit is configured to process the RISC-V instruction sequence.

[0031] The trigger circuit includes an input terminal and two output terminals, wherein the input terminal can be selectively electrically connected to one of the two output terminals, and the trigger circuit switches its input terminal from the current state of being electrically connected to one output terminal to the state of being electrically connected to the other output terminal in response to receiving the trigger signal. One of the two output terminals of the trigger circuit is electrically connected to the translation unit, and the other is electrically connected to the instruction processing unit; the translation unit is electrically connected to the instruction processing unit.

[0032] In one embodiment of the present invention, see Figure 3 , the input port of the instruction reading unit is electrically connected to the state machine and the trigger circuit respectively, and the instruction stream received by the instruction reading unit is transmitted to the state machine and the trigger circuit at the same time. In this embodiment, the state machine is only configured to monitor the target instruction sequence in the instruction stream, and it is not configured to transmit the instruction stream to the trigger circuit. When the state machine detects the target instruction sequence, it jumps its sub-state to send a trigger signal to the trigger circuit, prompting the connection state of the trigger circuit to change. In this embodiment, the instruction stream is directly transmitted to the trigger circuit and then passes through one of the two transmission paths. This method can ensure that the switching of instruction sets can be carried out without interrupting the normal working process of the CPU, improve the compatibility and flexibility of the CPU, and will not extend the transmission path of the instruction stream, which can ensure the processing efficiency of cross-architecture instruction sets.

[0033] In this embodiment, the working principle of the state machine is as follows: Figure 4As shown, the state machine includes a counter, and the counter is configured to count according to the target instruction sequence to obtain a target count value, and the target count value is unique. In response to the count of the counter being the target count value, the state machine sends a trigger signal to the trigger circuit.

[0034] Specifically, the target instruction sequence includes a plurality of consecutive empty instructions; the counter is incremented by one in response to receiving an empty instruction, otherwise the counter is reset. Preferably, the size of the target instruction sequence is equal to the size of the cache line of the processor. And the number of the empty instructions is the same as the number of stages of the pipeline architecture of the processor.

[0035] The state machine synchronously receives the instruction binary code stream and detects a specific string (4-byte NOP instruction) of several cache lines, i.e., the target instruction sequence ( Figure 3 The number of bits of the specific string is the number of pipeline stages divided by 16 and rounded up to ensure that it is equal to the size of the cache line of the processor. This setting method can ensure that before switching the X86 or RISC-V instruction, the previous RISC-V or X86 instruction is completely executed in the CPU pipeline, thereby avoiding data errors in the CPU register due to switching the running instruction set, and ensuring the integrity and security of the data.

[0036] like Figure 4 As shown, in a 16-stage pipeline architecture, the cache line size is 64Byte, and the empty instructions of the X86 architecture and the RISC-V architecture are 4 bytes 0x0F1F4000 and 0x00000013 respectively. When the state machine is in X86 mode, it detects an empty instruction of 1 cache line (the target instruction sequence represented by the X86 instruction), that is, 16 consecutive (0x0F1F4000), the state machine jumps to the first sub-state to switch to RISC-V mode, and the state machine sends a trigger signal to the trigger circuit to change the connection state of the trigger circuit, so that the binary code stream enters the instruction reading unit and then directly enters the instruction processing unit.

[0037] When the state machine is in RISC-V mode and detects an empty instruction of one cache line, that is, 16 consecutive empty instructions (0x00000013), the state machine jumps to the second sub-state to switch to X86 mode. The state machine sends a trigger signal to the trigger circuit to change the connection state of the trigger circuit, so that the binary code stream enters the instruction reading unit and then passes through the translation unit, and then enters the instruction processing unit after being translated into RISC-V instructions by the translation unit.

[0038] Wherein, the translation unit is preferably a hardware translator, and the hardware translator is configured to translate the X86 instruction sequence into a RISC-V instruction sequence by calling the instruction processing result pre-stored in the hardware device; the instruction processing result includes a mapping relationship between the X86 instruction sequence and the RISC-V instruction sequence. The use of this hardware translation method can avoid the delay problem caused by traditional software translation, and also reduce the problem that the existing hardware cannot be dynamically translated, and reduce the complexity and cost of hardware translation.

[0039] In one embodiment of the present invention, the technical solution proposed in the Chinese patent application with application number 2025101518660 is used to obtain the instruction processing result in the following manner: for any X86 instruction sequence in the target X86 instruction set; it is determined whether there is an equivalent RISC-V standard instruction sequence to replace the X86 instruction sequence, and the function of the equivalent RISC-V standard instruction sequence is consistent with the function of the X86 instruction sequence and the execution efficiency difference between the two is within a preset range. If so, the X86 instruction sequence is determined to be the first instruction sequence, and the equivalent RISC-V standard instruction sequence is determined to be the second instruction sequence.

[0040] If not, determine whether there is a non-equivalent RISC-V standard instruction sequence that replaces the X86 instruction sequence. If so, determine whether the execution efficiency of the non-equivalent RISC-V standard instruction sequence meets the preset requirements. If so, determine that the X86 instruction sequence is the third instruction sequence, and determine that the non-equivalent RISC-V standard instruction sequence is the fourth instruction sequence. If not, determine a RISC-V custom instruction sequence that replaces the X86 instruction sequence, determine that the X86 instruction sequence is the fifth instruction sequence, and determine that the RISC-V custom instruction sequence is the sixth instruction sequence.

[0041] If there is no equivalent RISC-V standard instruction sequence to replace the X86 instruction sequence, and there is no non-equivalent RISC-V standard instruction sequence to replace the X86 instruction sequence; then determine a RISC-V custom instruction sequence to replace the X86 instruction sequence, determine the X86 instruction sequence to be the fifth instruction sequence, and determine the RISC-V custom instruction sequence to be the sixth instruction sequence.

[0042] Based on the above steps, an instruction sequence processing result is obtained and stored in a hardware device, wherein the instruction sequence processing result includes: taking the first instruction sequence as input, the second instruction sequence as output; taking the third instruction sequence as input, the fourth instruction sequence as output; taking the fifth instruction sequence as input, the sixth instruction sequence as output.

[0043] In one embodiment of the present invention, if the instruction sequence received by the state machine for the first time is an X86 instruction sequence, it sends a first signal to the trigger circuit, and the trigger circuit is electrically connected to the translation unit in response to receiving the first signal. If the instruction sequence received by the state machine for the first time is a RISC-V instruction sequence, it sends a second signal to the trigger circuit, and the trigger circuit is electrically connected to the instruction processing unit in response to receiving the second signal. Specifically, it can be distinguished and judged whether the instruction received by the processor is an X86 instruction sequence or a RISC-V instruction sequence after each startup according to the difference in operands. This embodiment is applicable to application scenarios where it is unclear whether the instruction sequence first processed by the processor after each startup is an X86 instruction sequence or a RISC-V instruction sequence.

[0044] In one embodiment of the present invention, after the processor starts working each time, the first group of instruction sequences in the instruction stream are all X86 instruction sequences; after the processor starts working each time, the initial state of the trigger circuit is configured to be electrically connected to the translation unit. This embodiment is applicable to application scenarios in which the first instruction processed by the processor after each startup is an X86 instruction, and RISC-V instructions may be processed in subsequent work processes.

[0045] In one embodiment of the present invention, after the processor starts working each time, the first group of instruction sequences in the instruction stream are all RISC-V instruction sequences. After the processor starts working each time, the initial state of the trigger circuit is configured to be electrically connected to the instruction processing unit. This embodiment is applicable to application scenarios in which the first instruction processed by the processor after each startup is a RISC-V instruction, and X86 instructions may be processed in subsequent work processes.

[0046] According to another aspect of the present invention, a processing method for dynamically switching RISC-V and X86 instruction sets is provided, wherein the instruction stream to be processed includes an X86 instruction sequence and a RISC-V instruction sequence, such as Figure 1 As shown, the method comprises the following steps: A trigger circuit is pre-configured, the trigger circuit includes an input end and two output ends, the input end is selectively electrically connected to the two output ends, one of the output ends is electrically connected to the translation unit, and the other output end is electrically connected to the instruction processing unit; wherein the translation unit is configured to translate the X86 instruction sequence into a RISC-V instruction sequence, and the instruction processing unit is configured to process the RISC-V instruction sequence; in this way, the trigger circuit can selectively control the instruction stream to pass through one of two transmission paths, wherein one transmission path is that the instruction stream is translated by the translation unit and then input into the instruction processing unit, and the other transmission path is that the instruction stream is directly input into the instruction processing unit; Configure a target instruction sequence between any adjacent X86 instruction sequence and RISC-V instruction sequence in the instruction stream to be processed; Detecting the instruction stream to be processed by a state machine, and generating a trigger signal and transmitting it to the trigger circuit if the state machine detects the target instruction sequence; In response to receiving the trigger signal, the trigger circuit switches the input terminal currently connected to one of the output terminals to be connected to another of the output terminals, thereby switching the transmission path of the instruction stream.

[0047] Preferably, the state machine is configured to detect the target instruction sequence using a counter, and the counter is configured to count according to the target instruction sequence to obtain a target count value, and the target count value is unique; the state machine sends a trigger signal to the trigger circuit in response to the count value of the counter being the target count value.

[0048] In one embodiment of the present invention, a computer system is provided, comprising a processor for dynamically switching between RISC-V and X86 instruction sets as described in any one of the above embodiments or a combination of multiple embodiments.

[0049] It should be noted that the processing method and computer system embodiment for dynamically switching RISC-V and X86 instruction sets provided by the present invention are the same as the inventive concept of the processor embodiment for dynamically switching RISC-V and X86 instruction sets mentioned above, and all the contents of the processor embodiment for dynamically switching RISC-V and X86 instruction sets are incorporated into the processing method and computer system embodiment for dynamically switching RISC-V and X86 instruction sets by introduction.

[0050] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0051] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A processor that dynamically switches between RISC-V and X86 instruction sets, characterized in that: It includes an instruction reading unit, a translation unit and an instruction processing unit; The instruction reading unit includes a state machine and a trigger circuit, and the instruction reading unit is configured to receive an instruction stream to be processed and transmit it to the state machine, the instruction stream includes an X86 instruction sequence and a RISC-V instruction sequence, and a target instruction sequence is configured between any adjacent X86 instruction sequence and RISC-V instruction sequence; The state machine is configured to send a trigger signal to the trigger circuit in response to receiving the target instruction sequence, and otherwise not send a trigger signal to the trigger circuit; The trigger circuit is selectively electrically connected to one of the translation unit and the instruction processing unit, and in response to receiving the trigger signal, the trigger circuit switches from a state of currently connecting to one of the translation unit and the instruction processing unit to a state of connecting to the other of the translation unit and the instruction processing unit; The translation unit is configured to translate the X86 instruction sequence into a RISC-V instruction sequence; The instruction processing unit is configured to process the RISC-V instruction sequence.

2. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 1, characterized in that: The instruction reading unit is further configured to transmit the received instruction stream to the state machine and the trigger circuit simultaneously.

3. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 1, characterized in that: The state machine includes a counter, wherein the counter is configured to count according to the target instruction sequence to obtain a target count value, wherein the target count value is unique; In response to the count of the counter being the target count value, the state machine sends a trigger signal to the trigger circuit.

4. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 3, characterized in that: The size of the target instruction sequence is not less than the size of the cache line of the processor; and / or, The number of single instructions included in the target instruction sequence is not less than the number of pipeline stages of the processor.

5. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 4, characterized in that: The size of the target instruction sequence is the same as the size of a cache line of the processor; and / or, The number of single instructions included in the target instruction sequence is equal to the number of pipeline stages of the processor.

6. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 3, characterized in that: Also includes: For adjacent X86 instruction sequences and RISC-V instruction sequences, determining an instruction set corresponding to the previous instruction sequence as a target instruction set, wherein the instruction set includes a RISC-V instruction set and an X86 instruction set; The target instruction sequence is configured as a corresponding instruction sequence in the target instruction set.

7. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 3, characterized in that: The target instruction sequence includes a plurality of consecutive empty instructions; The counter is incremented by one in response to receiving a null instruction, otherwise the counter is reset.

8. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 1, characterized in that: If the instruction sequence first received by the state machine is an X86 instruction sequence, the state machine sends a first signal to the trigger circuit, and the trigger circuit is electrically connected to the translation unit in response to receiving the first signal; If the instruction sequence first received by the state machine is a RISC-V instruction sequence, the state machine sends a second signal to the trigger circuit, and the trigger circuit is electrically connected to the instruction processing unit in response to receiving the second signal.

9. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 1, characterized in that: After the processor starts working each time, the first group of instruction sequences in the instruction stream are all X86 instruction sequences; After the processor starts working each time, the initial state of the trigger circuit is configured to be electrically connected to the translation unit.

10. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 1, characterized in that: After the processor starts working each time, the first group of instruction sequences in the instruction stream are all RISC-V instruction sequences; After the processor starts working each time, the initial state of the trigger circuit is configured to be electrically connected to the instruction processing unit.

11. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 1, characterized in that: The translation unit is configured as a hardware translator, and the hardware translator is configured to translate the X86 instruction sequence into a RISC-V instruction sequence by calling an instruction processing result pre-stored in a hardware device; The instruction processing result includes a mapping relationship between the X86 instruction sequence and the RISC-V instruction sequence.

12. A processing method for dynamically switching between RISC-V and X86 instruction sets, characterized in that: The instruction stream to be processed includes an X86 instruction sequence and a RISC-V instruction sequence, and the method includes the following steps: Pre-configure a trigger circuit, the trigger circuit includes an input terminal and two output terminals, the input terminal is selectively electrically connected to the two output terminals, one of the output terminals is electrically connected to the translation unit, and the other output terminal is electrically connected to the instruction processing unit; wherein the translation unit is configured to translate the X86 instruction sequence into the RISC-V instruction sequence, and the instruction processing unit is configured to process the RISC-V instruction sequence; Configure a target instruction sequence between any adjacent X86 instruction sequence and RISC-V instruction sequence in the instruction stream to be processed; The state machine is used to monitor the instruction stream to be processed, and if the state machine detects the target instruction sequence, a trigger signal is generated and transmitted to the trigger circuit; In response to receiving the trigger signal, the trigger circuit switches the input terminal currently connected to one of the output terminals to be connected to another of the output terminals.

13. The method for dynamically switching RISC-V and X86 instruction sets according to claim 12, characterized in that: The following steps are also included: The state machine is configured to detect the target instruction sequence using a counter, and the counter is configured to count according to the target instruction sequence to obtain a target count value, and the target count value is unique; In response to the count value of the counter being the target count value, the state machine sends a trigger signal to the trigger circuit.

14. A computer system, characterized in that: A processor comprising a processor for dynamically switching between RISC-V and X86 instruction sets as described in any one of claims 1 to 11.

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