Mainboard interface self-adaptive configuration method and computer

Abstract

The invention provides a self-adaptive configuration method for a mainboard interface, which is executed in a BIOS (Basic Input / Output System) and comprises the following steps of: judging a current configuration mode according to a mode flag bit stored in a nonvolatile memory during startup and electrification; when the configuration mode is an automatic configuration mode, reading record information of each interface on a mainboard from a register of a field programmable gate array (FPGA) on the mainboard; and when the recorded information of each interface is successfully read, configuring each interface on the mainboard according to the recorded information. According to the self-adaptive configuration method of the mainboard interface and the computer, self-adaptive configuration of each interface on the mainboard can be achieved, and the requirement for professional knowledge or repeated power-on is avoided.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method for adaptively configuring a mainboard interface and a computer. Background Art

[0002] Due to multiple factors such as application scenarios and costs, different customers or even the same customer will have different configuration requirements for the same server product. Among them, the allocation and layout of the CPU direct high-speed channel depends on the motherboard (hardware wiring, etc.). On the motherboard, physical interfaces such as MCIO interface, M.2 slot, Slim-SAS and PCIe slot need to be reserved according to customer needs. Based on these reserved physical interfaces, different external cards (such as Riser card, NVMe backplane, SATA backplane, etc.) will be connected to expand slots that can connect different types of devices (such as NVMe SSD, x4 / x8 / x16 PCIe network card, SATA SSD, etc.). Different slots need to configure the corresponding CPU direct channel with different types and bandwidths. This step is generally completed by modifying the interface provided in the BIOS Setup setting interface, or by modifying the BIOS Code. Neither of these two methods can achieve efficient and flexible configuration modification, and requires a lot of time and manpower, which is not conducive to subsequent server maintenance. Summary of the invention

[0003] The adaptive configuration method of the mainboard interface and the computer provided by the present invention can realize the adaptive configuration of each interface on the mainboard, avoiding the need for professional knowledge or the need for repeated power-on.

[0004] In a first aspect, the present invention provides a method for adaptively configuring a motherboard interface, which is executed in a basic input / output system BIOS, and the method comprises:

[0005] When the device is powered on, the current configuration mode is determined based on the mode flag stored in the non-volatile memory;

[0006] When the configuration mode is the automatic configuration mode, reading the record information of each interface on the mainboard from the register of the field programmable gate array FPGA on the mainboard;

[0007] When the record information of each interface is successfully read, each interface on the mainboard is configured according to the record information.

[0008] Optionally, when the device is powered on, after determining the current configuration mode according to the mode flag bit stored in the non-volatile memory, the method further comprises:

[0009] When the configuration mode is a manual configuration mode, receiving a setting option selected by a user in the non-volatile memory through an interactive interface or a remote command;

[0010] When the setting options are successfully obtained, each interface on the mainboard is configured according to the setting options.

[0011] Optionally, after receiving the setting option selected by the user in the non-volatile memory through an interactive interface or a remote command, the method further includes:

[0012] When the setting options are not successfully obtained, each interface on the mainboard is configured according to a preset default configuration.

[0013] Optionally, after reading the record information of each interface on the mainboard from the register of the field programmable gate array FPGA on the mainboard, the method further comprises:

[0014] When the record information of each interface is not read successfully, each interface on the mainboard is configured according to a preset default configuration.

[0015] Optionally, the method further includes: receiving a mode flag bit selected by a user in the non-volatile memory through an interactive interface or a remote command and storing the selected mode flag bit.

[0016] Optionally, reading the record information of each interface on the mainboard from a register of a field programmable gate array FPGA on the mainboard includes:

[0017] The record information corresponding to each interface is read from each field in the register, wherein the field and the interface have a one-to-one correspondence.

[0018] Optionally, configuring each interface on the mainboard includes:

[0019] The channel type and bandwidth of each interface on the mainboard are configured.

[0020] In a second aspect, the present invention provides an adaptive configuration method for a motherboard interface, which is executed in a field programmable gate array FPGA on a motherboard, and the method comprises:

[0021] When the computer is powered on, the external card information of each interface on the mainboard is read through the hardware circuit;

[0022] According to a preset conversion method, the external card information of each interface is converted into the record information of each interface;

[0023] The record information of each interface is stored in a field corresponding to the register, so that the basic input and output system BIOS can execute any one of the above-mentioned adaptive configuration methods of the mainboard interface executed in the BIOS according to the record information.

[0024] Optionally, storing the record information of each interface in a field corresponding to the register includes:

[0025] Acquire a one-to-one correspondence between a plurality of interfaces on the mainboard and a plurality of fields in the register;

[0026] The record information of each interface is stored in a corresponding field according to the corresponding relationship.

[0027] In a third aspect, the present invention provides a computer, comprising:

[0028] Motherboard,

[0029] A basic input-output system BIOS arranged on a mainboard, wherein the basic input-output system BIOS is used to execute any one of the above-mentioned methods for adaptively configuring the mainboard interface executed in the BIOS;

[0030] A field programmable gate array FPGA is arranged on a mainboard, wherein the field programmable gate array FPGA is used to execute any one of the aforementioned methods for adaptively configuring the mainboard interface executed in the FPGA.

[0031] In the technical solution provided by the present invention, the record information corresponding to each interface can be stored through the register in the FPGA, and each interface can be adaptively configured according to the record information, which does not require the user to have high professional knowledge, nor does it require repeated restart and power-on, which can facilitate user use. At the same time, for development engineers, multiple configuration methods can be pre-configured and adaptively configured when in use, thereby reducing redundant workload. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A flowchart of a method for adaptively configuring a motherboard interface according to an embodiment of the present invention;

[0033] Figure 2a This is a schematic diagram of an exemplary configuration of a method for adaptively configuring a motherboard interface according to another embodiment of the present invention;

[0034] Figure 2b This is a schematic diagram of an exemplary configuration of a method for adaptively configuring a motherboard interface according to another embodiment of the present invention;

[0035] Figure 2c This is a schematic diagram of an exemplary configuration of a method for adaptively configuring a motherboard interface according to another embodiment of the present invention;

[0036] Figure 2d This is a schematic diagram of an exemplary configuration of a method for adaptively configuring a motherboard interface according to another embodiment of the present invention;

[0037] Figure 2e This is a schematic diagram of an exemplary configuration of a method for adaptively configuring a motherboard interface according to another embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] The embodiment of the present invention provides a method for adaptively configuring a motherboard interface. Figure 1 As shown, the method is executed in a basic input and output system BIOS, and includes:

[0040] When the device is powered on, the current configuration mode is determined based on the mode flag stored in the non-volatile memory;

[0041] In some embodiments, in order to achieve adaptive configuration and reserve manual control, a mode flag for mode switching needs to be established; the mode flag includes two modes, 0 and 1. For example, 0 is automatic configuration mode and 1 is manual configuration mode. The two modes are used to implement different ways of configuring the direct channel type and bandwidth of each CPU, that is, the configuration of each interface of the motherboard.

[0042] When the configuration mode is the automatic configuration mode, reading the record information of each interface on the mainboard from the register of the field programmable gate array FPGA on the mainboard;

[0043] In some embodiments, the BIOS reads the FPGA register. For example, in the FPGA register, each interface existing on the motherboard has a corresponding 2-byte (or more, depending on project requirements) record information; based on the recorded two-byte record information, the type (such as PCIe protocol or SATA protocol) and bandwidth (such as x16, x8 or x4) of the corresponding motherboard interface can be configured; a single FPGA register interface field directly corresponds to a single motherboard interface and indirectly corresponds to the CPU direct connection channel group. The interface information includes the configuration type and configuration bandwidth of the interface. The FPGA will identify the external card connected to the motherboard interface, convert it into a negotiated format, and store it in the FPGA register. Each interface field corresponds to a motherboard interface. Each motherboard interface will be automatically identified, judged, recorded and saved, and cannot be manually modified.

[0044] When the record information of each interface is successfully read, each interface on the mainboard is configured according to the record information.

[0045] In some embodiments, different record information corresponds to different external cards and configuration methods. For example, the type of external card connected to the channel interface is divided into NVMe backplane, Riser card-1, Riser card-2, SATA backplane, etc.; the record information can be expressed in hexadecimal format, for example, it can be expressed as follows: 0x00 represents NVMe backplane, 0x01 represents Riser card-1, 0x02 represents Riser card-2, and 0x03 represents SATA backplane.

[0046] In the technical solution provided by the embodiment of the present invention, the record information corresponding to each interface can be stored through the register in the FPGA, and each interface can be adaptively configured according to the record information, which does not require the user to have high professional knowledge, nor does it require repeated restart and power on, which can facilitate user use. At the same time, for development engineers, multiple configuration methods can be pre-configured and adaptively configured when in use, thereby reducing redundant workload.

[0047] As an optional implementation, continue as Figure 1 As shown, when the device is powered on, after determining the current configuration mode according to the mode flag bit stored in the non-volatile memory, the method further includes:

[0048] When the configuration mode is a manual configuration mode, receiving a setting option selected by a user in the non-volatile memory through an interactive interface or a remote command;

[0049] When the setting options are successfully obtained, each interface on the mainboard is configured according to the setting options.

[0050] In some embodiments, in the non-volatile memory NVRAM, each existing interface on the motherboard has a corresponding 1 (or more, depending on project requirements) setting option; each option value of the setting option corresponds to the expected configuration of the interface corresponding to the current setting option in manual mode; in manual mode, the option value of the setting option can be indirectly modified through the remote control software Redfish or directly modified by entering the BIOS setup interface. The value of a single setting option directly corresponds to a single motherboard interface and indirectly corresponds to a CPU direct connection channel group. The value of the setting option will include the configuration type and configuration bandwidth of the interface for manual active selection and will not change automatically. In manual configuration mode, the BIOS reads the setting option value in the non-volatile memory NVRAM, configures the corresponding motherboard interface according to the recorded setting option value, and configures the interface type (e.g., PCIe protocol or Sata protocol) and bandwidth (e.g., x16, x8, or x4).

[0051] As an optional implementation, continue as Figure 1 As shown, after receiving the setting option selected by the user in the non-volatile memory through the interactive interface or remote command, the method further includes:

[0052] When the setting options are not successfully obtained, each interface on the mainboard is configured according to a preset default configuration.

[0053] In some embodiments, the default configuration is written into the BIOS firmware in the form of code. In the manual configuration mode, when the setting options cannot be successfully obtained, each interface will be configured with the default configuration.

[0054] As an optional implementation, continue as Figure 1 As shown, after reading the record information of each interface on the mainboard from the register of the field programmable gate array FPGA on the mainboard, the method further includes:

[0055] When the record information of each interface is not read successfully, each interface on the mainboard is configured according to a preset default configuration.

[0056] In some embodiments, the default configuration is written into the BIOS firmware in the form of code. In the automatic configuration mode, when the record information cannot be successfully obtained, each interface will be configured with the default configuration.

[0057] As an optional implementation, the method further includes: receiving a mode flag bit selected by a user in the non-volatile memory through an interactive interface or a remote command and storing the selected mode flag bit.

[0058] In some embodiments, the mode flag is stored in the non-volatile memory NVRAM in the form of a setting variable. The setting value can be retained when the power is off. It is divided into automatic mode and manual mode. When the mode flag value is 0, it corresponds to automatic mode. When the mode flag value is 1, it corresponds to manual mode. The default value of the mode flag is 0, or the BIOS setting interface will provide an interface to directly modify the mode flag.

[0059] As an optional implementation manner, the reading of the record information of each interface on the mainboard from the register of the field programmable gate array FPGA on the mainboard includes:

[0060] The record information corresponding to each interface is read from each field in the register, wherein the field and the interface have a one-to-one correspondence.

[0061] In some embodiments, the FPGA register start address, space size, format and actual meaning of each interface field are set in combination with the actual situation of the motherboard and project requirements. The FPGA register filling is automatically implemented by the FPGA and hardware circuits without the need for BIOS software control.

[0062] As an optional implementation manner, configuring each interface on the mainboard includes:

[0063] The channel type and bandwidth of each interface on the mainboard are configured.

[0064] In a second aspect, the present invention provides an adaptive configuration method for a motherboard interface, which is executed in a field programmable gate array FPGA on a motherboard, and the method comprises:

[0065] When the computer is powered on, the external card information of each interface on the mainboard is read through the hardware circuit;

[0066] According to a preset conversion method, the external card information of each interface is converted into the record information of each interface;

[0067] The record information of each interface is stored in a field corresponding to the register, so that the basic input and output system BIOS can execute any one of the above-mentioned adaptive configuration methods of the mainboard interface executed in the BIOS according to the record information.

[0068] In some embodiments, the FPGA can detect through hardware lines, for example, by reading the levels of each pin, to collect the status of the external cards currently connected to each interface of the mainboard (whether an external card is connected and the type of external card); according to the specified format, convert the card connection status of each channel into hexadecimal information and record it in the FPGA register.

[0069] As an optional implementation manner, storing the record information of each interface in a field corresponding to the register includes:

[0070] Acquire a one-to-one correspondence between a plurality of interfaces on the mainboard and a plurality of fields in the register;

[0071] The record information of each interface is stored in a corresponding field according to the corresponding relationship.

[0072] In a third aspect, the present invention provides a computer, comprising:

[0073] Motherboard,

[0074] A basic input-output system BIOS arranged on a mainboard, wherein the basic input-output system BIOS is used to execute any one of the above-mentioned methods for adaptively configuring the mainboard interface executed in the BIOS;

[0075] A field programmable gate array FPGA is arranged on a mainboard, wherein the field programmable gate array FPGA is used to execute any one of the aforementioned methods for adaptively configuring the mainboard interface executed in the FPGA.

[0076] A specific exemplary embodiment is provided below to exemplify the above-mentioned embodiments, which are as follows:

[0077] For example, based on the AMD Genoa platform, the AMD EPYC (Xiaolong) 9684X CPU has a total of 128 CPU direct connection channels, divided into 8 groups: G0 (0-15 Lane) / G1 (16-31 Lane) / G2 (32-47 Lane) / G3 (48-63 Lane) / P0 (64-79 Lane) / P1 (80-95 Lane) / P2 (96-111 Lane) / P3 (112-127 Lane).

[0078] The FPGA register allocates a total of 16 bytes of storage space for 8 groups of direct-connected channels, and each group of channels occupies 2 bytes: 0 bytes and 1 bytes; the starting address of the storage space is 0x30, as shown in the following table:

[0079]

[0080] In the above table, each field is divided into two subfields. Bit 0-7 of each field is the first subfield, which indicates the type of external card connected to the channel interface, which is divided into NVMe backplane, Riser card-1, Riser card-2, SATA backplane, etc. In the first subfield, 0x00 indicates NVMe backplane, 0x01 indicates Riser card-1, 0x02 indicates Riser card-2, and 0x03 indicates SATA backplane; more external cards can be set according to project requirements, and values ​​not listed are invalid. Bit 8-15 of each field is the second subfield, which indicates whether the external card connected to the channel interface is a Retimer card; 0x00 indicates that the Retimer is in place, and 0x01 indicates that the Retimer is not in place; the rest of the values ​​are invalid. The specific configuration method is as follows: Figure 2a-2e shown.

[0081] Take the G0 channel group as an example. The G0 channel group is two MCIO interfaces (x8*2) on the motherboard. In automatic mode (the mode flag is 0), the BIOS will read two bytes of data from the FPGA registers 0x30 and 0x31 during the startup process, and configure different types and bandwidths according to the data, as follows:

[0082] When reading 0x30:0x00, 0x31:0x00, BIOS will configure the G0 channel as PCIe type with a bandwidth of x4x4x4x4;

[0083] When reading 0x30:0x01, 0x31:0x00, BIOS will configure the G0 channel as PCIe type with a bandwidth of x16;

[0084] When reading 0x30:0x02, 0x31:0x00, BIOS will configure the G0 channel as PCIe type with a bandwidth of x8x8;

[0085] When reading 0x30:0x01, 0x31:0x01, BIOS will configure the G0 channel as PCIe type with a bandwidth of x4x4x4x4;

[0086] When reading 0x30:0x03, 0x31:0x00, BIOS will configure the G0 channel as SATA type with a bandwidth of x8x8.

[0087] Under the aforementioned exemplary implementation, BIOS and FPGA can combine the actual situation of the project, negotiate the meaning of different data, and formulate unified standards to cover all device types and realize CPU direct channel type and bandwidth adaptive configuration. The present invention can eliminate the manpower and time cost required for CPU channel configuration changes caused by server configuration changes under the premise that the project configuration remains unchanged. The purpose of the present invention is to improve the adaptability of server products and reduce the maintenance cost of products.

[0088] Those skilled in the art can understand that all or part of the processes in the above method embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes in the above method embodiments. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0089] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for adaptively configuring a motherboard interface, characterized in that: Executed in a basic input and output system BIOS, the method includes: When the device is powered on, the current configuration mode is determined based on the mode flag stored in the non-volatile memory; When the configuration mode is the automatic configuration mode, reading the record information of each interface on the mainboard from the register of the field programmable gate array FPGA on the mainboard; When the record information of each interface is successfully read, each interface on the mainboard is configured according to the record information.

2. The method according to claim 1, characterized in that When the device is powered on, after determining the current configuration mode according to the mode flag bit stored in the non-volatile memory, the method further comprises: When the configuration mode is a manual configuration mode, receiving a setting option selected by a user in the non-volatile memory through an interactive interface or a remote command; When the setting options are successfully obtained, each interface on the mainboard is configured according to the setting options.

3. The method according to claim 2, characterized in that After receiving the setting option selected by the user in the non-volatile memory through an interactive interface or a remote command, the method further includes: When the setting options are not successfully obtained, each interface on the mainboard is configured according to a preset default configuration.

4. The method according to claim 1, characterized in that: After reading the record information of each interface on the mainboard from the register of the field programmable gate array FPGA on the mainboard, the method further includes: When the record information of each interface is not read successfully, each interface on the mainboard is configured according to a preset default configuration.

5. The method according to claim 1, characterized in that The method further includes: receiving a mode flag bit selected by a user in the non-volatile memory through an interactive interface or a remote command and storing the selected mode flag bit.

6. The method according to claim 1, characterized in that The step of reading the record information of each interface on the mainboard from the register of the field programmable gate array FPGA on the mainboard comprises: The record information corresponding to each interface is read from each field in the register, wherein the field and the interface have a one-to-one correspondence.

7. The method according to claim 1 or 2, characterized in that: The configuring each interface on the mainboard includes: The channel type and bandwidth of each interface on the mainboard are configured.

8. A method for adaptively configuring a motherboard interface, characterized in that: Executed in a field programmable gate array FPGA on a mainboard, the method comprises: When the computer is powered on, the external card information of each interface on the mainboard is read through the hardware circuit; According to a preset conversion method, the external card information of each interface is converted into the record information of each interface; The record information of each interface is stored in a field corresponding to the register, so that the basic input and output system BIOS can execute the adaptive configuration method of the mainboard interface according to any one of claims 1 to 7 according to the record information.

9. The method according to claim 8, characterized in that The storing of the record information of each interface in a field corresponding to the register includes: Acquire a one-to-one correspondence between a plurality of interfaces on the mainboard and a plurality of fields in the register; The record information of each interface is stored in a corresponding field according to the corresponding relationship.

10. A computer, characterized in that: include: Motherboard, A basic input / output system BIOS set on a mainboard, wherein the basic input / output system BIOS is used to execute the adaptive configuration method of the mainboard interface according to any one of claims 1 to 7; A field programmable gate array FPGA is arranged on a mainboard, wherein the field programmable gate array FPGA is used to execute the adaptive configuration method of the mainboard interface as described in any one of claims 8-9.

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