Batch de-mapping method and device and heterogeneous equipment

Abstract

The invention discloses a batch demapping method and device and heterogeneous equipment. The method comprises the following steps: after a heterogeneous device allocates a de-mapping request of a heterogeneous component to a de-mapping queue, when the number of de-mapping requests of a first de-mapping queue reaches a set length threshold value, extracting the de-mapping requests with the number corresponding to the set length threshold value to another de-mapping queue; and batch processing is carried out on all the demapping requests of the other demapping queue, so that asynchronous processing of the plurality of demapping requests is realized. And when at least two virtual addresses in virtual addresses in all de-mapping requests de-physical mapping of the other de-mapping queue are continuous virtual addresses, the heterogeneous equipment sends a TLB failure instruction capable of directly losing efficacy of entries of a plurality of TLBs to the TLB, so that the number of sent TLB failure instructions is reduced, and the time delay of batch de-mapping is reduced.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and in particular to a batch demapping method, device and heterogeneous equipment. Background Art

[0002] Heterogeneous devices refer to the integration of different types of components in a system, and these components have different architectures, functions and characteristics. The different types of components of heterogeneous devices can be processors, accelerators, chipsets, etc. Heterogeneous devices can integrate different types of components into a system, which can give full play to the advantages of each component and provide richer computing capabilities and functions. For example, a heterogeneous computing system can integrate a central processing unit (CPU) and a graphics processing unit (GPU), using the CPU to perform general computing tasks, and using the GPU to perform graphics rendering and parallel computing tasks.

[0003] Typically, heterogeneous devices use a memory management unit (MMU) to manage and control their memory accesses to support different types of processors or devices working together in the same system to achieve higher performance and energy efficiency. When heterogeneous devices use MMUs, a translation lookaside buffer (TLB) in the MMU is used to accelerate address translation. Since the size and capacity of the TLB are limited, if the virtual address accessed by the MMU exceeds the range of the TLB, or the mapping entry of a frequently accessed virtual address fails, additional queries and delays are required to re-acquire the correct mapping, which will affect the performance of the heterogeneous device. Summary of the invention

[0004] In order to solve the above problems, a batch demapping method is provided in an embodiment of the present application, which performs batch demapping in the order of clearing the physical page table, clearing the physical mapping of the TLB, releasing the physical memory and releasing the virtual address, thereby ensuring the security of asynchronous processing, reducing the number of TLB invalidation instructions sent, and reducing the delay of batch demapping. In addition, the present application also provides a batch demapping device and heterogeneous equipment corresponding to the batch demapping method.

[0005] To this end, the following technical solutions are adopted in the embodiments of the present application:

[0006] In a first aspect, an embodiment of the present application provides a batch demapping method, wherein a heterogeneous device includes a main processor and at least one heterogeneous component, and the method is executed by the main processor, and the method includes: allocating a demapping request to a first demapping queue of a target heterogeneous component; the demapping request instructs the main processor to release the physical mapping of the target heterogeneous component, wherein the physical mapping of the target heterogeneous component is a mapping relationship between a virtual address and a physical address of the target heterogeneous component, and the at least one heterogeneous component includes the target heterogeneous component; when the length of the first demapping queue is greater than or equal to a set length threshold, the first demapping queue is allocated to the main processor; All demapping requests of a queue or the number of demapping requests corresponding to the set length threshold at the front of the first demapping queue are extracted into the second demapping queue of the target heterogeneous component; the length represents the number of demapping requests; when it is detected that there are at least two consecutive virtual addresses in the virtual addresses in the physical demapping of all the demapping requests of the second demapping queue, a first TLB invalidation instruction is sent to the bypass block table cache TLB, and the first TLB invalidation instruction instructs the TLB to invalidate the TLB entries corresponding to the consecutive virtual addresses, and the TLB entries record the physical mapping of the target heterogeneous component.

[0007] In this implementation, after the heterogeneous device assigns a demapping request of a heterogeneous component to a demapping queue, when the number of demapping requests in the first demapping queue reaches a set length threshold, the heterogeneous device extracts the number of demapping requests corresponding to the set length threshold into another demapping queue, and batch processes all the demapping requests in the other demapping queue to achieve asynchronous processing of multiple demapping requests. When at least two virtual addresses are continuous virtual addresses in the virtual addresses in the physical demapping of all the demapping requests in another demapping queue, the heterogeneous device sends a TLB invalidation instruction to the TLB that can directly invalidate multiple TLB entries, so as to reduce the number of TLB invalidation instructions sent and reduce the delay of batch demapping.

[0008] In one embodiment, when it is detected that there are at least two consecutive virtual addresses in the virtual addresses in the physical mapping of all demapping requests of the demapping second queue, before sending a first TLB invalidation instruction to the bypass block table cache TLB, the method also includes: sending a cleanup instruction to the main memory; the main memory is used to store a physical page table, the physical page table records the mapping relationship between the virtual address and the physical address, and the cleanup instruction instructs the main memory to clean up the physical page table corresponding to the demapping request of the demapping second queue.

[0009] In this implementation, after the heterogeneous device cleans up the physical page table in the main memory, it needs to clean up the physical mapping in the TLB to avoid the situation where, after the physical page table in the main memory is cleaned up, the cached page table in the TLB still exists, causing the heterogeneous device to illegally access physical addresses that should not be accessed by accessing the page table mapping cached in the TLB that should be expired, posing a security risk of being attacked.

[0010] In one embodiment, the method further includes: releasing a physical address corresponding to a demapping request of the second demapping queue; and releasing a virtual address corresponding to a demapping request of the second demapping queue.

[0011] In this embodiment, the heterogeneous device marks the physical memory that needs to be released as available or releases it back to the memory pool so that the physical memory can be used by other processes or tasks, and marks the virtual address that needs to be released as available or invalid so that the virtual address can be reallocated and used by other processes or tasks.

[0012] In one embodiment, before the demapping request is assigned to the first demapping queue of the target heterogeneous component, the method further includes: writing data to the target heterogeneous component; when a page fault is triggered, modifying the logical mapping of the current virtual address to point the current virtual address to its own physical address; the page fault means that the main processor cannot access the physical address based on the virtual address; after completing the data write operation, clearing the modified logical mapping.

[0013] In this implementation, when a heterogeneous device triggers a page fault when reading or writing data, the logical mapping corresponding to the current virtual address is updated, so that the device and physical memory mapped by the current virtual address can be tracked through the logical mapping. After completing the read or write data operation, the heterogeneous device can clear the logical mapping corresponding to the current virtual address, so that the upper-layer application or operating system can re-establish a new mapping relationship or release related resources.

[0014] In one embodiment, the method also includes: detecting the remaining memory; the remaining memory is the memory in an idle state allocated by the heterogeneous device to the target heterogeneous component; when the remaining memory is less than or equal to the set memory threshold, reducing the set length threshold; when the remaining memory is greater than the set memory threshold, increasing the set length threshold.

[0015] In this implementation, when the heterogeneous device determines that the remaining memory is relatively large, the set length threshold can be slowly increased, thereby gradually increasing the number of demapping requests for batch processing, thereby improving the throughput of batch processing. When the heterogeneous device determines that the remaining memory is relatively small, the set length threshold can be reduced, thereby reducing the number of demapping requests for batch processing, thereby improving the batch demapping processing speed in a short time and alleviating the problem of insufficient remaining memory.

[0016] In one embodiment, the method also includes: detecting the frequency of demapping; the frequency of demapping refers to the number of demapping requests for the target heterogeneous component generated by the heterogeneous device per unit time; when the frequency of demapping is greater than a set frequency threshold, increasing the sleep time of the background daemon process; the background daemon process refers to a process that automatically handles the demapping requests of the first demapping queue; when the frequency of demapping is less than or equal to the set frequency threshold, reducing the sleep time of the background daemon process.

[0017] In this implementation, when the heterogeneous device determines that the frequency of demapping is relatively frequent, the sleep time of the background daemon process can be increased, and the throughput of batch processing can be improved by sacrificing individual tail delays. When the heterogeneous device determines that the frequency of demapping is not frequent, the sleep time of the background daemon process can be reduced to ensure the delay when the throughput remains unchanged.

[0018] In one embodiment, the method further includes: when it is detected that the number of all demapping requests in the demapping second queue is less than a set number, sending a second TLB invalidation instruction to the TLB; the second TLB invalidation instruction instructs the TLB to invalidate the TLB entry corresponding to a single virtual address.

[0019] In a second aspect, an embodiment of the present application provides a batch demapping device, comprising: a first processing unit, configured to assign a demapping request to a first demapping queue of a target heterogeneous component; the demapping request instructs the main processor to release the physical mapping of the target heterogeneous component, the physical mapping of the target heterogeneous component being a mapping relationship between a virtual address and a physical address of the target heterogeneous component, and the at least one heterogeneous component includes the target heterogeneous component; a second processing unit, configured to extract all the demapping requests of the first demapping queue or the number of demapping requests corresponding to the set length threshold at the front of the first demapping queue into a second demapping queue of the target heterogeneous component when the length of the first demapping queue is greater than or equal to a set length threshold; the length represents the number of demapping requests; the first processing unit, configured to send a first TLB invalidation instruction to a bypass block table cache TLB when detecting that at least two virtual addresses in the virtual addresses in the physical demapping of all the demapping requests of the second demapping queue are continuous virtual addresses, wherein the first TLB invalidation instruction instructs the TLB to invalidate the TLB entries corresponding to the continuous virtual addresses, and the TLB entries record the physical mapping of the target heterogeneous component.

[0020] In one embodiment, the third processing unit is also used to send a cleanup instruction to the main memory; the main memory is used to store a physical page table, which records the mapping relationship between virtual addresses and physical addresses, and the cleanup instruction instructs the main memory to clean up the physical page table corresponding to the demapping request of the demapping second queue.

[0021] In one embodiment, the third processing unit is further used to release the physical address corresponding to the demapping request of the second demapping queue; and release the virtual address corresponding to the demapping request of the second demapping queue.

[0022] In one embodiment, the first processing unit is also used to write data to the target heterogeneous component; when a page fault is triggered, the logical mapping of the current virtual address is modified to point the current virtual address to its own physical address; the page fault means that the main processor cannot access the physical address based on the virtual address; after completing the data write operation, the modified logical mapping is cleared.

[0023] In one embodiment, the third processing unit is also used to detect the remaining memory; the remaining memory is the memory in the idle state allocated by the heterogeneous device to the target heterogeneous component; when the remaining memory is less than or equal to the set memory threshold, the set length threshold is reduced; when the remaining memory is greater than the set memory threshold, the set length threshold is increased.

[0024] In one embodiment, the third processing unit is also used to detect the frequency of demapping; the frequency of demapping refers to the number of demapping requests for the target heterogeneous component generated by the heterogeneous device per unit time; when the frequency of demapping is greater than the set frequency threshold, the sleep time of the background daemon process is increased; the background daemon process refers to the process that automatically handles the demapping requests of the first demapping queue; when the frequency of demapping is less than or equal to the set frequency threshold, the sleep time of the background daemon process is reduced.

[0025] In one embodiment, the third processing unit is also used to send a second TLB invalidation instruction to the TLB when it detects that the number of all demapping requests in the second demapping queue is less than a set number; the second TLB invalidation instruction instructs the TLB to invalidate the TLB entry corresponding to a single virtual address.

[0026] In a third aspect, an embodiment of the present application provides a heterogeneous device, comprising: at least one memory; at least one heterogeneous component, and a main processor, wherein the main processor is used to execute instructions stored in the memory, so that the heterogeneous device executes various possible implementation embodiments of the first aspect.

[0027] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, comprising computer program instructions. When the computer program instructions are executed by a heterogeneous device, the heterogeneous device executes various possible implementations of the first aspect.

[0028] In a fifth aspect, an embodiment of the present application provides a computer program product comprising instructions, characterized in that the computer program product stores instructions, and when the instructions are executed by a heterogeneous device, the heterogeneous device implements each possible implementation embodiment of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The following is a brief introduction to the drawings required for describing the embodiments or prior art.

[0030] Figure 1 It is a schematic diagram of the structure of a GPU in the related art;

[0031] Figure 2 A schematic diagram of the hardware structure of a heterogeneous device provided in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of the software structure of a heterogeneous device provided in an embodiment of the present application;

[0033] Figure 4 A schematic diagram of a process for maintaining a logical mapping provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of a process for batch processing of demapping requests provided in an embodiment of the present application;

[0035] Figure 6 A schematic diagram of the batch demapping process provided in an embodiment of the present application;

[0036] Figure 7 A schematic diagram of a process for adjusting batch parameters provided in an embodiment of the present application;

[0037] Figure 8 A schematic diagram of the structure of a batch demapping device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0039] The term "and / or" in this article is a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The symbol " / " in this article indicates that the associated objects are in an or relationship, for example, A / B means A or B.

[0040] The terms "first" and "second" in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of the objects. For example, a first response message and a second response message are used to distinguish different response messages rather than to describe a specific order of the response messages.

[0041] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0042] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more than two. For example, multiple processing units refer to two or more processing units, etc.; multiple elements refer to two or more elements, etc.

[0043] TLB is a high-speed cache used in computer architecture to accelerate the conversion of virtual addresses to physical addresses. TLB generally stores the physical mapping of the most recently accessed part, that is, the mapping relationship between virtual addresses and physical addresses. When the CPU issues a virtual address, if the TLB stores the physical mapping corresponding to the virtual address, the physical mapping can be directly obtained from the TLB to obtain the physical address corresponding to the virtual address, so as to quickly find the mapping relationship between the virtual address and the physical address, thereby reducing the overhead of accessing the physical page table.

[0044] Figure 1 FIG. 1 is a schematic diagram of the structure of a GPU in the related art. Figure 1 As shown, the GPU includes GPU memory (GPUMemory), GPU MMU, multiple streaming multiprocessors (SMs) and peripheral component interconnect (PCI) base address registers (BARs).

[0045] GPU memory is a high-speed memory dedicated to GPUs, which is used to store data and instructions during GPU computing and provides high-bandwidth and low-latency access. GPU Memory plays an important role in applications such as graphics rendering, deep learning, and scientific computing. It is used to store data such as images, textures, models, and intermediate computing results to support high-performance parallel computing and data processing.

[0046] The GPU MMU is responsible for managing memory access and address translation in the GPU system. It converts the video memory address (physical address) into a virtual address based on the memory address translation table (page table) and provides memory access control and isolation functions. The role of the GPU MMU is to enable the GPU to effectively manage large-scale memory and achieve memory isolation, protection, and virtualization.

[0047] SM is the core computing unit in the GPU, which is used to perform parallel computing tasks. Each SM includes an arithmetic logic unit (ALU), a floating-point unit (FPU), a special function unit (SFU), and a logical register. Among them, the ALU is the main computing unit in the SM, performing integer operations and logical operations. The ALU is responsible for processing integer arithmetic operations (such as addition, subtraction, multiplication, division, etc.) and logical operations (such as AND, OR, NOT, XOR, etc.). The FPU is used to perform floating-point operations. The FPU supports addition, subtraction, multiplication, division, and other more complex operations of floating-point numbers, such as square roots, trigonometric functions, etc. The SFU is used to perform floating-point operations. The FPU supports addition, subtraction, multiplication, division, and other more complex operations of floating-point numbers, such as square roots, trigonometric functions, etc. The logical register is used to store and manage the variables, states, and calculation results of threads in the SM. Each thread has its own set of logical registers to store thread-private data. Logical registers play a key role in computing tasks, supporting parallel execution of calculations on different threads and communicating and sharing data when needed. The ALU, FPU, SFU and logical registers in the SM are responsible for integer operations, floating-point operations, special function operations and thread data storage, respectively, and work together to achieve efficient parallel computing and processing tasks.

[0048] PCI BAR refers to the address register in the PCI bus device. The GPU communicates and exchanges data with the host system through the PCI bus. PCI BAR is used to specify the address range of the GPU in the physical memory address space so that the host system can read and write GPU memory. The host system can exchange data and work with the GPU by configuring and managing PCI BAR.

[0049] In the GPU, the GPU MMU can convert the virtual address of the SM into the physical address of the GPU memory, enabling the SM to access and operate the GPU memory. TLB is a key component in the GPU MMU, which is used to cache the mapping items from virtual addresses to physical addresses to speed up the address translation process. When the SM accesses a virtual address, the GPU MMU detects whether there is a mapping item for the virtual address in the TLB. If the TLB has a mapping item for the virtual address, the SM can directly use the physical address corresponding to the mapping item for the virtual address in the TLB, thereby avoiding the overhead of searching the page table.

[0050] The de-mapping operation refers to the process of releasing the mapping relationship between the virtual address and the physical address. It is generally used in thread switching in a multi-threaded environment or release operations in dynamic memory management. When a virtual address is no longer needed, the GPU MMU can release the mapping relationship between the virtual address and the physical address to release the physical memory corresponding to the physical address for use by other virtual addresses. If the SM accesses the virtual address that has been demapped again, the GPU MMU needs to re-query the page table, which causes additional memory access overhead. Frequent TLB failures mean more page table queries and address translation operations, which will lead to a decrease in GPU performance.

[0051] In order to avoid the performance degradation of GPU, the related art can delay the TLB invalidation action in the demapping operation, and then execute the TLB invalidation operation in batches. The related art executes the high-cost TLB invalidation operation asynchronously in batches, which can reduce the bottleneck of TLB invalidation. However, when the related art executes the TLB invalidation operation in batches, some TLB invalidation actions are delayed, and there is a situation where the TLB invalidation operation has not been executed after the physical page table is released, resulting in the device illegally accessing the physical address that should not be accessed by accessing the expired page table mapping cached in the TLB, which poses a security risk of being attacked.

[0052] In order to solve the defects existing in the related art, the embodiments of the present application provide a batch demapping method, a batch demapping device and a heterogeneous device. After the heterogeneous device assigns the demapping request of a heterogeneous component to a demapping queue, when the number of demapping requests of the first demapping queue reaches the set length threshold, the demapping requests corresponding to the set length threshold are extracted into another demapping queue, and all the demapping requests of the other demapping queue are processed in batches to realize asynchronous processing of multiple demapping requests. When there are at least two consecutive virtual addresses in the virtual addresses in the physical demapping of all the demapping requests of another demapping queue, the heterogeneous device sends a TLB invalidation instruction to the TLB that can directly invalidate multiple TLB entries, so as to reduce the number of TLB invalidation instructions sent and reduce the delay of batch demapping.

[0053] Figure 2 Schematic diagram of the hardware structure of a heterogeneous device provided in an embodiment of the present application. Figure 2As shown, the hardware of the heterogeneous device 200 may include a main processor 210, an MMU 220, a host memory 230, and at least one heterogeneous component 240. The at least one heterogeneous component may be a heterogeneous component 240-1, ..., a heterogeneous component 240-N. N is a positive integer greater than or equal to 2. The heterogeneous device 200 may be a server, an outdoor cabinet, a base station, an electric car, a drone, a smart phone, a computer, a laptop, etc.

[0054] The main processor 210 is one of the core components in the heterogeneous device 200, and can be a CPU, a GPU, or other dedicated processor. The main processor 210 is responsible for executing instructions and controlling the execution process of computing tasks. In the heterogeneous device 200, different types of main processors 210 may have different functions and characteristics. For example, the CPU is usually used for general computing and control processes, and the GPU is specifically used for parallel computing and graphics rendering.

[0055] MMU 220 is a hardware unit used to manage memory access and address translation in the system. In heterogeneous device 200, MMU 220 is responsible for maintaining the mapping of virtual addresses to physical addresses and controlling memory access rights. Heterogeneous device 200 can provide functions such as memory isolation, protection, and virtualization through MMU 220 to ensure security and isolation between different components and tasks.

[0056] The host memory 230 is a key component for storing data and instructions in the heterogeneous device 200. The host memory 230 may include main memory, cache, dedicated video memory, etc. Different types of memory have different access speeds, capacities, and uses. For example, the main memory is used to store data shared by the CPU and GPU, the cache is used to accelerate the data access of the processor, and the dedicated video memory is used to store textures, buffers, and calculation results required by the GPU to perform tasks.

[0057] Heterogeneous components 240 refer to other types of components different from the main processor 210, such as GPU, field programmable gate array (FPGA), digital signal processor (DSP), etc. Each heterogeneous component 240 has different architectures and characteristics, which can be used to perform specific computing tasks or optimize specific workloads. The heterogeneous device 200 can flexibly combine and coordinate the use of different heterogeneous components 240 to achieve more efficient and more specialized computing capabilities.

[0058] Figure 3 Schematic diagram of the software structure of a heterogeneous device provided in the embodiment of the present application. Figure 3As shown, the heterogeneous device 200 can be divided into an application 250 and an operating system 260 from a software perspective. The software of the heterogeneous device 200 can be stored in the host memory 230. The main processor 210 can call the software program stored in the host memory 230 to implement various functions of the application 250 and the operating system 260.

[0059] Application 250 refers to a computer program that completes one or more specific tasks. Application 250 is installed in operating system 260, can interact with users, and create one or more execution tasks after receiving user operation instructions. Each application 250 can run in an independent process and have an independent address space. In an embodiment of the present application, application 250 can be Netperf. Netperf is a tool for network performance testing and performance measurement. Netperf can run on different operating systems and provides a set of tools for testing network transmission performance, including the sending and receiving of network packets. Heterogeneous devices 200 can use Netperf to perform network packet sending and receiving tests to help evaluate network performance indicators such as throughput and latency.

[0060] The operating system 260 is a set of interrelated system software programs that manage and control computer operations, run and operate hardware and software resources, and provide public services to organize user interactions. The operating system 260 can schedule various resource blocks of the heterogeneous device 200, including hardware and software equipment, data information, etc. The use of a computer operating system can reduce the workload of manual resource allocation, reduce the degree of user intervention in computer operations, and greatly improve the intelligent work efficiency of the computer.

[0061] The operating system 260 can be divided into a device demapping unit 261 and a security demapping unit 262 according to the execution function. Among them, the device demapping unit 261 and the security demapping unit 262 can be implemented by software, or can be implemented by hardware, or can be implemented by a combination of software and hardware. Exemplarily, the implementation method of the device demapping unit 261 is introduced below by taking the device demapping unit 261 as an example. Similarly, the implementation method of the security demapping unit 262 can refer to the implementation method of the device demapping unit 261.

[0062] As an example of a software functional unit, the device demapping unit 261 may include code running on a computing instance. Among them, the computing instance may include at least one of a physical host (computing device), a virtual machine, and a container. Further, the above-mentioned computing instance may be one or more. For example, the device demapping unit 261 may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed in the same region (region) or in different regions. Furthermore, the multiple hosts / virtual machines / containers used to run the code may be distributed in the same availability zone (AZ) or in different AZs, each AZ including a data center or multiple data centers with similar geographical locations. Among them, usually a region may include multiple AZs.

[0063] Similarly, multiple hosts / virtual machines / containers used to run the code can be distributed in the same virtual private cloud (VPC) or in multiple VPCs. Usually, a VPC is set up in a region. For cross-region communication between two VPCs in the same region and between VPCs in different regions, a communication gateway needs to be set up in each VPC to achieve interconnection between VPCs through the communication gateway.

[0064] As an example of a hardware functional unit, the device demapping unit 261 may include at least one computing device, such as a computing device, etc. Alternatively, the device demapping unit 261 may also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0065] The multiple computing devices included in the device demapping unit 261 can be distributed in the same region or in different regions. The multiple computing devices included in the device demapping unit 261 can be distributed in the same AZ or in different AZs. Similarly, the multiple computing devices included in the device demapping unit 261 can be distributed in the same VPC or in multiple VPCs. The multiple computing devices can be any combination of computing devices such as computing devices, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0066] It should be noted that, in other embodiments, the device demapping unit 261 can be used to execute any step in the batch demapping method, and the security demapping unit 262 can be used to execute any step in the batch demapping method. The steps that the device demapping unit 261 and the security demapping unit 262 are responsible for implementing can be specified as needed, and the device demapping unit 261 and the security demapping unit 262 respectively implement different steps in the batch demapping method to realize the full functions of the operating system.

[0067] The device demapping unit 261 is used to execute the demapping operation of each heterogeneous component 240 after the demapping request is sent by the application 250, to clean up the physical page table, clean up the physical mapping and logical mapping of the TLB cache, and release the corresponding virtual address and physical address.

[0068] After receiving the demapping request from the device demapping unit 261, the secure demapping unit 262 can process the demapping requests of each heterogeneous component 240 in batches to implement secure batch execution of the demapping requests. In the embodiment of the present application, the secure demapping unit 262 can be divided into an MMU operation unit 2621, a logical mapping unit 2622, a demapping queue unit 2623, a demapping batch processing unit 2624, and a batch parameter adjustment unit 2625 according to the execution function.

[0069] During the initialization phase of the heterogeneous component 240, the MMU operation unit 2621 may receive component information such as the operation function of the physical page table and the TLB invalidation operation of the heterogeneous component 240. The MMU operation unit 2621 may configure an initialized demapping producer queue and a demapping consumer queue for each heterogeneous component 240 according to the component information of each heterogeneous component 240 using the producer-consumer model.

[0070] The producer-consumer model is a classic concurrent programming model used to solve data exchange and synchronization problems between producers and consumers. In the producer-consumer model, the producer is responsible for generating data and putting the data into a shared cache. The consumer is responsible for taking data out of the buffer and processing the data. In an embodiment of the present application, the demapping producer queue and the demapping consumer queue configured by the MMU operation unit 2621 for each heterogeneous component 240 are both a list for recording information related to the demapping request. Among them, the information related to the demapping request recorded by the demapping producer queue is sent by the device demapping unit 261. The information related to the demapping request recorded by the demapping consumer queue is migrated from the demapping producer queue. The MMU operation unit 2621 sets two queues, allowing one queue to receive information related to the demapping request and the other queue to read information related to the demapping request, so as to avoid competition between the writing process and the reading process on one queue.

[0071] The following takes the main processor 210 and the heterogeneous component 240 - 1 reading data as an example.

[0072] The logical mapping unit 2622 is used to maintain virtual mapping. Logical mapping refers to the process of mapping the logical structure abstracted by the high-level program or operating system to the underlying physical structure. For example, in the operating system, the file system maps the file name to the physical sector on the storage device. The logical mapping is responsible for handling the conversion between different levels and hiding the underlying details so that the upper-level application can easily access and operate the underlying resources.

[0073] When the main processor 210 reads data from the heterogeneous component 240-1, a page fault is triggered. A page fault means that the main processor 210 cannot access the physical address based on the virtual address. When the main processor 210 triggers a page fault, the logical mapping unit 2622 can call the driver of the heterogeneous component 240-1 to update the logical mapping corresponding to the current virtual address, and point the current virtual address to its own physical address, so as to track the components and physical memory mapped by the current virtual address through the logical mapping.

[0074] After the main processor 210 completes the data read and write operation, the current logical mapping becomes ineffective. After the logical mapping becomes ineffective, the logical mapping unit 2622 can clear the logical mapping to release the current virtual address.

[0075] Figure 4 Schematic diagram of the process of maintaining logical mapping provided in the embodiment of the present application. Figure 4 As shown, the process of maintaining the logical mapping by the logical mapping unit 2622 is specifically as follows:

[0076] S401, determining whether the main processor 210 performs a data read and write operation.

[0077] S402, when a page fault is triggered, update the logical mapping to point the current virtual address to its own physical address.

[0078] S403, after determining that the main processor 210 has completed the data reading and writing operations, a demapping operation is performed on the current virtual address.

[0079] S404, clear the logical mapping of the current virtual address.

[0080] In the embodiment of the present application, when a page fault is triggered during data reading and writing, the logical mapping unit 2622 updates the logical mapping corresponding to the current virtual address, and realizes tracking the device and physical memory mapped by the current virtual address through the logical mapping. After completing the data reading and writing operation, the logical mapping unit 2622 can clear the logical mapping corresponding to the current virtual address, so that the upper-layer application or operating system can re-establish a new mapping relationship or release related resources.

[0081] After receiving the demapping request from the logical mapping unit 2622 for demapping operation, the demapping queue unit 2623 can determine the virtual address and callback function of the demapping request according to the logical mapping. The demapping queue unit 2623 can determine the heterogeneous component 240 to which the physical address released by the demapping request belongs according to the demapping request, and assign the demapping request to the demapping producer queue of the heterogeneous component 240-1. The demapping request generally carries information such as the virtual address and the callback function. The virtual address is composed of the starting address and length of the virtual address, or the starting address and end address of the virtual address. The callback function is used to clean up management data.

[0082] The demapping queue unit 2623 monitors the length of the demapping producer queue of each heterogeneous component 240 in real time. The length of the queue refers to the number of demapping requests waiting to be executed on the demapping producer queue. When the demapping queue unit 2623 detects that the length of a demapping producer queue exceeds the set length threshold, all demapping requests of the demapping producer queue or the demapping requests of the set length threshold at the head of the queue are extracted into the corresponding demapping consumer queue, and all demapping requests in the demapping consumer queue are batch processed, which can avoid the background daemon process from automatically performing batch demapping operations. The background daemon process refers to a process that automatically processes the demapping requests recorded by the demapping producer queue. The background daemon process generally starts working periodically and then enters a sleep state. If the sleep time of the background daemon process is relatively long, the length of the demapping producer queue can easily exceed the set length threshold, resulting in a longer delay in processing the demapping request.

[0083] Figure 5FIG. 1 is a flow chart of batch processing of demapping requests provided in an embodiment of the present application. Figure 5 As shown, the process of batch processing of the demapping request by the demapping queue unit 2623 is specifically as follows:

[0084] S501, determine the demapping producer queue of the heterogeneous component 240-1 according to the demapping request.

[0085] S502, distribute the demapping request to the demapping producer queue of the heterogeneous component 240-1.

[0086] S503, detect whether the length of the demapped producer queue of the heterogeneous component 240-1 is less than the set length threshold. In one case, when the length of the demapped producer queue of the heterogeneous component 240-1 is greater than or equal to the set length threshold, execute step S504. In another case, when the length of the demapped producer queue of the heterogeneous component 240-1 is less than the set length threshold, end the operation.

[0087] S504, extract all demapping requests of the demapping producer queue of the heterogeneous component 240-1 or the demapping requests with a set length threshold at the head of the queue into the demapping consumer queue of the heterogeneous component 240-1.

[0088] S505, batch process all demapping requests in the demapping consumer queue of the heterogeneous component 240-1.

[0089] In the embodiment of the present application, when the demapping queue unit 2623 processes demapping requests in batches, the demapping requests are added to the demapping producer queue of the corresponding heterogeneous component 240-1. If the length of the demapping producer queue of the heterogeneous component 240-1 is greater than or equal to the set length threshold, the demapping queue unit 2623 extracts all demapping requests of the demapping producer queue of the heterogeneous component 240-1 or the demapping requests of the set length threshold at the head of the queue to the demapping consumer queue of the heterogeneous component 240-1, and performs batch demapping. If the length of the demapping producer queue of the heterogeneous component 240-1 is less than the set length threshold, the demapping request can be automatically processed by the background daemon.

[0090] The demapping batch processing unit 2624 is used to traverse the demapping consumer queues of all heterogeneous components 240-1, and can process all pending demapping requests in batches. Demapping can be divided into cleaning up the physical page table, cleaning up the physical mapping of the TLB, releasing physical memory, and releasing virtual addresses.

[0091] The physical page table is a data structure used to record the mapping relationship between virtual addresses and physical addresses. The physical page table is generally stored in the main memory and maintained and managed by the operating system. When the CPU issues a virtual address, the physical address corresponding to the virtual address can be found by querying the physical page table. In the demapping process, the corresponding physical page table needs to be cleared or marked as invalid so that the virtual address and physical address corresponding to the physical mapping recorded in the physical page table can be reused or recycled. TLB is a high-speed cache used to store recently accessed page table entries to increase the speed of address translation. In the demapping process, the relevant TLB entries need to be cleared or marked as invalid so that new address translation can proceed normally. Releasing physical memory means marking the relevant physical memory as available or releasing it back to the memory pool so that the physical memory can be used by other processes or tasks. Releasing a virtual address means marking the relevant virtual address as available or invalid so that the virtual address can be reallocated and used by other processes or tasks.

[0092] When the demapping batch processing unit 2624 performs batch processing on multiple demapping requests, it is executed in the order of clearing the physical page table, clearing the physical mapping of the TLB, releasing the physical memory and releasing the virtual address to ensure the security of the heterogeneous device 200. In the physical mapping stage of the TLB, if the virtual addresses recorded in the entries of the TLB released by at least two or more demapping requests are continuous virtual addresses, the demapping batch processing unit 2624 can send a TLB invalidation instruction to the TLB that can directly invalidate multiple TLB entries, so as to reduce the number of TLB invalidation instructions sent by the demapping batch processing unit 2624 and reduce the delay of batch demapping. In addition, since the driver of the heterogeneous component has secondary management of the physical memory, the demapping batch processing unit 2624 can use the callback function carried by the demapping request to clean up the management of the physical memory by the driver of the heterogeneous component during the demapping process.

[0093] Figure 6 Schematic diagram of the batch demapping process provided in the embodiment of the present application. Figure 6 As shown, the process of batch demapping processing unit 2624 performing batch demapping on multiple demapping requests is specifically as follows:

[0094] S601, clearing physical page tables corresponding to multiple demapping requests.

[0095] S602, detect whether all demapping requests of the demapping consumer queue of the heterogeneous component 240-1 have completed the cleaning of the physical page table. In one case, when all demapping requests of the demapping consumer queue of the heterogeneous component 240-1 have not completed the cleaning of the physical page table, step S601 is executed. In another case, when all demapping requests of the demapping consumer queue of the heterogeneous component 240-1 have completed the cleaning of the physical page table, step S603 is executed.

[0096] S603: Count the number of TLB invalid instructions.

[0097] S604, determining whether the number of TLB miss instructions is less than a set number. In one case, when the number of TLB miss instructions is greater than or equal to the set number, executing step S605. In another case, when the number of TLB miss instructions is less than the set number, executing step S606.

[0098] S605: Send a TLB invalidation instruction to invalidate multiple TLB entries.

[0099] S606: Send a TLB invalidation instruction to invalidate a single TLB entry.

[0100] S607, detecting whether all demapping requests of the demapping consumer queue of the heterogeneous component 240-1 have completed clearing the entries of the TLB. In one case, when all demapping requests of the demapping consumer queue of the heterogeneous component 240-1 have not completed clearing the entries of the TLB, step S606 is executed. In another case, when all demapping requests of the demapping consumer queue of the heterogeneous component 240-1 have completed clearing the entries of the TLB, step S608 is executed.

[0101] S608, release physical memory.

[0102] S609, releasing the virtual address.

[0103] S610, detecting whether all demapping requests of the demapping consumer queue of the heterogeneous component 240-1 have completed the release of physical memory and the release of virtual addresses. In one case, when all demapping requests of the demapping consumer queue of the heterogeneous component 240-1 have not completed the release of physical memory and the release of virtual addresses, step S608 is executed. In another case, when all demapping requests of the demapping consumer queue of the heterogeneous component 240-1 have completed the release of physical memory and the release of virtual addresses, the operation ends.

[0104] In an embodiment of the present application, the demapping batch processing unit 2624 can traverse the demapping requests of the demapping consumer queue of the heterogeneous component 240-1, and perform operations of clearing the physical page table, clearing the physical mapping of the TLB, releasing the physical memory, and releasing the virtual address for all demapping requests in turn. The demapping batch processing unit 2624 can execute the operation function of the physical page table, merge the continuous virtual addresses recorded in multiple physical page tables together to form a virtual address segment. When clearing the physical mapping of the TLB, the demapping batch processing unit 2624 can send a TLB invalidation instruction to the TLB corresponding to the merged virtual address segment, invalidate the TLB entries corresponding to multiple continuous virtual addresses, reduce the number of TLB invalidation instructions sent, and reduce the delay of batch demapping.

[0105] The batch parameter adjustment unit 2625 is used to count the demapping frequency, demapped memory size, number of TLB entries of MMU 220, and remaining memory of each heterogeneous component 240, and dynamically adjust the batch parameters of batch demapping of each heterogeneous component 240. The demapping frequency refers to the number of demapping requests generated per unit time. The demapped memory refers to the physical memory released by all demapping requests of a heterogeneous component 240. The remaining memory refers to the memory in the idle state in the memory allocated by the host memory 230 for a heterogeneous component 240. The batch parameters include the length of the two queues of the heterogeneous component 240, the sleep time of the background daemon process, and the set length threshold.

[0106] The batch parameter adjustment unit 2625 can adjust the set length threshold according to the size of the remaining memory. In one case, when the batch parameter adjustment unit 2625 determines that the remaining memory is relatively large (such as greater than the set memory), the set length threshold can be slowly increased, thereby gradually increasing the number of demapping requests for batch processing, thereby improving the throughput of batch processing. In another case, when the batch parameter adjustment unit 2625 determines that the remaining memory is relatively small (such as not greater than the set memory), the set length threshold can be reduced, thereby reducing the number of demapping requests for batch processing, thereby improving the batch demapping processing speed in a short time and alleviating the problem of insufficient remaining memory.

[0107] The batch parameter adjustment unit 2625 can adjust the sleep time of the background daemon according to the frequency of demapping. In one case, when the batch parameter adjustment unit 2625 determines that the frequency of demapping is relatively frequent (such as greater than the set frequency), the sleep time of the background daemon can be increased, and the throughput of batch processing can be improved by sacrificing individual tail delays. Tail delays refer to several delays with longer delays among the delays generated by each demapping request of batch processing. In another case, when the batch parameter adjustment unit 2625 determines that the frequency of demapping is not frequent (such as not greater than the set frequency), the sleep time of the background daemon can be reduced to ensure the delay while the throughput remains unchanged.

[0108] The length threshold is set to determine whether to invalidate the entire TLB entry. In one case, if the page table entries of the batch TLB invalidated memory exceed the TLB entries of the MMU, the entire TLB entry is invalidated.

[0109] Figure 7 Schematic diagram of the process of adjusting batch parameters provided in the embodiment of the present application. Figure 7 As shown, the process of adjusting batch parameters by the batch parameter adjustment unit 2625 is specifically as follows:

[0110] S701, counting remaining memory.

[0111] S702, determine whether the remaining memory is less than the set memory threshold. In one case, if the remaining memory is less than the set memory threshold, execute step S703. In another case, if the remaining memory pressure is greater than or equal to the set memory threshold, execute step S704.

[0112] S703, reduce the set length threshold corresponding to the demapped producer queue of the heterogeneous component 240-1.

[0113] S704, increase the set length threshold corresponding to the demapped producer queue of the heterogeneous component 240.

[0114] S705 , counting the demapping frequency of the heterogeneous component 240 .

[0115] S706, determine whether the demapping frequency of the heterogeneous component 240 is less than the set frequency threshold. In one case, if the demapping frequency of the heterogeneous component 240 is less than the set frequency threshold, step S707 is executed. In another case, if the demapping frequency of the heterogeneous component 240 is greater than or equal to the set frequency threshold, step S708 is executed.

[0116] S707, increase the sleep time of the background daemon process.

[0117] S708, reduce the sleep time of the background daemon process.

[0118] In the embodiment of the present application, the batch parameter adjustment unit 2625 can count the memory occupancy and remaining memory in the demapped producer queue of the heterogeneous component 240-1, and when there is too much physical memory to be released in the producer queue or there is relatively little remaining memory, reduce the set length threshold corresponding to the producer queue to ensure that the length of the producer queue is not too long and the memory to be released does not accumulate too much. The batch parameter adjustment unit 2625 can count the frequency of demapping of the heterogeneous component 240, increase the asynchronous delay time, and improve the overall batch processing throughput by sacrificing individual tail delays.

[0119] Figure 8 Schematic diagram of the structure of a batch demapping device provided in an embodiment of the present application. Figure 8 As shown, the batch demapping device 800 can be divided into a first processing unit 810, a second processing unit 820 and a third processing unit 830 according to the execution function. The functions executed by each unit of the batch demapping device 800 are as follows:

[0120] The first processing unit 810 is used to assign a demapping request to a first demapping queue of a target heterogeneous component. The demapping request instructs the main processor to release the physical mapping of the target heterogeneous component. The physical mapping of the target heterogeneous component is a mapping relationship between a virtual address and a physical address of the target heterogeneous component. At least one heterogeneous component includes a target heterogeneous component. The second processing unit 820 is used to extract all demapping requests of the first demapping queue or a number of demapping requests corresponding to a set length threshold of the front of the first demapping queue into a second demapping queue of the target heterogeneous component when the length of the first demapping queue is greater than or equal to a set length threshold. The length indicates the number of demapping requests. The third processing unit 830 is used to detect that at least two virtual addresses in the virtual addresses in the physical demapping of all demapping requests of the second demapping queue are continuous virtual addresses, and send a first TLB invalidation instruction to the bypass block table cache TLB. The first TLB invalidation instruction instructs the TLB to invalidate the entries of the TLB corresponding to the continuous virtual addresses. The entries of the TLB record the physical mapping of the target heterogeneous component.

[0121] In one embodiment, the third processing unit 830 is further configured to send a cleanup instruction to the main memory. The main memory is used to store a physical page table. The physical page table records the mapping relationship between the virtual address and the physical address. The cleanup instruction instructs the main memory to clean up the physical page table corresponding to the demapping request of the second demapping queue.

[0122] In one implementation, the third processing unit 830 is further configured to release the physical address corresponding to the demapping request of the second demapping queue. The third processing unit 830 is further configured to release the virtual address corresponding to the demapping request of the second demapping queue.

[0123] In one embodiment, the first processing unit 810 is further used to write data to the target heterogeneous component. The first processing unit 810 is further used to modify the logical mapping of the current virtual address when a page fault is triggered, and point the current virtual address to its own physical address. A page fault means that the main processor cannot access the physical address based on the virtual address. The first processing unit 810 is also used to clear the modified logical mapping after completing the write data operation.

[0124] In one embodiment, the third processing unit 830 is further used to detect the remaining memory. The remaining memory is the memory in the memory that is allocated to the target heterogeneous component by the heterogeneous device and is in an idle state. The third processing unit 830 is also used to reduce the set length threshold when the remaining memory is less than or equal to the set memory threshold. The third processing unit 830 is also used to increase the set length threshold when the remaining memory is greater than the set memory threshold.

[0125] In one embodiment, the third processing unit 830 is also used to detect the frequency of demapping. The frequency of demapping refers to the number of demapping requests for the target heterogeneous component generated by the heterogeneous device per unit time. The third processing unit 830 is also used to increase the sleep time of the background daemon process when the frequency of demapping is greater than the set frequency threshold. The background daemon process refers to a process that automatically processes the demapping request of the first demapping queue. The third processing unit 830 is also used to reduce the sleep time of the background daemon process when the frequency of demapping is less than or equal to the set frequency threshold.

[0126] In one embodiment, the third processing unit 830 is further configured to send a second TLB invalidation instruction to the TLB when detecting that the number of all demapping requests in the second demapping queue is less than a set number. The second TLB invalidation instruction instructs the TLB to invalidate the TLB entry corresponding to a single virtual address.

[0127] The present application also provides a heterogeneous device, which includes a processor, which can execute the following Figure 2-Figure 7 And the technical scheme corresponding to the above protection makes the heterogeneous device have the technical effect of the technical scheme corresponding to the above protection.

[0128] The present application also provides a computer-readable storage medium including computer program instructions. When the computer program instructions are executed by a heterogeneous device, the computing device executes the above Figure 2-Figure 7 and any method described in the corresponding description.

[0129] In an embodiment of the present application, a computer program product comprising instructions is further provided, wherein the computer program product stores instructions, and when the instructions are executed by a heterogeneous device, the heterogeneous device implements the above Figure 2-Figure 7 and any method described in the corresponding description.

[0130] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present application.

[0131] In addition, various aspects or features of the embodiments of the present application can be implemented as methods, devices or products using standard programming and / or engineering techniques. The term "product" used in this application covers computer programs that can be accessed from any computer-readable device, carrier or medium. For example, computer-readable media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks or tapes, etc.), optical disks (e.g., compact discs (CDs), digital versatile discs (DVDs), etc.), smart cards and flash memory devices (e.g., erasable programmable read-only memory (EPROM), cards, sticks or key drives, etc.). In addition, the various storage media described herein may represent one or more devices and / or other machine-readable media for storing information. The term "machine-readable medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing and / or carrying instructions and / or data.

[0132] In the above embodiment, Figure 8The batch demapping device 800 in the embodiment can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a high-density digital video disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0133] It should be understood that in various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0134] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0135] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0136] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0137] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or an access network device, etc.) to perform all or part of the steps of the method described in each embodiment of the embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0138] The above is only a specific implementation of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited to this. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the embodiments of the present application, which should be covered within the protection scope of the embodiments of the present application.

Claims

1. A batch demapping method, characterized in that: The heterogeneous device includes a main processor and at least one heterogeneous component, and the method is executed by the main processor, and the method includes: Allocating a demapping request to a first demapping queue of a target heterogeneous component; the demapping request instructs the main processor to release the physical mapping of the target heterogeneous component, the physical mapping of the target heterogeneous component being a mapping relationship between a virtual address and a physical address of the target heterogeneous component, and the at least one heterogeneous component including the target heterogeneous component; In the case where the length of the first demapping queue is greater than or equal to a set length threshold, all demapping requests of the first demapping queue or a number of demapping requests corresponding to the set length threshold at the front of the first demapping queue are extracted into a second demapping queue of the target heterogeneous component; the length represents the number of demapping requests; When it is detected that there are at least two consecutive virtual addresses among the virtual addresses in the physical mapping of all demapping requests of the second demapping queue, a first TLB invalidation instruction is sent to the bypass block table cache TLB, and the first TLB invalidation instruction instructs the TLB to invalidate the TLB entries corresponding to the consecutive virtual addresses, and the TLB entries record the physical mapping of the target heterogeneous component.

2. The method according to claim 1, characterized in that: When it is detected that at least two virtual addresses in the virtual addresses in the physical mapping of all demapping requests of the demapping second queue are continuous virtual addresses, before sending the first TLB invalidation instruction to the bypass block table cache TLB, the method further includes: A cleanup instruction is sent to the main memory; the main memory is used to store a physical page table, the physical page table records a mapping relationship between a virtual address and a physical address, and the cleanup instruction instructs the main memory to clean up the physical page table corresponding to the demapping request of the second demapping queue.

3. The method according to claim 1 or 2, characterized in that: The method further comprises: Releasing the physical address corresponding to the demapping request of the second demapping queue; The virtual address corresponding to the demapping request of the demapping second queue is released.

4. The method according to any one of claims 1 to 3, characterized in that: Before allocating the demapping request to the demapping first queue of the target heterogeneous component, the method further includes: Writing data to the target heterogeneous component; When a page fault is triggered, modify the logical mapping of the current virtual address to point the current virtual address to its own physical address; the page fault means that the main processor cannot access the physical address based on the virtual address; After the data writing operation is completed, the modified logical mapping is cleared.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: Detecting remaining memory; the remaining memory is the memory in an idle state allocated by the heterogeneous device to the target heterogeneous component; When the remaining memory is less than or equal to the set memory threshold, reducing the set length threshold; When the remaining memory is greater than the set memory threshold, the set length threshold is increased.

6. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: Detecting the frequency of demapping; the frequency of demapping refers to the number of demapping requests generated by the heterogeneous device for the target heterogeneous component per unit time; When the demapping frequency is greater than a set frequency threshold, increasing the sleep time of the background daemon process; the background daemon process refers to a process that automatically processes the demapping request of the first demapping queue; When the demapping frequency is less than or equal to the set frequency threshold, the sleep time of the background daemon process is reduced.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: When it is detected that the number of all demapping requests in the second demapping queue is less than a set number, a second TLB invalidation instruction is sent to the TLB; the second TLB invalidation instruction instructs the TLB to invalidate the TLB entry corresponding to the single virtual address.

8. A batch demapping device, characterized in that: include: A first processing unit, configured to distribute a demapping request to a demapping first queue of a target heterogeneous component; The demapping request instructs the main processor to release the physical mapping of the target heterogeneous component, the physical mapping of the target heterogeneous component being a mapping relationship between a virtual address and a physical address of the target heterogeneous component, and the at least one heterogeneous component includes the target heterogeneous component; a second processing unit, configured to extract, when the length of the first demapping queue is greater than or equal to a set length threshold, all demapping requests of the first demapping queue or a number of demapping requests corresponding to the set length threshold at the front of the first demapping queue into a second demapping queue of the target heterogeneous component; The length indicates the number of demapping requests; A third processing unit is configured to send a first TLB invalidation instruction to a bypass block table cache TLB when it is detected that at least two virtual addresses in the virtual addresses in the physical mapping released by all demapping requests of the second demapping queue are continuous virtual addresses, wherein the first TLB invalidation instruction instructs the TLB to invalidate the TLB entries corresponding to the continuous virtual addresses, and the TLB entries record the physical mapping of the target heterogeneous component.

9. The device according to claim 8, characterized in that The third processing unit is also used to send a cleanup instruction to the main memory; the main memory is used to store a physical page table, which records the mapping relationship between the virtual address and the physical address. The cleanup instruction instructs the main memory to clean up the physical page table corresponding to the demapping request of the demapping second queue.

10. The device according to claim 8 or 9, characterized in that The third processing unit is further used to release the physical address corresponding to the demapping request of the second demapping queue; The virtual address corresponding to the demapping request of the demapping second queue is released.

11. The device according to any one of claims 8 to 10, characterized in that: The first processing unit is further used to write data to the target heterogeneous component; When a page fault is triggered, modify the logical mapping of the current virtual address to point the current virtual address to its own physical address; The page fault means that the main processor cannot access the physical address based on the virtual address; After the data writing operation is completed, the modified logical mapping is cleared.

12. The device according to any one of claims 8 to 11, characterized in that: The third processing unit is further used to detect remaining memory; the remaining memory is the memory in an idle state allocated by the heterogeneous device to the target heterogeneous component; When the remaining memory is less than or equal to the set memory threshold, reducing the set length threshold; When the remaining memory is greater than the set memory threshold, the set length threshold is increased.

13. The device according to any one of claims 8 to 12, characterized in that: The third processing unit is further used to detect the frequency of demapping; the frequency of demapping refers to the number of demapping requests generated by the heterogeneous device for the target heterogeneous component per unit time; When the demapping frequency is greater than a set frequency threshold, increasing the sleep time of the background daemon process; the background daemon process refers to a process that automatically processes the demapping request of the first demapping queue; When the demapping frequency is less than or equal to the set frequency threshold, the sleep time of the background daemon process is reduced.

14. The device according to any one of claims 8 to 13, characterized in that: The third processing unit is further configured to send a second TLB invalidation instruction to the TLB when it is detected that the number of all demapping requests in the second demapping queue is less than a set number; the second TLB invalidation instruction instructs the TLB to invalidate the TLB entry corresponding to a single virtual address.

15. A heterogeneous device, characterized in that: include: at least one memory; at least one heterogeneous component, A main processor, wherein the main processor is used to execute instructions stored in the memory so that the heterogeneous device executes the method according to any one of claims 1 to 7.

16. A computer-readable storage medium, characterized in that: The method comprises computer program instructions, and when the computer program instructions are executed by a heterogeneous device, the computing device performs the method as claimed in any one of claims 1 to 7.

17. A computer program product comprising instructions, characterized in that The computer program product stores instructions, and when the instructions are executed by a heterogeneous device, the heterogeneous device implements the method according to any one of claims 1 to 7.

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