FLASH operation method and device, computer program product and medium

Abstract

The invention discloses a FLASH operation method and device, a computer program product and a medium, and the FLASH operation method comprises the steps: determining a target operation mode based on an operation demand; the chip of the system-on-chip can support five operation modes; sending mode indication information to the system-on-chip, wherein the mode indication information is used for indicating the target operation mode; when the target operation mode is a first mode, a first clock interface, a first master-output-slave-input interface and a first chip selection interface in the microcontroller are configured to be used for data input, and a first master-input-slave-output interface in the microcontroller is configured to be used for data output; and sending an operation instruction to the FLASH. According to the scheme, under the condition of not additionally increasing chip pins, when the microcontroller operates abnormally, the FLASH of the chip of the system on chip can be operated by multiplexing the existing GPIO pins of the chip, the difficulty of positioning the abnormal chip is reduced, and meanwhile, the operation efficiency of the FLASH is also greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of system on chip, and in particular to a FLASH operation method and device, a computer program product, and a medium. Background Art

[0002] With the rapid development of digital intelligence, automotive electronics, industrial automation and the Internet of Things, the market demand for microcontroller units (MCUs) is also growing. The functional requirements for product development using microcontrollers are becoming more and more diverse, resulting in a sharp increase in the amount of code, requiring microcontrollers to embed larger memory.

[0003] At present, the use of external FLASH has become the mainstream solution for development, which can effectively reduce the production cost of chips and increase product flexibility. External FLASH completes data burning and reading through the serial peripheral interface (Serial Peripheral Interface, SPI). External FLASH is usually packaged with MCU to form a complete system on chip (System on Chip, SoC).

[0004] In the prior art, external devices (such as a host computer, a debugger, etc.) perform operations such as reading, writing, and erasing on FLASH through a microcontroller. When the microcontroller cannot operate normally, the external devices cannot operate on FLASH. Summary of the invention

[0005] The present invention can directly operate the FLASH of the system-on-chip chip by reusing the existing GPIO pins of the system-on-chip chip when the microcontroller does not operate normally, thereby reducing the difficulty of locating the abnormal chip and greatly improving the operating efficiency of the FLASH.

[0006] In a first aspect, the present invention provides a FLASH operation method, wherein the FLASH is located in a system-on-chip chip, and the system-on-chip chip also includes a microcontroller; the SPI interface of the microcontroller includes a first clock interface, a first master-output slave input interface, a first master-input slave output interface, and a first chip select interface, the first master-output slave input interface is coupled to the first data interface of the FLASH through a first GPIO interface, and the first master-input slave output interface is coupled to the second data interface of the FLASH through a second GPIO interface; the FLASH operation method includes: determining a target operation mode based on operation requirements; the operation requirements include at least one of the following: a response speed for operating the FLASH, a speed of operating the FLASH, a The number of GPIOs required for the operation and whether encryption protection is required for the operation of the FLASH; sending mode indication information to the system-on-chip chip, the mode indication information is used to indicate the target operation mode; when the target operation mode is the first mode, the first clock interface, the first master-output slave-input interface and the first chip select interface in the microcontroller are configured for data input, and the first master-input slave-output interface in the microcontroller is configured for data output; the first mode is: an operation mode in which an operation instruction is sent to the FLASH through the SPI interface; sending an operation instruction to the FLASH, the operation instruction is used to perform any of the following operations on the FLASH: a read operation, a write operation, and an erase operation.

[0007] In the first mode, the host computer can complete the operation of the FLASH of the system-on-chip chip through the SPI interface of the burner / debugger. In the process of operating the FLASH, the microcontroller does not need to participate in the running program.

[0008] Moreover, in the process of operating FLASH, the response speed is related to the maximum rate supported by the GPIO interface and FLASH. At the same time, by reusing the GPIO interface of the microcontroller, there is no need to add a new GPIO interface, thus reducing the implementation complexity.

[0009] Optionally, when the target operating mode is the first mode, sending mode indication information to the microcontroller includes: outputting a low-level signal to a reset pin of the microcontroller to trigger the microcontroller to enter a reset state; outputting an unlock code to the microcontroller, wherein the unlock code is used to unlock the microcontroller; and outputting a first operating mode code to the microcontroller, wherein the first operating mode code indicates that the target operating mode is the first mode.

[0010] Optionally, the target operation mode also includes: a second mode of sending the operation instruction to the microcontroller system startup control boot module in the microcontroller through the UART interface; the target operation mode is the second mode, and the sending of mode indication information to the microcontroller includes: controlling the level of the boot pin of the microcontroller to be a first level; controlling the microcontroller to perform a reset operation; when the level of the boot pin is the first level, the target operation mode is the second mode; in the second mode, the first master input slave output interface is coupled to the receiving interface of the UART module in the microcontroller, and the first master output slave input interface is coupled to the sending interface of the UART module; the UART module is coupled to the microcontroller system startup control boot module.

[0011] Optionally, the target operation mode also includes: a third mode of sending the operation instruction to the microcontroller system startup control boot module in the microcontroller through the SPI interface; the target operation mode is the third mode, and the sending of mode indication information to the microcontroller includes: controlling the level of the boot pin of the microcontroller to be the second level; controlling the microcontroller to perform a reset operation; when the level of the boot pin is the second level, the target operation mode is the third mode; in the third mode, the SPI interface of the microcontroller is coupled one-to-one with the interface of the SPI module in the microcontroller.

[0012] Optionally, the microcontroller automatically encrypts the data corresponding to the write operation in hardware mode, and writes the encrypted data into the FLASH to protect the code.

[0013] Optionally, the microcontroller performs automatic hardware mode CRC verification on the data stored in the FLASH to improve the reliability of data writing and improve the efficiency of data reading verification.

[0014] Optionally, the FLASH operation method further includes: sending a boot instruction to the microcontroller, wherein the boot instruction instructs the microcontroller system to start a control boot module to guide the PC pointer of the processor core of the microcontroller to run in the FLASH, or to run in the SRAM of the microcontroller.

[0015] Optionally, the target operation mode also includes: a fourth mode of sending the operation instruction to the SWD debugging module in the processor core in the microcontroller through the serial wire debugging interface; the target operation mode is the fourth mode, and the sending of mode indication information to the microcontroller includes: sending a connection command to the microcontroller, and the connection command indicates that the target operation mode is the fourth mode.

[0016] Optionally, the FLASH operation method also includes: sending the fifth mode of the FLASH operation instruction to the protocol conversion module in the microcontroller through a two-wire ISP interface; the target operation mode is the fifth mode, and sending mode indication information to the microcontroller includes: outputting a low-level signal to a reset pin of the microcontroller to trigger the microcontroller to enter a reset state; outputting an unlock code to the microcontroller, the unlock code being used to unlock the microcontroller; outputting a fifth operation mode code to the microcontroller, the fifth operation mode code indicating that the target operation mode is the fifth mode.

[0017] Optionally, the microcontroller includes a mode unlocking and mode selection module, and a GPIO multiplexing selector; the mode unlocking and analog selection module is suitable for outputting the first operating mode code to the GPIO multiplexing selector to use the first mode as the target operating mode; or, the mode unlocking and analog selection module is suitable for outputting the fifth operating mode code to the GPIO multiplexing selector to use the fifth mode as the target operating mode.

[0018] Optionally, the protocol conversion module, the mode unlocking and analog selection module, and the GPIO multiplexing selector all operate in a high voltage domain; or, the protocol conversion module, the mode unlocking and analog selection module, and the GPIO multiplexing selector all operate in a low voltage domain.

[0019] In a second aspect, the present invention provides a FLASH operating device, wherein the FLASH is located in a system-on-chip chip, and the system-on-chip chip also includes a microcontroller; the SPI interface of the microcontroller includes a first clock interface, a first master-output slave input interface, a first master-input slave output interface, and a first chip select interface, the first master-output slave input interface is coupled to the first data interface of the FLASH through a first GPIO interface, and the first master-input slave output interface is coupled to the second data interface of the FLASH through a second GPIO interface; the FLASH operating device includes: a determination unit, which is used to determine a target operating mode based on an operation requirement; the operation requirement includes at least one of the following: a response speed for operating the FLASH, a G number required for operating the FLASH, The number of PIOs and whether encryption protection is required for operating the FLASH; a first sending unit is used to send mode indication information to the system-on-chip chip, and the mode indication information is used to indicate the target operation mode; when the target operation mode is the first mode, the first clock interface, the first master-output slave-input interface and the first chip select interface in the microcontroller are configured for data input, and the first master-input slave-output interface in the microcontroller is configured for data output; the first mode is: an operation mode in which operation instructions are sent to the FLASH through the SPI interface; a second sending unit is used to send operation instructions to the FLASH, and the operation instructions are used to perform any of the following operations on the FLASH: read operation, write operation, and erase operation.

[0020] In a third aspect, the present invention further provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above-mentioned FLASH operation methods are executed.

[0021] In a fourth aspect, the present invention provides a computer program product, comprising a computer program / instruction, wherein the computer program / instruction, when executed by a processor, implements the steps of any one of the above-mentioned FLASH operation methods.

[0022] In a fifth aspect, the present invention further provides another device, comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, and the processor executes the steps of any one of the above-mentioned FLASH operation methods when running the computer program. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural diagram of a FLASH operating system in an embodiment of the present invention;

[0024] Figure 2is a flow chart of a FLASH operation method in an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of the connection between a microcontroller and FLASH in a first mode in an embodiment of the present invention;

[0026] Figure 4 is a structural schematic diagram of a FLASH operating device in an embodiment of the present invention;

[0027] Figure 5 It is a schematic diagram of implementing GPIO pin coupling in a first mode in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] As described in the background art, in the prior art, external devices (such as host computers, debuggers, etc.) perform operations such as reading, writing, and erasing on FLASH through a microcontroller. When the microcontroller cannot operate normally, the external devices cannot operate on FLASH.

[0029] In the embodiment of the present invention, in the first mode, the host computer can complete the operation of the FLASH of the system-on-chip chip through the SPI interface of the burner / debugger. In the process of operating the FLASH, the microcontroller does not need to run the program. In addition, in the process of operating the FLASH, the response speed is related to the maximum rate supported by the GPIO interface and the FLASH. At the same time, by multiplexing the GPIO interface of the microcontroller, there is no need to add a new GPIO interface, thereby reducing the implementation complexity.

[0030] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] The embodiment of the present invention provides a FLASH operating system, referring to Figure 1 The FLASH operating system includes a host computer, a burner / debugger, and a system-on-chip chip.

[0032] In an embodiment of the present invention, the system-on-chip chip may include FLASH and a microcontroller, and the microcontroller and the FLASH are combined into a system-on-chip chip by means of internal sealing and wire bonding.

[0033] The system-on-chip chip is coupled to a burner / debugger, which can communicate with a host computer via data line transmission or wireless transmission to receive instructions input by a tester through the host computer.

[0034] In the embodiment of the present invention, the tester may send an operation instruction to the system-on-chip chip through the host computer, and the operation instruction may instruct to perform any one or more operations such as read operation, write operation, erase operation, etc. on the FLASH in the system-on-chip chip.

[0035] In a specific implementation, the microcontroller in the system-on-chip chip can be coupled to the burner / debugger via a serial peripheral interface (SPI) bus. The microcontroller may include an SPI interface, and accordingly, the burner / debugger also includes an SPI interface. The SPI interface of the microcontroller is connected to the SPI interface of the burner / debugger via the SPI bus.

[0036] In specific applications, it can be known that the SPI interface may include a clock (SPI_SCK) interface, a master-output slave-input (SPI_MOSI) interface, a master-input slave-output (SPI_MISO) interface, and a chip select (SPI_NSS) interface.

[0037] Among them, the clock (SPI_SCK) interface is used for communication data synchronization, which is generated by the host and determines the communication frequency. The highest clock frequency supported by different hosts can be different. The host reads the slave data through the master input slave output (SPI_MISO) interface, and the slave data is output to the host through the master input slave output (SPI_MISO) interface, that is, on the master input slave output (SPI_MISO) interface, the data transmission direction is from the slave to the host. The host outputs data to the slave through the master output slave input (SPI_MOSI) interface, and the slave reads the data sent by the host through the master output slave input (SPI_MOSI) interface, that is, on the master output slave input (SPI_MOSI) interface, the data transmission direction is from the host to the slave. The host selects the corresponding slave through the chip select (SPI_NSS) interface.

[0038] In the embodiment of the present invention, the host may be a host computer or a debugger, and correspondingly, the slave may be a microcontroller. The microcontroller includes a first clock (SPI_SCK) interface, a first master-output slave-input (SPI_MOSI) interface, a first master-input slave-output (SPI_MISO) interface, and a first chip select (SPI_NSS) interface.

[0039] like Figure 1 As shown, the first clock (SPI_SCK) interface of the microcontroller corresponds to the PA0 interface, the first master-output slave-input (SPI_MOSI) interface corresponds to the PA1 interface, the first master-input slave-output (SPI_MISO) interface corresponds to the PA2 interface, and the first chip select (SPI_NSS) interface corresponds to the PA3 interface.

[0040] In a specific implementation, the microcontroller may also include: a processor core, a static random access memory (SRAM), a microcontroller system boot control module (BOOT ROM), an extended SPI (QSPI) module, a universal asynchronous receiver transmitter (UART) module, a general purpose input / output interface (GPIO) multiplexer (MUX) and other modules. The processor core may include a serial wire debug (SWD) module and a core, etc.

[0041] In a specific implementation, the microcontroller can communicate with the FLASH through a GPIO interface. Specifically, the microcontroller can communicate with the FLASH through a GPIO multiplexer.

[0042] like Figure 1 As shown, the microcontroller communicates with FLASH through PC0~PC5 interfaces, wherein: the PC0 port is coupled to the chip select (CS) interface of FLASH, the PC1 interface is coupled to the clock (SCK) interface of FLASH, the PC2 interface is coupled to the first data (DQ0) interface of FLASH, the PC3 interface is coupled to the second data (DQ1) interface of FLASH, the PC4 interface is coupled to the third data (DQ2) interface of FLASH, and the PC5 interface is coupled to the fourth data (DQ3) interface of FLASH.

[0043] It should be noted that the above PC0-PC5 interfaces are only shown as 6 GPIO interfaces connected between the microcontroller and FLASH. In actual applications, the names and numbers of the GPIO interfaces connected between the microcontroller and FLASH may be different.

[0044] Figure 1 In the example, the PA0~PA3 interface, PB0 interface, PB1 interface, and MRST interface of the SoC chip are actually the wire bonding PAD headers of the corresponding interfaces in the microcontroller. In other words, the PA0 interface of the microcontroller is connected to the burner / debugger through the PA0 interface of the SoC chip, and so on.

[0045] The embodiment of the present invention also provides a FLASH operation method, referring to Figure 2 , the following combination Figure 1 Provide detailed explanation.

[0046] Step 201, determining a target operation mode based on operation requirements.

[0047] In an embodiment of the present invention, the host computer may determine the target operation mode based on the operation requirements, which may include any one or more of the response speed of the FLASH operation, the number of GPIOs required for the FLASH operation, and whether the FLASH operation requires encryption protection.

[0048] Alternatively, the operation requirement can also be associated with the tester's input. In other words, the tester can select the target operation mode through the host computer and the debugger.

[0049] Step 202: Send mode indication information to the system-on-chip chip.

[0050] In a specific implementation, the mode guide pin of the microcontroller is controlled and the host computer sends mode indication information to the system-on-chip chip to inform the microcontroller of the target operation mode.

[0051] In the embodiment of the present invention, the target operation mode may include a first mode, and the first mode may be an operation mode in which an operation instruction is directly sent to FLASH via an SPI interface.

[0052] In a specific implementation, the microcontroller may include a reset pin (MRST). When the host computer selects the first mode as the target operation mode, the host computer may output a low level signal to the reset pin of the microcontroller. When the microcontroller detects that the level on the reset pin is a low level signal, it enters a reset state.

[0053] The host computer and the debugger send an unlock code to the microcontroller through a two-wire ISP interface. The microcontroller receives the unlock code and performs an unlock operation. The host computer sends a first operation mode code to the microcontroller, and the first operation mode code indicates that the target operation mode is the first mode. The microcontroller receives the first operation mode code and determines that the current target operation mode is the first mode.

[0054] In a specific implementation, the unlock code may be of a fixed length. In some embodiments, the unlock code may be 18 bytes long. It is understood that the specific length of the unlock code may also be set according to different application scenarios.

[0055] Step 203: Send an operation instruction to FLASH.

[0056] In an embodiment of the present invention, when the microcontroller determines that the target operation mode is the first mode, the microcontroller can configure the first clock interface, the first master-output-slave-input interface and the first chip select interface for data input, and the first master-input-slave-output interface for data output.

[0057] Depend on Figure 1It can be seen that the first clock interface is coupled to the PC1 interface of the GPIO multiplexer, and the PC1 interface is coupled to the clock (SCK) interface of the FLASH; the first master-output slave-input interface is coupled to the first data (DQ0) interface of the FLASH through the first GPIO interface (PC2), the first master-input slave-output interface is coupled to the second data (DQ1) interface of the FLASH through the second GPIO interface (PC3), and the first chip select interface is coupled to the chip select (CS#) interface of the FLASH through the PC0 interface.

[0058] For FLASH, since the first master-output slave-input interface is used for data input and the first master-input slave-output interface is used for data output, the first data interface of FLASH is used to receive data and the second data interface of FLASH is used to output data. Therefore, the host computer and debugger can output operation instructions to FLASH to implement the operation of FLASH.

[0059] In a specific implementation, the operation instruction can be used to perform any of the following operations on the FLASH: a read operation, a write operation, an erase operation, etc.

[0060] Reference Figure 3 , gives a schematic diagram of the connection between the microcontroller and FLASH in a first mode in an embodiment of the present invention.

[0061] Figure 3 In the first mode: the PA0 interface of the microcontroller is used for data input (that is, for inputting data into FLASH), and is coupled to the SCK interface of FLASH through the PC1 interface of the GPIO multiplexer; the PA1 interface of the microcontroller is used for data input, and is coupled to the DQ0 interface of FLASH through the PC2 interface of the GPIO multiplexer; the PA2 interface of the microcontroller is used for data output (that is, for outputting data in FLASH), and is coupled to the DQ1 interface of FLASH through the PC3 interface of the GPIO multiplexer; the PA3 interface of the microcontroller is used for data input, and is coupled to the CS# interface of FLASH through the PC0 interface of the GPIO multiplexer.

[0062] It can be seen that in the first mode, the host computer can complete the operation of the FLASH of the system-on-chip chip through the SPI interface of the burner / debugger. In the process of operating the FLASH, it is only necessary for the microcontroller to be able to unlock and parse the first operation mode code normally, without the participation of the microcontroller running program. Therefore, in the process of operating the FLASH, the response speed is related to the maximum rate supported by the GPIO interface and the FLASH. At the same time, by reusing the GPIO interface of the microcontroller, there is no need to add a new GPIO interface, reducing the complexity of implementation.

[0063] In the embodiment of the present invention, the target operation mode may further include a fifth mode, and the fifth mode may be:

[0064] In a specific implementation, when the host computer selects the fifth mode as the target operation mode, the host computer can output a low level signal to the reset pin of the microcontroller. When the microcontroller detects that the level on the reset pin is a low level signal, it enters a reset state.

[0065] The host computer and the debugger send an unlock code to the microcontroller through the two-wire ISP interface. The microcontroller receives the unlock code and performs an unlock operation. The host computer sends a fifth operation mode code to the microcontroller, and the fifth operation mode code indicates that the target operation mode is the fifth mode. The microcontroller receives the fifth operation mode code and determines that the current target operation mode is the fifth mode.

[0066] In a specific implementation, the unlock code may be of a fixed length. In some embodiments, the unlock code may be 18 bytes long. It is understood that the specific length of the unlock code may also be set according to different application scenarios.

[0067] In an embodiment of the present invention, the microcontroller may further include a protocol conversion ISP module (ISPM_CTRL), the ISP module including a clock pin (ISP_SCK) and a data input / output pin (ISP_DIO). The clock pin of the ISP module is coupled to the clock (SPI_SCK) interface of the SPI interface, and the data input / output pin (ISP_DIO) of the ISP module is coupled to the first master-output-slave-input (SPI_MOSI) interface of the SPI interface.

[0068] In other words, the ISP module can reuse the clock (SPI_SCK) interface and the first master-output-slave-input (SPI_MOSI) interface of the SPI interface.

[0069] In a specific implementation, the microcontroller may further include a mode unlocking and mode selecting (FLS_CTRL) module. The mode unlocking and mode selecting module may be used to select the target operation mode as the first mode or the fifth mode.

[0070] like Figure 1 As shown, when the ISPM_EN output by the mode unlocking and mode selection module to the ISP module is a high level signal, it indicates that the target operation mode selected by the microcontroller is the fifth mode. When the SPIM_EN output by the mode unlocking and mode selection module to the GPIOMUX is a high level signal, it indicates that the target operation mode selected by the microcontroller is the first mode.

[0071] In a specific implementation, the ISP module can implement protocol conversion, and can convert a two-wire serial ISP interface into a four-wire SPI interface, thereby realizing communication with SPI_FLASH. The above-mentioned four-wire SPI interface can include ISP_NSS, ISP_SCK, ISP_MOSI, and ISP_MISO.

[0072] In the embodiment of the present invention, the above-mentioned FLS_CTRL, SIPM_CTRL, GPIO MUX and other circuits can be implemented by high-voltage circuits, such as 3.5V / 5V circuits; the above-mentioned FLS_CTRL, SIPM_CTRL, GPIO MUX and other circuits can also be implemented by low-voltage circuits, such as 1.1V / 1.5V circuits. The advantage of using high-voltage circuits is that when the low-dropout linear regulator (LDO) or DC-to-DC (DCDC) circuit of the system-on-chip chip is abnormal, the access operation to SPI_FLASH can also be implemented.

[0073] In an embodiment of the present invention, when the microcontroller includes a microcontroller system startup control boot module (BOOT ROM), the target operation mode may also include a second mode or a third mode, wherein: the second mode may be: sending operation instructions to the boot program storage module in the microcontroller through the UART interface; the third mode may be: sending operation instructions to the microcontroller system startup control boot module through the SPI interface.

[0074] In the microcontroller system startup control boot module, a section of application program is pre-cured. The host computer can interact with the boot program storage module through the UART interface or SPI interface, and can guide the microcontroller core to FLASH or SRAM to run the program.

[0075] In a specific implementation, the microcontroller may include a boot pin. The host computer or the debugger may indicate to the microcontroller that the target operation mode is the second mode or the third mode by controlling the level of the boot pin.

[0076] In an embodiment of the present invention, when the host computer determines that the target operation mode is the second mode, the level of the boot pin of the microcontroller is controlled to be the first level, and the microcontroller is reset. The microcontroller detects that the level of the boot pin is the first level, and determines that the target operation mode is the second mode.

[0077] In a specific implementation, when the target operation mode is the second mode, the host computer can send a startup code to the microcontroller. The microcontroller successfully receives the startup code (such as 0x3F) and can reply with a synchronization completion code (such as 0x79).

[0078] To ensure data security, the host computer can send control instructions only after the microcontroller has completed unlocking. The host computer can send an unlock code to the microcontroller. The microcontroller performs subsequent operations on the FLASH only after receiving the unlock code.

[0079] When the host computer determines that the target operation mode is the third mode, the level of the boot pin of the microcontroller is controlled to be the second level, and the microcontroller is reset. The microcontroller detects that the level of the boot pin is the second level, and determines that the target operation mode is the third mode. The first level is different from the second level.

[0080] When the microcontroller determines that the target operation mode is the third mode, the host computer can send an unlock code to the microcontroller. The microcontroller performs subsequent operations on the FLASH only after receiving the unlock code.

[0081] In some embodiments, the number of guide pins can be 1. When the level of the guide pin is a first level (such as a low level), the microcontroller determines that the target operation mode is the second mode; when the level of the guide pin is a second level (such as a high level), the microcontroller determines that the target operation mode is a third mode.

[0082] In other embodiments, Figure 1 As shown, the boot pins may include a first boot pin PB0 and a second boot pin PB1.

[0083] When the level of the first boot pin PB0 is low and the level of the second boot pin PB1 is low, the microcontroller system can start the control boot module to guide the microcontroller core to FLASH to run the program; when the level of the first boot pin PB0 is high and the level of the second boot pin PB1 is low, the microcontroller can determine that the target operation mode is the second mode, and the host computer operates the FLASH through the UART interface; when the level of the first boot pin PB0 is low and the level of the second boot pin PB1 is high, the microcontroller can guide the microcontroller core to SRAM to run the program through the boot program storage module; when the level of the first boot pin PB0 is low and the level of the second boot pin PB1 is low, the microcontroller can determine that the target operation mode is the third mode, and the host computer and the debugger can operate the FLASH through the SPI interface.

[0084] It is understandable that the number of the above-mentioned guide pins can also be one or other numbers. When the guide pins include the first guide pin PB0 and the second guide pin PB1, the corresponding relationship between the levels of the first guide pin PB0 and the second guide pin PB1 and the target operation mode can also be set according to the actual application scenario.

[0085] In the embodiment of the present invention, when the target operation mode is the second mode, the first master input slave output interface of the microcontroller is coupled to the receiving interface (RX) of the UART module in the microcontroller, and the first master output slave input interface of the microcontroller is coupled to the transmitting interface (TX) of the UART module. The UART module is coupled to the microcontroller system startup control boot module.

[0086] When the target operation mode is the second mode, it is only necessary to use the first master input slave output interface (PA0) to receive data and the first master output slave input interface (PA1) to send data to realize UART communication. That is to say, in the second mode, the host computer can use only two GPIO interfaces (PA0 and PA1) to realize UART communication with the microcontroller. The host computer can send operation instructions to the microcontroller system startup control boot module through the above two GPIO interfaces. The application in the microcontroller system startup control boot module controls the QSPI controller to perform corresponding operations on the FLASH based on the operation instructions.

[0087] When the first master-input-slave-output interface and the first master-output-slave-input interface are used to implement UART communication, automatic baud rate detection and setting are supported.

[0088] When the target operation mode is the third mode, the interface of the SPI module of the microcontroller is coupled to the SPI interface of the microcontroller in a one-to-one correspondence. The above-mentioned one-to-one correspondence coupling is: the NSS interface of the SPI module is coupled to the PA3 interface, the SCK interface of the SPI module is coupled to the PA0 interface, the MOSI interface of the SPI module is coupled to the PA1 interface, and the MISO interface of the SPI interface is coupled to the PA2 interface.

[0089] In the second mode, the host computer and debugger can use four GPIO interfaces (PA0, PA1, PA2 and PA3) to realize SPI communication with the microcontroller. The host computer and debugger can send operation instructions to the microcontroller system startup control boot module through the above four GPIO interfaces. The application in the boot program storage module enables the QSPI controller to perform corresponding operations on the FLASH based on the operation instructions.

[0090] In the second mode / third mode, after completing the operation on FLASH, the host computer can also send a boot instruction (such as a GO instruction) to the microcontroller, and boot the microcontroller core to SRAM or FLASH to run the program through the microcontroller system startup control boot module.

[0091] In the second mode / third mode, in order to ensure the data security in FLASH and prevent the data stored in FLASH from being read and cracked by external devices, the microcontroller can encrypt the data received from the host computer and debugger, and burn the encrypted data into FLASH to improve data security.

[0092] Specifically, the microcontroller can encrypt data using a preset key, the key length can be 128 bits or other lengths, and only supports write operations of application software but not read operations of application software. The key is only visible to the internal hardware circuit of the microcontroller. When the microcontroller runs a program, the corresponding key can be used to automatically decrypt the data stored in the FLASH.

[0093] In order to realize the read verification of the data stored in FLASH and improve the efficiency of the read verification, the microcontroller can also perform a cyclic redundancy check (CRC) on the data in FLASH. The host computer and debugger can send a CRC check command to the microcontroller. After receiving the CRC check command, the microcontroller can perform a CRC check operation on the data in FLASH to improve the reliability of data writing and the efficiency of data read verification.

[0094] If the data in FLASH has been encrypted, the data in FLASH is first decrypted, and then a CRC check operation is performed to determine whether the data in FLASH is correct; if the data in FLASH has not been encrypted, a CRC check operation is directly performed on the data in FLASH to determine whether the data in FLASH is correct.

[0095] In an embodiment of the present invention, the target operation mode may further include: a fourth mode of sending the operation instruction to the SWD debugging module in the microcontroller through the SWD debugging interface. The host computer may send a connection command to the microcontroller, and the connection command indicates that the target operation mode is the fourth mode. When the microcontroller receives the connection command, it can determine that the target operation mode is the fourth mode.

[0096] In the specific implementation, the host computer and debugger can transfer the burning algorithm of FLASH and the program code or data to be burned to the debugging module of the microcontroller through the USB interface. The host computer first burns the burning algorithm into SRAM, and then burns the program code to be burned into the data cache area of ​​SRAM. The execution process of the burning program is controlled by the host computer and the debugging module, and the program code stored in the data cache area of ​​SRAM is burned into FLASH.

[0097] Reference Figure 5, a schematic diagram of implementing GPIO pin coupling in a first mode in an embodiment of the present invention is given.

[0098] Figure 5 In the example, for PAD0-PAD2, it includes a Schmidt trigger and a level shifter. For PAD3, it includes a level shifter and a driver buffer. Correspondingly, for PC0-PC2, it includes a level shifter and a driver buffer. For PC3, it includes a Schmidt trigger and a level shifter.

[0099] FLS_CTRL can output SPIM_EN to GPIO MUX to select the first mode.

[0100] Figure 5 In the data input, FROMPAD represents data input, TOPAD represents data output, and PAD is the pad.

[0101] When the first mode is selected as the target operation mode, the GPIO MUX can select SPI_NSS, SPI_SCK, SPI_MOSI, and SPI_MISO to pass.

[0102] Reference Figure 4 The present invention further provides a FLASH operating device 40, comprising:

[0103] The determination unit 401 is used to determine the target operation mode based on the operation requirements; the operation requirements include at least one of the following: the response speed of the operation on the FLASH, the number of GPIOs required for the operation on the FLASH, and whether the operation on the FLASH requires encryption protection;

[0104] The first sending unit 402 is used to send mode indication information to the system-on-chip chip, where the mode indication information is used to indicate the target operation mode; when the target operation mode is the first mode, the first clock interface, the first master-output-slave-input interface and the first chip select interface in the microcontroller are configured for data input, and the first master-input-slave-output interface in the microcontroller is configured for data output; the first mode is an operation mode in which an operation instruction is sent to the FLASH via the SPI interface;

[0105] The second sending unit 403 is used to send an operation instruction to the FLASH, where the operation instruction is used to perform any of the following operations on the FLASH: a read operation, a write operation, and an erase operation.

[0106] In the embodiment of the present invention, the above-mentioned FLASH operating device 40 may correspond to the above-mentioned host computer.

[0107] The present invention also provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the FLASH operation method provided in any of the above embodiments are executed.

[0108] The present invention also provides a computer program product, including a computer program / instruction, which implements the steps of the FLASH operating method provided in any of the above embodiments when executed by a processor.

[0109] An embodiment of the present invention further provides another FLASH operating device, including a memory and a processor, wherein the memory stores a computer program executable on the processor, and the processor executes the steps of the FLASH operating method provided in any of the above embodiments when running the computer program.

[0110] A person skilled in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by instructing the relevant hardware through a program, and the program may be stored in a computer-readable storage medium, which may include: ROM, RAM, disk or CD, etc.

[0111] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A FLASH operation method, wherein the FLASH is located in a system-on-chip chip, and the system-on-chip chip also includes a microcontroller; characterized in that: The SPI interface of the microcontroller includes a first clock interface, a first master-output slave-input interface, a first master-input slave-output interface and a first chip select interface, the first master-output slave-input interface is coupled to the first data interface of the FLASH through a first GPIO interface, and the first master-input slave-output interface is coupled to the second data interface of the FLASH through a second GPIO interface; the FLASH operation method includes: Determine the target operation mode based on the operation requirements; the operation requirements include at least one of the following: the response speed of the operation on the FLASH, the number of GPIOs required for the operation on the FLASH, and whether the operation on the FLASH requires encryption protection; Sending mode indication information to the system-on-chip chip, wherein the mode indication information is used to indicate the target operation mode; when the target operation mode is the first mode, the first clock interface, the first master-output slave-input interface and the first chip select interface in the microcontroller are configured for data input, and the first master-input slave-output interface in the microcontroller is configured for data output; the first mode is: an operation mode in which an operation instruction is sent to the FLASH through the SPI interface; sending an operation instruction to the FLASH, wherein the operation instruction is used to perform any of the following operations on the FLASH: a read operation, a write operation, and an erase operation.

2. The FLASH operation method according to claim 1, characterized in that: When the target operation mode is the first mode, sending mode indication information to the microcontroller includes: Outputting a low level signal to a reset pin of the microcontroller to trigger the microcontroller to enter a reset state; Outputting an unlock code to the microcontroller, wherein the unlock code is used to unlock the microcontroller; A first operation mode code is output to the microcontroller, the first operation mode code indicating that the target operation mode is the first mode.

3. The FLASH operating method according to claim 1, characterized in that: The target operation mode also includes: a second mode in which the operation instruction is sent to a microcontroller system startup control boot module in the microcontroller via a UART interface; The target operation mode is the second mode, and the sending mode indication information to the microcontroller includes: Controlling the level of the boot pin of the microcontroller to be a first level; Controlling the microcontroller to perform a reset operation; When the level of the boot pin is the first level, the target operation mode is the second mode; in the second mode, the first master input slave output interface is coupled to the receiving interface of the UART module in the microcontroller, and the first master output slave input interface is coupled to the transmitting interface of the UART module; the UART module is coupled to the microcontroller system startup control boot module.

4. The FLASH operating method according to claim 1, wherein: The target operation mode also includes: a third mode of sending the operation instruction to a microcontroller system startup control boot module in the microcontroller through an SPI interface; The target operation mode is the third mode, and the sending mode indication information to the microcontroller includes: Controlling the level of the boot pin of the microcontroller to be a second level; Controlling the microcontroller to perform a reset operation; When the level of the boot pin is the second level, the target operation mode is the third mode; in the third mode, the SPI interface of the microcontroller is coupled to the interface of the SPI module in the microcontroller in a one-to-one correspondence.

5. The FLASH operating method according to claim 3 or 4, characterized in that: Also includes: The microcontroller automatically performs hardware mode encryption on the data corresponding to the write operation, and writes the encrypted data into the FLASH.

6. The FLASH operating method according to claim 3 or 4, characterized in that: Also includes: The microcontroller performs an automatic hardware mode cyclic redundancy check on the data stored in the FLASH.

7. The FLASH operating method according to claim 3 or 4, characterized in that: Also includes: A boot instruction is sent to the microcontroller, wherein the boot instruction instructs the microcontroller system to start a control boot module to guide the PC pointer of the processor core of the microcontroller to run in the FLASH or in the SRAM of the microcontroller.

8. The FLASH operating method according to claim 1, characterized in that: The target operation mode also includes: a fourth mode of sending the operation instruction to the processor core SWD debug module of the microcontroller through the serial wire debug interface; The target operation mode is the fourth mode, and the sending mode indication information to the microcontroller includes: A connection command is sent to the microcontroller, wherein the connection command indicates that the target operation mode is the fourth mode.

9. The FLASH operating method according to claim 1, characterized in that: Also includes: A fifth mode of sending the FLASH operation instruction to a protocol conversion module in the microcontroller through an ISP interface; The ISP interface is a two-wire interface; The target operation mode is the fifth mode, and the sending mode indication information to the microcontroller includes: Outputting a low level signal to a reset pin of the microcontroller to trigger the microcontroller to enter a reset state; Outputting an unlock code to the microcontroller, wherein the unlock code is used to unlock the microcontroller; A fifth operation mode code is output to the microcontroller, wherein the fifth operation mode code indicates that the target operation mode is the fifth mode.

10. The FLASH operating method according to claim 9, characterized in that: The microcontroller includes a mode unlocking and mode selecting module, and a GPIO multiplexing selector; the mode unlocking and analog selecting module is suitable for outputting the first operation mode code to the GPIO multiplexing selector to use the first mode as the target operation mode; or, the mode unlocking and analog selecting module is suitable for outputting the fifth operation mode code to the GPIO multiplexing selector to use the fifth mode as the target operation mode.

11. The FLASH operating method according to claim 10, characterized in that: The protocol conversion module, the mode unlocking and analog selection module, and the GPIO multiplexing selector all operate in a high voltage domain; or, the protocol conversion module, the mode unlocking and analog selection module, and the GPIO multiplexing selector all operate in a low voltage domain.

12. A FLASH operating device, wherein the FLASH is located in a system-on-chip chip, and the system-on-chip chip also includes a microcontroller; characterized in that: The SPI interface of the microcontroller includes a first clock interface, a first master-output slave-input interface, a first master-input slave-output interface and a first chip select interface, the first master-output slave-input interface is coupled to the first data interface of the FLASH through a first GPIO interface, and the first master-input slave-output interface is coupled to the second data interface of the FLASH through a second GPIO interface; the FLASH operating device includes: A determination unit, configured to determine a target operation mode based on an operation requirement; the operation requirement includes at least one of the following: a response speed of operating the FLASH, a number of GPIOs required for operating the FLASH, and whether encryption protection is required for operating the FLASH; A first sending unit is used to send mode indication information to the system-on-chip chip, wherein the mode indication information is used to indicate the target operation mode; when the target operation mode is the first mode, the first clock interface, the first master-output-slave-input interface and the first chip select interface in the microcontroller are configured for data input, and the first master-input-slave-output interface in the microcontroller is configured for data output; the first mode is an operation mode of sending operation instructions to the FLASH through the SPI interface; The second sending unit is used to send an operation instruction to the FLASH, where the operation instruction is used to perform any of the following operations on the FLASH: a read operation, a write operation, and an erase operation.

13. A computer-readable storage medium, wherein the computer-readable storage medium is a non-volatile storage medium or a non-transient storage medium, and a computer program is stored thereon, wherein: When the computer program is executed by a processor, the steps of the FLASH operating method according to any one of claims 1 to 11 are executed.

14. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the FLASH operating method according to any one of claims 1 to 11 are implemented.

15. A FLASH operating device, comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, characterized in that: When the processor runs the computer program, the steps of the FLASH operating method according to any one of claims 1 to 11 are executed.

Images