Chip pin processing method and device, storage medium and electronic equipment

Abstract

Embodiments of the present application provide a chip pin processing method and device, a storage medium and an electronic device, which are related to the field of computers and include the following steps: obtaining a first array composed of attribute information of each pin in a first group of pins of a target chip, wherein a group of signal lines exist around the target chip and are not connected with wires; determining a second group of pins with a network name to be replaced from the first group of pins based on the first array and a second array composed of signal attributes of each signal line in the group of signal lines; saving the attribute information of each pin in the second group of pins into a target array corresponding to a target region according to a region division rule, wherein the target region is obtained by dividing a region occupied by the target chip; and replacing a network name of a candidate pin with a target network name of a target pin based on first position information of a signal line of the target pin in the target array.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically, to a method and apparatus for processing chip pins, a storage medium, and an electronic device. Background Technology

[0002] With the development of cloud computing applications, people's work and life have placed higher demands on the computing speed, storage capacity and management efficiency of servers. In order to meet these demands, the number of pins of the chips in the server has increased, making the PCB (Printed Circuit Board) design increasingly complex.

[0003] In the PCB design process, considering factors such as signal trace length and PCB layer limitations, it is often necessary to change the pin signal names of chips. In related technologies, Allegro software is usually used to change the pin net names. For example, first find an empty pin on the chip, then click the corresponding change command to change the net name of the current pin to the empty pin, and then repeat the change command to change other net names to the current pin.

[0004] However, as chips become larger and have more pins, this method of manually changing network names is prone to duplication or omission of network names, resulting in low accuracy in the process of changing network names of chip pins.

[0005] There is currently no effective solution to the problem of low accuracy in changing the network names of chip pins in related technologies. Summary of the Invention

[0006] This application provides a method and apparatus for processing chip pins, a storage medium, and an electronic device to at least solve the problem of low accuracy in the process of changing the network name of chip pins.

[0007] According to one embodiment of this application, a method for processing chip pins is provided, comprising: obtaining a first array composed of attribute information of each pin in a first group of pins of a target chip, wherein there is a group of unconnected signal lines around the target chip, and the first array includes description information of each pin in multiple attributes; determining a second group of pins to be renamed from the first group of pins based on the first array and a second array composed of signal attributes of each signal line in the group of signal lines; saving the attribute information of each pin in the second group of pins to a target array corresponding to a target area according to a region division rule, wherein the target area is obtained by dividing the area occupied by the target chip; and replacing the network name of a pre-determined candidate pin with the target network name of the target pin based on the first position information of the signal lines of the target pin in the target array.

[0008] In an exemplary embodiment, the process of determining a second group of pins with the desired network name from a first group of pins, based on a first array and a second array composed of the signal attributes of each signal line in a group of signal lines, includes: filtering attribute information of power pins from the first array based on the pin type of each pin; constructing a third array based on the remaining attribute information in the first array excluding the attribute information of power pins; determining at least a portion of signal lines whose network names are the same as at least a portion of the pins in the third array by traversing the second array; constructing a fourth array based on the signal attributes of at least a portion of the signal lines and the attribute information of at least a portion of the pins, wherein the fourth array includes descriptive information of multiple element attribute lines, one of which is a virtual connection line between a breakpoint of one of the signal lines and a pin of at least a portion of the pins, and a signal line has the same network name as a pin; and obtaining the second group of pins with the desired network name by traversing the fourth array.

[0009] In an exemplary embodiment, the above-mentioned method of obtaining the second set of pins for the network name to be replaced by traversing the fourth array includes: obtaining the chip area occupied by each pin in the target chip; dividing the chip area into a preset number of sub-regions by the first dividing line and the second dividing line, wherein the preset number of sub-regions includes the target area; and obtaining the second set of pins for the network name to be replaced by traversing the description information of multiple element attribute lines in the fourth array.

[0010] In an exemplary embodiment, the above-mentioned method of obtaining the second set of pins for changing the network name by traversing the description information of multiple element attribute lines in the fourth array includes: sequentially obtaining the description information of each element attribute line from the description information of multiple element attribute lines as the description information of the current element attribute line; and determining the current pin on the current element attribute line as the pin in the second set of pins when the current element attribute line intersects with at least one of the first dividing line and the second dividing line.

[0011] In an exemplary embodiment, the above-described method of saving the attribute information of each pin in the second group of pins to a target array corresponding to the target region according to the region division rules includes: dividing the chip region into a preset number of sub-regions by a first dividing line and a second dividing line, wherein the first dividing line and the second dividing line are two diagonals on the closed region formed by the chip region; sequentially obtaining each pin from the second group of pins as the current pin; and, if the signal attribute line of the current signal on the current pin passes through the current sub-region of the preset number of sub-regions first, saving the current attribute information of the current pin to the current array corresponding to the current sub-region, wherein the current array is the target array.

[0012] In an exemplary embodiment, the above-mentioned replacement of the network name of a predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array includes: determining a candidate pin from the pin set outside the target chip when the first position information of the signal line of the target pin indicates that the target pin is located on the surface layer of the target chip; replacing the network name of the candidate pin with the target network name; or determining a candidate pin from the pin set outside the target chip when the first position information of the signal line of the target pin indicates that the layer where the target pin is located is inconsistent with the surface layer of the target chip; obtaining the location of the target via through which the target signal line connecting the target pin and the candidate pin passes; and connecting the signal line of the target pin to the candidate pin through the target via.

[0013] In an exemplary embodiment, after replacing the network name of a predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array, the method further includes: when the chip area is divided into multiple sub-regions, sequentially obtaining each sub-region as the current sub-region from the multiple sub-regions; backing up the element information of the current group of pins in the current sub-region to the current backup array; comparing the target array after updating the network name with the current backup array based on the network name to obtain a first comparison result; if the first comparison result indicates that the target array after updating the network name is consistent with the network name in the current backup array, determining that the target network name of the target pin has been accurately replaced. Alternatively, when the chip area is divided into multiple sub-regions, update element information of multiple sets of pins is obtained. This update element information represents the element information of each pin in each of the multiple sub-regions after the network name has been changed, and the multiple sub-regions correspond to the multiple sets of pins. Based on the update element information of the multiple sets of pins, the target array is updated to obtain the updated target array. The network name in the updated target array is compared with the network names of each pin in the second set of pins to obtain a second comparison result. The second set of pins consists of multiple sets of pins in the multiple sub-regions. If the second comparison result indicates that the network name in the updated target array matches the network name of each pin in the second set of pins, it is determined that the target network name of the target pin has been accurately changed.

[0014] According to another embodiment of the present application, a chip pin processing apparatus is also provided, comprising: a first acquisition unit, configured to acquire a first array composed of attribute information of each pin in a first group of pins of a target chip, wherein a group of unconnected signal lines exists around the target chip, and the first array includes descriptive information of each pin in multiple attributes; a first processing unit, configured to determine a second group of pins whose network names are to be changed from the first group of pins based on the first array and a second array composed of signal attributes of each signal line in the group of signal lines; a second processing unit, configured to save the attribute information of each pin in the second group of pins to a target array corresponding to a target region according to a region division rule, wherein the target region is obtained by dividing the region occupied by the target chip; and a third processing unit, configured to replace the network name of a pre-determined candidate pin with the target network name of the target pin based on the first position information of the signal lines of the target pin in the target array.

[0015] According to yet another embodiment of this application, a computer-readable storage medium is also provided, in which a computer program is stored, wherein the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0016] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein a computer program is stored in the memory and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0017] According to yet another embodiment of this application, a computer program product is also provided, which includes a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0018] Through the embodiments provided in this application, based on the attribute information of all pins in the target chip and a group of signal lines around the target chip that are not connected, a second group of pins whose routing layout needs to be optimized (net names changed) is identified. Then, through region division rules, the second group of pins whose net names need to be changed are divided into different regions. Based on the first position information of the signal lines of the pins in each region on the target chip, the net names of the pins in each region are automatically determined to be changed to the candidate pins closest to the signal lines. In other words, by adopting the above-described replacement method, not only is the optimal connection between signal lines and pins achieved, but also the omission and duplication of pin net names are avoided, thus improving the accuracy of the process of changing the net names of chip pins. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0020] Figure 1 This is a hardware structure block diagram of a server device according to an embodiment of the present application of a chip pin processing method;

[0021] Figure 2 This is a flowchart of an optional chip pin processing method according to an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of the signal routing of chip pins in related technologies;

[0023] Figure 4 This is a schematic diagram of an optional element attribute line and a set of signal lines according to an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of an optional method of dividing a chip area into multiple sub-regions according to an embodiment of this application;

[0025] Figure 6 This is an overall flowchart of an optional chip pin processing method according to an embodiment of this application;

[0026] Figure 7 This is a structural block diagram of a chip pin processing device according to an embodiment of this application;

[0027] Figure 8 This is a schematic diagram of the structure of an optional electronic device according to an embodiment of this application. Detailed Implementation

[0028] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0030] The chip pin processing method provided in this application can be executed in a server device or similar computing device. Taking running on a server device as an example, Figure 1 This is a hardware structure block diagram of a server device for a chip pin processing method according to an embodiment of this application. For example... Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The server device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the server equipment described above. For example, the server equipment may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0031] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the chip pin processing method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to server devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0032] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the server device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0033] The chip pin processing method in this application embodiment can be applied, but is not limited to, to signal routing optimization in the PCB design process of chips in servers, such as... Figure 3 Therefore, traditional chip pin routing suffers from severe crossovers and is quite messy. When signal traces cannot be routed internally to the chip, it is usually necessary to increase the number of chip layers or change the net naming of the chip pins.

[0034] PCB traces can refer to, but are not limited to, copper conductors of a certain width and thickness distributed across various layers. They are divided into striplines and microstrip lines. Striplines are ribbon traces that run on the inner layers of the PCB, embedded between two conductor layers, making them less susceptible to external radiation interference. Microstrip lines are ribbon traces attached to the surface layer of the PCB. To avoid being exposed to air, they are distributed within the insulating medium of the PCB on one side, making them more susceptible to surrounding radiation interference.

[0035] Increasing the number of layers simply to solve the problem of chip pin crossings would be wasteful, and more layers would increase cost and manufacturing difficulty, which does not meet the requirements of cost optimization. Therefore, we consider solving the problem of severe signal trace crossings by changing the network names of the chip pins.

[0036] To address the aforementioned problems in related technologies, this embodiment provides a method for processing chip pins. The execution entity includes, but is not limited to, a software system that automatically changes the network name of the chip pins, such as... Figure 2 As shown, the process includes the following steps S202-S208:

[0037] Step S202: Obtain a first array consisting of attribute information of each pin in the first group of pins of the target chip, wherein there is a group of signal lines around the target chip that are not connected to the traces, and the first array includes description information of each pin in multiple attributes;

[0038] Step S204: Based on the first array and the second array consisting of the signal attributes of each signal line in a set of signal lines, determine the second set of pins from the first set of pins to replace the network name;

[0039] Step S206: According to the region division rules, save the attribute information of each pin in the second group of pins to the target array corresponding to the target region. The target region is obtained by dividing the region occupied by the target chip.

[0040] Step S208: Based on the first position information of the signal line of the target pin in the target array, replace the predetermined network name of the candidate pin with the target network name of the target pin.

[0041] In the embodiments of this application, the PCB can be designed using, but is not limited to, Allegro software, which supports secondary development by users and provides a good software foundation for methods of quickly replacing chip pins or chip pin networks.

[0042] Allegro software, as a PCB design tool, provides comprehensive design and simulation tools, enabling developers to perform high-speed, high-density, multi-layer complex PCB design and routing. Depending on the complexity of the circuit design, a PCB board can include different numbers of layers. Layers used for chip routing are also called signal layers, which can transmit electrical signals. Point-to-point paths (which can also be understood as traces) on the PCB board connect to the chip's pins, realizing the electrical connection between the chip's internal circuitry and external circuitry. These traces transmit electrical signals, power, and ground planes, ensuring that the chip can function properly.

[0043] It should be noted that a PCB board may include signal layers, power layers, and ground layers, and may include multiple signal layers.

[0044] After selecting the target chip whose network needs to be replaced, create a first array corresponding to the original pin signal attributes of the target chip M whose network needs to be replaced. The first array can be, but is not limited to, a one-dimensional or multi-dimensional array, specifically including pin number, coordinates, part number, network name, and layer.

[0045] As shown in Figure 2, multiple circular connection points are distributed on the left side of the circuit board, representing the connection points between the chip pins and other components. The right side area marks a group of signal lines around the target chip that are not connected. The signal attributes of this group of signal lines are saved to a second array. Then, based on the first and second arrays, the second group of pins whose network names need to be changed is determined. The implementation method for determining the second group of pins will be described in detail below with reference to specific embodiments.

[0046] After identifying the second set of pins, the area containing the target chip is divided into a predetermined number of sub-regions, for example, such as... Figure 5 As shown, the area is divided into four sub-regions, M1 to M4. According to the principle of first-passing, the second group of pins is stored in four arrays A1 to A4 that correspond to the four sub-regions.

[0047] Specifically, by traversing each pin in the second group of pins, it determines which of the four sub-regions M1 to M4 the signal trace of each pin passes through first, and then stores the current pin in the first sub-region it passes through. The reason for this is that the first sub-region it passes through has the shortest signal trace length and fewer loops. The purpose is to optimize the trace layout, reduce unnecessary loops, and reduce the crossing between signal traces.

[0048] After storing all pins in four sub-regions, create four arrays A1 to A4 corresponding to the four sub-regions. Array A1 stores the attribute information of the pins stored in the first sub-region M1, such as the pin number, coordinates, part number, network name, and layer. Array A2 stores the attribute information of the pins stored in the second sub-region M2, and so on, creating arrays A3 and A4.

[0049] After determining the region division of the second set of pins, a network name replacement strategy will be executed based on the signal trace location information in each sub-region (each target region). Specifically, the algorithm will analyze whether the signal trace of each pin in each sub-region is located on the same layer as the target chip, such as whether it is located on the upper surface layer or the lower surface layer of the target chip. If so, the network name of the current pin will be replaced with a candidate pin on the first or second row of pins on the outside of the target chip.

[0050] In an optional example, the system can find candidate pins closest to the signal trace by calculating the distance from the signal line to the external pin of the chip. These candidate pins are typically the first or second row of pins on the external chip because they can be directly connected to the signal line without passing through a VIA (via), effectively reducing trace length and routing. The system automatically replaces the netname of the candidate pin with the target netname of the target pin, achieving optimal connection between the signal line and the pin. Furthermore, the system automatically verifies the netnames before and after the replacement to ensure no omissions or duplications, improving design accuracy and consistency.

[0051] This approach not only simplifies pin network replacement in PCB design and improves design efficiency, but also ensures optimal signal line connections and reduces costs, representing a significant innovation in server chip design. Automated processing not only reduces the workload of designers but also significantly improves design accuracy and quality.

[0052] In one example embodiment, the above-described determination of a second set of pins from a first set of pins, based on a first array and a second array consisting of the signal attributes of each signal line in a set of signal lines, of the second set of pins to be replaced includes:

[0053] Based on the pin type of each pin, the attribute information of the power supply pins is filtered out from the first array;

[0054] Based on the remaining attribute information in the first array, excluding the attribute information of the power supply pins, a third array is constructed;

[0055] By traversing the second array, at least a portion of the signal lines whose network names are the same as those of at least a portion of the pins in the third array are identified from each signal line.

[0056] Based on the signal attributes of at least some signal lines and the attribute information of at least some pins, a fourth array is constructed, wherein the fourth array includes description information of multiple element attribute lines, one of the multiple element attribute lines is a virtual connection line between the break point of one of the signal lines and one of the pins, and the network name of one signal line is the same as that of one pin.

[0057] By traversing the fourth array, the second set of pins for the network name to be changed is obtained.

[0058] After obtaining the attribute information of all pins on the target chip, it is necessary to filter out the attribute information of non-power network pins and save them to the third array. In other words, power and ground pins that do not need to participate in the signal line connection optimization process are separated from the first array, improving overall processing efficiency.

[0059] As described in the above embodiments, the second array contains attribute information of signal lines around the target chip that are not connected. By traversing the second array and comparing it with the third array, it is possible to identify which signal lines have the same net names as the pin net names in the third array. These identical net names indicate potential connection requirements between the signal lines and pins, but direct connection is not possible due to trace length or layer limitations. Therefore, after identifying these signal lines and pins, these pins are identified as pins that may require a change of net name.

[0060] In this process, by traversing the second array and comparing it with the third array, while identifying signal lines whose network names match the pin network names in the third array, it is also necessary to determine whether the attribute display indicates a disconnected signal line. Then, the relevant attributes of signal lines whose network names match the network names in the third array and whose attributes indicate a disconnected signal line are stored in the fourth array, thus identifying these signal lines as those requiring network swapping. This method can eliminate signals on the surface that can be directly connected to pull-up / pull-down resistors without drilling, reducing the workload of replacing pin networks.

[0061] The fourth array contains virtual connection information (which can also be logically represented as element attribute lines). These connections link signal line breaks to pins with the same net name. This construction of virtual connections provides an intuitive data structure for subsequent net name replacement strategies, helping to more accurately understand and handle the connection relationships between signal lines and pins.

[0062] In this embodiment, the filtering process for changing network names is further optimized. It not only considers that the network names of signal lines and pins can only be matched after the network name is changed, but also provides a more intuitive data structure through the construction of virtual connection lines. This ensures that the connection requirements between signal lines and pins can be identified and processed more effectively, and improves the accuracy of filtering pins that need to have their network names changed.

[0063] In one example embodiment, the second set of pins for which the network name to be changed is obtained by traversing the fourth array, including:

[0064] Obtain the chip area occupied by each pin in the target chip;

[0065] The chip area is divided into a preset number of sub-regions by the first dividing line and the second dividing line, wherein the preset number of sub-regions includes the target area;

[0066] By traversing the description information of multiple element attribute lines in the fourth array, the second set of pins for the network name to be changed is obtained.

[0067] In this embodiment, it is assumed that the area occupied by the target chip is Figure 5 The square area shown is then divided into four sub-regions, M1 to M4, by introducing the first dividing line L1 and the second dividing line L2. Then, by traversing multiple element attribute lines in the fourth array, the second group of pins whose network names need to be changed is determined.

[0068] It should be noted that the fourth array includes, but is not limited to, two parts: one part contains attribute information related to signal lines whose network names are the same as those in the third array and whose attributes are displayed as disconnected; the other part contains descriptive information for multiple element attribute lines, including, but not limited to, element attribute lines such as... Figure 4 The diagram shows the connection lines between pins in the target chip and breakpoints in surrounding unconnected signal lines. Clearly, the net name of the pin connected to each element attribute line is the same as the net name of the signal line corresponding to the breakpoint.

[0069] In addition, the first dividing line L1 and the second dividing line L2 may be, but are not limited to, the two diagonals of the square corresponding to the chip area. Obviously, L1 and L2 are only examples and are not limited to them.

[0070] By introducing a preset first dividing line and a second dividing line in the embodiments of this application, the chip area can be divided into multiple sub-regions. This region division strategy aims to manage the connection relationship between signal lines and pins more finely, ensuring that signal lines can be directly connected to pins as much as possible, reducing unnecessary trace length and winding, and improving the efficiency and accuracy of PCB design.

[0071] In one example embodiment, the second set of pins for which the network name to be changed is obtained by traversing the description information of multiple element attribute lines in the fourth array, including:

[0072] Each element attribute line is sequentially obtained from multiple element attribute lines and used as the current element attribute line;

[0073] If the current element attribute line intersects with at least one of the first dividing line and the second dividing line, the current pin on the current element attribute line is determined as a pin in the second group of pins.

[0074] By traversing the description information of all element attribute lines in the fourth array, it is determined whether each element attribute line intersects with the first dividing line L1 or the second dividing line L2. If so, the pin connected to the element attribute line is identified as the pin whose network name needs to be changed, and the attribute information of the pin is stored in the fifth array.

[0075] If an element attribute line intersects both the first dividing line L1 and the second dividing line L2, the pin network name connected to that element attribute line also needs to be changed. Similarly, the attribute information of that pin is stored in the fifth array.

[0076] The intersection of the aforementioned element attribute lines with the first and second dividing lines indicates that the signal line's routing path crosses the boundary of the chip area. This means that there are limitations on the routing length or layer when directly connecting to the internal pins of the chip. Therefore, the pins that intersect with the dividing lines need to have their net names changed to optimize the signal line connection.

[0077] The pin selection strategy in this embodiment ensures that the system can accurately identify the pins that need to have their network names changed, avoiding unnecessary network name changes and improving processing accuracy and efficiency.

[0078] In one example, according to the region division rules, the attribute information of each pin in the second group of pins is saved to the target array corresponding to the target region, including:

[0079] The chip region is divided into a predetermined number of sub-regions by the first dividing line and the second dividing line, wherein the first dividing line and the second dividing line are two diagonals on the closed region formed by the chip region.

[0080] Take each pin from the second group of pins in sequence as the current pin;

[0081] If the signal attribute line of the current signal on the current pin passes through the current sub-region of a preset number of sub-regions first, the current attribute information of the current pin is saved to the current array corresponding to the current sub-region, where the current array is the target array.

[0082] After determining the second group of pins that need to have their network names changed through the above embodiments, these pins are further analyzed one by one. Specifically, based on the first and second dividing lines, the chip area is divided into four sub-regions, M1 to M4. Then, it is determined which sub-region among the four sub-regions the signal line of each pin in the second group passes through first.

[0083] Following the principle of first-passing, the signal attribute line of each pin in the second group of pins is determined first to pass through one of the four sub-regions. Then, the pin is stored in one of the sub-regions, and the attribute information of the pin is saved to one of the arrays corresponding to one of the sub-regions.

[0084] For example, when the signal attribute line of pin 1 first passes through sub-region M1, the attribute information of pin 1 is saved to array A1 corresponding to sub-region M1; when the signal attribute line of pin 2 first passes through sub-region M2, the attribute information of pin 2 is saved to array A2 corresponding to sub-region M2.

[0085] This embodiment further refines the classification and storage process of pin attribute information, ensuring the optimal execution of the subsequent network name replacement strategy. This approach not only significantly improves the efficiency of PCB design and reduces design costs, but also effectively reduces trace length and winding, thereby improving the performance and stability of signal transmission.

[0086] In addition, through the above methods, designers can quickly and accurately replace and optimize chip pin networks, solving the problem of inconsistencies among multiple designers, improving design uniformity, reducing design error rates, and enhancing the overall quality of PCB design, thus providing strong technical support for the high-performance and low-cost design of server equipment.

[0087] In one example embodiment, the above-mentioned replacement of the pre-determined candidate pin network name with the target pin network name based on the first position information of the signal line of the target pin in the target array includes:

[0088] When the first position information of the signal line of the target pin indicates that the target pin is located on the surface layer of the target chip, candidate pins are determined from the pin set outside the target chip;

[0089] Replace the candidate pin's network name with the target network name; or

[0090] When the first position information of the signal line of the target pin indicates that the layer where the target pin is located is inconsistent with the surface layer of the target chip, the candidate pin is determined from the pin set outside the target chip.

[0091] Find the location of the target signal line connecting the target pin and the target via that the candidate pin needs to pass through;

[0092] Connect the signal line of the target pin to the candidate pin through the target via.

[0093] In this embodiment, the strategy for changing the network name can be determined based on the first position information of the signal line of the target pin. If the signal line of the target pin is located on the surface layer of the target chip, that is, the first position information is located on the same level as the surface layer (including the upper and lower layers) of the target chip, then the network name of the signal line is swapped to the first or second row of pins on the outside of the target chip.

[0094] In other words, when the signal trace is located on the surface of the target chip, the pin outside the chip closest to the signal trace will be selected as the candidate pin, and the network name of the candidate pin will be directly changed to the target network name of the target pin, thereby optimizing the signal transmission path.

[0095] When the signal line of the target pin is located on a non-surface layer, that is, the layer where the first position information is located is different from the surface layer of the target chip, a VIA (via) is required because the pin inside the target chip appears. The signal line of the target pin is connected to the first or second row of pins on the outside of the chip through the target via.

[0096] Obviously, it is easy to understand that after the target network name of the target pin is changed to that of the candidate pin, the network name of other pins will also be changed to that of the target pin according to the above-mentioned replacement strategy.

[0097] By selecting candidate pins in different ways based on whether the signal line of the target pin is located on the same layer as the surface layer of the target chip, the routing constraints of the signal line on different layers are fully considered. Through intelligent pin selection and optimized via usage, the shortest path for signal transmission is ensured, crossover between signals is reduced, and the performance and stability of signal transmission are improved.

[0098] In addition, this embodiment not only considers the matching of signal lines and pin net names, but also analyzes in depth the specific routing position and layer of the signal lines on the PCB board, ensuring the optimal execution of the net name replacement strategy. At the same time, it improves the work efficiency of designers, reduces the design error rate, improves the overall quality of PCB design, and realizes the flexibility and adaptability of the net name replacement strategy.

[0099] In one example embodiment, after replacing the network name of a predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array, the above method further includes:

[0100] When the chip area is divided into multiple sub-regions, each sub-region is sequentially obtained from the multiple sub-regions as the current sub-region;

[0101] Back up the element information of the current group of pins in the current sub-region to the current backup array;

[0102] Based on the network name, the target array after updating the network name is compared with the current backup array to obtain the first comparison result;

[0103] If the first comparison result indicates that the target network name after the network name update matches the network name in the current backup array, it is determined that the target network name of the target pin has been accurately replaced; or

[0104] When the chip area is divided into multiple sub-regions, the updated element information of multiple sets of pins is obtained. The updated element information of multiple sets of pins represents the element information of each pin in multiple sub-regions after the network name is changed. Multiple sub-regions and multiple sets of pins have a corresponding relationship.

[0105] Based on the update element information of multiple sets of pins, the target array is updated to obtain the updated target array;

[0106] The network names in the updated target array are compared with the network names of each pin in the second group of pins to obtain the second comparison result. The second group of pins consists of multiple groups of pins in multiple sub-regions.

[0107] If the second comparison result indicates that the network name in the updated target array matches the network name of each pin in the second group of pins, it is determined that the target network name of the target pin has been accurately changed.

[0108] To ensure the accuracy of the pin network name replacement results, this embodiment also provides two checking methods to check for omissions and duplicates of network names.

[0109] The first type is aimed at... Figure 5 The pins within each of the four sub-regions M1 to M4 shown are inspected individually. Based on the inspection results of each sub-region, the accuracy of the replacement result is determined. Specifically, arrays A1 to A4 corresponding to the four sub-regions M1 to M4 are obtained, and an array A1 is selected from each of arrays A1 to A4. i , array A i The element information is backed up to a backup array, where i is a positive integer greater than or equal to 1 and less than or equal to 4.

[0110] Determine array A i Check whether the signal traces of each pin are on the same level as the target chip. If they are on the same level, swap the network name of the signal trace to the first or second row of pins on the outside of the chip. If they are not on the same level, connect the pins inside the chip to the first or second row of pins on the outside of the chip through the target via, thereby changing the network name.

[0111] In achieving A i After changing the network names of each pin, compare array A. i Compare the element information in array A with the element information in the backup array. For example, compare array A. i Check if the network name in the database is exactly the same as the network name in the backup array. If they are exactly the same, then determine the Mth network name. i There were no omissions or duplicates in the network names of all pins in each sub-region.

[0112] Following the above method, back up the element information in the array corresponding to each sub-region one by one. Then, for each sub-region, execute the above network name replacement strategy. By comparing the element information in the array after replacement in each sub-region with the element information in the backup array, ensure that the replacement result of the network name of the pins used in that sub-region is accurate.

[0113] It is easy to understand that each of the above sub-regions corresponds to an array (e.g., A1) containing element information of all pins within that sub-region and a backup array.

[0114] The second type is about... Figure 5 The pins in all areas of the four sub-regions M1 to M4 shown are checked uniformly. Specifically, for each sub-region's corresponding array, the above-mentioned network name replacement strategy is executed. During the replacement process, the network names in each array A1 to A4 are updated to obtain the updated arrays A′1 to A′4. Then, all elements in arrays A′1 to A′4 are merged into an array F (which can also be understood as the updated target array).

[0115] By comparing the network names in array F with the network names of each pin in the second group of pins, it is determined that there are no omissions or duplicates if the two are completely consistent.

[0116] It should be noted that after the inspection process is completed, the array consisting of the element information of the second group of pins and the element information in array F can be printed into a table. The table includes the chip reference number, chip pin number, network name before replacement (or network name), network name after replacement, etc., and an Excel spreadsheet is output so that the chip pin network name can be changed in the schematic diagram.

[0117] To better understand the above technical solutions, the following will be combined with... Figure 6 The overall flowchart shown further describes the processing method for the chip pins mentioned above.

[0118] S602, select the chip whose network name needs to be changed;

[0119] S604, Creates an array A of the raw pin signal attributes of the target chip;

[0120] That is, for each pin on the target chip, record the element information in multiple dimensions such as pin number, coordinates, part number, network name and layer, to obtain array A. Array A can be a one-dimensional array or a multi-dimensional array.

[0121] S606: Filter out the element information of non-power supply or ground pins from array A to obtain array B;

[0122] S608, store the signal attributes of unconnected surrounding traces in array C and the signal line attributes with the same network name in array B into array D;

[0123] like Figure 4As shown, there is a group of unconnected signal lines around the target chip. The attribute information of the signal lines in the group whose network name is the same as that in array B and whose attributes are displayed as disconnected is stored in array D.

[0124] S610, Determine whether the attribute lines of the elements in array D intersect with the first dividing line and / or the second dividing line;

[0125] Among them, element attribute lines include but are not limited to, such as Figure 4 The diagram shows the connection lines between pins in the target chip and breakpoints in surrounding unconnected signal lines. Clearly, the net name of the pin connected to each element attribute line is the same as the net name of the signal line corresponding to the breakpoint.

[0126] In addition, the first dividing line L1 and the second dividing line L2 may be, but are not limited to, the two diagonals of the square corresponding to the chip area. Obviously, L1 and L2 are only examples and are not limited to them.

[0127] If the element attribute line intersects with at least one of L1 and L2, then proceed to step S612; otherwise, no network name replacement is performed.

[0128] S612, the pin connected to the element attribute line that intersects with at least one of L1 and L2 is identified as the pin whose network name needs to be changed, and the attribute information of the pin is stored in array E;

[0129] S614, according to the first-to-last principle, store the element information in array E into arrays A1 to A4 respectively;

[0130] For example, suppose the signal attribute line in array E connected to a pin first passes through, such as... Figure 5 The four sub-regions shown are divided into sub-region M1, and the pins are stored in region M1. The attribute information of the pins is saved to array A1 corresponding to sub-region M1.

[0131] Similarly, when the signal attribute line of pin 2 first passes through sub-region M2, the attribute information of pin 2 is saved to array A2 corresponding to sub-region M2, and so on.

[0132] S616 executes the network name swapping process for each array in A1 to A4;

[0133] For example, for each signal line of a pin in array A1, determine whether its layer is on the same layer as the target chip. If so, swap the network name of the pin to the first and second rows of pins on the outside of the target chip; otherwise, connect the pin inside the chip to the first and second rows of pins on the outside of the chip through the target via.

[0134] For A2 to A4 above, you can refer to the replacement process of each pin in array A1 above, change their network names respectively, and then obtain arrays A1 to A4 after changing the network names.

[0135] S618, compare each array after the network name is changed with the network name in the pre-set backup array to obtain 4 comparison results;

[0136] For example, assuming the array A1 after the network name change is denoted as array A′1, the element information in array A1 is backed up in advance to an array N1. The network names in array A′1 are compared with those in the backup array N1 to obtain a second comparison result. If the first comparison result indicates that all network names are completely consistent, then it is determined that the network name replacement process for the pins in sub-region M1 is accurate.

[0137] Similarly, assuming the array A2 after the network name change is denoted as array A′2, the element information in array A2 is backed up in advance to an array N2. The network names in array A′2 are compared with those in the backup array N2 to obtain the second comparison result. The comparison process for the remaining two arrays can refer to the execution process in arrays A1 and A2 after the network name change described above, and will not be repeated here.

[0138] S620, if all four comparison results indicate that the network name in the backup array is consistent with the network name in the array after the network name is changed, it is determined that there is no duplication or omission of network names during the replacement process.

[0139] S622, for each signal line of each pin in array A1, change the network name and merge the element information after the name change into array F;

[0140] S624, compare the network names in array F with those in array E;

[0141] The array F contains element information for each pin after the network name has been changed.

[0142] S626, if the network names in array F and array E are the same, determine that there are no duplicate or missing pin or network names.

[0143] In another alternative embodiment, the above-described chip pin processing method can be implemented through, but is not limited to, the following steps:

[0144] S11, Load the program in the command window to automatically change the network name;

[0145] S12, the program will automatically pop up a window to prompt the developer about the chip that needs to be replaced for the network currently selected;

[0146] S13, The program automatically creates an array of the original pin signal attributes of the chip whose network needs to be replaced;

[0147] S14, the software provides a window where you can enter the pin number of the network that cannot be switched;

[0148] S15, the software automatically filters out signals that need to be replaced by a different network;

[0149] S16, The software automatically executes the automatic switching network policy;

[0150] For details, please refer to the description in the above implementation; it will not be repeated here.

[0151] S17, the software automatically outputs an Excel spreadsheet of the final chip switching pin network names, and uses this spreadsheet to change the chip pin network names in the schematic.

[0152] The method for quickly changing chip pin networks provided in this application enables the chip to automatically match the most suitable network based on the signal line routing, complete the network naming change for all pins, and verify the changes against the original network names. After checking for omissions or duplicates, a table of corresponding swapped pin network names is output, quickly and accurately completing the chip pin network naming change and outputting a table in a uniform format, eliminating the need for manual matching and checking. This improves efficiency and accuracy, and avoids repeatedly swapping chip pin network names.

[0153] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0154] This embodiment also provides a chip pin processing device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the modules described in the following embodiments are preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0155] Figure 7 This is a structural block diagram of a chip pin processing apparatus according to an embodiment of this application. The apparatus includes:

[0156] The first acquisition unit 702 is used to acquire a first array consisting of attribute information of each pin in the first group of pins of the target chip, wherein there is a group of signal lines around the target chip that are not connected to the traces, and the first array includes description information of each pin in multiple attributes.

[0157] The first processing unit 704 is used to determine the second set of pins to be replaced from the first set of pins based on the first array and the second array consisting of the signal attributes of each signal line in the first set of signal lines.

[0158] The second processing unit 706 is used to save the attribute information of each pin in the second group of pins to the target array corresponding to the target area according to the area division rules. The target area is obtained by dividing the area occupied by the target chip.

[0159] The third processing unit 708 is used to replace the network name of a pre-determined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array.

[0160] In an exemplary embodiment, the first processing unit 704 described above includes:

[0161] The first processing module is used to filter the attribute information of the power supply pins from the first array based on the pin type of each pin.

[0162] The second processing module is used to construct a third array based on the remaining attribute information in the first array, excluding the attribute information of the power supply pins.

[0163] The third processing module is used to determine, by traversing the second array, at least a portion of the signal lines whose network names are the same as those of at least a portion of the pins in the third array;

[0164] The fourth processing module is used to construct a fourth array based on the signal attributes of at least some signal lines and the attribute information of at least some pins. The fourth array includes description information of multiple element attribute lines. One of the multiple element attribute lines is a virtual connection line between the breakpoint of one of the signal lines and one of the pins. The network name of a signal line and a pin are the same.

[0165] The fifth processing module is used to obtain the second set of pins for the network name to be changed by traversing the fourth array.

[0166] In one exemplary embodiment, the fifth processing module described above includes:

[0167] The first acquisition submodule is used to acquire the chip area occupied by each pin in the target chip;

[0168] The first division submodule is used to divide the chip area into a preset number of sub-regions by using a first dividing line and a second dividing line, wherein the preset number of sub-regions includes the target area.

[0169] The first processing submodule is used to obtain the second set of pins for the network name to be changed by traversing the description information of multiple element attribute lines in the fourth array.

[0170] In one exemplary embodiment, the fifth processing module described above includes:

[0171] The second acquisition submodule is used to sequentially acquire the description information of each element attribute line from the description information of multiple element attribute lines as the description information of the current element attribute line.

[0172] The second processing submodule determines the current pin on the current element attribute line as a pin in the second group of pins when the current element attribute line intersects with at least one of the first dividing line and the second dividing line.

[0173] In an exemplary embodiment, the second processing unit 706 described above includes:

[0174] The first division module is used to divide the chip area into a preset number of sub-regions by using a first dividing line and a second dividing line, wherein the first dividing line and the second dividing line are two diagonals on the closed region formed by the chip area.

[0175] The first acquisition module is used to sequentially acquire each pin from the second group of pins as the current pin;

[0176] The storage module is used to save the current attribute information of the current pin to the current array corresponding to the current sub-region when the signal attribute line of the current signal on the current pin first passes through the current sub-region of a preset number of sub-regions. The current array is the target array.

[0177] In one exemplary embodiment, the third processing unit 708 described above includes:

[0178] The fifth processing module is used to determine candidate pins from the pin set outside the target chip when the first position information of the signal line of the target pin indicates that the target pin is located on the surface layer of the target chip;

[0179] Replace the candidate pin's network name with the target network name; or

[0180] When the first position information of the signal line of the target pin indicates that the layer where the target pin is located is inconsistent with the surface layer of the target chip, the candidate pin is determined from the pin set outside the target chip.

[0181] Find the location of the target signal line connecting the target pin and the target via that the candidate pin needs to pass through;

[0182] Connect the signal line of the target pin to the candidate pin through the target via.

[0183] In one exemplary embodiment, the above-described apparatus further includes:

[0184] The fourth processing unit is used to, after replacing the network name of the predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array, and in the case of dividing the chip area into multiple sub-regions, sequentially obtain each sub-region as the current sub-region from the multiple sub-regions.

[0185] Back up the element information of the current group of pins in the current sub-region to the current backup array;

[0186] Based on the network name, the target array after updating the network name is compared with the current backup array to obtain the first comparison result;

[0187] If the first comparison result indicates that the target network name after the network name update matches the network name in the current backup array, it is determined that the target network name of the target pin has been accurately replaced; or

[0188] When the chip area is divided into multiple sub-regions, the updated element information of multiple sets of pins is obtained. The updated element information of multiple sets of pins represents the element information of each pin in multiple sub-regions after the network name is changed. Multiple sub-regions and multiple sets of pins have a corresponding relationship.

[0189] Based on the update element information of multiple sets of pins, the target array is updated to obtain the updated target array;

[0190] The network names in the updated target array are compared with the network names of each pin in the second group of pins to obtain the second comparison result. The second group of pins consists of multiple groups of pins in multiple sub-regions.

[0191] If the second comparison result indicates that the network name in the updated target array matches the network name of each pin in the second group of pins, it is determined that the target network name of the target pin has been accurately changed.

[0192] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0193] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0194] Optionally, in this embodiment, the computer program described above can be configured to perform the following steps:

[0195] S1, after replacing the predetermined candidate pin network name with the target pin network name based on the first position information of the signal line of the target pin in the target array;

[0196] S2, based on the first array and the second array consisting of the signal attributes of each signal line in a set of signal lines, determine the second set of pin information of the network name to be changed from the first set of pins;

[0197] S3, according to the region division rules, save the attribute information of each pin in the second group of pins to the target array corresponding to the target region. The target region is obtained by dividing the region occupied by the target chip.

[0198] S4, based on the first position information of the signal line of the target pin in the target array, replace the pre-determined network name of the candidate pin with the target network name of the target pin.

[0199] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0200] Embodiments of this application also provide an electronic device, such as... Figure 8 As shown, the electronic device includes a memory 802 and a processor 804. The memory 802 stores a computer program, and the processor 804 is configured to execute the steps in any of the above method embodiments via the computer program.

[0201] Optionally, in this embodiment, the processor 804 can be configured to perform the following steps by a computer program: S1, after replacing the network name of a predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array;

[0202] S2, based on the first array and the second array consisting of the signal attributes of each signal line in a set of signal lines, determine the second set of pin information of the network name to be changed from the first set of pins;

[0203] S3, according to the region division rules, save the attribute information of each pin in the second group of pins to the target array corresponding to the target region. The target region is obtained by dividing the region occupied by the target chip.

[0204] S4, based on the first position information of the signal line of the target pin in the target array, replace the pre-determined network name of the candidate pin with the target network name of the target pin.

[0205] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0206] Alternatively, as those skilled in the art will understand, Figure 8 The structure shown is for illustrative purposes only. Figure 8 This does not limit the structure of the aforementioned electronic devices. For example, the electronic device may also include components that are more... Figure 8 The more or fewer components shown (such as network interfaces, etc.), or having the same Figure 8 The different configurations shown.

[0207] The memory 802 can be used to store software programs and modules, such as the program instructions / modules corresponding to the chip pin processing method and alarm information blowing device in this embodiment. The processor 804 executes various functional applications and data processing by running the software programs and modules stored in the memory 802, thereby implementing the aforementioned chip pin processing method. The memory 802 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 802 may further include memory remotely located relative to the processor 804, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. Specifically, the memory 802 may be used, but is not limited to, to store information such as first location information and target network name. As an example, such as Figure 8As shown, the memory 802 may include, but is not limited to, the first acquisition unit 702, the first processing unit 704, the second processing unit 706, and the third processing unit 708 in the processing device for the chip pins described above. Furthermore, it may include, but is not limited to, other module units in the verification device for the soft decoding function described above, which will not be elaborated upon in this example.

[0208] Optionally, the transmission device 806 described above is used to receive or send data via a network. Specific examples of the network described above may include wired networks and wireless networks. In one example, the transmission device 806 includes a Network Interface Controller (NIC), which can be connected to other network devices and a router via a network cable to communicate with the Internet or a local area network. In another example, the transmission device 806 is a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0209] In addition, the above-mentioned electronic device also includes: a display 808; and a connection bus 810 for connecting the various module components in the above-mentioned electronic device.

[0210] In other embodiments, the aforementioned electronic device can be a node in a distributed system, which can be a blockchain system. This blockchain system is formed by connecting multiple nodes through network communication. The nodes can form a peer-to-peer (P2P) network, and any type of computing device, such as a server or terminal, can become a node in the blockchain system by joining this peer-to-peer network.

[0211] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0212] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0213] The embodiments described herein also provide a computer program that includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps in any of the above method embodiments.

[0214] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0215] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for processing chip pins, characterized in that, include: Obtain a first array consisting of attribute information of each pin in the first group of pins of the target chip, wherein there is a group of signal lines around the target chip that are not connected to the traces, and the first array includes description information of each pin in multiple attributes; Based on the first array and the second array composed of the signal attributes of each signal line in the first set of signal lines, the second set of pins to be replaced is determined from the first set of pins; According to the region division rules, the attribute information of each pin in the second group of pins is saved to the target array corresponding to the target region, wherein the target region is obtained by dividing the region occupied by the target chip; Based on the first position information of the signal line of the target pin in the target array, the network name of the pre-determined candidate pin is replaced with the target network name of the target pin; The step of replacing the network name of a predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array includes: determining the candidate pin from the pin set outside the target chip when the first position information of the signal line of the target pin indicates that the target pin is located on the surface layer of the target chip; replacing the network name of the candidate pin with the target network name; or determining the candidate pin from the pin set outside the target chip when the first position information of the signal line of the target pin indicates that the layer where the target pin is located is inconsistent with the surface layer of the target chip; obtaining the location of the target via through which the target signal line connecting the target pin and the candidate pin passes; and connecting the signal line of the target pin to the candidate pin through the target via.

2. The method according to claim 1, characterized in that, The step of determining the second set of pins to be replaced from the first set of pins, based on the first array and the second array composed of the signal attributes of each signal line in the first set of signal lines, includes: Based on the pin type of each pin, the attribute information of the power supply pins is filtered out from the first array; Based on the remaining attribute information in the first array, excluding the attribute information of the power supply pins, a third array is constructed; By traversing the second array, at least a portion of the signal lines whose network names are the same as at least a portion of the pin network names in the third array are determined from each of the signal lines; Based on the signal attributes of the at least some signal lines and the attribute information of the at least some pins, a fourth array is constructed, wherein the fourth array includes description information of multiple element attribute lines, and one of the multiple element attribute lines is a virtual connection line between the breakpoint of one of the at least some signal lines and one of the at least some pins, and the network name of the signal line is the same as that of the pin. By traversing the fourth array, the second group of pins for the network name to be changed is obtained.

3. The method according to claim 2, characterized in that, The step of obtaining the second set of pins for the network name to be changed by traversing the fourth array includes: Obtain the chip area occupied by each pin in the target chip; The chip region is divided into a preset number of sub-regions by the first dividing line and the second dividing line, wherein the preset number of sub-regions includes the target region; By traversing the description information of the multiple element attribute lines in the fourth array, the second group of pins for which the network name to be changed is obtained.

4. The method according to claim 3, characterized in that, The process of obtaining the second set of pins for the network name to be changed by traversing the description information of the multiple element attribute lines in the fourth array includes: The description information of each element attribute line is sequentially obtained from the description information of the plurality of element attribute lines as the description information of the current element attribute line; If the current element attribute line intersects with at least one of the first dividing line and the second dividing line, the current pin on the current element attribute line is determined as a pin in the second group of pins.

5. The method according to claim 1, characterized in that, The step of saving the attribute information of each pin in the second group of pins to the target array corresponding to the target region according to the region division rules includes: The chip region is divided into a predetermined number of sub-regions by a first dividing line and a second dividing line, wherein the first dividing line and the second dividing line are two diagonal lines on the closed region formed by the chip region. Take each pin from the second group of pins in sequence as the current pin; If the signal attribute line of the current signal on the current pin passes through the current sub-region of the preset number of sub-regions first, the current attribute information of the current pin is saved to the current array corresponding to the current sub-region, wherein the current array is the target array.

6. The method according to any one of claims 1 to 5, characterized in that, After replacing the network name of a predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array, the method further includes: When the chip region is divided into multiple sub-regions, each sub-region is sequentially obtained from the multiple sub-regions as the current sub-region; Back up the element information of the current group of pins in the current sub-region to the current backup array; Based on the network name, the target array after updating the network name is compared with the current backup array to obtain the first comparison result; If the first comparison result indicates that the target array after the updated network name matches the network name in the current backup array, then it is determined that the target network name of the target pin has been accurately replaced; or When the chip area is divided into multiple sub-regions, update element information of multiple sets of pins is obtained, wherein the update element information of multiple sets of pins represents the element information of each pin in the multiple sub-regions after the network name is changed, and the multiple sub-regions correspond to the multiple sets of pins. Based on the updated element information of the multiple sets of pins, the target array is updated to obtain the updated target array; By comparing the network names in the updated target array with the network names of each pin in the second group of pins, a second comparison result is obtained, wherein the second group of pins consists of multiple groups of pins in the multiple sub-regions; If the second comparison result indicates that the network name in the updated target array is consistent with the network name of each pin in the second group of pins, it is determined that the target network name of the target pin has been accurately replaced.

7. A chip pin processing apparatus, characterized in that, include: The first acquisition unit is used to acquire a first array consisting of attribute information of each pin in the first group of pins of the target chip, wherein there is a group of signal lines around the target chip that are not connected to the traces, and the first array includes description information of each pin in multiple attributes; The first processing unit is used to determine the second set of pins whose network name is to be changed from the first set of pins based on the first array and the second array composed of the signal attributes of each signal line in the first set of signal lines; The second processing unit is used to save the attribute information of each pin in the second group of pins to the target array corresponding to the target area according to the area division rules, wherein the target area is obtained by dividing the area occupied by the target chip; The third processing unit is used to replace the network name of the predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array. The device is further configured to: determine the candidate pin from the pin set outside the target chip when the first position information of the signal line of the target pin indicates that the target pin is located on the surface layer of the target chip; replace the network name of the candidate pin with the target network name; or determine the candidate pin from the pin set outside the target chip when the first position information of the signal line of the target pin indicates that the layer where the target pin is located is inconsistent with the surface layer of the target chip; obtain the location of the target via through which the target signal line connecting the target pin and the candidate pin passes; and connect the signal line of the target pin to the candidate pin through the target via.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 6.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 6.

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