Quantum bit control signal generation device, quantum measurement and control system and quantum computer
By designing a multi-channel qubit control signal generation device, frequency amplification and multiple output technologies are used to generate qubit control signals that meet the working needs of qubits, the problem of difficult control of DAC main clock and synchronous clock in the prior art is solved, and the quality of the qubit control signal and the control effect on qubits are improved.
Patent Information
- Application Number
- CN202311403908.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-26
- Publication Date
- 2025-04-29
AI Technical Summary
The prior art is difficult to generate qubit control signals that meet the qubit operation needs by controlling the main clock and synchronous clock of the DAC, resulting in erroneous operation of the qubit.
A multi-channel qubit control signal generation device is designed, including multiple DAC modules, FPGA modules, clock signal generation modules and clock signal processing modules. By performing frequency amplification and frequency multiplexing of the first-stage clock signal, multiple second-stage clock signals are output, and combined with quantum information and synchronous clock signals, a qubit control signal that meets the working needs of qubits is generated.
The quality of the qubit control signal generated by this device is improved, thereby improving the control effect of qubits in quantum chips, avoiding the problem of qubit error operation.
Smart Images
Figure CN119903929A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of quantum measurement and control technology, and specifically to a quantum bit control signal generating device, a quantum measurement and control system, and a quantum computer. Background Art
[0002] In quantum computers, the logical state of quantum bits can undergo controllable changes, thereby achieving quantum computing, and the quantum bit control signal is used to act on the quantum bits of the quantum chip to change the logical state of the quantum bits.
[0003] For the qubit control signal, the sampling clock of the qubit control signal is the main influencing factor for collecting the qubit control signal. When the sampling clock of the qubit control signal is out of sync or unstable, the collected qubit control signal will not meet the working requirements of the qubit and the qubit will work incorrectly. The qubit control signal is affected by the master clock and synchronization clock received by the DAC (Digital to Analog Converter). Therefore, how to control the master clock and synchronization clock of the DAC to generate a qubit control signal that meets the working requirements of the qubit is a technical problem that needs to be solved urgently.
[0004] Application Contents
[0005] The present application provides a quantum bit control signal generating device, a quantum measurement and control system and a quantum computer, which are used to solve the problem of how to generate a quantum bit control signal that satisfies the operation of the quantum bit by controlling the master clock and the synchronous clock of the DAC.
[0006] The embodiment of this specification provides a multi-channel quantum bit control signal generating device, including:
[0007] Multiple DAC modules;
[0008] An FPGA module, used for storing and sending quantum information related to quantum bit control signals to the plurality of DAC modules;
[0009] A clock signal generating module, used for outputting a first-level clock signal and a first-type synchronous clock signal according to the received clock source signal and the synchronous pulse signal, wherein the first-type synchronous clock signal is used for synchronizing the plurality of DAC modules;
[0010] A clock signal processing module, used for frequency amplification and frequency multi-channel output of the first-stage clock signal, and outputting multiple channels of second-stage clock signals acting on multiple DAC modules respectively;
[0011] The plurality of DAC modules generate quantum bit control signals based on the quantum information, the second-level clock signal and the first-type synchronous clock signal.
[0012] Optionally, the clock source signal is provided by an external clock and / or a local clock.
[0013] Optionally, the external clock and / or local clock is connected to the clock signal generating module via a connector.
[0014] Optionally, the frequencies of the first-level clock signal and the first-type synchronous clock signal are different.
[0015] Optionally, the clock signal processing module includes:
[0016] A clock synthesis unit, used for amplifying the clock frequency of the first-level clock signal and outputting a second-level clock signal;
[0017] The clock fan-out unit is used to fan out the frequency of the second-stage clock signal from a plurality of channels.
[0018] Optionally, the clock signal generating module is further used to output multiple auxiliary clock signals according to the received clock source signal, wherein the auxiliary clock signals are used to provide working clock signals to the FPGA module;
[0019] Alternatively, the clock signal generating module is further used to output a second type of synchronous clock signal based on the received synchronous pulse signal, wherein the second type of synchronous clock signal is used to provide a synchronized working clock signal to the FPGA module.
[0020] Optionally, the FPGA module is provided with a plurality of information storage units for storing the quantum information, and different information storage units share one auxiliary clock signal.
[0021] Optionally, the FPGA module is communicatively connected to the plurality of DAC modules via an SPI bus.
[0022] Optionally, the frequency level of the first-level clock signal is hundreds of hertz, and the frequency level of the second-level clock signal is gigahertz.
[0023] A quantum measurement and control system comprises the multi-channel quantum bit control signal generating device to generate quantum bit control signals.
[0024] A quantum computer comprises the multi-channel quantum bit control signal generating device or the quantum measurement and control system.
[0025] Its beneficial effects are as follows: the present application performs frequency amplification and frequency multi-channel output on the first-stage clock signal, and outputs multiple second-stage clock signals that act on multiple DAC modules respectively; multiple DAC modules generate quantum bit control signals that meet the working requirements of quantum bits based on quantum information, the second-stage clock signal and the first-type synchronous clock signal, so as to improve the quality of the quantum bit control signal, and thereby improve the control effect of the quantum bits in the quantum chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0027] Figure 1 A schematic diagram of the structure of a multi-channel quantum bit control signal generating device provided in an embodiment of this specification;
[0028] Figure 2 This is a schematic diagram of the structure between the synchronization pulse signal providing module and various boards provided in the embodiments of this specification. DETAILED DESCRIPTION
[0029] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.
[0030] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.
[0031] It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise.
[0032] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present application, its application, or uses.
[0033] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.
[0034] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.
[0035] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.
[0036] Manipulating qubits is a necessary process for realizing quantum computing, and the quantum pulse control signal for manipulating qubits is based on the DAC output. Therefore, in order to avoid signal errors, disorder, and non-compliance with requirements in the collected quantum pulse control signal, it is necessary to solve this problem from the source. Therefore, it is necessary to provide a qubit control signal generating device, which provides the master clock and synchronization clock of the multi-channel DAC to control the generation of qubit control signals that meet the working requirements of the qubit, thereby realizing precise control of the qubit control signal.
[0037] Reference Figure 1 A schematic diagram of the structure of a multi-channel quantum bit control signal generating device provided in an embodiment of this specification includes:
[0038] A plurality of DAC modules 103;
[0039] The FPGA module 105 is used to store and send quantum information related to the quantum bit control signal to the multiple DAC modules 103.
[0040] In an optional embodiment, the FPGA module 105 is communicatively connected to the multiple DAC modules 103 via a SPI (Serial Peripheral Interface) bus, and the FPGA module 105 sends quantum information related to the quantum bit control signal stored in the FPGA module 105 to the multiple DAC modules 103 via the SPI bus to realize information transmission, wherein the quantum information can be understood as a digital signal of the quantum bit control signal.
[0041] The clock signal generating module 101 is used to output a first-level clock signal and a first-type synchronous clock signal according to the received clock source signal and the synchronous pulse signal, wherein the first-type synchronous clock signal is used to synchronize the plurality of DAC modules 103 .
[0042] In an optional embodiment, the clock signal generating module 101 may be a clock generator, which uses the resonant circuit, amplifier, etc. inside the clock generator to perform frequency amplification and frequency synthesis processing on the received clock source signal and synchronization pulse signal, thereby providing a stable clock signal that meets the frequency requirements to the clock signal processing module 102, that is, the above-mentioned first-level clock signal, and at the same time provides an accurate time reference, that is, the above-mentioned multi-channel synchronous clock signal, to ensure the clock synchronization of the subsequent multi-channel DAC module 103. The clock source signal is initially processed in the above manner to ensure that the frequency of the second-level clock signal of the subsequent multi-channel DAC module 103 meets the requirements of generating the quantum bit control signal. Optionally, the frequencies of the first-level clock signal and the first-class synchronous clock signal can be different or the same. The specific frequencies of the first-level clock signal and the first-class synchronous clock signal are set accordingly according to the requirements of the quantum bit control signal, and different quantum bit control signals need to be set to different frequencies.
[0043] Optionally, the clock source signal is provided by an external clock and / or a local clock.
[0044] In an optional embodiment, the clock source signal is provided by a local clock 105 and / or an external clock 105. Specifically, the clock source signal provided by the external clock 105 is transmitted from other parts of the quantum computing measurement and control system; the clock source signal provided by the internal clock 105 is generated by an oscillation circuit embedded in the quantum bit control signal generating device, thereby improving the source diversity of the clock source signal, ensuring the same source of the clock, and avoiding errors in the sampling clock of the quantum bit control signal caused by different phase offsets of the clock signal.
[0045] In an optional embodiment, the external clock 105 and / or the local clock 105 are connected to the clock signal generating module 101 via a connector. Specifically, the external clock 105 and / or the local clock 105 are connected to the clock signal generating module 101 via an SMP (Symmetr ic Multi-Processor). The use of the SMP linking method improves the performance of the quantum bit control signal generating device and avoids the phenomenon that the quantum bit control signal generating device cannot operate normally due to the failure of a single processor.
[0046] The clock signal processing module 102 is used to perform frequency amplification and frequency multi-channel output on the first-stage clock signal, and output multiple channels of second-stage clock signals that act on the plurality of DAC modules 103 respectively.
[0047] In an optional embodiment, the frequency of the first-stage clock signal is in the order of 100 Hz, and the frequency of the second-stage clock signal is in the order of GHz. Specifically, the frequency of the first-stage clock signal is controlled at 200 Hz-400 Hz, and the frequency of the second-stage clock signal is optimally 6.4 GHz.
[0048] Optionally, the clock signal processing module 102 includes:
[0049] A clock synthesis unit 1020, configured to amplify the clock frequency of the first-stage clock signal and output a second-stage clock signal;
[0050] The clock fan-out unit 1021 is used to fan out the frequency of the second-stage clock signal from multiple channels.
[0051] In an optional embodiment, the clock signal processing module 102 includes a clock synthesis unit 1020 and a clock fan-out unit 1021. When executing the quantum computing operation process, the operating frequency of the quantum processor is usually between 6GHz and 8GHz. In order to realize the manipulation of the quantum bit state and the reading of the quantum bit state after the quantum gate operation, the clock frequency of the sampling clock of the quantum bit control signal needs to be close to the operating frequency of the quantum processing unit. Therefore, it is necessary to perform frequency amplification processing on the clock frequency of the first-level clock signal through the clock synthesis unit 1020 to obtain a second-level clock signal close to the operating frequency of the quantum processor to meet the accuracy requirements of the quantum processor; then, the frequency of the second-level clock signal is fanned out from multiple channels through the clock fan-out unit 1021, thereby providing the second-level clock signal of the same frequency to the multi-channel DAC, and completing the supply demand of the clock signal of the multi-channel DAC module 103. Among them, the clock synthesis unit 1020 can use a microwave broadband frequency synthesizer, and the clock fan-out unit 1021 can use a fan-out buffer.
[0052] In an optional embodiment, the clock synthesis unit 1020 and the clock fan-out unit 1021 may also exist as separate modules, which is not limited here.
[0053] Optionally, the clock signal generating module 101 is further used to output multiple auxiliary clock signals according to the received clock source signal, wherein the auxiliary clock signals are used to provide a working clock signal to the FPGA module 105;
[0054] Alternatively, the clock signal generating module 101 is further used to output a second type of synchronous clock signal based on the received synchronous pulse signal, wherein the second type of synchronous clock signal is used to provide a synchronized working clock signal to the FPGA module 105.
[0055] In an optional embodiment, the clock signal generating module 101 can also output multiple auxiliary clock signals based on the received clock source signal and output a second type of synchronous clock signal based on the received synchronous pulse signal. When the FPGA module 105 sends a quantum signal to the multi-channel DAC module 103, it can send the quantum signal to the corresponding DAC module 103 based on the multiple auxiliary clock signals alone, or it can send the quantum signal to the corresponding DAC module 103 based on the multiple auxiliary clock signals and the second type of synchronous clock signal at the same time. The setting can be selected according to the actual frequency requirements when the quantum signal is sent.
[0056] Optionally, the FPGA module 105 is provided with a plurality of information storage units for storing the quantum information, and different information storage units share one auxiliary clock signal.
[0057] In an optional embodiment, a plurality of information storage units for storing the quantum information are provided in the FPGA module 105. Under the premise of not affecting the sending of quantum signals by the FPGA module 105, adjacent information storage units can adopt a method of sharing an auxiliary clock signal to improve the efficiency of sending quantum signals and simplify wiring.
[0058] In the present application, multiple DAC modules 103 generate quantum bit control signals that meet the working requirements of quantum bits based on quantum information, second-level clock signals and first-class synchronous clock signals, so as to improve the quality and effect of quantum bit control signals, and thus improve the control effect of quantum bits in quantum chips. It should be noted that quantum information is a digital signal of the quantum bit control signal, which is converted into an analog signal of the quantum bit control signal through the DAC module 103, and then the analog signal carries the second-level clock signal and the first-class synchronous clock signal to act on the corresponding quantum bit to realize the manipulation of the quantum bit state.
[0059] Optionally, the device further includes a synchronization pulse signal providing module 104 for providing a third type of synchronization clock signal to the clock signal generating module 101 .
[0060] In an optional embodiment, since there are many boards 1 in the quantum measurement and control system, sometimes it is necessary to synchronize the clocks between multiple boards 1. Therefore, in order to synchronize the clocks between multiple boards 1, the following method is used: Figure 2 In the manner shown, the synchronization pulse signal providing module 104 is used to simultaneously provide multiple third-category synchronization clock signals to each board 1. It should be noted that the synchronization pulse signal providing module 104 is not limited to the connection with the clock signal generating module 101, and can also be connected to other modules or chips on the board 1. Here, it is only for providing clock synchronization between multiple boards, and no restrictions are made on other aspects. Among them, the board 1 can be a printed circuit board.
[0061] One embodiment of the present specification provides a quantum measurement and control system, comprising the multi-channel quantum bit control signal generating device to generate a quantum bit control signal.
[0062] One embodiment of the present specification provides a quantum computer, including a quantum computing measurement and control system and a quantum processor, wherein the quantum processor operates the quantum computer according to a quantum pulse control signal output by the quantum computing measurement and control system.
[0063] It should be understood that the specific examples in this specification are only intended to help those skilled in the art to better understand the implementation methods of this specification, rather than to limit the scope of this application.
[0064] It can be understood that in the various implementations of this specification, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation methods of this specification.
[0065] It can be understood that the various embodiments described in this specification can be implemented individually or in combination, and the embodiments of this specification are not limited to this.
[0066] Unless otherwise specified, all technical and scientific terms used in the embodiments of this specification have the same meaning as those generally understood by those skilled in the art of the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms of "a", "above", and "the" used in the embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.
[0067] In the several embodiments provided in this specification, it should be understood that the disclosed device can be implemented in other ways. For example, the device implementation described above is only schematic. For example, the division of the device or module is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.
[0068] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of this implementation scheme.
[0069] In addition, each functional module in each embodiment of the present specification may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.
[0070] The above is only a specific implementation of this specification, but the protection scope of this application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in this specification, which should be included in the protection scope of this specification. Therefore, the protection scope of this application should be based on the protection scope of the claims.
Claims
1. A multi-channel quantum bit control signal generating device, characterized in that: include: Multiple DAC modules; An FPGA module, used for storing and sending quantum information related to quantum bit control signals to the plurality of DAC modules; A clock signal generating module, used for outputting a first-level clock signal and a first-type synchronous clock signal according to the received clock source signal and the synchronous pulse signal, wherein the first-type synchronous clock signal is used for synchronizing the plurality of DAC modules; A clock signal processing module, used for frequency amplification and frequency multi-channel output of the first-stage clock signal, and outputting multiple channels of second-stage clock signals acting on multiple DAC modules respectively; The plurality of DAC modules generate quantum bit control signals based on the quantum information, the second-level clock signal and the first-type synchronous clock signal.
2. The device according to claim 1, characterized in that The clock source signal is provided by an external clock and / or a local clock.
3. The device according to claim 2, characterized in that The external clock and / or the local clock is connected to the clock signal generating module via a connector.
4. The device according to claim 1, characterized in that The frequencies of the first-level clock signal and the first-type synchronous clock signal are different.
5. The device according to claim 1, characterized in that The clock signal processing module comprises: A clock synthesis unit, used for amplifying the clock frequency of the first-level clock signal and outputting a second-level clock signal; The clock fan-out unit is used to fan out the frequency of the second-stage clock signal from multiple channels.
6. The device according to claim 1, characterized in that The clock signal generating module is further used to output multiple auxiliary clock signals according to the received clock source signal, wherein the auxiliary clock signals are used to provide working clock signals to the FPGA module; Alternatively, the clock signal generating module is further used to output a second type of synchronous clock signal based on the received synchronous pulse signal, wherein the second type of synchronous clock signal is used to provide a synchronized working clock signal to the FPGA module.
7. The device according to claim 6, characterized in that The FPGA module is provided with a plurality of information storage units for storing the quantum information, and different information storage units share one auxiliary clock signal.
8. The device according to claim 1, characterized in that The FPGA module is connected to the plurality of DAC modules via an SPI bus communication.
9. The device according to claim 1, characterized in that The frequency of the first-stage clock signal is in the order of hundreds of hertz, and the frequency of the second-stage clock signal is in the order of gigahertz.
10. A quantum measurement and control system, comprising a device as described in any one of claims 1 to 9 to generate a quantum bit control signal.
11. A quantum computer, comprising the multi-channel quantum bit control signal generating device according to any one of claims 1 to 9 or the quantum measurement and control system according to claim 10.