Method and device for determining quantum program mapping scheme and medium

Abstract

The invention discloses a quantum program mapping scheme determination method and device and a medium, and the method comprises the steps: firstly determining a quantum logic gate set which cannot be directly executed on a quantum chip in a quantum program to be executed, then constructing a tree-shaped search structure of SWAP gates, and obtaining all initial mapping schemes inserted with the SWAP gates in the quantum logic gate set; finally, according to the evaluation functions of the mapping schemes, evaluation function values of all initial mapping schemes are calculated to determine a target mapping scheme, the optimal target mapping scheme is determined by constructing a tree search structure and combining the mapping scheme evaluation functions, the compiling time of the quantum program is further shortened, efficient compiling of the quantum program is achieved, and the compiling efficiency of the quantum program is improved. And the development of quantum calculation is promoted.

Description

Technical Field

[0001] The present invention belongs to the field of quantum computing technology, and in particular to a method, device and medium for determining a quantum program mapping scheme. Background Art

[0002] Quantum computers are physical devices that follow the laws of quantum mechanics to perform high-speed mathematical and logical operations, store and process quantum information. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Quantum computers have become a key technology under research because they have the ability to process mathematical problems more efficiently than ordinary computers. For example, they can speed up the time to crack RSA keys from hundreds of years to a few hours.

[0003] In the noisy intermediate-scale quantum computing stage, for multiple physical bits on the same physical chip, the states of each physical bit are unstable. Factors such as the operation noise of two-bit quantum logic gates, measurement noise, and the decoherence time of physical bits will interfere with the effective utilization of the physical bits, thereby having an unknown impact on the operation results of the entire quantum circuit.

[0004] For example, in the actual operation of quantum circuits, in order to meet the execution of two-bit quantum logic gates, SWAP gates are often added to update the mapping. The addition of SWAP gates will seriously increase the compilation time of quantum programs and the running time of quantum circuits. Once the compilation time exceeds the decoherence time of the physical bit, it will directly lead to errors in the calculation results. Therefore, optimizing the mapping scheme of quantum programs, thereby shortening the compilation time of quantum programs, achieving efficient compilation of quantum programs, and promoting the development of quantum computing is an urgent problem to be solved. Summary of the invention

[0005] The purpose of the present invention is to provide a method, device and medium for determining a quantum program mapping scheme to address the deficiencies in the prior art. The method determines the optimal target mapping scheme by constructing a tree search structure and combining a mapping scheme evaluation function, thereby further shortening the compilation time of the quantum program, achieving efficient compilation of the quantum program and promoting the development of quantum computing.

[0006] An embodiment of the present application provides a method for determining a quantum program mapping scheme, the method comprising:

[0007] Determine the set of quantum logic gates in the quantum program to be executed that cannot be directly executed on the quantum chip;

[0008] Constructing a tree search structure of SWAP gates, and obtaining initial mapping schemes of all inserted SWAP gates in the quantum logic gate set;

[0009] According to the evaluation function of the mapping scheme, the evaluation function values ​​of all the initial mapping schemes are calculated to determine a target mapping scheme, wherein the evaluation function value of the target mapping scheme is the largest.

[0010] Optionally, determining a set of quantum logic gates in the quantum program to be executed that cannot be directly executed on the quantum chip includes:

[0011] Obtain a directed acyclic graph of the quantum program to be executed;

[0012] According to the topological sequence of the directed acyclic graph and the execution timing of the quantum logic gates, all quantum logic gates in the directed acyclic graph that cannot be directly executed on the quantum chip are determined respectively, and a set of quantum logic gates in the quantum program to be executed that cannot be directly executed on the quantum chip is generated; wherein the quantum logic gates that cannot be directly executed on the quantum chip include two-bit quantum logic gates whose logical bits are not adjacent.

[0013] Optionally, the tree search structure for constructing the SWAP gate includes:

[0014] A tree search structure using a SWAP gate is generated according to the quantum logic gate set and the number of layers and nodes of the pre-set tree search structure.

[0015] Optionally, generating a tree search structure using a SWAP gate according to the quantum logic gate set and the number of layers and nodes of a preset tree search structure includes:

[0016] Determining in sequence the quantum logic gates contained in each layer after the quantum logic gate set is divided according to the number of layers and the corresponding initial mapping scheme;

[0017] The operation of inserting SWAP gates into the quantum bits acting on the quantum logic gates contained in each layer is respectively performed, and a mapping scheme after the SWAP gates are inserted and updated is generated, until a tree search structure using the SWAP gates is generated; wherein the nodes of the tree search structure represent the updated mapping schemes, the edges of the tree search structure represent the SWAP gates of the updated mapping schemes, and the root node of the tree search structure represents the initial mapping scheme.

[0018] Optionally, before calculating the evaluation function values ​​of all the initial mapping schemes according to the evaluation function of the mapping scheme to determine the target mapping scheme, the method further includes:

[0019] The distance of each operation of inserting a SWAP gate is calculated by the following cost function:

[0020]

[0021] Where D represents the cost function, d represents the distance of each SWAP gate, g represents the quantum logic gate that needs to be inserted into the SWAP gate, F represents the quantum logic gate set, and π l+1 For the mapping scheme π l The sub-terms of l The updated mapping scheme obtained after inserting the SWAP gate, g qi and g qj They represent the two quantum bits that need to be inserted into the SWAP gate.

[0022] Optionally, the step of calculating evaluation function values ​​of all the initial mapping schemes according to the evaluation function of the mapping scheme to determine the target mapping scheme includes:

[0023] The mapping scheme evaluation function is calculated by the following formula:

[0024]

[0025] Among them, l represents the depth index of the tree search structure, p represents the horizontal position index of the tree search structure, m represents the child node index in the tree search structure, and C l,p represents the evaluation function of the current mapping scheme, C l+1,m C l,p The child of G l,p In the mapping scheme π l,p The gain of the two-bit quantum logic gate under l,p In the mapping scheme π l,p The parallel parameter overhead of the two-bit quantum logic gate under l,p In the mapping scheme π l,p The number of parameters that need to be re-optimized in the quantum logic gate, β is the weight coefficient of the number of parameters that need to be re-optimized in the mapping scheme, γ is the sub-item weight coefficient of the current mapping scheme, and γ∈(0,1).

[0026] Another embodiment of the present application provides a device for determining a quantum program mapping scheme, the device comprising:

[0027] A determination module, used to determine a set of quantum logic gates in a quantum program to be executed that cannot be directly executed on a quantum chip;

[0028] A construction module, used to construct a tree search structure of SWAP gates and obtain an initial mapping scheme for all inserted SWAP gates in the quantum logic gate set;

[0029] The calculation module is used to calculate the evaluation function values ​​of all the initial mapping schemes according to the evaluation function of the mapping scheme to determine the target mapping scheme, wherein the evaluation function value of the target mapping scheme is the largest.

[0030] Optionally, the determining module includes:

[0031] An obtaining unit, used for obtaining a directed acyclic graph of a quantum program to be executed;

[0032] A determination unit is used to determine all quantum logic gates in the directed acyclic graph that cannot be directly executed on the quantum chip according to the topological sequence of the directed acyclic graph and the execution timing of the quantum logic gates, and generate a set of quantum logic gates in the quantum program to be executed that cannot be directly executed on the quantum chip; wherein the quantum logic gates that cannot be directly executed on the quantum chip include two-bit quantum logic gates whose logical bits are not adjacent.

[0033] Optionally, the construction module includes:

[0034] A generating unit is used to generate a tree search structure using a SWAP gate according to the quantum logic gate set and the number of layers and nodes of the preset tree search structure.

[0035] Optionally, the generating unit includes:

[0036] A determination subunit, used to sequentially determine the quantum logic gates contained in each layer after the quantum logic gate set is divided according to the number of layers and the corresponding initial mapping scheme;

[0037] The execution subunit is used to respectively execute the operation of inserting SWAP gates into the quantum bits acting on the quantum logic gates contained in each layer, and generate an updated mapping scheme after the SWAP gates are inserted, until a tree search structure using the SWAP gates is generated; wherein the nodes of the tree search structure represent the updated mapping schemes, the edges of the tree search structure represent the SWAP gates of the updated mapping schemes, and the root node of the tree search structure represents the initial mapping scheme.

[0038] An embodiment of the present application provides a storage medium, in which a computer program is stored, wherein the computer program is configured to execute any of the above methods when running.

[0039] An embodiment of the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute any one of the methods described above.

[0040] Compared with the prior art, the present application first determines the set of quantum logic gates in the quantum program to be executed that cannot be directly executed on the quantum chip, then constructs a tree search structure of the SWAP gate, and obtains the initial mapping schemes of all inserted SWAP gates in the quantum logic gate set, and finally calculates the evaluation function values ​​of all initial mapping schemes according to the evaluation function of the mapping scheme to determine the target mapping scheme. It determines the optimal target mapping scheme by constructing a tree search structure and combining the mapping scheme evaluation function, further shortens the compilation time of the quantum program, realizes efficient compilation of the quantum program, and promotes the development of quantum computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a system network block diagram of a method for determining a quantum program mapping scheme provided by an embodiment of the present invention;

[0042] Figure 2 It is a flowchart of a method for determining a quantum program mapping scheme provided by an embodiment of the present invention;

[0043] Figure 3 is a schematic diagram of a quantum circuit corresponding to a quantum program to be executed provided by an embodiment of the present invention;

[0044] Figure 4 is a schematic diagram of a directed acyclic graph corresponding to a quantum program to be executed provided by an embodiment of the present invention;

[0045] Figure 5 It is a structural schematic diagram of a device for determining a quantum program mapping scheme provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, but should not be construed as limiting the present invention.

[0047] The embodiment of the present invention first provides a method for determining a quantum program mapping scheme, which can be applied to electronic devices such as computer terminals, specifically ordinary computers, quantum computers, etc.

[0048] The following describes it in detail by taking running on a computer terminal as an example. Figure 1 1 is a system network block diagram of a method for determining a quantum program mapping scheme provided by an embodiment of the present invention. The system applied to the method for determining a quantum program mapping scheme may include a network 110, a server 120, a wireless device 130, a client 140, a storage unit 150, a classical processing system 160, a quantum processing system 170, and may also include additional memories, classical processors, quantum processors, and other devices not shown.

[0049] The network 110 is a medium that provides communication links between various devices and computers connected together in the system network used for the method for determining the quantum program mapping scheme, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks and combinations thereof. The connection method can be wired, wireless communication links or optical fiber cables, etc.

[0050] The server 120 and the client 140 are conventional data processing systems that may contain data and applications or software tools that perform conventional computing processes. The client 140 may be a personal computer or a network computer, so the data may also be provided by the server 120. The wireless device 130 may be a smart phone, a tablet, a laptop, a smart wearable device, etc. The storage unit 150 may include a database 151, which may be configured to store data such as quantum bit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc.

[0051] The classical processing system 160 (quantum processing system 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 163 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application 162 (application 173). The application 162 (application 173) may be used to implement a quantum algorithm compiled according to a method for determining a quantum program mapping scheme provided in an embodiment of the present invention.

[0052] Any data or information stored or generated in the classical processing system 160 (quantum processing system 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0053] It should be noted that a true quantum computer is a hybrid structure, which includes at least Figure 1 There are two major parts in it: the classical processing system 160, which is responsible for performing classical calculations and control; and the quantum processing system 170, which is responsible for running quantum programs and thus realizing quantum calculations.

[0054] The classical processing system 160 and the quantum processing system 170 may be integrated into one device or distributed in two different devices. For example, the first device including the classical processing system 160 runs a classical computer operating system, on which quantum application development tools and services are provided, as well as storage and network services required for quantum applications. Users develop quantum applications through the quantum application development tools and services thereon, and send quantum programs to the second device including the quantum processing system 170 through the network services thereon. The second device runs a quantum computer operating system, parses the code of the quantum program through the quantum computer operating system, and compiles it into instructions that can be recognized and executed by the quantum computer measurement and control system. The quantum processor 170 implements the quantum algorithm corresponding to the quantum program according to the instructions.

[0055] In the classic processing system 160 based on silicon chips, the unit of the classic processor 161 is a CMOS tube. This computing unit is not limited by time and coherence, that is, this computing unit is not limited by the length of use and is available at any time. In addition, in the silicon chip, the number of such computing units is also sufficient. At present, the number of computing units in a classic processor is tens of thousands. The number of computing units is sufficient and the computing logic that can be selected by the CMOS tube is fixed, for example: AND logic. When calculating with the help of CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the calculation effect.

[0056] Unlike this logic unit in the classical processing system 160, the basic computing unit of the quantum processor 171 in the quantum processing system 170 is a quantum bit, and the input of the quantum bit is limited by coherence and coherence time, that is, the quantum bit is limited by the use time and is not available at any time. Making full use of the quantum bit within the available use time of the quantum bit is a key problem in quantum computing. In addition, the number of quantum bits in a quantum computer is one of the representative indicators of the performance of a quantum computer. Each quantum bit realizes the computing function through the logical function configured on demand. In view of the limited number of quantum bits, the logical functions in the field of quantum computing are diverse, such as: Hadamard gate (Hadamard gate, H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate) Pauli-Z gate (Z gate), X gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. In quantum computing, it is necessary to use limited quantum bits combined with a variety of logical functions to achieve the computing effect.

[0057] Based on these differences, the design of the logical function acting on the quantum bit (including the design of whether the quantum bit is used or not and the design of the efficiency of each quantum bit) is the key to improving the computing performance of the quantum computer, and a special design is required. The above-mentioned design for quantum bits is a technical problem that ordinary computing devices do not need to consider or face. In the face of the actual operation of the quantum circuit in this application, in order to meet the execution of the two-bit quantum logic gate, the SWAP gate is often added to update the mapping, and the addition of the SWAP gate will seriously increase the compilation of the quantum program and the running time of the quantum circuit. Once the compilation time exceeds the decoherence time of the physical bit, it will directly lead to errors in the calculation results. Therefore, optimizing the mapping scheme of the quantum program, thereby shortening the compilation time of the quantum program, realizing the efficient compilation of the quantum program, and promoting the development of quantum computing is an urgent problem to be solved. This application solves the deficiencies in the prior art by providing a method for determining a quantum program mapping scheme. It determines the optimal target mapping scheme by constructing a tree search structure and combining a mapping scheme evaluation function, further shortening the compilation time of the quantum program, realizing the efficient compilation of the quantum program, and promoting the development of quantum computing.

[0058] See also Figure 2 , Figure 2 It is a flowchart of a method for determining a quantum program mapping scheme provided by an embodiment of the present invention.

[0059] This embodiment provides an embodiment of a method for determining a quantum program mapping scheme. The method for determining a quantum program mapping scheme may include:

[0060] S201: Determine a set of quantum logic gates in a quantum program to be executed that cannot be directly executed on a quantum chip.

[0061] Specifically, the quantum program to be executed corresponds to a quantum circuit as a whole, and the quantum program in this application refers to the quantum circuit, wherein the total number of quantum bits in the quantum circuit is the same as the total number of quantum bits in the quantum program. It can be understood that a quantum program can be composed of a quantum circuit, a measurement operation on the quantum bits in the quantum circuit, a register for storing the measurement results, and a control flow node (jump instruction), and a quantum circuit can contain dozens, hundreds, or even thousands of quantum logic gate operations.

[0062] It should be noted that the way to operate quantum bits is quantum logic gates. Using quantum logic gates, quantum states can evolve. Quantum logic gates are the basis of quantum circuits. Quantum logic gates include single-bit quantum logic gates, such as Hadamard gates, Pauli-X gates, Pauli-Y gates, Pauli-Z gates (RX gates, RY gates, RZ gates, etc.; multi-bit quantum logic gates, such as CNOT gates, CR gates, iSWAP gates, Toffoli gates, etc. Quantum logic gates are generally represented by unitary matrices, which are not only in matrix form, but also an operation and transformation. The effect of a general quantum logic gate on a quantum state is calculated by multiplying the unitary matrix on the left by the matrix corresponding to the right vector of the quantum state.

[0063] In an optional implementation, determining a set of quantum logic gates in a quantum program to be executed that cannot be directly executed on a quantum chip may include:

[0064] 1. Obtain a directed acyclic graph of the quantum program to be executed.

[0065] A directed acyclic graph (DAG) is a type of directed graph. The literal meaning is that there is no loop in the graph. It is a directed graph without loops. If there is a non-directed acyclic graph, starting from point A to point B through point C and returning to point A, a loop is formed. If the direction from point C to point A is changed to point A to point C, it becomes a directed acyclic graph, which is often used to represent the driving dependency between events, the scheduling between tasks, etc.

[0066] To obtain a directed acyclic graph of a quantum program to be executed, the nodes in the quantum program to be executed can be first obtained. The so-called node in the quantum program refers to a data of a specific structure at a relative position of the entire program, which can be a quantum logic gate, a measurement operation (Measure), etc. In this application, the quantum logic gate node is mainly considered. For example, the quantum logic gate node in the quantum program can be obtained by traversing the nodes of the quantum program.

[0067] For example, see Figure 3 , Figure 3It is a schematic diagram of a quantum circuit corresponding to a quantum program to be executed provided by an embodiment of the present invention. It can be understood that an entire quantum program corresponds to a total quantum circuit. Among them, the quantum program to be executed is CNOT(q[0], q[1]) << CNOT(q[2], q[4]) << CNOT(q[2], q[3]) << CNOT(q[0], q[2]) << CNOT(q[2], q[4]) << CNOT(q[1], q[4]) << CNOT(q[0], q[1]). Starting from CNOT(q[0], q[1]) for traversal, the nodes 1 to 7 in the quantum program to be executed are obtained as CNOT(q[0], q[1]), CNOT(q[2], q[4]), CNOT(q[2], q[3]), CNOT(q[0], q[2]), CNOT(q[2], q[4]), CNOT(q[1], q[4]), CNOT(q[0], q[1]) respectively.

[0068] Subsequently, according to the qubits operated by the nodes, the correlation relationships between the nodes are determined. For each quantum operation node, among all the quantum operation nodes sequentially executed starting from the qubits operated by this node, the next node of this node is determined to obtain the adjacent relationship between this node and the next node. Finally, according to the nodes and the correlation relationships between the nodes, a directed acyclic graph corresponding to the quantum program to be executed is generated. Among them, the vertices in the directed acyclic graph represent the nodes, the edges in the directed acyclic graph represent the correlation relationships between the nodes, and the direction of the edge represents the timing relationship of the execution of the nodes corresponding to the vertices connected by this edge.

[0069] 2. According to the topological sequence of the directed acyclic graph and the execution timing of quantum logic gates, respectively determine all quantum logic gates in the directed acyclic graph that cannot be directly executed on a quantum chip, and generate a set of quantum logic gates in the quantum program to be executed that cannot be directly executed on a quantum chip; among them, the quantum logic gates that cannot be directly executed on a quantum chip include two-bit quantum logic gates with non-adjacent logical qubits.

[0070] Specifically, according to the topological sequence of the directed acyclic graph and the execution timing of quantum logic gates, the nodes with in-degree zero in the directed acyclic graph and the quantum logic gates that can be directly executed are classified into one set; the nodes with in-degree zero in the directed acyclic graph and the quantum logic gates that cannot be directly executed are classified into another set.

[0071] Exemplarily, refer to Figure 4 , Figure 4 It is a schematic diagram of a directed acyclic graph corresponding to a quantum program to be executed provided by an embodiment of the present invention. According to Figure 4For the directed acyclic graph shown, the nodes with zero in-degree and the quantum logic gates that can be directly executed are CNOT(q[0], q[1]) and CNOT(q[2], q[4]) respectively. Among them, the logical qubits of the CNOT(q[0], q[1]) operation are adjacent, which is a quantum logic gate that can be directly executed; among them, the logical qubits of the CNOT(q[2], q[4]) operation are not adjacent, which is a quantum logic gate that cannot be directly executed.

[0072] Delete the quantum logic gates for which the set partitioning is completed, and continue to determine all the quantum logic gates in the directed acyclic graph that cannot be directly executed on the quantum chip according to the above method, and generate a set of quantum logic gates in the to-be-executed quantum program that cannot be directly executed on the quantum chip. Therefore Figure 4 The set of quantum logic gates that ultimately cannot be directly executed on the quantum chip includes: CNOT(q[2], q[4]), CNOT(q[0], q[2]), CNOT(q[2], q[4]) and CNOT(q[1], q[4]).

[0073] S202: Construct a tree search structure for the SWAP gates and obtain all the initial mapping schemes for inserting SWAP gates in the set of the quantum logic gates.

[0074] The to-be-executed quantum program can be composed of dozens, hundreds or even thousands of quantum logic gates. The execution process of the quantum program is a process of executing all the quantum logic gates in a certain time sequence. It should be noted that the time sequence is the time order in which a single quantum logic gate is executed. For the sake of distinction, generally, the quantum bit structure in the quantum chip is called a physical bit, and the object bit operated in the quantum circuit is called a logical bit. The initial mapping relationship between the logical bit and the physical bit refers to the relationship in which the bits between the logical bit and the physical bit "correspond" to each other.

[0075] Exemplarily, for a to-be-executed quantum program CNOT(q[0], q[1]) << CNOT(q[2], q[4]) << CNOT(q[2], q[3]) << CNOT(q[0], q[2]) << CNOT(q[2], q[4]) << CNOT(q[1], q[4]) << CNOT(q[0], q[1]), the logical bits it operates on are q[0], q[1], q[2], q[3], q[4] respectively. Then the initial mapping relationship between the logical bit and the physical bit can be set to multiple initial mapping relationships such as q[0] corresponding to Q[0], q[1] corresponding to Q[1], q[2] corresponding to Q[2], q[3] corresponding to Q[3], q[4] corresponding to Q[4], etc., which are not limited here.

[0076] Wherein, constructing the tree search structure of the SWAP gate may include: generating a tree search structure using the SWAP gate according to the quantum logic gate set and the number of layers and nodes of the pre-set tree search structure.

[0077] In an optional implementation, the tree search structure can be obtained by the following steps:

[0078] Step 1: sequentially determining the quantum logic gates contained in each layer after the quantum logic gate set is divided according to the number of layers and the corresponding initial mapping scheme;

[0079] Step 2: respectively inserting SWAP gates into the quantum bits acting on the quantum logic gates contained in each layer, and generating an updated mapping scheme after the SWAP gates are inserted, until a tree search structure using the SWAP gates is generated; wherein the nodes of the tree search structure represent the updated mapping schemes, the edges of the tree search structure represent the SWAP gates of the updated mapping schemes, and the root node of the tree search structure represents the initial mapping scheme.

[0080] Among them, the quantum program to be executed is converted into a directed acyclic graph, and then according to the topological order of the directed acyclic graph and the execution timing of the quantum logic gate, the set of front quantum logic gates that cannot be directly executed in the topological sequence of the directed acyclic graph is determined, that is, the gates that cannot be executed in the front layer are selected, which can be defined as the front quantum logic gate set (front_layer), and then each dual quantum logic gate in the front quantum logic gate set is traversed in turn. If the current front quantum logic gate cannot be directly executed under the current mapping, the SWAP gate is inserted. It should be noted that the SWAP gate needs to be inserted between the quantum bits connected by the coupler. For example, in the SWAP gate S ij Previously, the mapping was π l :q i →Q i ,q j →Q j , after inserting the SWAP gate, the mapping arrangement changes to π l+1 :q i →Q j ,q j →Q i .

[0081] In order to find a more suitable mapping, a tree search structure of SWAP gates is constructed to list all mapping schemes that insert SWAP gates. The nodes of the tree represent the mapping states, the edges represent the SWAP gates that change the mapping, and the root node of the tree is the current mapping state π lDuring the construction process, the specific values ​​of M and L are set according to the performance of the current hardware computing device; the look-ahead degree of the subsequent tree search is controlled by the tree depth L, and the breadth of the tree search is controlled by the number of child nodes M of each node; in order to reduce complexity, M<S is set at the same time, where S represents the number of all SWAP gates that can be selected.

[0082] Building a tree search structure based on SWAP gates is an iterative process, with the initial mapping π l Take this as an example. First, obtain the quantum logic gates that cannot be directly executed and their corresponding mappings. Then, insert the SWAP gate operation into the two qubits of all quantum logic gates to be executed to obtain the new mapping (π l+1, , π l+1, , …, π l+1, ); then iterate the second step until the (L-1) layer mapping is obtained. For each SWAP gate S in the tree search structure based on the SWAP gate ij , insert it into the quantum program to be executed, and calculate S ij Distance cost For example, the distance of each operation of inserting a SWAP gate can be calculated by the following cost function:

[0083]

[0084] Where D represents the cost function, d represents the distance of each SWAP gate, g represents the quantum logic gate that needs to be inserted into the SWAP gate, F represents the quantum logic gate set, and π l+1 For the mapping scheme π l The sub-terms of l The updated mapping scheme obtained after inserting the SWAP gate, g qi and g qj They represent the two quantum bits that need to be inserted into the SWAP gate.

[0085] S203: Calculate the evaluation function values ​​of all the initial mapping schemes according to the evaluation function of the mapping scheme to determine a target mapping scheme, wherein the evaluation function value of the target mapping scheme is the largest.

[0086] Specifically, after obtaining the first M nodes with the smallest distance according to the above cost function, perform the exchange operation S on the current mapping. ij After that, we get M child nodes Finally, after obtaining the L×M search tree, we start from the last child node and evaluate the quality of the current mapping. For example, the mapping scheme evaluation function can be calculated by the following formula:

[0087]

[0088] Among them, l represents the depth index of the tree search structure, p represents the horizontal position index of the tree search structure, m represents the child node index in the tree search structure, and C l,p represents the evaluation function of the current mapping scheme, C l+1,m C l,p The child of G l,p In the mapping scheme π l,p The gain of the two-bit quantum logic gate under l,p In the mapping scheme π l,p The parallel parameter overhead of the two-bit quantum logic gate under l,p In the mapping scheme π l,p The number of parameters that need to be re-optimized in the quantum logic gate, β is the weight coefficient of the number of parameters that need to be re-optimized in the mapping scheme, γ is the sub-item weight coefficient of the current mapping scheme, and γ∈(0,1).

[0089] Finally, when we go back to the step of converting the quantum program to be executed into a directed acyclic graph, we can choose the maximum C l+1,p The corresponding SWAP gate, after inserting the SWAP gate p, obtains a new mapping π l,p Repeat the above steps until all the quantum logic gates that cannot be directly executed are remapped, and the mapping schemes for all inserted SWAP gates can be obtained. The optimal mapping scheme for the quantum program to be executed can be determined by combining the above cost function with the evaluation function with the largest value.

[0090] It can be seen that the present application first determines the set of quantum logic gates in the quantum program to be executed that cannot be directly executed on the quantum chip, then constructs a tree search structure of the SWAP gate, and obtains the initial mapping schemes of all inserted SWAP gates in the quantum logic gate set, and finally calculates the evaluation function values ​​of all initial mapping schemes according to the evaluation function of the mapping scheme to determine the target mapping scheme. It determines the optimal target mapping scheme by constructing a tree search structure and combining the mapping scheme evaluation function, further shortens the compilation time of the quantum program, realizes efficient compilation of the quantum program, and promotes the development of quantum computing.

[0091] See also Figure 5 , Figure 5 is a schematic diagram of a structure of a device for determining a quantum program mapping scheme provided by an embodiment of the present invention, and Figure 2 Corresponding to the process shown, the device includes:

[0092] A determination module 501 is used to determine a set of quantum logic gates in a quantum program to be executed that cannot be directly executed on a quantum chip;

[0093] A construction module 502 is used to construct a tree search structure of SWAP gates and obtain an initial mapping scheme for all inserted SWAP gates in the quantum logic gate set;

[0094] The calculation module 503 is used to calculate the evaluation function values ​​of all the initial mapping schemes according to the evaluation function of the mapping scheme to determine the target mapping scheme, wherein the evaluation function value of the target mapping scheme is the largest.

[0095] Specifically, the determination module includes:

[0096] An obtaining unit, used for obtaining a directed acyclic graph of a quantum program to be executed;

[0097] A determination unit is used to determine all quantum logic gates in the directed acyclic graph that cannot be directly executed on the quantum chip according to the topological sequence of the directed acyclic graph and the execution timing of the quantum logic gates, and generate a set of quantum logic gates in the quantum program to be executed that cannot be directly executed on the quantum chip; wherein the quantum logic gates that cannot be directly executed on the quantum chip include two-bit quantum logic gates whose logical bits are not adjacent.

[0098] Specifically, the construction module includes:

[0099] A generating unit is used to generate a tree search structure using a SWAP gate according to the quantum logic gate set and the number of layers and nodes of the preset tree search structure.

[0100] Specifically, the generating unit includes:

[0101] A determination subunit, used to sequentially determine the quantum logic gates contained in each layer after the quantum logic gate set is divided according to the number of layers and the corresponding initial mapping scheme;

[0102] The execution subunit is used to respectively execute the operation of inserting SWAP gates into the quantum bits acting on the quantum logic gates contained in each layer, and generate an updated mapping scheme after the SWAP gates are inserted, until a tree search structure using the SWAP gates is generated; wherein the nodes of the tree search structure represent the updated mapping schemes, the edges of the tree search structure represent the SWAP gates of the updated mapping schemes, and the root node of the tree search structure represents the initial mapping scheme.

[0103] An embodiment of the present invention further provides a storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0104] Specifically, in this embodiment, the above storage medium may be configured to store a computer program for performing the following steps:

[0105] S201: Determine a set of quantum logic gates in the quantum program to be executed that cannot be directly executed on the quantum chip;

[0106] S202: constructing a tree search structure of SWAP gates, and obtaining initial mapping schemes of all inserted SWAP gates in the quantum logic gate set;

[0107] S203: Calculate the evaluation function values ​​of all the initial mapping schemes according to the evaluation function of the mapping scheme to determine a target mapping scheme, wherein the evaluation function value of the target mapping scheme is the largest.

[0108] Specifically, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0109] An embodiment of the present invention further provides an electronic device, comprising a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0110] Specifically, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0111] Specifically, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0112] S201: Determine a set of quantum logic gates in the quantum program to be executed that cannot be directly executed on the quantum chip;

[0113] S202: constructing a tree search structure of SWAP gates, and obtaining initial mapping schemes of all inserted SWAP gates in the quantum logic gate set;

[0114] S203: Calculate the evaluation function values ​​of all the initial mapping schemes according to the evaluation function of the mapping scheme to determine a target mapping scheme, wherein the evaluation function value of the target mapping scheme is the largest.

[0115] An embodiment of the present invention may also provide a quantum computer operating system, which implements the determination of a quantum program mapping scheme according to any of the above method embodiments provided in the embodiments of the present invention.

[0116] An embodiment of the present application may also provide a quantum computer, wherein the quantum computer includes the quantum computer operating system.

[0117] The above describes in detail the structure, features and effects of the present invention based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the drawings. Any changes made according to the concept of the present invention, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the protection scope of the present invention.

Claims

1. A method for determining a quantum program mapping scheme, characterized in that: The method comprises: Determine the set of quantum logic gates in the quantum program to be executed that cannot be directly executed on the quantum chip; Constructing a tree search structure of SWAP gates, and obtaining initial mapping schemes of all inserted SWAP gates in the quantum logic gate set; According to the evaluation function of the mapping scheme, the evaluation function values ​​of all the initial mapping schemes are calculated to determine a target mapping scheme, wherein the evaluation function value of the target mapping scheme is the largest.

2. The method according to claim 1, characterized in that The step of determining a set of quantum logic gates in the quantum program to be executed that cannot be directly executed on the quantum chip includes: Obtain a directed acyclic graph of the quantum program to be executed; According to the topological sequence of the directed acyclic graph and the execution timing of the quantum logic gates, all quantum logic gates in the directed acyclic graph that cannot be directly executed on the quantum chip are determined respectively, and a set of quantum logic gates in the quantum program to be executed that cannot be directly executed on the quantum chip is generated; wherein the quantum logic gates that cannot be directly executed on the quantum chip include two-bit quantum logic gates whose logical bits are not adjacent.

3. The method according to claim 2, characterized in that The tree search structure for constructing the SWAP gate includes: A tree search structure using a SWAP gate is generated according to the quantum logic gate set and the number of layers and nodes of the pre-set tree search structure.

4. The method according to claim 3, characterized in that The step of generating a tree search structure using a SWAP gate according to the quantum logic gate set and the number of layers and nodes of the pre-set tree search structure comprises: Determining in sequence the quantum logic gates contained in each layer after the quantum logic gate set is divided according to the number of layers and the corresponding initial mapping scheme; The operation of inserting SWAP gates into the quantum bits acting on the quantum logic gates contained in each layer is respectively performed, and a mapping scheme after the SWAP gates are inserted and updated is generated, until a tree search structure using the SWAP gates is generated; wherein the nodes of the tree search structure represent the updated mapping schemes, the edges of the tree search structure represent the SWAP gates of the updated mapping schemes, and the root node of the tree search structure represents the initial mapping scheme.

5. The method according to claim 1, characterized in that Before calculating the evaluation function values ​​of all the initial mapping schemes according to the evaluation function of the mapping scheme to determine the target mapping scheme, the method further includes: The distance of each operation of inserting a SWAP gate is calculated by the following cost function: Where D represents the cost function, d represents the distance of each SWAP gate, g represents the quantum logic gate that needs to be inserted into the SWAP gate, F represents the quantum logic gate set, and π l+1 For the mapping scheme π l The sub-terms of l The updated mapping scheme obtained after inserting the SWAP gate, and They represent the two quantum bits that need to be inserted into the SWAP gate.

6. The method according to any one of claims 1 to 5, characterized in that: The step of calculating the evaluation function values ​​of all the initial mapping schemes according to the evaluation function of the mapping scheme to determine the target mapping scheme includes: The mapping scheme evaluation function is calculated by the following formula: Among them, l represents the depth index of the tree search structure, p represents the horizontal position index of the tree search structure, m represents the child node index in the tree search structure, and C l,p represents the evaluation function of the current mapping scheme, C l+1,m C l,p The child of G l,p In the mapping scheme π l，p The gain of the two-bit quantum logic gate under l，p In the mapping scheme π l，p The parallel parameter overhead of the two-bit quantum logic gate under l，p In the mapping scheme π l，p The number of parameters that need to be re-optimized in the quantum logic gate, β is the weight coefficient of the number of parameters that need to be re-optimized in the mapping scheme, γ is the sub-item weight coefficient of the current mapping scheme, and γ∈(0,1).

7. A device for determining a quantum program mapping scheme, characterized in that: The device comprises: A determination module, used to determine a set of quantum logic gates in a quantum program to be executed that cannot be directly executed on a quantum chip; A construction module, used to construct a tree search structure of SWAP gates and obtain an initial mapping scheme for all inserted SWAP gates in the quantum logic gate set; The calculation module is used to calculate the evaluation function values ​​of all the initial mapping schemes according to the evaluation function of the mapping scheme to determine the target mapping scheme, wherein the evaluation function value of the target mapping scheme is the largest.

8. The device according to claim 7, characterized in that The determining module comprises: An obtaining unit, used for obtaining a directed acyclic graph of a quantum program to be executed; A determination unit is used to determine all quantum logic gates in the directed acyclic graph that cannot be directly executed on the quantum chip according to the topological sequence of the directed acyclic graph and the execution timing of the quantum logic gates, and generate a set of quantum logic gates in the quantum program to be executed that cannot be directly executed on the quantum chip; wherein the quantum logic gates that cannot be directly executed on the quantum chip include two-bit quantum logic gates whose logical bits are not adjacent.

9. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to execute the method according to any one of claims 1 to 6 when executed.

10. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 6.

Images