Display device

Abstract

The present application relates to a display device including: a display panel including pixels and emission lines connected to the pixels; a transmission driver providing a transmission signal defining a transmission period and a non-transmission period to the transmission line; and a controller that determines a transmission cycle corresponding to the number of discontinuous transmission periods during the frame period and a transmission cut-off ratio that is a ratio of a sum of non-transmission periods to the frame period. Wherein an n-th frame period between an (n-1)-th frame period and an (n + 1)-th frame period in which the transmission cycles are different and the transmission cut-off ratios are equal includes first to m-th subframe periods in which the transmission cut-off ratios are different.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to display devices, and more particularly, to display devices with improved image quality. Background Art

[0002] The display device may display an image having different brightness for a frame period. The frame period may include at least one emission period, and a pixel included in the display device may emit light in the emission period.

[0003] Between adjacent frame periods, the emission cycle corresponding to the number of discontinuous emission periods during one frame period may change. When the emission cycle changes, a flash may occur in which the brightness of the image displayed by the display device increases or decreases instantaneously. When a flash occurs in the image, the image quality of the display device may deteriorate. Summary of the invention

[0004] Embodiments of the present disclosure provide a display device with improved image quality.

[0005] A display device according to an embodiment of the present disclosure includes: a display panel including pixels and emission lines connected to the pixels; and an emission driver providing an emission signal to the emission line. The emission signal defines discontinuous emission periods and non-emission periods during a frame period in a plurality of frame periods. The display device also includes a controller that determines an emission cycle corresponding to the number of discontinuous emission periods during the frame period and an emission cutoff ratio that is a ratio of the sum of non-emission periods to the frame period. The plurality of frame periods include an n-1th frame period, an n+1th frame period, and an nth frame period between the n-1th frame period and the n+1th frame period. The emission cycle of the n-1th frame period is different from the emission cycle of the n+1th frame period, the emission cutoff ratio of the n-1th frame period is equal to the emission cutoff ratio of the n+1th frame period, and the nth frame period includes a first subframe period to an mth subframe period having different emission cutoff ratios. Each of m and n is a positive integer greater than 1.

[0006] In an embodiment, when the emission cycle of the n+1th frame period is greater than the emission cycle of the n-1th frame period, the emission cutoff ratio of the first subframe period to the mth subframe period decreases from the first subframe period to the mth subframe period.

[0007] In an embodiment, the emission cutoff ratio of the first subframe period is greater than the emission cutoff ratio of the (n-1)th subframe period.

[0008] In an embodiment, when the emission cycle of the n+1th frame period is smaller than the emission cycle of the n-1th frame period, the emission cutoff ratio of the first subframe period to the mth subframe period increases from the first subframe period to the mth subframe period.

[0009] In an embodiment, the emission cutoff ratio of the mth subframe period is greater than the emission cutoff ratio of the n+1th frame period.

[0010] In an embodiment, the transmission cycle of the nth frame period is equal to the transmission cycle of the frame period having a larger transmission cycle among the n-1th frame period and the n+1th frame period.

[0011] In an embodiment, the emission cycles of the first subframe period to the mth subframe period are different.

[0012] In an embodiment, when the transmission cycle of the (n+1)th frame period is greater than the transmission cycle of the (n-1)th frame period, the transmission cycle increases from the first subframe period to the mth subframe period.

[0013] In an embodiment, the emission cutoff ratio of the first subframe period is greater than the emission cutoff ratio of the (n-1)th subframe period.

[0014] In an embodiment, the emission cycle of the first subframe period is greater than the emission cycle of the (n-1)th frame period, and the emission cycle of the (m)th subframe period is less than the emission cycle of the (n+1)th frame period.

[0015] In an embodiment, when the emission cycle of the (n+1)th frame period is smaller than the emission cycle of the (n-1)th frame period, the emission cycles of the first subframe period to the mth subframe period decrease from the first subframe period to the mth subframe period.

[0016] In an embodiment, the emission cutoff ratio of the mth subframe period is greater than the emission cutoff ratio of the n+1th frame period.

[0017] In an embodiment, the emission cycle of the first subframe period is smaller than the emission cycle of the (n-1)th frame period, and the emission cycle of the (m)th subframe period is larger than the emission cycle of the (n+1)th frame period.

[0018] In an embodiment, the transmission cycle of the nth frame period is between the transmission cycle of the (n-1)th frame period and the transmission cycle of the (n+1)th frame period.

[0019] In an embodiment, the transmission cycle of one of the n-1th frame period and the n+1th frame period is 1, and the transmission cycle of the other of the n-1th frame period and the n+1th frame period may be 12, 16, 24 or 32.

[0020] In an embodiment, the brightness of the (n-1)th frame period and the brightness of the (n+1)th frame period are equal.

[0021] A display device according to an embodiment of the present disclosure includes: a display panel including pixels and emission lines connected to the pixels; and an emission driver providing an emission signal to the emission line. The emission signal defines discontinuous emission periods and non-emission periods during a frame period in a plurality of frame periods. The display device also includes a controller that determines an emission cycle corresponding to the number of discontinuous emission periods during the frame period and an emission cutoff ratio that is a ratio of the sum of the non-emission periods to the frame period. The first frame period has a first emission cycle, a second frame period adjacent to the first frame period has a second emission cycle that is larger than the first emission cycle, and the length of the non-emission period of the first frame period is equal to the length of the non-emission period of the second frame period.

[0022] In an embodiment, the first frame period has a first emission cutoff ratio as a minimum emission cutoff ratio, and the second frame period has a second emission cutoff ratio greater than the first emission cutoff ratio.

[0023] In an embodiment, a magnitude of a data voltage of a first frame period is smaller than a magnitude of a data voltage of a second frame period.

[0024] In an embodiment, the first transmission cycle is 1 and the second transmission cycle is 12, 16, 24 or 32.

[0025] In a display device according to an embodiment of the present disclosure, when the emission cycle changes between adjacent frame periods, a buffer frame period including subframe periods with different emission cutoff ratios may be inserted between adjacent frame periods, or the lengths of non-emission periods of adjacent frame periods may be equal. Therefore, although the difference in the emission cycle between adjacent frame periods is large, the flash of the image displayed by the display device may not occur. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0027] Figure 1 is a block diagram showing a display device according to an embodiment.

[0028] Figure 2 It is shown that the Figure 1 Circuit diagram of a pixel in a display device in FIG.

[0029] Figure 3 It shows the direction Figure 2 Timing diagram of the signals provided by the pixel.

[0030] Figure 4 It is shown that the Figure 1 Block diagram of the brightness controller in the controller.

[0031] Figure 5 is a diagram used to describe a data dimming scheme.

[0032] Figure 6 is a diagram used to describe the pulse width modulation (PWM) dimming scheme.

[0033] Figure 7 and Figure 8 is a diagram for describing a change in an emission cycle according to a comparative example.

[0034] Fig. 9 and Fig.10 is a diagram for describing a change of an emission cycle according to an embodiment.

[0035] Fig.11 and Fig.12 is a diagram for describing a change of an emission cycle according to an embodiment.

[0036] Fig.13 and Fig.14 is a diagram for describing a change of an emission cycle according to an embodiment.

[0037] Fig.15 is a block diagram showing an electronic device according to an embodiment. DETAILED DESCRIPTION

[0038] Hereinafter, a display device according to an embodiment of the present disclosure will be described in more detail with reference to the accompanying drawings. Throughout the accompanying drawings, the same reference numerals may represent the same elements.

[0039] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another, and the elements are not limited by these terms. Therefore, a "first" element in an embodiment may be described as a "second" element in another embodiment.

[0040] It should be understood that descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, unless the context clearly dictates otherwise.

[0041] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0042] In this article, when two or more elements or values ​​are described as being substantially the same as each other or approximately equal to each other, it should be understood that elements or values ​​are identical to each other, elements or values ​​are equal to each other within measurement error or if measurably unequal, then as understood by those of ordinary skill in the art, sufficiently close to the values ​​functionally equal to each other. For example, in view of the measurement discussed and the error (for example, the limitation of the measurement system) related to the measurement of a specific amount, the term "about" as used herein includes the value and means within the acceptable deviation range of the specific value as determined by those of ordinary skill in the art. For example, "about" can mean within one or more standard deviations as understood by those of ordinary skill in the art. In addition, it should be understood that although a parameter can be described as having "about" a certain value in this article, according to an embodiment, a parameter can be exactly this certain value or approximately this certain value within the measurement error as understood by those of ordinary skill in the art.

[0043] Figure 1 is a block diagram showing a display device 100 according to an embodiment.

[0044] refer to Figure 1 The display device 100 may include a display panel 110, a gate driver 120 (also referred to as a gate driver circuit), a data driver 130 (also referred to as a data driver circuit), an emission driver 140 (also referred to as an emission driver circuit), and a controller 150 (also referred to as a controller circuit).

[0045] The display panel 110 may include a plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of emission lines EML.

[0046] The pixels PX may include pixels emitting light of a plurality of colors. In an embodiment, the pixels PX may include a red pixel emitting red light, a green pixel emitting green light, and a blue pixel emitting blue light.

[0047] The gate line GL may be connected to the pixel PX. The gate line GL may extend in a first direction D1 and be arranged in a second direction D2 crossing the first direction D1. The gate line GL may provide a gate signal GS to the pixel PX.

[0048] The data lines DL may be connected to the pixels PX. The data lines DL may extend in the second direction D2 and be arranged in the first direction D1. The data lines DL may provide a data voltage VDAT to the pixels PX.

[0049] The emission lines EML may be connected to the pixels PX. The emission lines EML may extend in the first direction D1 and be arranged in the second direction D2. The emission lines EML may provide emission signals EM to the pixels PX.

[0050] The gate driver 120 may provide a gate signal GS to the gate line GL. The gate driver 120 may generate the gate signal GS based on the first control signal CNT1. The first control signal CNT1 may include, for example, a gate start signal, a gate clock signal, and the like.

[0051] The data driver 130 may provide a data voltage VDAT to the data line DL. The data driver 130 may generate the data voltage VDAT based on the output image data IMD2 and the second control signal CNT2. The output image data IMD2 may include an output grayscale value corresponding to the pixel PX. The second control signal CNT2 may include, for example, a load signal, a data clock signal, etc.

[0052] The emission driver 140 may provide an emission signal EM to the emission line EML. The emission driver 140 may generate the emission signal EM based on the third control signal CNT3. The third control signal CNT3 may include, for example, an emission start signal, an emission clock signal, and the like.

[0053] The controller 150 may control the operation (or driving) of the gate driver 120, the operation (or driving) of the data driver 130, and the operation (or driving) of the emission driver 140. The controller 150 may receive input image data IMD1 and a control signal CNT from a host (e.g., a processor). The input image data IMD1 may include an input grayscale value corresponding to the pixel PX. The control signal CNT may include, for example, a clock signal, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, etc. The controller 150 may provide a first control signal CNT1 to the gate driver 120, provide output image data IMD2 and a second control signal CNT2 to the data driver 130, and provide a third control signal CNT3 to the emission driver 140. The controller 150 may generate a first control signal CNT1, a second control signal CNT2, and a third control signal CNT3 based on the control signal CNT, and generate output image data IMD2 based on the input image data IMD1.

[0054] Figure 2 It is shown that the Figure 1 1 is a circuit diagram of a pixel PX in a display device 100 in FIG.

[0055] refer to Figure 2 , the pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST and a light emitting diode LE. The gate signal ( Figure 1GS) may include a first gate signal GW (or a write gate signal), a second gate signal GC (or a compensation gate signal), a third gate signal GI (or an initialization gate signal) and a fourth gate signal GB (or a bypass gate signal).

[0056] The first transistor T1 may include a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The first transistor T1 may be referred to as a driving transistor.

[0057] The second transistor T2 may include a gate electrode receiving the first gate signal GW, a first electrode receiving the data voltage VDAT, and a second electrode connected to the second node N2. The second transistor T2 may be referred to as a write transistor.

[0058] The third transistor T3 may include a gate electrode receiving the second gate signal GC, a first electrode connected to the third node N3, and a second electrode connected to the first node N1. The third transistor T3 may be referred to as a compensation transistor.

[0059] The fourth transistor T4 may include a gate electrode receiving the third gate signal GI, a first electrode receiving the first initialization voltage VINT, and a second electrode connected to the first node N1. The fourth transistor T4 may be referred to as an initialization transistor.

[0060] The fifth transistor T5 may include a gate electrode receiving the emission signal EM, a first electrode receiving the first power voltage ELVDD, and a second electrode connected to the second node N2. The fifth transistor T5 may be referred to as a first light emitting transistor.

[0061] The sixth transistor T6 may include a gate electrode receiving the emission signal EM, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The sixth transistor T6 may be referred to as a second light emitting transistor.

[0062] The seventh transistor T7 may include a gate electrode receiving the fourth gate signal GB, a first electrode receiving the second initialization voltage VAINT, and a second electrode connected to the fourth node N4. The seventh transistor T7 may be referred to as a bypass transistor.

[0063] Figure 2An embodiment in which each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 is a P-type transistor (e.g., a PMOS transistor) is shown, but the present disclosure is not limited thereto. For example, in an embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be an N-type transistor (e.g., an NMOS transistor).

[0064] The storage capacitor CST may include a first electrode connected to the first node N1 and a second electrode receiving the first power voltage ELVDD.

[0065] Figure 2 The pixel PX is shown to include seven transistors T1, T2, T3, T4, T5, T6 and T7 and one capacitor CST, but the present disclosure is not limited thereto. For example, in an embodiment, the pixel PX may include 2 to 6 transistors, 8 or more transistors and / or 2 or more capacitors.

[0066] The light emitting diode LE may include a first electrode (or anode) connected to the fourth node N4 and a second electrode (or cathode) receiving the second power voltage ELVSS. In an embodiment, the light emitting diode LE may be an organic light emitting diode. In an embodiment, the light emitting diode LE may be, for example, an inorganic light emitting diode, a quantum dot light emitting diode, or a micro light emitting diode.

[0067] Figure 3 It shows the direction Figure 2 A timing diagram of the signals provided by the pixel PX.

[0068] refer to Figure 2 and Figure 3 , wherein a frame period FRM of one frame of a displayed image may include at least one non-emission period PNE and at least one emission period PE. The non-emission period PNE may be defined by a cut-off voltage (e.g., a logic high voltage) of an emission signal EM, and the emission period PE may be defined by a turn-on voltage (e.g., a logic low voltage) of the emission signal EM.

[0069] In an embodiment, the light emitting diode LE does not emit light in the non-emission period PNE. The non-emission period PNE may include a first period P1 (or initialization period), a second period P2 (or compensation and writing period), and a third period P3 (or bypass period).

[0070] In the first period P1, the fourth transistor T4 may be turned on in response to the turn-on voltage of the third gate signal GI, and the first initialization voltage VINT may be applied to the first node N1. Therefore, the first node N1 may be initialized.

[0071] In the second period P2, the third transistor T3 may be turned on in response to the turn-on voltage of the second gate signal GC, and the first transistor T1 may be diode-connected. In addition, the second transistor T2 may be turned on in response to the turn-on voltage of the first gate signal GW, and the data voltage VDAT compensating for the threshold voltage of the first transistor T1 may be applied to the first node N1. Therefore, the data voltage VDAT compensating for the threshold voltage of the first transistor T1 may be written to the first node N1.

[0072] In the third period P3, the seventh transistor T7 may be turned on in response to the turn-on voltage of the fourth gate signal GB, and the second initialization voltage VAINT may be applied to the fourth node N4. Therefore, the fourth node N4 may be initialized.

[0073] The light emitting diode LE may emit light in the emission period PE. The fifth transistor T5 and the sixth transistor T6 may be turned on in response to the turn-on voltage of the emission signal EM in the emission period PE, and a current path of the driving current generated in the first transistor T1 may be formed from the first power voltage ELVDD to the second power voltage ELVSS. Therefore, the light emitting diode LE may emit light having a brightness corresponding to the driving current.

[0074] Figure 4 It is shown that the Figure 1 150 in the controller 152.

[0075] refer to Figure 1 and Figure 4 , the brightness controller 152 may determine the brightness LUM of the image based on the input grayscale value of the input image data IMD1 and the dimming level DBV, and determine the emission cutoff ratio AOR and the emission cycle CYC based on the brightness LUM of the image.

[0076] The brightness LUM of the image may be determined based on the dimming level DBV. The dimming level DBV may be set by a user or by detecting the ambient illumination. For example, the brightness controller 152 may receive the dimming level DBV from the host.

[0077] The emission cutoff ratio AOR may be the ratio of the sum of the non-emission periods to one frame period. For example, the emission cutoff ratio AOR may be obtained by dividing the sum of the non-emission periods PNE by the period including the non-emission period ( Figure 3 PNE in) and the emission period ( Figure 3The frame period of PE in Figure 3 The value obtained by using the FRM in .

[0078] The transmission cycle CYC may correspond to the number of discontinuous transmission periods during one frame period. For example, the transmission cycle CYC may correspond to the number of discontinuous transmission periods during the frame period FRM by the transmission signal ( Figure 3 The number of pulses is defined by the falling edge, the on-state voltage and the rising edge of the EM).

[0079] The controller 150 may generate an emission start signal included in the third control signal CNT3 based on the emission off ratio AOR and the emission cycle CYC, and the emission driver 140 may generate an emission signal EM based on the third control signal CNT3.

[0080] Figure 5 is a diagram used to describe a data dimming scheme.

[0081] refer to Figure 4 and Figure 5 , when the brightness LUM of the image is included in the first brightness range (or high brightness range), the brightness controller 152 can control the brightness LUM by changing the data voltage VDAT while maintaining the emission cutoff ratio AOR constant. Controlling the brightness LUM by changing the data voltage VDAT while maintaining the emission cutoff ratio AOR constant can be called a data dimming scheme. When the brightness LUM is included in the first brightness range, the emission cycle CYC can be 1. In an embodiment, the emission cutoff ratio AOR can be the minimum emission cutoff ratio. For example, the minimum emission cutoff ratio can be 1%. For example, the first brightness range can be about 500 nits to about 110 nits.

[0082] When the image has the first brightness LUM1 included in the first brightness range in the first frame period FRM1, the brightness controller 152 may set the data voltage VDAT to the first data voltage VDAT1 while maintaining the emission cutoff ratio AOR at the minimum emission cutoff ratio in the first frame period FRM1.

[0083] When the image has a second brightness LUM2 included in the first brightness range and lower than the first brightness LUM1 in the second frame period FRM2, the brightness controller 152 may set the data voltage VDAT to the second data voltage VDAT2 while maintaining the emission cutoff ratio AOR at the minimum emission cutoff ratio in the second frame period FRM2. The magnitude of the second data voltage VDAT2 may be smaller than the magnitude of the first data voltage VDAT1. Therefore, the second brightness LUM2 of the image in the second frame period FRM2 may be lower than the first brightness LUM1 of the image in the first frame period FRM1.

[0084] Figure 6 is a diagram used to describe the pulse width modulation (PWM) dimming scheme.

[0085] refer to Figure 4 and Figure 6 , when the brightness LUM of the image is included in the second brightness range (or medium brightness range) or the third brightness range (or low brightness range), the brightness controller 152 can control the brightness LUM by changing the emission cutoff ratio AOR while maintaining the data voltage VDAT constant. Controlling the brightness LUM by changing the emission cutoff ratio AOR while maintaining the data voltage VDAT constant can be called a PWM dimming scheme. When the brightness LUM is included in the second brightness range, the emission cycle CYC can be 1. For example, the second brightness range can be from about 110 nits to about 80 nits, and the third brightness range can be from about 80 nits to about 0 nits.

[0086] When the image has a third brightness LUM3 included in the second brightness range in the third frame period FRM3, and the image has a fourth brightness LUM4 included in the second brightness range and lower than the third brightness LUM3 in the fourth frame period FRM4, the brightness controller 152 may increase the emission cutoff ratio AOR while maintaining the data voltage VDAT at the third data voltage VDAT3 of the third frame period FRM3 in the fourth frame period FRM4. In other words, the brightness controller 152 may increase the length of the non-emission period PNE in the fourth frame period FRM4. Therefore, the emission cutoff ratio AOR (or the length of the non-emission period PNE) in the fourth frame period FRM4 may be greater than the emission cutoff ratio AOR (or the length of the non-emission period PNE) in the third frame period FRM3. Therefore, the fourth brightness LUM4 of the image in the fourth frame period FRM4 may be lower than the third brightness LUM3 of the image in the third frame period FRM3.

[0087] When the image has a fifth brightness LUM5 included in the third brightness range and lower than the fourth brightness LUM4 in the fifth frame period FRM5, the brightness controller 152 may increase the emission cutoff ratio AOR while maintaining the data voltage VDAT at the third data voltage VDAT3 in the fifth frame period FRM5. In other words, the brightness controller 152 may increase the sum of the lengths of the non-emission periods PNE in the fifth frame period FRM5. In addition, the brightness controller 152 may increase the emission cycle CYC in the fifth frame period FRM5. When the brightness LUM is included in the third brightness range, the emission cycle CYC may be greater than 1. Therefore, the emission cutoff ratio AOR (or the sum of the lengths of the non-emission periods PNE) in the fifth frame period FRM5 may be greater than the emission cutoff ratio AOR (or the length of the non-emission period PNE) in the fourth frame period FRM4, and the emission cycle CYC in the fifth frame period FRM5 may be greater than the emission cycle CYC in the fourth frame period FRM4. Therefore, the fifth brightness LUM5 of the image in the fifth frame period FRM5 may be lower than the fourth brightness LUM4 of the image in the fourth frame period FRM4. Furthermore, in the fifth frame period FRM5 in which an image having a fifth brightness LUM5 included in the third brightness range as a low brightness range is displayed, the emission cycle CYC may be increased, and flicker may be prevented from being recognized in the low brightness image.

[0088] Figure 7 and Figure 8 is a diagram for describing changes in the emission cycle CYC according to the comparative example.

[0089] refer to Figure 7 and Figure 8 In the comparative example, when the emission cycle CYC changes between the n-1th (n is a positive integer greater than 1) frame period FRMn-1 and the nth frame period FRMn, the emission cutoff ratio AOR of the n-1th frame period FRMn-1 and the emission cutoff ratio AOR of the nth frame period FRMn may be equal, and the emission cycle CYC of the n-1th frame period FRMn-1 and the emission cycle CYC of the nth frame period FRMn may be different. For example, the emission cutoff ratio AOR of the n-1th frame period FRMn-1 and the emission cutoff ratio AOR of the nth frame period FRMn may be 12%. In addition, the brightness LUMn-1 of the n-1th frame period FRMn-1 and the brightness LUMn of the nth frame period FRMn may be equal. For example, the brightness LUMn-1 of the n-1th frame period FRMn-1 and the brightness LUMn of the nth frame period FRMn may be approximately 80 nits.

[0090] like Figure 7As shown in , when the emission cycle CYC increases from 1 to 12 between the n-1 frame period FRMn-1 and the n-th frame period FRMn, there may be a frame corresponding period FRM' corresponding to the length of one frame period and including an emission period having a sum of lengths greater than the sum of the lengths of the emission periods of the n-1 frame period FRMn or the length of the emission period of the n-1 frame period FRMn-1, and the brightness LUM_H of the frame corresponding period FRM' may be higher than the brightness LUMn-1 of the n-1 frame period FRMn-1 and the brightness LUMn of the n-1 frame period FRMn. For example, the brightness LUM_H of the frame corresponding period FRM' may be approximately 81 nits. In this case, a flash corresponding to an increase in the brightness of the image may occur between the n-1 frame period FRMn-1 and the n-th frame period FRMn.

[0091] like Figure 8 As shown in , when the emission cycle CYC decreases from 12 to 1 between the n-1 frame period FRMn-1 and the n-th frame period FRMn, there may be a frame corresponding period FRM' corresponding to the length of one frame period and including an emission period whose sum of lengths is smaller than the sum of the lengths of the emission periods of the n-1 frame period FRMn-1 or the length of the emission period of the n-th frame period FRMn, and the brightness LUM_H of the frame corresponding period FRM' may be lower than the brightness LUMn-1 of the n-1 frame period FRMn-1 and the brightness LUMn of the n-th frame period FRMn. For example, the brightness LUM_H of the frame corresponding period FRM' may be about 79 nits. In this case, a flash corresponding to the decrease in brightness may occur between the n-1 frame period FRMn-1 and the n-th frame period FRMn.

[0092] Fig. 9 and Fig.10 is a diagram for describing changes in the emission cycle CYC according to an embodiment.

[0093] refer to Fig. 9 and Fig.10 , when the transmission cycle CYC changes between the n-1th frame period FRMn-1 and the n+1th frame period FRMn+1, the transmission cycle CYC of one of the n-1th frame period FRMn-1 and the n+1th frame period FRMn+1 may be 1, and the transmission cycle CYC of the other of the n-1th frame period FRMn-1 and the n+1th frame period FRMn+1 may be 12, 16, 24 or 32. Fig. 9 and Fig.10, an embodiment in which the emission cycle CYC of the frame period having a larger emission cycle CYC in the n-1th frame period FRMn-1 and the n+1th frame period FRMn+1 is 12 is shown, but the present disclosure is not limited thereto. For example, in an embodiment, the emission cycle CYC of the frame period having a larger emission cycle CYC in the n-1th frame period FRMn-1 and the n+1th frame period FRMn+1 may be 16, 24, or 32.

[0094] The nth frame period FRMn (or buffer frame period) between the n-1th frame period FRMn-1 and the n+1th frame period FRMn+1, in which the emission cycles CYC are different and the emission cutoff ratio AOR is equal, may include the first subframe period to the mth subframe period (m is a positive integer greater than 1) with different emission cutoff ratios AOR. For example, the emission cutoff ratio AOR of the n-1th frame period FRMn-1 and the emission cutoff ratio AOR of the n+1th frame period FRMn+1 may be 12%. In addition, the brightness LUMn-1 of the n-1th frame period FRMn-1 and the brightness LUMn+1 of the n+1th frame period FRMn+1 may be equal. For example, the brightness LUMn-1 of the n-1th frame period FRMn-1 and the brightness LUMn+1 of the n+1th frame period FRMn+1 may be approximately 80 nits.

[0095] The emission cycle CYC of the nth frame period FRMn may be equal to the emission cycle CYC of the frame period having a larger emission cycle CYC among the n-1th frame period FRMn-1 and the n+1th frame period FRMn+1. For example, the emission cycle CYC of the nth frame period FRMn may be 12.

[0096] In an embodiment, the nth frame period FRMn may include three sub-frame periods SFM1, SFM2, and SFM3. However, the present disclosure is not limited thereto. For example, in an embodiment, the nth frame period FRMn may include two or four or more sub-frame periods.

[0097] like Fig. 9As shown in , when the emission cycle CYC of the n+1th frame period FRMn+1 is greater than the emission cycle CYC of the n-1th frame period FRMn-1, the emission cutoff ratio AOR may be reduced from the first subframe period to the mth subframe period. For example, the emission cutoff ratio AOR of the second subframe period SFM2 may be less than the emission cutoff ratio AOR of the first subframe period SFM1, and the emission cutoff ratio AOR of the third subframe period SFM3 may be less than the emission cutoff ratio AOR of the second subframe period SFM2. In an embodiment, the emission cutoff ratio AOR of the first subframe period may be greater than the emission cutoff ratio AOR of the n-1th frame period FRMn-1. In addition, the emission cutoff ratio AOR of the mth subframe period may be less than the emission cutoff ratio AOR of the n+1th frame period FRMn+1. For example, the emission cutoff ratio AOR of the first subframe period SFM1 may be 23%, the emission cutoff ratio AOR of the second subframe period SFM2 may be 19%, and the emission cutoff ratio AOR of the third subframe period SFM3 may be 10%.

[0098] like Fig.10 As shown in , when the emission cycle CYC of the n+1th frame period FRMn+1 is less than the emission cycle CYC of the n-1th frame period FRMn-1, the emission cutoff ratio AOR may increase from the first subframe period to the mth subframe period. For example, the emission cutoff ratio AOR of the second subframe period SFM2 may be greater than the emission cutoff ratio AOR of the first subframe period SFM1, and the emission cutoff ratio AOR of the third subframe period SFM3 may be greater than the emission cutoff ratio AOR of the second subframe period SFM2. In an embodiment, the emission cutoff ratio AOR of the mth subframe period may be greater than the emission cutoff ratio AOR of the n+1th frame period FRMn+1. In addition, the emission cutoff ratio AOR of the first subframe period may be less than the emission cutoff ratio AOR of the n-1th frame period FRMn-1. For example, the emission cutoff ratio AOR of the first subframe period SFM1 may be 10%, the emission cutoff ratio AOR of the second subframe period SFM2 may be 19%, and the emission cutoff ratio AOR of the third subframe period SFM3 may be 23%.

[0099] In an embodiment, when the emission cycle CYC changes between the n-1th frame period FRMn-1 and the n+1th frame period FRMn+1, a buffer frame period FRMn including subframe periods having different emission cutoff ratios AOR may be inserted between the n-1th frame period FRMn-1 and the n+1th frame period FRMn+1. As a result, it is possible to prevent flashes from occurring when the emission cycle CYC changes.

[0100] Fig.11 and Fig.12 is a diagram for describing changes in the emission cycle CYC according to an embodiment.

[0101] For the sake of convenience, the reference Fig. 9 and Fig.10 The emission cycle CYC described herein is substantially the same as or similar to the reference Fig.11 and Fig.12 Description of the changes in the emission cycle CYC.

[0102] refer to Fig.11 and Fig.12 , the emission cutoff ratios AOR from the first subframe period to the mth subframe period may be different, and the emission cycles CYC from the first subframe period to the mth subframe period may be different. The emission cycle CYC of the nth frame period FRMn may be between the emission cycle CYC of the n-1th frame period FRMn-1 and the emission cycle CYC of the n+1th frame period FRMn+1. For example, the emission cycle CYC of the nth frame period FRMn may be greater than 1 and less than 12.

[0103] like Fig.11 As shown in , when the emission cycle CYC of the n+1th frame period FRMn+1 is greater than the emission cycle CYC of the n-1th frame period FRMn-1, the emission cutoff ratio AOR may decrease from the first subframe period to the mth subframe period, and the emission cycle CYC may increase from the first subframe period to the mth subframe period. For example, the emission cycle CYC of the second subframe period SFM2 may be greater than the emission cycle CYC of the first subframe period SFM1, and the emission cycle CYC of the third subframe period SFM3 may be greater than the emission cycle CYC of the second subframe period SFM2. The emission cycle CYC of the subframe period may be a value obtained by multiplying the number of discontinuous emission time periods included in the subframe period by the number of subframe periods included in the nth frame period FRMn. In an embodiment, the emission cutoff ratio AOR of the first subframe period may be greater than the emission cutoff ratio AOR of the n-1th frame period FRMn-1, and the emission cutoff ratio AOR of the mth subframe period may be less than the emission cutoff ratio AOR of the n+1th frame period FRMn+1. In addition, the emission cycle CYC of the first subframe period may be greater than the emission cycle CYC of the n-1th frame period FRMn-1, and the emission cycle CYC of the mth subframe period may be less than the emission cycle CYC of the n+1th frame period FRMn+1. For example, the emission cutoff ratio AOR of the first subframe period SFM1 may be 30%, the emission cutoff ratio AOR of the second subframe period SFM2 may be 11%, and the emission cutoff ratio AOR of the third subframe period SFM3 may be 10%. In addition, the emission cycle CYC of the first subframe period SFM1 may be 3, the emission cycle CYC of the second subframe period SFM2 may be 6, and the emission cycle CYC of the third subframe period SFM3 may be 9.

[0104] like Fig.12 As shown in , when the emission cycle CYC of the n+1th frame period FRMn+1 is less than the emission cycle CYC of the n-1th frame period FRMn-1, the emission cutoff ratio AOR may increase from the first subframe period to the mth subframe period, and the emission cycle CYC may decrease from the first subframe period to the mth subframe period. For example, the emission cycle CYC of the second subframe period SFM2 may be less than the emission cycle CYC of the first subframe period SFM1, and the emission cycle CYC of the third subframe period SFM3 may be less than the emission cycle CYC of the second subframe period SFM2. In an embodiment, the emission cutoff ratio AOR of the first subframe period may be less than the emission cutoff ratio AOR of the n-1th frame period FRMn-1, and the emission cutoff ratio AOR of the mth subframe period may be greater than the emission cutoff ratio AOR of the n+1th frame period FRMn+1. In addition, the emission cycle CYC of the first subframe period may be less than the emission cycle CYC of the n-1th frame period FRMn-1, and the emission cycle CYC of the mth subframe period may be greater than the emission cycle CYC of the n+1th frame period FRMn+1. For example, the emission cutoff ratio AOR of the first subframe period SFM1 may be 10%, the emission cutoff ratio AOR of the second subframe period SFM2 may be 11%, and the emission cutoff ratio AOR of the third subframe period SFM3 may be 30%. In addition, the emission cycle CYC of the first subframe period SFM1 may be 9, the emission cycle CYC of the second subframe period SFM2 may be 6, and the emission cycle CYC of the third subframe period SFM3 may be 3.

[0105] In an embodiment, when the emission cycle CYC changes between the n-1th frame period FRMn-1 and the n+1th frame period FRMn+1, a buffer frame period FRMn including sub-frame periods having different emission cutoff ratios AOR and different emission cycles CYC may be inserted between the n-1th frame period FRMn-1 and the n+1th frame period FRMn+1. As a result, it is possible to prevent flashes from occurring when the emission cycle CYC changes.

[0106] Fig.13 and Fig.14 is a diagram for describing changes in the emission cycle CYC according to an embodiment.

[0107] refer to Fig.13 and Fig.14, when the emission cycle CYC changes between the n-1th frame period FRMn-1 and the nth frame period FRMn, the emission cycle CYC of one of the n-1th frame period FRMn-1 and the nth frame period FRMn may be 1, and the emission cycle CYC of the other of the n-1th frame period FRMn-1 and the nth frame period FRMn may be 12, 16, 24 or 32. Fig.13 and Fig.14 An embodiment in which the emission cycle CYC of the frame period having a larger emission cycle CYC in the n-1th frame period FRMn-1 and the n-th frame period FRMn is 12 is shown, but the present disclosure is not limited thereto. For example, in an embodiment, the emission cycle CYC of the frame period having a larger emission cycle CYC in the n-1th frame period FRMn-1 and the n-th frame period FRMn may be 16, 24, or 32. In addition, the brightness LUMn-1 of the n-1th frame period FRMn-1 and the brightness LUMn of the n-th frame period FRMn may be equal. For example, the brightness LUMn-1 of the n-1th frame period FRMn-1 and the brightness LUMn of the n-th frame period FRMn may be approximately 80 nits.

[0108] The length of the non-emission period PNE of the first frame period (one of the n-1th frame period FRMn-1 and the nth frame period FRMn) can be basically equal to the length of the non-emission period PNE of the second frame period (the other of the n-1th frame period FRMn-1 and the nth frame period FRMn) adjacent to the first frame period. Fig.13 It is shown that the first frame period and the second frame period are respectively the n-1th frame period FRMn-1 and the nth frame period FRMn, and Fig.14 It is shown that the first frame period and the second frame period are the nth frame period FRMn and the n-1th frame period FRMn-1, respectively.

[0109] The first frame period may have a first emission cycle and a first emission cutoff ratio, and the second frame period may have a second emission cycle greater than the first emission cycle and a second emission cutoff ratio greater than the first emission cutoff ratio. The first emission cutoff ratio may be a minimum emission cutoff ratio.

[0110] like Fig.13As shown in, when the emission cycle CYC of the n-th frame period FRMn is greater than the emission cycle CYC of the n-1-th frame period FRMn-1, the emission cutoff ratio AOR of the n-1-th frame period FRMn-1 may be the minimum emission cutoff ratio, and the size of the data voltage VDATn-1 of the n-1-th frame period FRMn-1 may be less than the size of the data voltage VDATn of the n-1-th frame period FRMn. For example, the emission cutoff ratio AOR of the n-1-th frame period FRMn-1 may be 1%, and the emission cutoff ratio AOR of the n-1-th frame period FRMn may be 12%.

[0111] like Fig.14 As shown in, when the emission cycle CYC of the n-th frame period FRMn is less than the emission cycle CYC of the n-1-th frame period FRMn-1, the emission cutoff ratio AOR of the n-th frame period FRMn may be the minimum emission cutoff ratio, and the size of the data voltage VDATn of the n-th frame period FRMn may be less than the size of the data voltage VDATn-1 of the n-1-th frame period FRMn-1. For example, the emission cutoff ratio AOR of the n-1-th frame period FRMn-1 may be 12%, and the emission cutoff ratio AOR of the n-th frame period FRMn may be 1%.

[0112] In an embodiment, when the emission cycle CYC changes between the n-1th frame period FRMn-1 and the n-th frame period FRMn, the length of a non-emission period PNE of the n-1th frame period FRMn-1 and the length of a non-emission period PNE of the n-1th frame period FRMn may be substantially equal, and the length of the non-emission period PNE of the n-1th frame period FRMn-1 and the length of the non-emission period PNE of the n-1th frame period FRMn-1 may be substantially equal. As a result, it is possible to prevent flashes from occurring when the emission cycle CYC changes.

[0113] Fig.15 is a block diagram showing an electronic device 1000 according to an embodiment.

[0114] refer to Fig.15 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output ("I / O") device 1040, a power supply 1050, and a display device 1060. The display device 1060 may correspond to Figure 1 The electronic device 1000 also includes a plurality of ports for communicating with, for example, a graphics card, a sound card, a memory card, a universal serial bus ("USB") device, and the like.

[0115] Processor 1010 may perform calculations or tasks. In embodiments, processor 1010 may be, for example, a microprocessor, a central processing unit ("CPU"), etc. Processor 1010 may be coupled to other components via, for example, an address bus, a control bus, a data bus, etc. In embodiments, processor 1010 may be coupled to an expansion bus such as a peripheral component interconnect ("PCI") bus. In embodiments, processor 1010 may provide input image data (e.g., Figure 1 IMD1 in the Figure 1 CNT in ).

[0116] The memory device 1020 may store data used for the operation of the electronic device 1000. In an embodiment, the memory device 1020 may include a non-volatile memory device such as, for example, an erasable programmable read-only memory ("EPROM") device, an electrically erasable programmable read-only memory ("EEPROM") device, a flash memory device, a phase change random access memory ("PRAM") device, a resistive random access memory ("RRAM") device, a nano floating gate memory ("NFGM") device, a polymer random access memory ("PoRAM") device, a magnetic random access memory ("MRAM") device, a ferroelectric random access memory ("FRAM") device, etc. and / or a volatile memory device such as, for example, a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a mobile DRAM device, etc.

[0117] The storage device 1030 may include, for example, a solid state drive ("SSD") device, a hard disk drive ("HDD") device, a CD-ROM device, etc. The I / O device 1040 may include an input device such as, for example, a keyboard, a key, a touch pad, a touch screen, a mouse device, etc. and an output device such as, for example, a speaker, a printer, etc. The power supply 1050 may supply power for the operation of the electronic device 1000. The display device 1060 may be coupled to other components via a bus or other communication links.

[0118] The display device according to the embodiment of the present disclosure may be applied to a display device included in, for example, a computer, a notebook computer, a mobile phone, a smart phone, a smart tablet, a smart watch, a PMP, a PDA, an MP3 player, etc.

[0119] As is customary in the field of the present disclosure, embodiments are described and illustrated in the accompanying drawings for functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electrical circuits (or optical circuits) such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connectors, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and they can be selectively driven by firmware and / or software. Optionally, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions.

[0120] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. A display device, comprising: A display panel including pixels and emission lines connected to the pixels; an emission driver that provides an emission signal to the emission line, wherein the emission signal defines a discontinuous emission period and a non-emission period during a frame period in a plurality of frame periods; and a controller that determines a transmission cycle corresponding to the number of the discontinuous transmission periods during the frame period and a transmission cutoff ratio that is a ratio of the sum of the non-transmission periods to the frame period, The plurality of frame periods include an n-1th frame period, an n+1th frame period, and an nth frame period between the n-1th frame period and the n+1th frame period, wherein the emission cycle of the n-1th frame period is different from the emission cycle of the n+1th frame period, the emission cutoff ratio of the n-1th frame period is equal to the emission cutoff ratio of the n+1th frame period, and the nth frame period includes a first subframe period to an mth subframe period having different emission cutoff ratios, Here, each of m and n is a positive integer greater than 1.

2. The display device according to claim 1, wherein: When the emission cycle of the n+1th frame period is greater than the emission cycle of the n-1th frame period, the emission cutoff ratio of the first subframe period to the mth subframe period decreases from the first subframe period to the mth subframe period.

3. The display device according to claim 2, wherein: The emission cutoff ratio of the first subframe period is greater than the emission cutoff ratio of the n-1th frame period.

4. The display device according to claim 1, wherein: When the emission cycle of the n+1th frame period is smaller than the emission cycle of the n-1th frame period, the emission cutoff ratio of the first subframe period to the mth subframe period increases from the first subframe period to the mth subframe period.

5. The display device according to claim 4, wherein: The emission cutoff ratio of the mth subframe period is greater than the emission cutoff ratio of the n+1th frame period.

6. The display device according to claim 1, wherein: The transmission cycle of the nth frame period is equal to the transmission cycle of the frame period having a larger transmission cycle among the n-1th frame period and the n+1th frame period.

7. The display device according to claim 1, wherein: The transmission cycles from the first subframe period to the mth subframe period are different.

8. The display device according to claim 7, wherein: When the emission cycle of the n+1th frame period is greater than the emission cycle of the n-1th frame period, the emission cycles of the first subframe period to the mth subframe period increase from the first subframe period to the mth subframe period.

9. The display device according to claim 8, wherein: The emission cutoff ratio of the first subframe period is greater than the emission cutoff ratio of the n-1th frame period.

10. The display device according to claim 8, wherein: The transmission cycle of the first subframe period is greater than the transmission cycle of the n-1th frame period, and The transmission cycle of the m-th subframe period is smaller than the transmission cycle of the n+1-th frame period.

11. The display device according to claim 7, wherein: When the emission cycle of the n+1th frame period is smaller than the emission cycle of the n-1th frame period, the emission cycles of the first subframe period to the mth subframe period decrease from the first subframe period to the mth subframe period.

12. The display device according to claim 11, wherein: The emission cutoff ratio of the mth subframe period is greater than the emission cutoff ratio of the n+1th frame period.

13. The display device according to claim 11, wherein: The transmission cycle of the first subframe period is smaller than the transmission cycle of the n-1th frame period, and The transmission cycle of the mth subframe period is greater than the transmission cycle of the n+1th frame period.

14. The display device according to claim 7, wherein: The transmission cycle of the nth frame period is between the transmission cycle of the n-1th frame period and the transmission cycle of the n+1th frame period.

15. The display device according to claim 1, wherein: The transmission cycle of one of the n-1th frame period and the n+1th frame period is 1, and The transmission cycle of the other of the n-1th frame period and the n+1th frame period is 12, 16, 24 or 32.

16. The display device according to claim 1, wherein: The brightness of the n-1th frame period is equal to that of the n+1th frame period.

17. A display device comprising: A display panel including pixels and emission lines connected to the pixels; an emission driver that provides an emission signal to the emission line, wherein the emission signal defines a discontinuous emission period and a non-emission period during a frame period in a plurality of frame periods; and a controller that determines a transmission cycle corresponding to the number of the discontinuous transmission periods during the frame period and a transmission cutoff ratio that is a ratio of the sum of the non-transmission periods to the frame period, Wherein, the first frame period has a first transmission cycle, A second frame period adjacent to the first frame period has a second emission cycle greater than the first emission cycle, and The length of the non-emission period of the first frame cycle is equal to the length of the non-emission period of the second frame cycle.

18. The display device according to claim 17, wherein: The first frame period has a first emission cutoff ratio as a minimum emission cutoff ratio, and The second frame period has a second emission cutoff ratio that is greater than the first emission cutoff ratio.

19. The display device according to claim 18, wherein: The magnitude of the data voltage in the first frame period is smaller than the magnitude of the data voltage in the second frame period.

20. The display device according to claim 17, wherein: The first transmission cycle is 1, and The second transmission cycle is 12, 16, 24 or 32.

Images