Display panel

Abstract

The display panel provided by the present application is provided with a plurality of pixel modules arranged in an array in the display area, and the pixel modules include a first driving layer, a second driving layer and a light-emitting device layer, the first driving layer includes a plurality of first transistors; the second driving layer includes a plurality of grayscale data signal storage units, which are used to store the grayscale data signal transmitted by the bit line based on the first control signal transmitted by the word line and output the grayscale data signal to the first transistor; the anode of the light-emitting device in the light-emitting device layer is electrically connected to the first node, and the cathode of the light-emitting device is electrically connected to the second power supply terminal of the display panel; the plurality of grayscale data signal storage units provided in the second driving layer can replace the static random access memory circuit composed of a plurality of transistors provided in the non-display area, so that the non-display area of ​​the display panel does not need to be provided with a data storage circuit, thereby realizing a narrow frame of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] A silicon-based display panel is a special display panel based on silicon semiconductor technology that forms a large field of view through optical magnification. A silicon-based display panel usually includes a driving circuit and a light-emitting device. The light-emitting materials of micro light-emitting diodes (Micro-LED) or organic light-emitting diodes (OLED) can be grown on a silicon substrate to make a silicon-based display panel. Silicon-based display panels can be used in near-eye display devices and virtual display devices.

[0003] Currently, digital subfield scanning technology is often used to drive the light-emitting devices of silicon-based display panels. Figure 1 As shown, taking a full grayscale of 256 levels (L0 to L255) as an example, digital subfield scanning technology involves dividing a single frame display cycle H1 of a silicon-based display panel into eight subfields (F1 to F8). Each subfield includes a data writing phase t1 and a light-emitting phase t2. By setting different weights for each subfield, the duration of the light-emitting phase t2 is controlled to be different, thereby controlling the lighting duration of the light-emitting device in each subfield. Full grayscale display of the light-emitting device is then achieved by superimposing the grayscale values ​​of all subfields. Using digital subfield scanning technology to achieve 256-level grayscale display requires storing 8 bits of binary display data for each light-emitting device. This requires a data buffer circuit to be provided in the non-display area of ​​the silicon-based display panel to store image data consisting of at least 8 bits of binary display data.

[0004] However, the data buffer circuit needs to occupy the non-display area of ​​the driving backplane of the display panel, so that the frame of the display panel is larger, affecting the overall module size of the display panel. Summary of the Invention

[0005] The present application provides a display panel that solves the problem of increasing the display panel frame due to the provision of a data buffer circuit.

[0006] The present application provides a display panel having a display area and a non-display area surrounding the display area. The display area is provided with a plurality of pixel modules arranged in an array. Along the thickness direction of the display panel, the pixel modules include:

[0007] a first driving layer, the first driving layer comprising a plurality of first transistors, sources of the plurality of first transistors being electrically connected to a driving current terminal of the first driving layer, drains of the plurality of first transistors being electrically connected to a first node, the first transistors being configured to provide a driving current from the driving current terminal to the first node based on a grayscale data signal;

[0008] a second driving layer, the second driving layer being located on a surface of the first driving layer, the second driving layer comprising a plurality of grayscale data signal storage units, the plurality of grayscale data signal storage units corresponding one-to-one to and electrically connected to the gates of the plurality of first transistors, the plurality of grayscale data signal storage units being electrically connected to the same word line of the display panel, the plurality of grayscale data signal storage units corresponding one-to-one to and electrically connected to the plurality of bit lines of the display panel, the plurality of grayscale data signal storage units being electrically connected to a first power supply terminal of the display panel, the grayscale data signal storage units being configured to store the grayscale data signals transmitted by the bit lines based on a first control signal transmitted by the word lines and output the grayscale data signals to the first transistors, wherein each of the grayscale data signal storage units comprises a second transistor and a capacitor, the drain of the second transistor being electrically connected to the gate of the first transistor and the first plate of the capacitor, the gate of the second transistor being electrically connected to the word line, the source of the second transistor being electrically connected to the bit line, and the second substrate of the capacitor being electrically connected to the first power supply terminal;

[0009] A light-emitting device layer, wherein the light-emitting device layer is located on a surface of the second driving layer away from the first driving layer, the light-emitting device layer includes at least one light-emitting device, the anode of at least one light-emitting device is electrically connected to the first node, and the cathode of at least one light-emitting device is electrically connected to the second power supply terminal of the display panel, wherein the first node is a node of the circuit between the drain of the first transistor and the light-emitting device.

[0010] In the display panel provided in the present application, the first driving layer also includes a driving current regulating unit, which is electrically connected to the first power supply terminal and the reference voltage terminal of the display panel. The driving current regulating unit is also electrically connected to the driving current terminal. The driving current regulating unit is used to provide the driving current to the first transistor based on a third control signal provided by the reference voltage terminal.

[0011] In the display panel provided in the present application, the first driving layer also includes a plurality of third transistors, the sources of the plurality of third transistors correspond one-to-one to the drains of the plurality of first transistors and are electrically connected, the drains of the plurality of third transistors are electrically connected to the first node, and the gates of the plurality of third transistors correspond one-to-one to the plurality of pulse width modulation signal control terminals of the display panel and are electrically connected, and the third transistors are used to output the driving current provided by the first transistor to the light-emitting device in a time-sharing manner based on the second control signal provided by the pulse width modulation signal control terminal.

[0012] In the display panel provided in the present application, the pixel module includes at least 8 first transistors and at least 8 grayscale data signal storage units, the sources of at least 8 first transistors are electrically connected to the driving current end, the drains of at least 8 first transistors are electrically connected to the first node, the gates of at least 8 first transistors correspond one-to-one to and are electrically connected to the drains of at least 8 second transistors, the drains of at least 8 second transistors correspond one-to-one to and are electrically connected to the first plates of at least 8 capacitors, the gates of at least 8 second transistors are electrically connected to the same word line, the sources of at least 8 second transistors correspond one-to-one to and are electrically connected to at least 8 bit lines, and the second plates of at least 8 capacitors are electrically connected to the first power supply end.

[0013] In the display panel provided in the present application, the pixel modules in the same row are electrically connected to the same word line, multiple rows of pixel modules correspond one-to-one and are electrically connected to multiple word lines, and the starting time points of the pixel modules in two adjacent rows receiving the effective level of the first control signal differ by a preset time length.

[0014] In the display panel provided in the present application, the second transistor is a metal oxide thin film transistor.

[0015] In the display panel provided in the present application, along the thickness direction of the display panel, the second driving layer includes:

[0016] a first source-drain layer, the first source-drain layer being disposed on a surface of the first driving layer, the first source-drain layer comprising a first sub-source portion of the second transistor and a first sub-drain portion of the second transistor being insulated;

[0017] a second source-drain layer, the second source-drain layer being disposed on a side of the first source-drain layer away from the first driving layer, the second source-drain layer comprising a second sub-source portion of the second transistor and a second sub-drain portion of the second transistor that are insulated, the second sub-source portion being connected to the first sub-source portion, and the second sub-drain portion being connected to the first sub-drain portion;

[0018] a metal oxide semiconductor layer, the metal oxide semiconductor layer being disposed between the first source-drain electrode layer and the second source-drain electrode layer, the metal oxide semiconductor layer including a metal oxide semiconductor portion of the second transistor;

[0019] A gate layer, wherein the gate layer is arranged between the first source-drain layer and the second source-drain layer, and the gate layer is insulated from the metal oxide semiconductor layer, the gate layer includes a gate portion of the second transistor, and an orthographic projection of the gate portion on the first driving layer coincides with an orthographic projection of a channel portion of the metal oxide semiconductor portion on the first driving layer.

[0020] In the display panel provided in the present application, the second driving layer further includes a first insulating layer, a second insulating layer and a third insulating layer;

[0021] The first insulating layer is provided on the surface of the first sub-source portion and the first sub-drain portion away from the first driving layer, and covers the first driving layer;

[0022] The metal oxide semiconductor portion is provided on a surface of the first insulating layer away from the first driving layer;

[0023] The second insulating layer is provided on a surface of the metal oxide semiconductor portion away from the first driving layer and covers the first insulating layer;

[0024] The gate portion is provided on a surface of the second insulating layer away from the first driving layer;

[0025] The third insulating layer is provided on a surface of the gate portion away from the first driving layer and covers the second insulating layer;

[0026] The second sub-source portion and the second sub-drain portion are arranged on the surface of the third insulating layer away from the first driving layer, the second sub-source portion is connected to the first sub-source portion through the third insulating layer, the second insulating layer and the first insulating layer, the second sub-source portion is connected to the source contact portion of the metal oxide semiconductor portion through the third insulating layer and the second insulating layer, the second sub-drain portion is connected to the first sub-drain portion through the third insulating layer, the second insulating layer and the first insulating layer, and the second sub-drain portion is connected to the drain contact portion of the metal oxide semiconductor portion through the third insulating layer and the second insulating layer.

[0027] In the display panel provided in the present application, the second driving layer further includes a first insulating layer and a second insulating layer;

[0028] The first insulating layer is provided on the surface of the first sub-source portion and the first sub-drain portion away from the first driving layer, and covers the first driving layer;

[0029] The gate portion is provided on a surface of the first insulating layer away from the first driving layer;

[0030] The second insulating layer is provided on a surface of the gate portion away from the first driving layer and covers the first insulating layer;

[0031] The metal oxide semiconductor portion is provided on a surface of the second insulating layer away from the first driving layer;

[0032] The second sub-source portion is at least partially disposed on a surface of the metal oxide semiconductor portion where the source contact portion is away from the first driving layer, and the second sub-source portion is connected to the first sub-source portion via the second insulating layer and the first insulating layer. The second sub-drain portion is at least partially disposed on a surface of the metal oxide semiconductor portion where the drain contact portion is away from the first driving layer, and the second sub-drain portion is connected to the first sub-drain portion via the second insulating layer and the first insulating layer.

[0033] In the display panel provided in the present application, the second driving layer further includes an interlayer dielectric layer, the interlayer dielectric layer being provided on a surface of the second source / drain electrode layer away from the first driving layer and covering the first driving layer;

[0034] The second driving layer also includes a bonding hole and a bonding metal part. The bonding hole passes through the second driving layer through the interlayer dielectric layer to expose a portion of the first driving layer. The bonding metal part is located in the bonding hole. The bonding metal part connects the first driving layer and the light-emitting device respectively.

[0035] The display panel provided by the present application adds a second driving layer between the first driving layer and the light-emitting device layer of the pixel module, and sets multiple grayscale data signal storage units in the second driving layer, and any grayscale data signal storage unit includes a second transistor and a capacitor. The second transistors of the multiple grayscale data signal storage units read the grayscale data signals transmitted by the multiple bit lines respectively, and then the capacitors of the multiple grayscale data signal storage units store the grayscale data signals read by the second transistors. Therefore, the multiple grayscale data signal storage units composed of the multiple second transistors and the multiple capacitors arranged in the display area can replace the static random access memory circuit composed of the multiple transistors arranged in the non-display area, so that the non-display area of ​​the display panel does not need to be provided with a data storage circuit, thereby realizing a narrow frame of the display panel; in addition, compared with the static random access memory circuit composed of multiple transistors, the dynamic random access memory circuit composed of the second transistor and the capacitor can significantly reduce the area occupied by the pixel module in the display area of ​​the display panel, and the display panel can achieve a higher pixel density. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of sub-field segmentation corresponding to 256 grayscale levels in the related art;

[0037] Figure 2 A schematic diagram of the structure of a display panel in the related art;

[0038] Figure 3 A schematic diagram of a data cache circuit in the related art;

[0039] Figure 4 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0040] Figure 5 A first schematic diagram of a cross section of a pixel module provided in an embodiment of the present application;

[0041] Figure 6 for Figure 5 A schematic diagram of a circuit of a pixel module is shown;

[0042] Figure 7 for Figure 6 A schematic diagram of the timing of controlling the luminous duration of the sub-field corresponding to the circuit shown;

[0043] Figure 8 for Figure 6 A schematic diagram of the timing of the circuit performing rolling scanning is shown;

[0044] Figure 9 A schematic diagram of a display panel processing display image data provided by an embodiment of the present application;

[0045] Figure 10A second schematic diagram of a cross section of a pixel module provided in an embodiment of the present application;

[0046] Figure 11 A schematic diagram of the steps of a method for preparing a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. The described embodiments are only used to explain the ideas created by the present invention and should not be regarded as limiting the scope of protection of this application.

[0048] Silicon-based display panels can not only realize active addressing of light-emitting devices, but also can prepare circuits including pixel circuits, timing control circuits (TCON), gate driver circuits (GOA), source driver circuits (Source driver), power circuits (Power), overcurrent protection circuits, etc. on silicon-based substrates through semiconductor manufacturing processes, which is conducive to reducing the system volume of the display panel and achieving lightweight display panels.

[0049] like Figure 2 As shown, in the related art, a silicon-based display panel may include a driving backplane 601 and a light-emitting layer 602. The silicon-based display panel has a display area AA and a non-display area NA. The light-emitting layer 602 is provided on one side of the driving backplane 601, and the light-emitting layer 602 is provided in the display area AA. The light-emitting layer 602 includes a plurality of light-emitting devices, and the plurality of light-emitting devices are provided corresponding to the display area AA. The driving layer ( Figure 2 The backplane 601 includes a driving circuit for driving the light-emitting device to emit light, and the driving circuit is correspondingly arranged in the display area AA. The timing control circuit, gate driving circuit, source driving circuit and other circuits are arranged in the non-display area NA of the driving backplane 601.

[0050] like Figure 1 as well as Figure 2 As shown, to increase the brightness of the light-emitting devices displaying the maximum grayscale value L255, the gate driver circuit outputs a scan signal to the display area AA to scan each row of light-emitting devices. Each row of light-emitting devices can immediately emit light after the addressing scan time has elapsed. Each light-emitting device can continuously emit light during each light-emitting phase T2 within the display cycle H1 of a complete display frame. Therefore, a data buffer circuit (frame buffer) capable of storing 8-bit binary image data is required in the non-display area NA of the driver backplane 601.

[0051] like Figure 3As shown, the data cache circuit 610 storing 1-bit binary data in the related art includes a grayscale data receiving unit 611 and a grayscale data storage unit 612, that is, the data cache circuit 610 includes a circuit architecture of a 1-bit binary static random-access memory (SRAM).

[0052] The grayscale data receiving unit 611 is electrically connected to the scan signal terminal Scan of the driving backplane 601, the grayscale data signal terminal Data of the driving backplane 601, and the grayscale data storage unit 612. The grayscale data receiving unit 611 is configured to output a grayscale data signal provided by the grayscale data signal terminal Data to the grayscale data storage unit 612 based on a scan signal provided by the scan signal terminal Scan.

[0053] The grayscale data receiving unit 611 includes a first transistor T1 and a second transistor T2 , and the grayscale data signal terminal Data includes a first sub-grayscale data signal terminal Data1 and a second sub-grayscale data signal terminal Data2 .

[0054] The gate of the first transistor T1 is electrically connected to the scan signal terminal Scan, one of the source and drain of the first transistor T1 is electrically connected to the first sub-grayscale data signal terminal Data1, and the other of the source and drain of the first transistor T1 is electrically connected to the grayscale data storage unit 612. After receiving the scan signal that turns on the first transistor T1, the gate of the first transistor T1 outputs the grayscale data signal provided by the first sub-grayscale data signal terminal Data1 to the grayscale data storage unit 612.

[0055] The gate of the second transistor T2 is electrically connected to the scan signal terminal Scan, one of the source and drain of the second transistor T2 is electrically connected to the second sub-grayscale data signal terminal Data2, and the other of the source and drain of the second transistor T2 is electrically connected to the grayscale data storage unit 612. After receiving the scan signal that turns on the second transistor T2, the gate of the second transistor T2 outputs the grayscale data signal provided by the second sub-grayscale data signal terminal Data2 to the grayscale data storage unit 012.

[0056] When the scan driving unit in the gate driving circuit addresses the light emitting devices L in the current row row by row, the first transistor T1 and the second transistor T2 read the grayscale data signal in the source driving circuit and provide the grayscale data signal to the grayscale data signal terminal Data.

[0057] The grayscale data storage unit 612 is electrically connected to the light control unit 621, the first power terminal VDD of the driving backplane 601, and the second power terminal VSS of the driving backplane 601. The grayscale data storage unit 612 is used to store grayscale data signals and output the grayscale data signals to the light control unit 621.

[0058] The grayscale data storage unit 612 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The gate of the third transistor T3 is electrically connected to the first grayscale data receiving unit 611, one of the source and drain of the third transistor T3 is electrically connected to one of the source and drain of the fifth transistor T5, and the other of the source and drain of the third transistor T3 is electrically connected to the second power supply terminal VSS. The gate of the fifth transistor T5 is electrically connected to the gate of the third transistor T3, and the other of the source and drain of the fifth transistor T5 is electrically connected to the first power supply terminal VDD. One of the third transistor T3 and the fifth transistor T5 is an N-type transistor, and the other of the third transistor T3 and the fifth transistor T5 is a P-type transistor. The third transistor T3 and the fifth transistor T5 are electrically connected to form an inverter.

[0059] The gate of the fourth transistor T4 is electrically connected to the first grayscale data receiving unit 611. One of the source and drain of the fourth transistor T4 is electrically connected to one of the source and drain of the sixth transistor T6. The other of the source and drain of the fourth transistor T4 is electrically connected to the second power supply terminal VSS. One of the source and drain of the fourth transistor T4 is also electrically connected to the gate of the third transistor T3. The gate of the fourth transistor T4 is also electrically connected to one of the source and drain of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the gate of the fourth transistor T4. The other of the source and drain of the sixth transistor T6 is electrically connected to the first power supply terminal VDD. One of the fourth transistor T4 and the sixth transistor T6 is an N-type transistor, and the other of the fourth transistor T4 and the sixth transistor T6 is a P-type transistor. The fourth transistor T4 and the sixth transistor T6 are electrically connected to form another inverter.

[0060] Based on the cross-coupling of two inverters consisting of the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 to form a bistable trigger, when the scan driving unit in the gate driving circuit addresses the light-emitting device L in the current row row by row, the first transistor T1 and the second transistor T2 provide the grayscale data signal in the source driving circuit to the grayscale data signal terminal Data, and then store the grayscale data signal in the bistable trigger, that is, store the grayscale data signal in the grayscale data storage unit 612, so that the data cache circuit 610 can realize the reading and storage of the grayscale data signal.

[0061] The light-emitting control unit 621 is also electrically connected to the grayscale data storage unit 612 and the light-emitting device L. The light-emitting control unit 621 is configured to provide a driving current to the light-emitting device L based on the grayscale data signal and the first power signal, thereby driving the light-emitting device L to emit light. The light-emitting control unit 621 may include a seventh transistor T7, the gate of which is electrically connected to the grayscale data storage unit 612, one of the source and drain of the seventh transistor T7 is electrically connected to the driving current adjustment unit 622, and the other of the source and drain of the seventh transistor T7 is electrically connected to the anode of the light-emitting device L. The grayscale data signal provided by the grayscale data storage unit 612 controls the on / off state of the seventh transistor T7, thereby controlling the lighting and extinguishing of the light-emitting device L.

[0062] The driving current regulating unit 622 is electrically connected to the first power supply terminal VDD, the light emitting control unit 621, and the reference voltage terminal of the driver backplane 601. The driving current regulating unit 622 is configured to output a first power signal from the first power supply terminal VDD to the light emitting control unit 621 based on a reference voltage signal provided by the reference voltage terminal. The driving current regulating unit 622 includes an eighth transistor T8, wherein the gate of the eighth transistor T8 is electrically connected to the reference voltage terminal, one of the source and drain of the eighth transistor T8 is electrically connected to the first power supply terminal VDD, and the other of the source and drain of the eighth transistor T8 is electrically connected to the light emitting control unit 621.

[0063] The reference voltage terminal is electrically connected to a current mirror unit 623 via a reference signal line Iref line. The current mirror unit 623 is also electrically connected to a first power supply terminal VDD and a second power supply terminal VSS. The current mirror unit 623 is configured to adjust the magnitude of the reference voltage signal at the reference voltage terminal. The current mirror unit 623 includes a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11, and a current source i.

[0064] The gate of the ninth transistor T9 is electrically connected to the reference voltage terminal and one of the source and drain of the ninth transistor T9. One of the source and drain of the ninth transistor T9 is also electrically connected to one of the source and drain of the tenth transistor T10. The other of the source and drain of the ninth transistor T9 is electrically connected to the first power supply terminal VDD. The ninth transistor T9 and the eighth transistor T8 are both N-type transistors, or the ninth transistor T9 and the eighth transistor T8 are both P-type transistors.

[0065] The gate of the tenth transistor T10 is electrically connected to the gate of the eleventh transistor T11. One of the source and drain of the tenth transistor T10 is electrically connected to one of the source and drain of the ninth transistor T9. The other of the source and drain of the tenth transistor T10 is electrically connected to the second power supply terminal VSS. One of the source and drain of the eleventh transistor T11 is electrically connected to the second power supply terminal VSS. The other of the source and drain of the eleventh transistor T11 is electrically connected to the gate of the eleventh transistor T11. The other of the source and drain of the eleventh transistor T11 is also electrically connected to the current source i. The tenth transistor T10 and the eleventh transistor T11 are both N-type transistors, or the tenth transistor T10 and the eleventh transistor T11 are both P-type transistors. Based on the fact that the greater the reference voltage supplied by the current mirror unit 023 to the reference voltage terminal, the greater the current flowing through the light-emitting device L, and the greater the brightness of the light-emitting device L, the brightness of the light-emitting device L can be adjusted by changing the reference voltage signal size of the reference voltage terminal.

[0066] However, in order to enable each light-emitting device L to display at least 256 levels of grayscale, it is necessary to integrate 8-bit binary data of each light-emitting device L into the driver backplane 601, that is, the driver backplane 601 needs to store at least 8-bit binary frame buffer data of the display image in the non-display area NA. The data cache circuit uses a bit plane to store the processed display image data. The size of the display image data stored in the data cache circuit is at least the product of the number of light-emitting devices and the color depth, so that the border of the display panel with the driver backplane 601 is larger, thereby affecting the overall size of the display panel, which is not conducive to the narrow border of the display panel.

[0067] On the other hand, in related art, after video source data provided by an external device is input into the display panel, the display panel must first perform image scaling and gamma correction on the video source data to obtain processed display image data, and then transmit the processed display image data to the data buffer circuit for storage. In order to write the image data corresponding to each light-emitting device to the corresponding light-emitting device driver circuit in the display area AA, it is necessary to divide the display period H1 of each frame of display image data into at least eight subfields to read the display image data from the data buffer circuit and write the display image data to each light-emitting device driver circuit in the display area AA. The above-mentioned display image data processing is relatively cumbersome, and the power consumption required to drive the backplane 601 to read and write data is relatively high.

[0068] In view of the above problems existing in the related art, the present application provides a display panel, such as Figure 4 As shown, the display panel 100 has a display area AA and a non-display area NA surrounding the display area AA. The display area AA is provided with a plurality of pixel modules 10 arranged in an array.

[0069] like Figure 5 As shown, along the thickness direction of the display panel 100 , the pixel module 10 sequentially includes a first driving layer 11 , a second driving layer 12 and a light emitting device layer 13 .

[0070] A plurality of first transistors are located in the first driving layer 11. The first driving layer 11 includes a silicon substrate 1101 and a CMOS device circuit layer 1102 disposed on a surface of the silicon substrate 1101.

[0071] The silicon substrate 1101 includes multiple well regions 11011, each of which has two doped regions 11011a spaced apart. A CMOS device circuit layer 1102 is formed on the silicon substrate 1101 using a semiconductor process and includes multiple transistors in both the display area AA and the non-display area NA.

[0072] Along the thickness direction of the display panel 100 , the CMOS device circuit layer 1102 at least includes a gate wiring layer 11021 and a source / drain wiring layer 11022 .

[0073] Take a well region 11011 in the display area AA corresponding to a first transistor as an example for explanation: the orthographic projection of the gate portion 11021a in the gate wiring layer 11021 on the silicon substrate 1101 is located between the two doped regions 11011a, and the source portion ( Figure 5 not shown) and the drain portion ( Figure 5 The two doped regions 11011a of the same well region 11011 are respectively connected (not shown), thereby forming a first transistor through the well region 11011 and the gate portion 11021a, source portion, and drain portion corresponding to the well region 11011. On this basis, the CMOS device circuit layer 1102 may further include other metal wiring layers, and the transistors are connected through each wiring layer to form a driving circuit in the first driving layer 11. The specific connection lines and wiring patterns in the driving circuit can be determined according to actual needs and are not specifically limited in this embodiment.

[0074] In the first driving layer 11 corresponding to the non-display area NA of the display panel 100, as shown in FIG. Figure 4 As shown, it also includes circuits such as a timing control circuit (TCON), a gate drive circuit (GOA), a source drive circuit (Source driver), a power circuit (Power), and an overcurrent protection circuit.

[0075] The second driving layer 12 is located on the surface of the first driving layer 11 , that is, the second driving layer 12 is located on the surface of the CMOS device circuit layer 1102 away from the silicon substrate 1101 .

[0076] Multiple grayscale data signal storage units are located in the second driving layer 12. The multiple grayscale data signal storage units correspond one-to-one with and are electrically connected to the gates of the multiple first transistors. The multiple grayscale data signal storage units are electrically connected to the same word line of the display panel 100. The multiple grayscale data signal storage units correspond one-to-one with and are electrically connected to multiple bit lines of the display panel 100. The multiple grayscale data signal storage units are electrically connected to a first power terminal of the display panel 100. The grayscale data signal storage units are configured to store grayscale data signals transmitted by corresponding bit lines based on first control signals transmitted by the word lines and output the grayscale data signals to corresponding first transistors.

[0077] The light emitting device layer 13 is located on a surface of the second driving layer 12 away from the first driving layer 11. At least one light emitting device L is located in the light emitting device layer 13, and the light emitting device L may be a micro light emitting diode or an organic light emitting diode.

[0078] like Figure 6 As shown, in a pixel module 10, the sources of the plurality of first transistors T1 are electrically connected to the driving current terminal of the first driving layer 11, the drains of the plurality of first transistors T1 are electrically connected to the first node S, and the gates of the plurality of first transistors T1 correspond one-to-one to and are electrically connected to the drains of the plurality of second transistors T2. The first transistors T1 are configured to output the driving current from the driving current terminal to the first node S based on the grayscale data signal provided by the second transistors T2.

[0079] In the second driving layer 12 of a pixel module 10, each grayscale data signal storage unit 121 includes at least a second transistor T2 and a capacitor Cst. The gates of the plurality of second transistors T2 are electrically connected to the same word line WL of the display panel 100, and the sources of the plurality of second transistors T2 are electrically connected to the plurality of bit lines BL ( Figure 6 The first plates of the plurality of capacitors Cst correspond one-to-one to the gates of the plurality of first transistors T1 and are electrically connected. The second transistor T2 is used to output the grayscale data signal transmitted by the bit line BL to the gate of the first transistor T1 based on the first control signal transmitted by the word line WL. The first plates of the plurality of capacitors Cst correspond one-to-one to the gates of the plurality of first transistors T1 and are electrically connected. The second plates of the plurality of capacitors Cst are electrically connected to the first power supply terminal VDD of the display panel 100, and the capacitor Cst is used to store the voltage at the gate of the first transistor T1. In other words, a second transistor T2 and a capacitor Cst constitute a circuit of a dynamic random access memory (DRAM) having one transistor and one storage capacitor (1T1C), that is, the grayscale data signal storage unit 121 has the function of a dynamic random access memory.

[0080] The anode of the light-emitting device L is electrically connected to the first node S, and the cathode of the light-emitting device L is electrically connected to the second power supply terminal VSS of the display panel 100. A pixel module 10 may include one light-emitting device L or multiple light-emitting devices L. When a pixel module 10 includes multiple light-emitting devices L, the multiple light-emitting devices L may be connected in parallel, in series, or a mixture of series and parallel.

[0081] The first node S refers to a node between the drain of the first transistor T1 and the anode of the light emitting device L.

[0082] In the display panel 100 provided in this embodiment, a second driving layer 12 is added between the first driving layer 11 and the light-emitting device layer 13 of the pixel module 10, and multiple grayscale data signal storage units 121 are provided in the second driving layer 12. Each grayscale data signal storage unit 121 includes a second transistor T2 and a capacitor Cst. The second transistors T2 of the multiple grayscale data signal storage units 121 read grayscale data signals respectively transmitted by the multiple bit lines BL, and the capacitors Cst of the multiple grayscale data signal storage units 121 then store the grayscale data signals read by the second transistors T2. Therefore, the grayscale data signal storage units 121 composed of the second transistors T2 provided in the display area AA can replace the static random access memory circuit composed of at least six transistors provided in the non-display area NA in the related art. Therefore, the display panel 100 of this embodiment does not need to provide a data storage circuit composed of a static random access memory circuit in the non-display area NA, saving space for providing a data cache circuit in the non-display area NA, which is conducive to achieving a narrow frame of the display panel 100. On the other hand, compared to a static random access memory circuit composed of multiple transistors, the display panel 100 provided in this embodiment, which is composed of a dynamic random access memory circuit based on the second transistor T2 and the capacitor Cst, can significantly reduce the area occupied by the pixel module 10 in the display area AA of the display panel 100, and the display panel 100 can achieve a higher pixel density (Pixels Per Inch, PPI).

[0083] In some embodiments provided herein, the second transistor T2 is a metal oxide thin film transistor (MOST). Because the second transistor T2 is a MOST, which has low leakage current and low-frequency drive characteristics, the 1T1C DRAM circuit consisting of the second transistor T2 and the capacitor Cst requires a low refresh rate. Compared to an SRAM circuit that requires at least six transistors, this embodiment, by placing the 1T1C DRAM circuit in the display area AA of the display panel 100, can significantly reduce the area of ​​the display area AA occupied by a single pixel module 10. This eliminates the need for the wafer fab to use high-precision processes to prepare the first drive layer 11, allowing the display panel 100 to achieve a higher pixel density.

[0084] like Figure 6 As shown, in a pixel module 10, the first driving layer 11 further includes a driving current regulating unit 112. The driving current regulating unit 112 is electrically connected to the first power supply terminal VDD and the reference voltage terminal V_bias of the display panel 100. The driving current regulating unit 112 is also electrically connected to the driving current terminal. The driving current regulating unit 112 is configured to provide a constant driving current to the plurality of first transistors T1 based on a third control signal provided by the reference voltage terminal V_bias.

[0085] The reference voltage terminal V_bias can be electrically connected to the current mirror unit via the reference signal line Iref line, and the current mirror unit is used to adjust the magnitude of the reference voltage signal of the reference voltage terminal V_bias. Figure 3 The specific circuit architecture of the current mirror unit 023 is shown.

[0086] The driving current regulating unit 112 includes a fourth transistor T4 having a gate electrically connected to the reference voltage terminal V_bias, a source electrically connected to the first power terminal VDD, and a drain electrically connected to the sources of the plurality of first transistors T1.

[0087] like Figure 6 As shown, in a pixel module 10, the first driving layer 11 further includes a plurality of third transistors T3, the sources of the plurality of third transistors T3 correspond one-to-one to the drains of the plurality of first transistors T1 and are electrically connected, the drains of the plurality of third transistors T3 are electrically connected to the first node S, and the gates of the plurality of third transistors T3 are electrically connected to the plurality of pulse width modulation signal control terminals PWM ( Figure 6 The third transistor T3 is used to output the driving current provided by the first transistor T1 to the light-emitting device L in a time-sharing manner based on the second control signal provided by the pulse width modulation signal control terminal PWM. In other words, the third transistor T3 is a transistor for controlling the light-emitting duration of the light-emitting device L.

[0088] like Figure 6 as well as Figure 7As shown, for a pixel module 10 including m+1 first transistors T1, m+1 second transistors T2, and m+1 third transistors T3, the first pulse width modulation signal control terminal PWM_0 to the m+1th pulse width modulation signal control terminal PWM_m sequentially control the on and off states of the corresponding third transistors T3. The duration of the second control signal provided by the first pulse width modulation signal control terminal PWM_0 to the m+1th pulse width modulation signal control terminal PWM_m to turn on the third transistor T3 is different. For example, the duration of the second control signal provided by the first pulse width modulation signal control terminal PWM_0 to turn on the third transistor T3 is T*2 0 , then the duration of the second control signal of the second pulse width modulation signal control terminal PWM_1 to turn on the third transistor T3 is T*2 1 Similarly, the duration of the second control signal of the mth pulse width modulation signal control terminal PWM_m-1 that turns on the third transistor T3 is T*2 (m-1) The duration of the second control signal of the m+1th pulse width modulation signal control terminal PWM_m that turns on the third transistor T3 is T*2 m .

[0089] The duration F1 of one frame display period of the display panel 100 is the duration 1H, T*2 of the word line WL controlling the second transistor T2 to be turned on. 0 To T*2 m and a blank time.

[0090] To enable the light-emitting device L of the pixel module 10 to display at least 256 grayscale levels, at least 8 bits of data must be integrated within the pixel module 10. Specifically, the pixel module 10 must include at least eight first transistors T1 and at least eight grayscale data signal storage units 121. The sources of the at least eight first transistors T1 are electrically connected to the driving current terminal, the drains of the at least eight first transistors T1 are electrically connected to the first node S, and the gates of the at least eight first transistors T1 correspond one-to-one with and are electrically connected to the drains of at least eight second transistors T2. The gates of the at least eight second transistors T2 are electrically connected to the same word line WL, and the sources of the at least eight second transistors T2 correspond one-to-one with and are electrically connected to at least eight bit lines BL. The first plates of at least eight capacitors correspond one-to-one with and are electrically connected to the gates of the at least eight first transistors T1, and the second plates of the at least eight capacitors are electrically connected to the first power supply terminal VDD. Consequently, the pixel module 10 includes at least an 8-bit 1T1C dynamic random access memory circuit. In this way, compared with the related art that requires a sufficiently large storage space to store repeatedly written and read display image data due to the data processing process, thereby increasing the driving power consumption and display delay of the display panel, the display panel 100 of this embodiment can directly write and store the display image data into the corresponding pixel module 10, without the display panel 100 providing additional storage space to store repeatedly written and read display image data, thereby saving the driving power consumption of the display panel 100.

[0091] like Figure 8 As shown, in the display area AA of the display panel 100, the same row of pixel modules 10 is electrically connected to the same word line WL. Multiple rows of pixel modules 10 correspond to and are electrically connected to the multiple word lines WL in a one-to-one manner. The difference between the start times when two adjacent rows of pixel modules 10 receive the active level of the first control signal is a predetermined time length h1. In other words, the image display data corresponding to the multiple rows of pixel modules 10 of the display panel 100 of this embodiment is sequentially read from the multiple word lines WL using a rolling scan method.

[0092] The effective level of the first control signal refers to the level of the first control signal that causes the second transistor T2 to be in a conducting state.

[0093] In this embodiment, the preset duration may be 1H of the duration of the effective level of the first control signal. Thus, the starting time point at which the word line WL_(n+1) of the n+1th row turns on the second transistor T2 in the pixel module 10 of the n+1th row is 1H later than the starting time point at which the word line WL_n of the nth row starts to turn on the second transistor T2 in the pixel module 10 of the nth row.

[0094] Similarly, the starting time point at which the first pulse width modulation signal control terminal PWM_0 to the m+1th pulse width modulation signal control terminal PWM_m of the n+1th row turn on the third transistor T3 in the pixel module 10 in the n+1th row is 1H later than the starting time point at which the first pulse width modulation signal control terminal PWM_0 to the m+1th pulse width modulation signal control terminal PWM_m of the nth row turn on the third transistor T3 in the pixel module 10 in the nth row.

[0095] Based on this, the shift scanning rate of two adjacent rows of pixel modules 10 is consistent with the rate at which each word line WL controls the corresponding row of pixel modules 10 to read the bit line BL and output grayscale data. Therefore, the display panel 100 not only does not need to set up a frame buffer circuit to cache the read display image data, but can also effectively avoid the display delay problem of the display panel 100.

[0096] like Figure 9 As shown, the display data stream provided by an external device sequentially passes through the display interface module, data input latch module, display algorithm module, line buffer module, source driver module, and pixel module to drive the corresponding light-emitting devices to emit light. In other words, the display panel 100 of this embodiment can simplify the data flow, eliminating the need for grayscale data to be written and read through the frame buffer circuit, thereby reducing driving power consumption.

[0097] like Figure 5 As shown, along the thickness direction of the display panel 100 , the second driving layer 12 includes a first source-drain electrode layer 121 , a second source-drain electrode layer 124 , a metal oxide semiconductor layer 122 and a gate layer 123 .

[0098] The first source-drain layer 121 is arranged on the surface of the first driving layer 11, and the first source-drain layer 121 includes a first sub-source portion 121S of the second transistor and a first sub-drain portion 121D of the second transistor that are insulated. The first sub-source portion 121S and the first sub-drain portion 121D are connected to the conductive portion 11023a in the first driving layer 11 to achieve electrical connection between the first sub-source portion 121S and the transistor in the first driving layer 11, so as to achieve electrical connection between the first sub-drain portion 121D and the transistor in the first driving layer 11.

[0099] The second source-drain layer 124 is arranged on a side of the first source-drain layer 121 away from the first driving layer 11, and the second source-drain layer 124 includes a second sub-source portion 124S of the second transistor and a second sub-drain portion 124D of the second transistor that are insulated. The second sub-source portion 124S is connected to the first sub-source portion 121S to form the source of the second transistor, and the second sub-drain portion 124D is connected to the first sub-drain portion 121D to form the drain of the second transistor.

[0100] The metal oxide semiconductor layer 122 is disposed between the first source / drain electrode layer 121 and the second source / drain electrode layer 124. The metal oxide semiconductor layer 122 includes a metal oxide semiconductor portion 1221 of the second transistor. The material of the metal oxide semiconductor layer 122 can be any one of indium zinc oxide (IZO), indium-tin-zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), zinc oxide (ZnO), tin oxide (SnO), gallium zinc oxide (GZO), and zinc tin oxide (ZTO), or a combination of the foregoing materials.

[0101] The gate layer 123 is arranged between the first source and drain layer 121 and the second source and drain layer 124, and is insulated from the metal oxide semiconductor layer 122. The gate layer 123 includes a gate portion 1231 of the second transistor, and the orthographic projection of the gate portion 1231 on the first driving layer 11 coincides with the orthographic projection of the channel portion 1221A of the metal oxide semiconductor portion 1221 on the first driving layer 11.

[0102] like Figure 5 As shown, the second driving layer 12 may further include a first insulating layer 125 , a second insulating layer 126 and a third insulating layer 127 .

[0103] The first insulating layer 125 is provided on the surface of the first sub-source portion 121S and the first sub-drain portion 121D away from the first driving layer 11 . The first insulating layer 125 also covers the surface of the first driving layer 11 .

[0104] The metal oxide semiconductor portion 1221 is arranged on the surface of the first insulating layer 125 away from the first driving layer 11, and the orthographic projection of the metal oxide semiconductor portion 1221 on the first driving layer 11 is between the orthographic projection of the first sub-source portion 121S on the first driving layer 11 and the orthographic projection of the first sub-drain portion 121D on the first driving layer 11.

[0105] The second insulating layer 126 is disposed on a surface of the metal oxide semiconductor portion 1221 away from the first driving layer 11 . The second insulating layer 126 also covers a surface of the first insulating layer 125 .

[0106] The gate portion 1231 is disposed on a surface of the second insulating layer 126 away from the first driving layer 11 .

[0107] The third insulating layer 127 is disposed on a surface of the gate portion 1231 away from the first driving layer 11 . The third insulating layer 127 also covers a surface of the second insulating layer 126 .

[0108] The second sub-source portion 124S and the second sub-drain portion 124D are disposed on a surface of the third insulating layer 127 away from the first driving layer 11 .

[0109] The first through hole K1 in the second driving layer 12 passes through the third insulating layer 127 to the first insulating layer 125 to expose a portion of the first sub-source electrode portion 121S, and the second sub-source electrode portion 124S is connected to the first sub-source electrode portion 121S through the first through hole K1, that is, the second sub-source electrode portion 124S is connected to the first sub-source electrode portion 121S through the third insulating layer 127, the second insulating layer 126 and the first insulating layer 125 in sequence.

[0110] The second through hole K2 in the second driving layer 12 passes through the third insulating layer 127 to the second insulating layer 126 to expose the source contact portion 1221S of the metal oxide semiconductor portion 1221, and the second sub-source portion 124S is connected to the source contact portion 1221S through the second through hole K2, that is, the second sub-source portion 124S is connected to the source contact portion 1221S through the third insulating layer 127 and the second insulating layer 126 in sequence.

[0111] The third through hole K3 in the second driving layer 12 passes through the third insulating layer 127 to the first insulating layer 125 to expose a portion of the first sub-drain portion 121D, and the second sub-drain portion 124D is connected to the first sub-drain portion 121D through the third through hole K3, that is, the second sub-drain portion 124D is connected to the first sub-drain portion 121D through the third insulating layer 127, the second insulating layer 126 and the first insulating layer 125 in sequence.

[0112] The fourth through hole K4 in the second driving layer 12 passes through the third insulating layer 127 to the second insulating layer 126 to expose the drain contact portion 1221D of the metal oxide semiconductor portion 1221, and the second sub-drain portion 124D is connected to the drain contact portion 1221D via the fourth through hole K4. That is, the second sub-drain portion 124D is connected to the drain contact portion 1221D via the third insulating layer 127 and the second insulating layer 126 in sequence.

[0113] Figure 5 The second transistor T2 in the second driving layer 12 shown is a metal oxide transistor with a top gate structure. In other embodiments provided in the present application, for example, Figure 10 As shown, the second transistor T2 in the second driver 12 may also be a metal oxide transistor with a bottom-gate structure.

[0114] Figure 10 The second driving layer 12 shown is Figure 5The second driving layer 12 shown differs in that:

[0115] Figure 10 The second driving layer shown may further include only the first insulating layer 125 and the second insulating layer 126 .

[0116] The gate portion 1231 is disposed on a surface of the first insulating layer 125 away from the first driving layer 11 .

[0117] The second insulating layer 126 is disposed on a surface of the gate portion 1231 away from the first driving layer 11 . The second insulating layer 126 also covers the first insulating layer 125 .

[0118] The metal oxide semiconductor portion 1221 is disposed on a surface of the second insulating layer 126 away from the first driving layer 11 .

[0119] The second sub-source portion 124S is at least partially disposed on a surface of the metal oxide semiconductor portion 1221 away from the source contact portion 1221S and the first driving layer 11 . The second sub-drain portion 124D is at least partially disposed on a surface of the metal oxide semiconductor portion 1221 away from the drain contact portion 1221D and the first driving layer 11 .

[0120] The fifth through hole K5 in the second driving layer 12 passes through the second insulating layer 126 to the first insulating layer 125 to expose the first sub-source electrode portion 121S, and the second sub-source electrode portion 124S is connected to the first sub-source electrode portion 121S through the fifth through hole K5, that is, the second sub-source electrode portion 124S is connected to the first sub-source electrode portion 121S through the second insulating layer 126 and the first insulating layer 125 in sequence.

[0121] The sixth through hole K6 in the second driving layer 12 passes through the second insulating layer 126 to the first insulating layer 125 to expose the first sub-drain portion 121D, and the second sub-drain portion 124D is connected to the first sub-drain portion 121D through the sixth through hole K6, that is, the second sub-drain portion 124D is connected to the first sub-drain portion 121D through the second insulating layer 126 and the first insulating layer 125 in sequence.

[0122] like Figure 5 as well as Figure 10 As shown, the second driving layer 12 also includes an interlayer dielectric layer 128. The interlayer dielectric layer 128 is arranged on the surface of the second source and drain layer 124 away from the first driving layer 11 and covers the first driving layer 11. The interlayer dielectric layer 128 is used to insulate the second source and drain layer 124 and the light-emitting device layer 13. In addition, the interlayer dielectric layer 128 is also used to flatten the surface of the second driving layer 12 away from the first driving layer 11 to ensure that the film thickness of the light-emitting device layer 13 is uniform, thereby ensuring the uniformity of light emission of the light-emitting device.

[0123] The second drive layer 12 also includes a bonding hole K7 and a bonding metal portion. The bonding hole K7 sequentially penetrates the interlayer dielectric layer 128 and the multiple insulating layers disposed between the interlayer dielectric layer 128 and the first drive layer 11 to expose a portion of the first drive layer 11. The light-emitting device is connected to a conductive portion 11023a in the first drive layer 11 via the bonding hole K7, thereby enabling the light-emitting device to be electrically connected to the first transistor in the first drive layer 11. The bonding metal portion is located within the bonding hole K7 and connects the first drive layer and the light-emitting device, respectively, so that the light-emitting device is electrically connected to the first drive layer 11 via the bonding hole K7. The bonding metal portion can be a metallic conductive material such as copper or tungsten, and the bonding metal portion can completely fill the bonding hole K7.

[0124] like Figure 5 and to Figure 10 As shown, along the thickness direction of the display panel 100 , the light emitting device layer 13 further includes a bonding metal layer 131 , an anode layer 132 , an epitaxial layer 133 , a dielectric layer 134 and a cathode layer 135 .

[0125] The bonding metal layer 131 is disposed on a surface of the second driving layer 12 away from the first driving layer 11 , and the bonding metal layer 131 is electrically connected to the first driving layer 11 through the bonding hole K7 .

[0126] The anode layer 132 is disposed on the surface of the bonding metal layer 131 away from the first driving layer 11.

[0127] The epitaxial layer 133 is disposed on the surface of the anode layer 132 away from the first driving layer 11.

[0128] The dielectric layer 134 is disposed on the sidewalls of the bonding metal layer 131 , the anode layer 132 , and the epitaxial layer 133 to insulate adjacent light emitting devices from each other.

[0129] The cathode layer 135 is entirely disposed on a surface of the epitaxial layer 133 away from the first driving layer 11 , and covers the dielectric layer 134 and the second driving layer 12 .

[0130] In this embodiment, in order to ensure that the display panel 100 has a high pixel density, an epitaxial layer is formed on the entire surface of the second drive layer 12 away from the first drive layer 11 and metal bonding is performed, and then the light-emitting device layer 13 is etched to prepare a higher density of light-emitting devices, and a light-emitting device is separately connected to a pixel circuit, thereby solving the technical problem of low alignment accuracy caused by bonding the light-emitting device to the first drive layer 11 through mass transfer.

[0131] The present application also provides a method for preparing the aforementioned display panel. Figure 11 As shown, the preparation method 200 includes:

[0132] Step S2001: Prepare a first drive layer. A CMOS device circuit layer is fabricated on a silicon substrate using a CMOS process to form the first drive layer. Part of the pixel circuits in the display area and the peripheral drive circuits in the non-display area are formed in the first drive layer.

[0133] Step S2002: Prepare a second driving layer on the surface of the first driving layer. The second driving layer includes a second transistor with a top-gate structure or a second transistor with a bottom-gate structure.

[0134] Taking the second transistor as a top-gate transistor as an example, step S2602 may be specifically as follows:

[0135] A first source-drain electrode layer is deposited on the surface of the first driving layer and patterned to form a first sub-source portion and a first sub-drain portion of the second transistor.

[0136] A first insulating layer is deposited on a surface of the first source / drain electrode layer away from the first driving layer; a metal oxide semiconductor layer is deposited on a surface of the first insulating layer away from the first driving layer and patterned to form a metal oxide semiconductor portion of the second transistor.

[0137] A second insulating layer is deposited on a surface of the metal oxide semiconductor layer away from the first driving layer; a gate layer is deposited on a surface of the second insulating layer away from the first driving layer and patterned to form a gate portion of a second transistor.

[0138] A third insulating layer is deposited on the surface of the gate layer away from the first driving layer, and the third insulating layer, the second insulating layer and the first insulating layer are etched accordingly to form at least four through holes to respectively expose the first sub-source portion, the first sub-drain portion, the source contact portion of the metal oxide semiconductor portion and the drain contact portion of the metal oxide semiconductor portion.

[0139] A second source-drain metal layer is deposited on the surface of the third insulating layer away from the first driving layer and the second source-drain layer is patterned to form a second sub-source portion and a second sub-drain portion, the second sub-source portion is respectively connected to the source contact portion of the first sub-source portion and the metal oxide semiconductor portion, and the second sub-drain portion is respectively connected to the drain contact portion of the first sub-drain portion and the metal oxide semiconductor portion.

[0140] An interlayer dielectric layer is deposited on a surface of the second source / drain electrode layer away from the first driving layer.

[0141] In step S2003, the surface of the second driving layer away from the first driving layer is ground flat, and a bonding hole is formed in the second driving layer, through which a portion of the first driving layer is exposed. Specifically, the conductive portion that overlaps with the orthographic projection of the bonding hole on the first driving layer is exposed through the bonding hole.

[0142] Step S2004 : depositing an epitaxial structure of a light-emitting device layer on the entire surface of the second driving layer away from the first driving layer.

[0143] Step S2005 , peeling off the epitaxial substrate of the light emitting device layer and patterning the epitaxial structure to form a single light emitting device, and the light emitting device is connected to the first driving layer via the bonding hole.

[0144] Step S2006 , depositing a dielectric layer on the sidewalls of the patterned light-emitting device, and depositing a cathode on the entire surface of the patterned light-emitting device.

[0145] Of course, the present application may have many other embodiments. Without departing from the spirit and essential points of the present application, technicians familiar with the field may make various corresponding changes and modifications based on the present application, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present application.

Claims

1. A display panel, characterized in that: The display panel has a display area and a non-display area surrounding the display area. The display area is provided with a plurality of pixel modules arranged in an array. Along the thickness direction of the display panel, the pixel modules include: a first driving layer, the first driving layer comprising a plurality of first transistors, sources of the plurality of first transistors being electrically connected to a driving current terminal of the first driving layer, drains of the plurality of first transistors being electrically connected to a first node, the first transistors being configured to provide a driving current from the driving current terminal to the first node based on a grayscale data signal; a second driving layer, the second driving layer being located on a surface of the first driving layer, the second driving layer comprising a plurality of grayscale data signal storage units, the plurality of grayscale data signal storage units corresponding one-to-one to and electrically connected to the gates of the plurality of first transistors, the plurality of grayscale data signal storage units being electrically connected to the same word line of the display panel, the plurality of grayscale data signal storage units corresponding one-to-one to and electrically connected to the plurality of bit lines of the display panel, the plurality of grayscale data signal storage units being electrically connected to a first power supply terminal of the display panel, the grayscale data signal storage units being configured to store the grayscale data signals transmitted by the bit lines based on a first control signal transmitted by the word lines and output the grayscale data signals to the first transistors, wherein each of the grayscale data signal storage units comprises a second transistor and a capacitor, the drain of the second transistor being electrically connected to the gate of the first transistor and the first plate of the capacitor, the gate of the second transistor being electrically connected to the word line, the source of the second transistor being electrically connected to the bit line, and the second plate of the capacitor being electrically connected to the first power supply terminal; A light-emitting device layer, wherein the light-emitting device layer is located on a surface of the second driving layer away from the first driving layer, the light-emitting device layer includes at least one light-emitting device, the anode of at least one light-emitting device is electrically connected to the first node, and the cathode of at least one light-emitting device is electrically connected to the second power supply terminal of the display panel, wherein the first node is a node of the circuit between the drain of the first transistor and the light-emitting device.

2. The display panel according to claim 1, wherein: The first driving layer also includes a driving current regulating unit, which is electrically connected to the first power supply terminal and the reference voltage terminal of the display panel. The driving current regulating unit is also electrically connected to the driving current terminal. The driving current regulating unit is used to provide the driving current to the first transistor based on a third control signal provided by the reference voltage terminal.

3. The display panel according to claim 1, wherein: The first driving layer also includes multiple third transistors, the sources of the multiple third transistors correspond one-to-one to the drains of the multiple first transistors and are electrically connected, the drains of the multiple third transistors are electrically connected to the first node, and the gates of the multiple third transistors correspond one-to-one to the multiple pulse width modulation signal control terminals of the display panel and are electrically connected. The third transistors are used to output the driving current provided by the first transistor to the light-emitting device in a time-sharing manner based on the second control signal provided by the pulse width modulation signal control terminal.

4. The display panel according to claim 1, wherein: The pixel module includes at least 8 first transistors and at least 8 grayscale data signal storage units, the sources of at least 8 first transistors are electrically connected to the driving current end, the drains of at least 8 first transistors are electrically connected to the first node, the gates of at least 8 first transistors correspond one-to-one to and are electrically connected to the drains of at least 8 second transistors, the drains of at least 8 second transistors correspond one-to-one to and are electrically connected to the first plates of at least 8 capacitors, the gates of at least 8 second transistors are electrically connected to the same word line, the sources of at least 8 second transistors correspond one-to-one to and are electrically connected to at least 8 bit lines, and the second plates of at least 8 capacitors are electrically connected to the first power supply end.

5. The display panel according to claim 1, wherein: The pixel modules in the same row are electrically connected to the same word line, and multiple rows of pixel modules correspond to and are electrically connected to multiple word lines one by one. The starting time points of the pixel modules in two adjacent rows receiving the effective level of the first control signal differ by a preset time length.

6. The display panel according to any one of claims 1 to 5, characterized in that: The second transistor is a metal oxide thin film transistor.

7. The display panel according to claim 6, wherein: Along the thickness direction of the display panel, the second driving layer includes: a first source-drain layer, the first source-drain layer being disposed on a surface of the first driving layer, the first source-drain layer comprising a first sub-source portion of the second transistor and a first sub-drain portion of the second transistor being insulated; a second source-drain layer, the second source-drain layer being disposed on a side of the first source-drain layer away from the first driving layer, the second source-drain layer comprising a second sub-source portion of the second transistor and a second sub-drain portion of the second transistor that are insulated, the second sub-source portion being connected to the first sub-source portion, and the second sub-drain portion being connected to the first sub-drain portion; a metal oxide semiconductor layer, the metal oxide semiconductor layer being disposed between the first source-drain electrode layer and the second source-drain electrode layer, the metal oxide semiconductor layer including a metal oxide semiconductor portion of the second transistor; A gate layer, wherein the gate layer is arranged between the first source-drain layer and the second source-drain layer, and the gate layer is insulated from the metal oxide semiconductor layer, the gate layer includes a gate portion of the second transistor, and an orthographic projection of the gate portion on the first driving layer coincides with an orthographic projection of a channel portion of the metal oxide semiconductor portion on the first driving layer.

8. The display panel according to claim 7, wherein: The second driving layer further includes a first insulating layer, a second insulating layer and a third insulating layer; The first insulating layer is provided on the surface of the first sub-source portion and the first sub-drain portion away from the first driving layer, and covers the first driving layer; The metal oxide semiconductor portion is provided on a surface of the first insulating layer away from the first driving layer; The second insulating layer is provided on a surface of the metal oxide semiconductor portion away from the first driving layer and covers the first insulating layer; The gate portion is provided on a surface of the second insulating layer away from the first driving layer; The third insulating layer is provided on a surface of the gate portion away from the first driving layer and covers the second insulating layer; The second sub-source portion and the second sub-drain portion are arranged on the surface of the third insulating layer away from the first driving layer, the second sub-source portion is connected to the first sub-source portion through the third insulating layer, the second insulating layer and the first insulating layer, the second sub-source portion is connected to the source contact portion of the metal oxide semiconductor portion through the third insulating layer and the second insulating layer, the second sub-drain portion is connected to the first sub-drain portion through the third insulating layer, the second insulating layer and the first insulating layer, and the second sub-drain portion is connected to the drain contact portion of the metal oxide semiconductor portion through the third insulating layer and the second insulating layer.

9. The display panel according to claim 7, wherein: The second driving layer further includes a first insulating layer and a second insulating layer; The first insulating layer is provided on the surface of the first sub-source portion and the first sub-drain portion away from the first driving layer, and covers the first driving layer; The gate portion is provided on a surface of the first insulating layer away from the first driving layer; The second insulating layer is provided on a surface of the gate portion away from the first driving layer and covers the first insulating layer; The metal oxide semiconductor portion is provided on a surface of the second insulating layer away from the first driving layer; The second sub-source portion is at least partially disposed on a surface of the metal oxide semiconductor portion where the source contact portion is away from the first driving layer, and the second sub-source portion is connected to the first sub-source portion via the second insulating layer and the first insulating layer. The second sub-drain portion is at least partially disposed on a surface of the metal oxide semiconductor portion where the drain contact portion is away from the first driving layer, and the second sub-drain portion is connected to the first sub-drain portion via the second insulating layer and the first insulating layer.

10. The display panel according to claim 7, wherein: The second driving layer further includes an interlayer dielectric layer, which is provided on a surface of the second source / drain electrode layer away from the first driving layer and covers the first driving layer; The second driving layer also includes a bonding hole and a bonding metal part. The bonding hole passes through the second driving layer through the interlayer dielectric layer to expose a portion of the first driving layer. The bonding metal part is located in the bonding hole. The bonding metal part connects the first driving layer and the light-emitting device respectively.

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